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JonatanAntoniJonatanAntoni
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Merge branch 'develop/upstream' into master/upstream
Change-Id: I3de07af0117bfcdcbb4cab85b6de281c6c4ac773
2 parents 49ac527 + 8619da0 commit d8515eb

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‎ARM.CMSIS.pdsc

Lines changed: 323 additions & 142 deletions
Large diffs are not rendered by default.

‎CMSIS/Core/Include/cmsis_armcc.h

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -337,8 +337,6 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
337337
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
338338

339339

340-
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
341-
342340
/**
343341
\brief Get FPSCR
344342
\details Returns the current value of the Floating Point Status/Control register.
@@ -372,9 +370,6 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
372370
#endif
373371
}
374372

375-
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
376-
377-
378373

379374
/*@} end of CMSIS_Core_RegAccFunctions */
380375

‎CMSIS/Core/Include/cmsis_armclang.h

Lines changed: 9 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -237,7 +237,7 @@ __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
237237
*/
238238
__STATIC_FORCEINLINE uint32_t __get_PSP(void)
239239
{
240-
register uint32_t result;
240+
uint32_t result;
241241

242242
__ASM volatile ("MRS %0, psp" : "=r" (result) );
243243
return(result);
@@ -252,7 +252,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSP(void)
252252
*/
253253
__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
254254
{
255-
register uint32_t result;
255+
uint32_t result;
256256

257257
__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
258258
return(result);
@@ -291,7 +291,7 @@ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
291291
*/
292292
__STATIC_FORCEINLINE uint32_t __get_MSP(void)
293293
{
294-
register uint32_t result;
294+
uint32_t result;
295295

296296
__ASM volatile ("MRS %0, msp" : "=r" (result) );
297297
return(result);
@@ -306,7 +306,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSP(void)
306306
*/
307307
__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
308308
{
309-
register uint32_t result;
309+
uint32_t result;
310310

311311
__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
312312
return(result);
@@ -346,7 +346,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
346346
*/
347347
__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
348348
{
349-
register uint32_t result;
349+
uint32_t result;
350350

351351
__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
352352
return(result);
@@ -581,7 +581,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
581581
// without main extensions, the non-secure PSPLIM is RAZ/WI
582582
return 0U;
583583
#else
584-
register uint32_t result;
584+
uint32_t result;
585585
__ASM volatile ("MRS %0, psplim" : "=r" (result) );
586586
return result;
587587
#endif
@@ -603,7 +603,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
603603
// without main extensions, the non-secure PSPLIM is RAZ/WI
604604
return 0U;
605605
#else
606-
register uint32_t result;
606+
uint32_t result;
607607
__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
608608
return result;
609609
#endif
@@ -669,7 +669,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
669669
// without main extensions, the non-secure MSPLIM is RAZ/WI
670670
return 0U;
671671
#else
672-
register uint32_t result;
672+
uint32_t result;
673673
__ASM volatile ("MRS %0, msplim" : "=r" (result) );
674674
return result;
675675
#endif
@@ -691,7 +691,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
691691
// without main extensions, the non-secure MSPLIM is RAZ/WI
692692
return 0U;
693693
#else
694-
register uint32_t result;
694+
uint32_t result;
695695
__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
696696
return result;
697697
#endif
@@ -742,10 +742,6 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
742742
#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
743743
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
744744

745-
746-
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
747-
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
748-
749745
/**
750746
\brief Get FPSCR
751747
\details Returns the current value of the Floating Point Status/Control register.
@@ -770,10 +766,6 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
770766
#define __set_FPSCR(x) ((void)(x))
771767
#endif
772768

773-
#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
774-
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
775-
776-
777769

778770
/*@} end of CMSIS_Core_RegAccFunctions */
779771

‎CMSIS/Core/Include/cmsis_gcc.h

Lines changed: 18 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11
/**************************************************************************//**
22
* @file cmsis_gcc.h
33
* @brief CMSIS compiler GCC header file
4-
* @version V5.0.3
5-
* @date 16. January 2018
4+
* @version V5.0.4
5+
* @date 09. April 2018
66
******************************************************************************/
77
/*
8-
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
8+
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
99
*
1010
* SPDX-License-Identifier: Apache-2.0
1111
*
@@ -246,7 +246,7 @@ __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
246246
*/
247247
__STATIC_FORCEINLINE uint32_t __get_PSP(void)
248248
{
249-
register uint32_t result;
249+
uint32_t result;
250250

251251
__ASM volatile ("MRS %0, psp" : "=r" (result) );
252252
return(result);
@@ -261,7 +261,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSP(void)
261261
*/
262262
__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
263263
{
264-
register uint32_t result;
264+
uint32_t result;
265265

266266
__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
267267
return(result);
@@ -300,7 +300,7 @@ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
300300
*/
301301
__STATIC_FORCEINLINE uint32_t __get_MSP(void)
302302
{
303-
register uint32_t result;
303+
uint32_t result;
304304

305305
__ASM volatile ("MRS %0, msp" : "=r" (result) );
306306
return(result);
@@ -315,7 +315,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSP(void)
315315
*/
316316
__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
317317
{
318-
register uint32_t result;
318+
uint32_t result;
319319

320320
__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
321321
return(result);
@@ -355,7 +355,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
355355
*/
356356
__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
357357
{
358-
register uint32_t result;
358+
uint32_t result;
359359

360360
__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
361361
return(result);
@@ -596,7 +596,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
596596
// without main extensions, the non-secure PSPLIM is RAZ/WI
597597
return 0U;
598598
#else
599-
register uint32_t result;
599+
uint32_t result;
600600
__ASM volatile ("MRS %0, psplim" : "=r" (result) );
601601
return result;
602602
#endif
@@ -617,7 +617,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
617617
// without main extensions, the non-secure PSPLIM is RAZ/WI
618618
return 0U;
619619
#else
620-
register uint32_t result;
620+
uint32_t result;
621621
__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
622622
return result;
623623
#endif
@@ -683,7 +683,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
683683
// without main extensions, the non-secure MSPLIM is RAZ/WI
684684
return 0U;
685685
#else
686-
register uint32_t result;
686+
uint32_t result;
687687
__ASM volatile ("MRS %0, msplim" : "=r" (result) );
688688
return result;
689689
#endif
@@ -705,7 +705,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
705705
// without main extensions, the non-secure MSPLIM is RAZ/WI
706706
return 0U;
707707
#else
708-
register uint32_t result;
708+
uint32_t result;
709709
__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
710710
return result;
711711
#endif
@@ -758,9 +758,6 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
758758
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
759759

760760

761-
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
762-
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
763-
764761
/**
765762
\brief Get FPSCR
766763
\details Returns the current value of the Floating Point Status/Control register.
@@ -770,7 +767,9 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
770767
{
771768
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
772769
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
773-
#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
770+
#if __has_builtin(__builtin_arm_get_fpscr)
771+
// Re-enable using built-in when GCC has been fixed
772+
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
774773
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
775774
return __builtin_arm_get_fpscr();
776775
#else
@@ -794,7 +793,9 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
794793
{
795794
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
796795
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
797-
#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
796+
#if __has_builtin(__builtin_arm_set_fpscr)
797+
// Re-enable using built-in when GCC has been fixed
798+
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
798799
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
799800
__builtin_arm_set_fpscr(fpscr);
800801
#else
@@ -805,10 +806,6 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
805806
#endif
806807
}
807808

808-
#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
809-
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
810-
811-
812809

813810
/*@} end of CMSIS_Core_RegAccFunctions */
814811

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