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DanieleParraviciniDanieleParravicini
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First sersion of CICERO with pipelining, token ring topology and multi cc
Updates driver Tested on boardy
1 parent 2989330 commit 529f891

13 files changed

+358
-213
lines changed

‎hdl_src/rtl/AXI/AXI_top.sv

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -37,15 +37,15 @@ logic [ BRAM_WRITE_WIDTH -1:0 ] bram_w;
3737
logic bram_w_valid;
3838

3939
///// Coprocessor
40-
localparam BB_N = 8;
40+
localparam BB_N = 4;
4141
localparam BB_N_X = 0;
4242
localparam BB_N_Y = 0;
4343
localparam FIFO_COUNT_WIDTH = 5;
4444
localparam CHANNEL_COUNT_WIDTH = 4;
4545
localparam LATENCY_COUNT_WIDTH = 7;
4646
localparam CACHE_WIDTH_BITS = 4;
4747
localparam CACHE_BLOCK_WIDTH_BITS = 2;
48-
localparam BASIC_BLOCK_PIPELINED = 0;
48+
localparam BASIC_BLOCK_PIPELINED = 1;
4949
localparam PC_WIDTH = 8;
5050
localparam CHARACTER_WIDTH = 8;
5151
localparam CC_ID_BITS = 2;
@@ -224,7 +224,8 @@ coprocessor_top#(
224224
.CACHE_BLOCK_WIDTH_BITS (CACHE_BLOCK_WIDTH_BITS ),
225225
.CACHE_WIDTH_BITS (CACHE_WIDTH_BITS ),
226226
.BASIC_BLOCK_PIPELINED (BASIC_BLOCK_PIPELINED ),
227-
.REG_WIDTH (REG_WIDTH )
227+
.REG_WIDTH (REG_WIDTH ),
228+
.CC_ID_BITS (CC_ID_BITS )
228229
)a_regex_coprocessor (
229230
.clk (clk ),
230231
.rst (rst_master ),

‎hdl_src/rtl/CPU/regex_cpu_pipelined.sv

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -338,6 +338,6 @@ module regex_cpu_pipelined #(
338338
assign output_cc_id = output_pc_and_cc_id[CC_ID_BITS-1:0];
339339
assign accepts = EXE1_accepts || EXE2_accepts ;
340340
assign running = FETCH_REC_Instr_valid || EXE1_Instr_valid || EXE2_Instr_valid ;
341-
assign latency = 0; //EXE1_buffered_count + EXE2_buffered_count;
341+
342342

343343
endmodule

‎hdl_src/rtl/coprocessor/channel_multi_cc.sv

Lines changed: 28 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -9,13 +9,14 @@ module channel_multi_cc #(
99
input wire rst,
1010
channel_iface.in in,
1111
channel_iface.out out,
12-
output logic [2**CC_ID_BITS-1:0] present_cc_id
12+
output logic [(2**CC_ID_BITS)-1:0] present_cc_id
1313
);
1414
wire channel_input_ready , channel_input_not_ready;
1515
wire channel_output_valid , channel_output_not_valid;
1616
wire [CHANNEL_COUNT_WIDTH-1:0] fifo_count;
1717

18-
logic [CHANNEL_COUNT_WIDTH-1:0] cc_id_count [2**CC_ID_BITS-1:0];
18+
logic [CHANNEL_COUNT_WIDTH-1:0] cur_cc_id_count [(2**CC_ID_BITS)-1:0];
19+
logic [CHANNEL_COUNT_WIDTH-1:0] next_cc_id_count [(2**CC_ID_BITS)-1:0];
1920

2021
logic [LATENCY_COUNT_WIDTH-1:0] channel_old_latency, channel_old_latency_next;
2122

@@ -63,29 +64,43 @@ module channel_multi_cc #(
6364
begin
6465
if(rst)
6566
begin
66-
for (int i=0; i<2**CC_ID_BITS; ++i) begin
67-
cc_id_count[i] <= {(CHANNEL_COUNT_WIDTH){1'b0}};
67+
for (int i=0; i<(2**CC_ID_BITS); ++i) begin
68+
cur_cc_id_count[i] <= {(CHANNEL_COUNT_WIDTH){1'b0}};
6869
end
6970
end
7071
else
7172
begin
72-
if (in.valid && channel_input_ready)
73+
for (int i=0; i<(2**CC_ID_BITS); ++i)
7374
begin
74-
cc_id_count[in.data[0+:CC_ID_BITS]] <= cc_id_count[in.data[0+:CC_ID_BITS]]+1;
75-
end
76-
77-
if (out.ready && channel_output_valid)
78-
begin
79-
cc_id_count[in.data[0+:CC_ID_BITS]] <= cc_id_count[in.data[0+:CC_ID_BITS]]-1;
75+
cur_cc_id_count[i] <= next_cc_id_count[i];
8076
end
8177
end
8278
end
8379

8480
always_comb
8581
begin
86-
for (int i=0; i<2**CC_ID_BITS; ++i) begin
87-
present_cc_id[i] = (cc_id_count[in.data[0+:CC_ID_BITS]] == 0);
82+
for (int i=0; i<(2**CC_ID_BITS); ++i)
83+
begin
84+
present_cc_id[i] = (cur_cc_id_count[i] != 0);
8885
end
86+
87+
for (int i=0; i<(2**CC_ID_BITS); ++i)
88+
begin
89+
next_cc_id_count[i] = cur_cc_id_count[i];
90+
end
91+
92+
93+
if(in.valid && channel_input_ready )
94+
begin
95+
next_cc_id_count[in.data[0+:CC_ID_BITS]] = cur_cc_id_count[in.data[0+:CC_ID_BITS]]+1;
96+
end
97+
98+
if( out.ready && channel_output_valid )
99+
begin
100+
next_cc_id_count[out.data[0+:CC_ID_BITS]] = next_cc_id_count[out.data[0+:CC_ID_BITS]]-1;
101+
end
102+
103+
89104
end
90105

91106

‎hdl_src/rtl/coprocessor/coprocessor_package.sv

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,13 @@ package coprocessor_package;
44

55
localparam nr_bits_states = 3;
66
typedef enum logic[nr_bits_states-1 : 0] {
7-
CICERO_IDLE , CICERO_FETCH_1ST ,
8-
CICERO_FETCH_CCS_BUFFER , CICERO_FETCH_FROM_CCS_BUFFER,
9-
CICERO_EXE ,
10-
CICERO_COMPLETED_WITHOUT_ACCEPTING , CICERO_COMPLETED_ACCEPTING,
7+
CICERO_IDLE ,
8+
CICERO_FETCH_1ST ,
9+
CICERO_FETCH_CCS_BUFFER ,
10+
CICERO_FETCH_FROM_CCS_BUFFER ,
11+
CICERO_EXE ,
12+
CICERO_COMPLETED_WITHOUT_ACCEPTING ,
13+
CICERO_COMPLETED_ACCEPTING ,
1114
CICERO_ERROR
1215
} State;
1316

‎hdl_src/rtl/coprocessor/coprocessor_top.sv

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -203,7 +203,9 @@ module coprocessor_top #(
203203
//thanks to previous assumption * :
204204
//0. we can load the window in a bunch
205205
//$display("%d %d \n", cur_ccs_window_pointer_end[C_BUFFER_ADDR_OFFSET-1:CC_ID_BITS], cur_ccs_window_pointer_end[C_BUFFER_ADDR_OFFSET-1:CC_ID_BITS], cur_ccs_window_pointer_end[C_BUFFER_ADDR_OFFSET:CC_ID_BITS]*C_WINDOW_SIZE_IN_BITS);
206-
next_ccs_window = memory_for_cc.data[cur_ccs_window_pointer_end[C_BUFFER_ADDR_OFFSET-1:CC_ID_BITS]*C_WINDOW_SIZE_IN_BITS+:C_WINDOW_SIZE_IN_BITS];
206+
if (CC_ID_BITS == C_BUFFER_ADDR_OFFSET) next_ccs_window = memory_for_cc.data;
207+
else next_ccs_window = memory_for_cc.data[cur_ccs_window_pointer_end[C_BUFFER_ADDR_OFFSET-1:CC_ID_BITS]*C_WINDOW_SIZE_IN_BITS+:C_WINDOW_SIZE_IN_BITS];
208+
207209
//1. enable and first char in a fixed position
208210
next_ccs_enable = {1'b0,{(C_WINDOW_SIZE_IN_CHARS-1){1'b1}}};
209211
next_ccs_first_cc = {{(C_WINDOW_SIZE_IN_CHARS-1){1'b0}}, 1'b1};
@@ -264,10 +266,12 @@ module coprocessor_top #(
264266
end
265267
CICERO_EXE:
266268
begin
267-
logic first_window_char_executing = |(cur_ccs_first_cc & elaborating_chars);
269+
logic first_window_char_executing = |(cur_ccs_first_cc & elaborating_chars);
268270
logic first_window_char_is_end_of_s = |(cur_ccs_end_of_s & first_window_char_executing);
271+
logic no_other_work_to_do = !(|(elaborating_chars));
272+
logic time_to_fetch_ccs_buffer = cur_ccs_window_pointer_end[C_BUFFER_ADDR_OFFSET-1:0] == 0;
269273
//basic bock computation enable
270-
casez({ any_bb_accept, all_bb_full, first_window_char_executing, first_window_char_is_end_of_s || !any_bb_running, cur_ccs_window_pointer_end[C_BUFFER_ADDR_OFFSET-1:0] == 0})
274+
casez({ any_bb_accept, all_bb_full, !first_window_char_executing, first_window_char_is_end_of_s || no_other_work_to_do , time_to_fetch_ccs_buffer})
271275
5'b1????:
272276
begin // if during execution phase one basic block raise accept: end computations!
273277
next_state = CICERO_COMPLETED_ACCEPTING;
@@ -276,11 +280,11 @@ module coprocessor_top #(
276280
begin // if there's an instruction that should be saved but no one is able to save it
277281
next_state = CICERO_ERROR;
278282
end
279-
5'b0001?:
283+
5'b0011?:
280284
begin //if we reach the end of the string (i.e. current char is terminator)
281285
next_state = CICERO_COMPLETED_WITHOUT_ACCEPTING;
282286
end
283-
5'b00001:
287+
5'b00101:
284288
begin // if all basic blocks have finished to execute instructions related to current char
285289
// then it's time to move to the next character
286290
memory_for_cc.valid = 1'b1;
@@ -297,7 +301,7 @@ module coprocessor_top #(
297301
move_next_character = 1'b1;
298302
end
299303
end
300-
5'b00000:
304+
5'b00100:
301305
begin
302306
next_state = CICERO_FETCH_FROM_CCS_BUFFER;
303307
next_ccs_after_end_of_s = cur_ccs_after_end_of_s | {cur_ccs_after_end_of_s[C_WINDOW_SIZE_IN_CHARS-2:0],cur_ccs_after_end_of_s[C_WINDOW_SIZE_IN_CHARS-1]} | { cur_ccs_end_of_s[C_WINDOW_SIZE_IN_CHARS-2:0],cur_ccs_end_of_s[C_WINDOW_SIZE_IN_CHARS-1]};

‎hdl_src/rtl/coprocessor/engine.sv

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,6 @@ module engine #(
9797
logic [C_WINDOW_SIZE_IN_CHARS-1:0] regex_cpu_elaborating_chars;
9898

9999
localparam REGEX_CPU_FIFO_WIDTH_POWER_OF_2 = 2;
100-
logic [REGEX_CPU_FIFO_WIDTH_POWER_OF_2:0] regex_cpu_latency;
101100
//storage part of the basic block
102101
//cache wires
103102
wire regex_cpu_memory_ready ;
@@ -107,7 +106,7 @@ module engine #(
107106
wire regex_cpu_memory_valid ;
108107

109108
//FIFO signals
110-
logic fifo_data_in_ready [C_WINDOW_SIZE_IN_CHARS-1:0] ;
109+
logic [C_WINDOW_SIZE_IN_CHARS-1:0] fifo_data_in_ready ;
111110
logic [C_WINDOW_SIZE_IN_CHARS-1:0] fifo_data_in_not_ready ;
112111
logic [PC_WIDTH+CC_ID_BITS-1:0] fifo_data_in [C_WINDOW_SIZE_IN_CHARS-1:0] ;
113112
logic fifo_data_in_valid [C_WINDOW_SIZE_IN_CHARS-1:0] ;
@@ -142,8 +141,11 @@ module engine #(
142141
for (int j=0; j < C_WINDOW_SIZE_IN_CHARS; ++j) begin
143142
fifo_data_in_valid [j] = 1'b0;
144143
end
145-
fifo_data_in_valid[input_cc_id] = input_pc_valid;
146-
input_pc_ready = fifo_data_in_ready[input_cc_id];
144+
if ( input_pc_valid )
145+
begin
146+
fifo_data_in_valid[input_cc_id] = 1'b1;
147+
end
148+
input_pc_ready = &fifo_data_in_ready;
147149
end
148150

149151
//FIFOs
@@ -288,7 +290,6 @@ module engine #(
288290
.running (regex_cpu_running ),
289291
.elaborating_chars (regex_cpu_elaborating_chars )
290292
);
291-
assign regex_cpu_latency = 0;
292293
end
293294

294295

‎hdl_src/rtl/coprocessor/engine_and_station.sv

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,7 @@ switch station (
104104
);
105105

106106
assign elaborating_chars = elaborating_chars_channel | elaborating_chars_engine;
107-
assign bb_full = !switch2channel.ready && engine_full;
108-
assign bb_running = switch2channel.valid || engine_running ;
107+
assign bb_full = !switch2channel.ready && engine_full;
108+
assign bb_running = switch2channel.valid || engine_running ;
109109

110110
endmodule

‎hdl_src/rtl/coprocessor/engine_interfaced.sv

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -38,26 +38,26 @@ module engine_interfaced #(
3838
.CONSIDER_PIPELINE_FIFO (CONSIDER_PIPELINE_FIFO ),
3939
.CC_ID_BITS (CC_ID_BITS )
4040
) anEngine (
41-
.clk (clk ),
42-
.rst (rst ),
43-
.accepts (accepts ),
44-
.running (running ),
45-
.full (full ),
46-
.enable_chars (enable_chars ),
47-
.elaborating_chars (elaborating_chars ),
48-
.current_characters (current_characters ),
49-
.new_char (new_char ),
50-
.memory_ready (memory.ready ),
51-
.memory_addr (memory.addr ),
52-
.memory_data (memory.data ),
53-
.memory_valid (memory.valid ),
54-
.input_pc_valid (in.valid ),
55-
.input_pc_and_cc_id (in.data ),
56-
.input_pc_ready (in.ready ),
57-
.input_pc_latency (in.latency ),
58-
.output_pc_valid (out.valid ),
59-
.output_pc_and_cc_id (out.data ),
60-
.output_pc_ready (out.ready )
41+
.clk (clk ),
42+
.rst (rst ),
43+
.accepts (accepts ),
44+
.running (running ),
45+
.full (full ),
46+
.enable_chars (enable_chars ),
47+
.elaborating_chars (elaborating_chars ),
48+
.current_characters (current_characters ),
49+
.new_char (new_char ),
50+
.memory_ready (memory.ready ),
51+
.memory_addr (memory.addr ),
52+
.memory_data (memory.data ),
53+
.memory_valid (memory.valid ),
54+
.input_pc_valid (in.valid ),
55+
.input_pc_and_cc_id (in.data ),
56+
.input_pc_ready (in.ready ),
57+
.input_pc_latency (in.latency ),
58+
.output_pc_valid (out.valid ),
59+
.output_pc_and_cc_id (out.data ),
60+
.output_pc_ready (out.ready )
6161
//.output_pc_latency (out.latency ),
6262

6363
);

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