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DanieleParraviciniDanieleParravicini
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‎.gitmodules

Lines changed: 0 additions & 3 deletions
This file was deleted.

‎re2compiler

Lines changed: 0 additions & 1 deletion
This file was deleted.

‎rtl_src/AXI_package.sv

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
`timescale 1ns/1ps
2-
//contains signals used to interface regex_coprocessor
3-
//and software.
2+
// Author: Daniele Parravicini
3+
// This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
4+
// Furthermore no-copy is allowed without explicit permission of the authors.
45
package AXI_package;
56
localparam REG_WIDTH = 32;
67
parameter CMD_NOP = 'h0000_0000 ;

‎rtl_src/AXI_top.sv

Lines changed: 10 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -2,16 +2,15 @@
22

33
import AXI_package::*;
44

5-
//component intended to decouple the regex_coprocessor and the AXI interface.
6-
//It contains the memory of the regex_coprocessor so that is possible to show outside the contetn of the memory
7-
//It implements some commands that are intended to drive the regex_coprocessor and other component from software.
5+
// Author: Daniele Parravicini
6+
// This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
7+
// Furthermore no-copy is allowed without explicit permission of the authors.
88

99
module AXI_top(
1010
input logic clk,
1111
input logic reset,
1212
input logic [REG_WIDTH-1:0] data_in_register,
1313
input logic [REG_WIDTH-1:0] address_register,
14-
// input logic [REG_WIDTH-1:0] start_pc_register,
1514
input logic [REG_WIDTH-1:0] start_cc_pointer_register,
1615
input logic [REG_WIDTH-1:0] cmd_register,
1716
output logic [REG_WIDTH-1:0] status_register,
@@ -53,16 +52,13 @@ logic memory_addr_from_coprocessor_ready;
5352
logic [ BRAM_READ_ADDR_WIDTH-1:0] memory_addr_from_coprocessor;
5453
logic memory_addr_from_coprocessor_valid;
5554
logic start_valid, finish, accept, error;
56-
//logic [PC_WIDTH-1:0] start_pc;
5755
logic start_ready;
5856

59-
/////performace counters
6057
logic [REG_WIDTH-1:0] elapsed_cc, elapsed_cc_next;
6158

6259

6360
assign reset_master = reset || (cmd_register==CMD_RESET);
6461

65-
///// Sequential logic
6662
always_ff @(posedge clk)
6763
begin
6864
if(reset_master == 1'b1)
@@ -77,7 +73,6 @@ begin
7773
end
7874
end
7975

80-
//// Combinational logic
8176

8277
always_comb
8378
begin
@@ -100,10 +95,10 @@ begin
10095
case(status_register)
10196
STATUS_IDLE:
10297
begin
103-
if(cmd_register == CMD_WRITE) // to write the content of memory write in seuqence addr_0, cmd_write, data_0,
104-
begin // addr_1, data_1, ..., cmd_nop.
98+
if(cmd_register == CMD_WRITE)
99+
begin
105100

106-
bram_w_addr = address_register[0+:BRAM_WRITE_ADDR_WIDTH]; //use low
101+
bram_w_addr = address_register[0+:BRAM_WRITE_ADDR_WIDTH];
107102
bram_w_valid = { (BRAM_WE_WIDTH) {1'b1} };
108103
bram_w = data_in_register[0+:BRAM_WRITE_WIDTH];
109104
end
@@ -116,7 +111,6 @@ begin
116111
end
117112
else if(cmd_register == CMD_START)
118113
begin
119-
//start_pc = start_pc_register[0+:PC_WIDTH];
120114
start_ready = 1'b1;
121115
bram_r_addr = memory_addr_from_coprocessor;
122116
bram_r_valid = memory_addr_from_coprocessor_valid;
@@ -136,7 +130,7 @@ begin
136130
end
137131
STATUS_ACCEPTED, STATUS_REJECTED, STATUS_ERROR:
138132
begin
139-
if(cmd_register == CMD_WRITE) // to write the content of memory write in seuqence addr_0, cmd_write, data_0,
133+
if(cmd_register == CMD_WRITE)
140134
begin // addr_1, data_1, ..., cmd_nop.
141135

142136
bram_w_addr = address_register[0+:BRAM_WRITE_ADDR_WIDTH]; //use low
@@ -162,7 +156,6 @@ begin
162156
end
163157
STATUS_RUNNING:
164158
begin
165-
// leave memory control to coprocessor
166159
bram_r_addr = memory_addr_from_coprocessor;
167160
bram_r_valid = memory_addr_from_coprocessor_valid;
168161
memory_addr_from_coprocessor_ready = 1'b1;
@@ -178,7 +171,7 @@ begin
178171

179172

180173
if (&elapsed_cc == 1'b0)
181-
begin //if counter has not saturated
174+
begin
182175
elapsed_cc_next = elapsed_cc + 1;
183176
end
184177
end
@@ -208,31 +201,7 @@ bram #(
208201
);
209202

210203

211-
if (BB_N == 1) begin : g1
212-
regex_coprocessor_single_bb #(
213-
.PC_WIDTH (PC_WIDTH ),
214-
.CHARACTER_WIDTH (CHARACTER_WIDTH ),
215-
.MEMORY_WIDTH (BRAM_READ_WIDTH ),
216-
.MEMORY_ADDR_WIDTH (BRAM_READ_ADDR_WIDTH ),
217-
.FIFO_COUNT_WIDTH (FIFO_COUNT_WIDTH ),
218-
.BASIC_BLOCK_PIPELINED (BASIC_BLOCK_PIPELINED )
219-
) a_regex_coprocessor (
220-
.clk (clk ),
221-
.reset (reset_master ),
222-
.memory_ready (memory_addr_from_coprocessor_ready ),
223-
.memory_addr (memory_addr_from_coprocessor ),
224-
.memory_data (bram_r ),
225-
.memory_valid (memory_addr_from_coprocessor_valid ),
226-
.start_ready (start_ready ),
227-
.start_cc_pointer (start_cc_pointer_register ),
228-
.start_valid (start_valid ),
229-
.finish (finish ),
230-
.accept (accept ),
231-
.error (error )
232-
);
233-
end
234-
else
235-
begin : g1
204+
236205

237206
regex_coprocessor_n_bb#(
238207
.PC_WIDTH (PC_WIDTH ),
@@ -261,5 +230,5 @@ begin : g1
261230
.accept (accept ),
262231
.error (error )
263232
);
264-
end
233+
265234
endmodule

‎rtl_src/arbiter_fixed.sv

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
`timescale 1ns/1ps
2-
2+
// Author: Daniele Parravicini
3+
// This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
4+
// Furthermore no-copy is allowed without explicit permission of the authors.
35
module arbiter_fixed #(
46
parameter DWIDTH = 8 ,
57
parameter PRIORITY_0 = 1

‎rtl_src/arbiter_rr.sv

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,7 @@
11
`timescale 1ns/1ps
2+
// Author: Daniele Parravicini
3+
// This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
4+
// Furthermore no-copy is allowed without explicit permission of the authors.
25

36
module arbiter_rr #(
47
parameter DWIDTH = 16 ,
@@ -27,14 +30,9 @@ always_ff @( posedge clk ) begin
2730
last_in <= ~PRIORITY_0;
2831
end
2932
else
30-
//else if( out_ready && out_valid)
3133
begin
3234
last_in <= last_in_next;
3335
end
34-
//else
35-
//begin
36-
// last_in <= last_in;
37-
//end
3836

3937
end
4038

‎rtl_src/arbiter_rr_n.sv

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
`timescale 1ns/1ps
2-
2+
// Author: Daniele Parravicini
3+
// This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
4+
// Furthermore no-copy is allowed without explicit permission of the authors.
35
module arbiter_rr_n #(
46
parameter DWIDTH = 16 ,
57
parameter N = 2
@@ -19,10 +21,6 @@ module arbiter_rr_n #(
1921
logic tmp_ready [2*N-2:0];
2022
logic tmp_valid [2*N-2:0];
2123

22-
//we have to create a heap of arbiters to regulate access to output
23-
//hence for a number of requestor equal to N we need N-1 arbiters
24-
// signals related to requerstor will belong to the lowest part of the array [N-1->0]
25-
// signals related to arbiters will belong to the highest part of the array [2*N-2->N]
2624
genvar j;
2725
generate
2826
for (j=0; j < N; j++)

‎rtl_src/basic_block.sv

Lines changed: 4 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -1,43 +1,8 @@
11
`timescale 1ns/1ps
2-
//wraps
3-
//1.a regex_cpu and
4-
//2.two fifos to save instructions in the form of their program counters
5-
// for current and next character.
6-
//
7-
// /-<memory_data
8-
// /--->memory_addr
9-
// +------------------------------------------>memory_valid
10-
//+----------------------------------|------------------------+ \---<memory_ready
11-
//| Basic block | |
12-
//| +- - - - - - - + |
13-
//| cache |
14-
//| | (optional) | |
15-
//| |
16-
//| +- - - - - - - + |
17-
//| | |
18-
//| +-------|------+ |
19-
//| | Regex_cpu | | /--->output_pc_valid
20-
//| +-----> | ------>----------------------------->output_pc_and current
21-
//| | | | | \---<output_pc_ready
22-
//| | +--------------+ |
23-
//| | input_pc_and_current[0]
24-
//| | +------------------+ 1 +-----+ |
25-
//| +---- curr_char_fifo <--+--+--+ | |
26-
//| +------------------+ |demux| | | /---<input_pc_valid
27-
//| +------------------+ | <--+-----------------------<input_pc_and_current
28-
//| 0 --data_out_ready-->| next_char_fifo <--+-----+ +----------------------->input_pc_ready
29-
//| +------------------+ 0 | |
30-
//| | |
31-
//| even_in_ready | |
32-
//| and ---------------------+ |
33-
//| odd_in_ready |
34-
//| |
35-
//+-----------------------------------------------------------+
36-
//note that:
37-
//- curr_char_fifo and next_char_fifo are implemented by 2 fifos(called odd/even)
38-
// in which inputs/outputs are muxed/demuxed via cur_is_even_character (input)
39-
// not represented for sake of drawing simplicity
40-
2+
3+
// Author: Daniele Parravicini
4+
// This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
5+
// Furthermore no-copy is allowed without explicit permission of the authors.
416

427
module basic_block #(
438
parameter PC_WIDTH = 8 ,

‎rtl_src/bram.sv

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
`timescale 1ns / 10ps
2-
2+
// Author: Daniele Parravicini
3+
// This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
4+
// Furthermore no-copy is allowed without explicit permission of the authors.
35
module bram #(
46
parameter READ_WIDTH = 64,
57
parameter READ_ADDR_WIDTH = 9,

‎rtl_src/cache_block_directly_mapped.sv

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,7 @@
11
`timescale 1ns/1ps
2-
//A cache to decouple memory access between different
3-
//basic block.
4-
//Remember that in this context none write the memory
5-
//hence no synchronization problem can happen.
6-
//1. memory is supplied with an address (filling addr_in,raising addr_in_valid)
7-
//2.a if memory has this content in cache answers positively raising addr_in_ready.
8-
//2.b otherwise memory relays memory request on addr_out using the same protocol.
9-
//
2+
// Author: Daniele Parravicini
3+
// This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
4+
// Furthermore no-copy is allowed without explicit permission of the authors.
105
module cache_block_directly_mapped #(
116
parameter DWIDTH = 4,
127
parameter CACHE_WIDTH_BITS = 4,
@@ -43,15 +38,14 @@ logic [RAM_WIDTH-1:0] data_from_memory ;
4338
typedef enum logic[1:0] { S_IDLE,S_FETCH, S_WRITE } State;
4439
State curState, nextState;
4540

46-
//decompose addr_in in tag and cache_line
4741
logic [BLOCK_WIDTH_BITS-1:0] block_sel_in , block_sel_saved, block_sel_saved_next;
4842
logic [CACHE_WIDTH_BITS-1:0 ] cache_line_in, cache_line_saved, cache_line_saved_next ;
4943
logic [TAG_WIDTH-1:0] tag_in , tag_saved , tag_saved_next ;
5044

5145
assign block_sel_in = addr_in[0+:BLOCK_WIDTH_BITS];
5246
assign cache_line_in = addr_in[BLOCK_WIDTH_BITS+:CACHE_WIDTH_BITS];
5347
assign tag_in = addr_in[ADDR_IN_WIDTH-1-:TAG_WIDTH];
54-
//compute hit signal
48+
5549
logic hit;
5650
assign hit = (tag[cache_line_in] == tag_in && is_present[cache_line_in]) ;
5751

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