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lines changed Original file line number Diff line number Diff line change 4
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import C_TO_LOGIC
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+ from utilities import REPO_ABS_DIR
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+
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# TODO: Temporarily import from submodule, remove this hack when we create a proper pipelinec setup.py
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- sys .path .append ('.. /submodule/pycparser /pycparser' )
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+ sys .path .append (REPO_ABS_DIR () + ' /submodule/pycparser' )
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from pycparser import c_ast , c_generator
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# FSM funcs cant be main functions
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raise Exception ("'cpp' C preprocessor is not installed!" )
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# TODO: Temporarily import from submodule, remove this hack when we create a proper pipelinec setup.py
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- sys .path .append ('.. /submodule/pycparser /pycparser' )
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+ sys .path .append (REPO_ABS_DIR () + ' /submodule/pycparser' )
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from pycparser import c_ast , c_parser
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# Global default constants for inferring different VHDL implementations of operators
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import SW_LIB
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import VHDL
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+ from utilities import REPO_ABS_DIR
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+
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# TODO: Temporarily import from submodule, remove this hack when we create a proper pipelinec setup.py
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- sys .path .append ('.. /submodule/pycparser /pycparser' )
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+ sys .path .append (REPO_ABS_DIR () + ' /submodule/pycparser' )
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from pycparser import c_ast
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import SYN
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import VHDL
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+ from utilities import REPO_ABS_DIR
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+
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# TODO: Temporarily import from submodule, remove this hack when we create a proper pipelinec setup.py
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- sys .path .append ('.. /submodule/pycparser /pycparser' )
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+ sys .path .append (REPO_ABS_DIR () + ' /submodule/pycparser' )
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from pycparser import c_ast
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# Hey lets bootstrap for fun
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import VERILATOR
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import VIVADO
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+ from utilities import REPO_ABS_DIR
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+
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# TODO: Temporarily import from submodule, remove this hack when we create a proper pipelinec setup.py
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- sys .path .append ('.. /submodule/pycparser /pycparser' )
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+ sys .path .append (REPO_ABS_DIR () + ' /submodule/pycparser' )
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from pycparser import c_ast
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VHDL_FILE_EXT = ".vhd"
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