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FIX: Use root directory of repository instead of relative path
1 parent 642602a commit 2391519

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5 files changed

+13
-5
lines changed

5 files changed

+13
-5
lines changed

src/C_TO_FSM.py

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,10 @@
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import C_TO_LOGIC
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from utilities import REPO_ABS_DIR
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# TODO: Temporarily import from submodule, remove this hack when we create a proper pipelinec setup.py
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sys.path.append('../submodule/pycparser/pycparser')
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sys.path.append(REPO_ABS_DIR() + '/submodule/pycparser')
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from pycparser import c_ast, c_generator
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# FSM funcs cant be main functions

src/C_TO_LOGIC.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@
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raise Exception("'cpp' C preprocessor is not installed!")
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# TODO: Temporarily import from submodule, remove this hack when we create a proper pipelinec setup.py
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sys.path.append('../submodule/pycparser/pycparser')
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sys.path.append(REPO_ABS_DIR() + '/submodule/pycparser')
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from pycparser import c_ast, c_parser
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# Global default constants for inferring different VHDL implementations of operators

src/RAW_VHDL.py

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,10 @@
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import SW_LIB
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import VHDL
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from utilities import REPO_ABS_DIR
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# TODO: Temporarily import from submodule, remove this hack when we create a proper pipelinec setup.py
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sys.path.append('../submodule/pycparser/pycparser')
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sys.path.append(REPO_ABS_DIR() + '/submodule/pycparser')
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from pycparser import c_ast
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src/SW_LIB.py

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,10 @@
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import SYN
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import VHDL
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from utilities import REPO_ABS_DIR
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# TODO: Temporarily import from submodule, remove this hack when we create a proper pipelinec setup.py
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sys.path.append('../submodule/pycparser/pycparser')
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sys.path.append(REPO_ABS_DIR() + '/submodule/pycparser')
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from pycparser import c_ast
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# Hey lets bootstrap for fun

src/VHDL.py

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,8 +15,10 @@
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import VERILATOR
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import VIVADO
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from utilities import REPO_ABS_DIR
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# TODO: Temporarily import from submodule, remove this hack when we create a proper pipelinec setup.py
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sys.path.append('../submodule/pycparser/pycparser')
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sys.path.append(REPO_ABS_DIR() + '/submodule/pycparser')
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from pycparser import c_ast
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VHDL_FILE_EXT = ".vhd"

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