Merge pull request #428 from MikroElektronika/fix/ra-uart-core

esmaniksic · web-flow · commit e362daeef8a7 · 2025-08-19T10:55:47.000+02:00
Fixed UART interrupts
diff --git a/targets/arm/mikroe/core/include/hal_ll_core_defines.h b/targets/arm/mikroe/core/include/hal_ll_core_defines.h
@@ -430,7 +430,7 @@ extern "C"{
 
         #define NVIC_IPR ((NVIC_IPR_Type *) 0xE000E400UL)
 
-        #define hal_ll_core_irq(irq_val) (1 << irq_val)
+        #define hal_ll_core_irq(irq_val) (1 << (irq_val & HAL_LL_CORE_IRQ_MASK))
         #define hal_ll_core_pri(irq_pri) (irq_pri << 4)
 
         #define HAL_LL_CORE_IRQ_MASK 0x1F
diff --git a/targets/arm/mikroe/core/src/renesas/m4/hal_ll_core_port.c b/targets/arm/mikroe/core/src/renesas/m4/hal_ll_core_port.c
@@ -49,14 +49,14 @@ void hal_ll_core_port_nvic_enable_irq( uint8_t IRQn )
 {
     // Application vectors
     if (( IRQn <= 31 ) && ( IRQn >= 0 ))
-        set_reg_bits( HAL_LL_CORE_NVIC_ISER_0, ( ( hal_ll_core_irq( IRQn ) ) & HAL_LL_CORE_IRQ_MASK ) );
+        set_reg_bits( HAL_LL_CORE_NVIC_ISER_0, hal_ll_core_irq( IRQn ));
 }
 
 void hal_ll_core_port_nvic_disable_irq( uint8_t IRQn )
 {
     // Application vectors
     if (( IRQn <= 31 ) && ( IRQn >= 0 ))
-        set_reg_bits( HAL_LL_CORE_NVIC_ICER_0, ( ( hal_ll_core_irq( IRQn ) ) & HAL_LL_CORE_IRQ_MASK ) );
+        set_reg_bits( HAL_LL_CORE_NVIC_ICER_0, hal_ll_core_irq( IRQn ));
 }
 
 void hal_ll_core_port_nvic_set_priority_irq( uint8_t IRQn, uint8_t IRQn_priority )

Original file line number	Diff line number	Diff line change
`@@ -49,14 +49,14 @@ void hal_ll_core_port_nvic_enable_irq( uint8_t IRQn )`
`49`	`49`	`{`
`50`	`50`	`// Application vectors`
`51`	`51`	`if (( IRQn <= 31 ) && ( IRQn >= 0 ))`
`52`		`- set_reg_bits( HAL_LL_CORE_NVIC_ISER_0, ( ( hal_ll_core_irq( IRQn ) ) & HAL_LL_CORE_IRQ_MASK ) );`
	`52`	`+ set_reg_bits( HAL_LL_CORE_NVIC_ISER_0, hal_ll_core_irq( IRQn ));`
`53`	`53`	`}`
`54`	`54`
`55`	`55`	`void hal_ll_core_port_nvic_disable_irq( uint8_t IRQn )`
`56`	`56`	`{`
`57`	`57`	`// Application vectors`
`58`	`58`	`if (( IRQn <= 31 ) && ( IRQn >= 0 ))`
`59`		`- set_reg_bits( HAL_LL_CORE_NVIC_ICER_0, ( ( hal_ll_core_irq( IRQn ) ) & HAL_LL_CORE_IRQ_MASK ) );`
	`59`	`+ set_reg_bits( HAL_LL_CORE_NVIC_ICER_0, hal_ll_core_irq( IRQn ));`
`60`	`60`	`}`
`61`	`61`
`62`	`62`	`void hal_ll_core_port_nvic_set_priority_irq( uint8_t IRQn, uint8_t IRQn_priority )`