diff --git a/bsp/board/include/boards/clicker_ra4m1/board.h b/bsp/board/include/boards/clicker_ra4m1/board.h index e078ea5b28..6720f0c4ce 100644 --- a/bsp/board/include/boards/clicker_ra4m1/board.h +++ b/bsp/board/include/boards/clicker_ra4m1/board.h @@ -49,10 +49,39 @@ extern "C" { #endif +// Hardware revision number +#define BOARD_REV_MAJOR (1) +#define BOARD_REV_MINOR (01) + #define BOARD_NAME "RA4M1 Clicker" -// Mapping -// Only Bare Metal support is available at the moment +#include "mikrobus.h" + +/// Mapping +#define MIKROBUS_1 1 +#define MIKROBUS_1_AN GPIO_P000 +#define MIKROBUS_1_RST GPIO_P407 +#define MIKROBUS_1_CS GPIO_P103 +#define MIKROBUS_1_SCK GPIO_P102 +#define MIKROBUS_1_MISO GPIO_P100 +#define MIKROBUS_1_MOSI GPIO_P101 +#define MIKROBUS_1_PWM GPIO_P107 +#define MIKROBUS_1_INT GPIO_P302 +#define MIKROBUS_1_RX GPIO_P410 +#define MIKROBUS_1_TX GPIO_P411 +#define MIKROBUS_1_SCL GPIO_P205 +#define MIKROBUS_1_SDA GPIO_P206 + +// LEDs +#define LED_1 GPIO_P409 +#define LED_2 GPIO_P408 + +// Buttons +#define BUTTON_1 GPIO_P304 +#define BUTTON_2 GPIO_P301 + +#define USB_UART_TX HAL_PIN_NC +#define USB_UART_RX HAL_PIN_NC #ifdef __cplusplus } diff --git a/changelog/v2.15.0/changelog.md b/changelog/v2.15.0/changelog.md index d8d79afaed..898d90c617 100644 --- a/changelog/v2.15.0/changelog.md +++ b/changelog/v2.15.0/changelog.md @@ -16,12 +16,34 @@ - [`v2.15.0`](#v2150) - [Changes](#changes) - - [New Features](#new-features) + - [RENESAS](#renesas) - [Fixes](#fixes) - [mikroSDK](#mikrosdk) - [NEW HARDWARE](#new-hardware) -### New Features +### RENESAS + +**RA4M1 MCUs supported!** + +| MCU | +| :------------: | +| R7FA4M1AB3CFP | +| R7FA4M1AB2CLJ | +| R7FA4M1AB3CFM | +| R7FA4M1AB3CNB | +| R7FA4M1AB3CFL | +| R7FA4M1AB3CNE | +| R7FA4M1AB3CNF | + +**Supported modules:** + ++ ADC (Full module support) ++ SPI (Full module support) ++ UART (Full module support) ++ I2C (Full module support) ++ PWM (Full module support) ++ GPIO (Full module support) ++ 1-Wire (Full module support) ### Fixes diff --git a/cmake/utils.cmake b/cmake/utils.cmake index a44c579aea..5611427fb5 100644 --- a/cmake/utils.cmake +++ b/cmake/utils.cmake @@ -175,6 +175,8 @@ function(find_chip_architecture _chip_architecture) set(${_chip_architecture} "arm" PARENT_SCOPE) elseif(${MCU_NAME} MATCHES "^(AT)?SAM.*") set(${_chip_architecture} "arm" PARENT_SCOPE) + elseif(${MCU_NAME} MATCHES "^R7.*") + set(${_chip_architecture} "arm" PARENT_SCOPE) else() set(${_chip_architecture} "UNSUPPORTED_CHIP_SELECTED_FOR_FOLLOWING_IMPLEMENTATION" PARENT_SCOPE) endif() diff --git a/hal/interface/CMakeLists.txt b/hal/interface/CMakeLists.txt index 6359a32a8d..3489cb9932 100644 --- a/hal/interface/CMakeLists.txt +++ b/hal/interface/CMakeLists.txt @@ -25,6 +25,8 @@ elseif(${MCU_NAME} MATCHES "(^MK(.+)$)") set(vendor_id "nxp") elseif(${MCU_NAME} MATCHES "(^TM4C1(.+)$)") set(vendor_id "tiva") +elseif(${MCU_NAME} MATCHES "(^R7(.+)$)") + set(vendor_id "renesas") elseif(${MCU_NAME} MATCHES "(^PIC32(.+)$)") set(vendor_id "pic32") elseif(${MCU_NAME} MATCHES "(^PIC18(.+)$)") diff --git a/platform/ring/lib/src/ring.c b/platform/ring/lib/src/ring.c index b145eed239..adb3089d6f 100644 --- a/platform/ring/lib/src/ring.c +++ b/platform/ring/lib/src/ring.c @@ -70,7 +70,12 @@ bool ring_buf8_push( ring_buf8_t *ring, uint8_t data_ ) uint8_t ring_buf8_pop( ring_buf8_t *ring ) { uint8_t result; + + // TODO + // GCC & Clang compiler files for Renesas are not included into the project. + #if ( vendor != renesas ) assert( ring->size > 0 ); + #endif result = ring->buffer[ ring->tail ]; ring->tail = ( ring->tail + 1 ) % ring->capacity; diff --git a/targets/arm/mikroe/CMakeLists.txt b/targets/arm/mikroe/CMakeLists.txt index 904a304b76..49e9ea0197 100644 --- a/targets/arm/mikroe/CMakeLists.txt +++ b/targets/arm/mikroe/CMakeLists.txt @@ -6,6 +6,8 @@ elseif(${MCU_NAME} MATCHES "(^MK(.+)$)") elseif(${MCU_NAME} MATCHES "(^TM4C1(.+)$)") ## TIVA has only the 71 MCUs already implemented set(vendor_id "tiva") +elseif(${MCU_NAME} MATCHES "(^R7(.+)$)") + set(vendor_id "renesas") elseif(${MCU_NAME} MATCHES "(^(AT)?SAM(.+)$)") set(vendor_id "sam") else() diff --git a/targets/arm/mikroe/common/CMakeLists.txt b/targets/arm/mikroe/common/CMakeLists.txt index 810529ad29..c65778c1bc 100644 --- a/targets/arm/mikroe/common/CMakeLists.txt +++ b/targets/arm/mikroe/common/CMakeLists.txt @@ -41,6 +41,9 @@ elseif(${MCU_NAME} MATCHES "(^ATSAM(.+)$)") elseif(${MCU_NAME} MATCHES "(^TM4C1(.+)$)") set(architecture_macro "TIVA") set(architecture "TIVA") +elseif(${MCU_NAME} MATCHES "(^R7(.+)$)") + set(architecture_macro "RENESAS") + set(architecture "RENESAS") endif() set(header_files "") diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB2CLJ/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB2CLJ/mcu_definitions.h new file mode 100644 index 0000000000..d88846319b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB2CLJ/mcu_definitions.h @@ -0,0 +1,339 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#include "mcu_reg_addresses.h" + +//ADC +#define ADC0_P000_AN000 +#define ADC0_P001_AN001 +#define ADC0_P002_AN002 +#define ADC0_P003_AN003 +#define ADC0_P004_AN004 +#define ADC0_P005_AN011 +#define ADC0_P006_AN012 +#define ADC0_P007_AN013 +#define ADC0_P008_AN014 +#define ADC0_P010_AN005 +#define ADC0_P011_AN006 +#define ADC0_P012_AN007 +#define ADC0_P013_AN008 +#define ADC0_P014_AN009 +#define ADC0_P015_AN010 +#define ADC0_P100_AN022 +#define ADC0_P101_AN021 +#define ADC0_P102_AN020 +#define ADC0_P103_AN019 +#define ADC0_P500_AN016 +#define ADC0_P501_AN017 +#define ADC0_P502_AN018 +#define ADC0_P503_AN023 +#define ADC0_P504_AN024 +#define ADC0_P505_AN025 + +#define ADC_MODULE_0 1 + +#define ADC_MODULE_COUNT 1 +//EOF ADC + +//I2C +#define I2C0_SCL_P204_AF7 +#define I2C0_SCL_P400_AF7 +#define I2C0_SCL_P408_AF7 +#define I2C0_SDA_P401_AF7 +#define I2C0_SDA_P407_AF7 +#define I2C1_SCL_P100_AF7 +#define I2C1_SCL_P205_AF7 +#define I2C1_SDA_P101_AF7 +#define I2C1_SDA_P206_AF7 + +#define I2C_MODULE_0 1 +#define I2C_MODULE_1 2 + +#define I2C_MODULE_COUNT 2 +//EOF I2C + +//UART +#define UART0_RX_P100_AF4 +#define UART0_RX_P104_AF4 +#define UART0_RX_P206_AF4 +#define UART0_RX_P410_AF4 +#define UART0_TX_P101_AF4 +#define UART0_TX_P205_AF4 +#define UART0_TX_P411_AF4 +#define UART1_RX_P212_AF5 +#define UART1_RX_P402_AF5 +#define UART1_RX_P502_AF5 +#define UART1_RX_P708_AF5 +#define UART1_TX_P213_AF5 +#define UART1_TX_P401_AF5 +#define UART1_TX_P501_AF5 +#define UART2_RX_P301_AF4 +#define UART2_TX_P102_AF4 +#define UART2_TX_P112_AF4 +#define UART2_TX_P302_AF4 +#define UART9_RX_P110_AF5 +#define UART9_RX_P202_AF5 +#define UART9_RX_P408_AF5 +#define UART9_RX_P601_AF5 +#define UART9_TX_P109_AF5 +#define UART9_TX_P203_AF5 +#define UART9_TX_P409_AF5 +#define UART9_TX_P602_AF5 + +#define UART_MODULE_0 1 +#define UART_MODULE_1 2 +#define UART_MODULE_2 3 +#define UART_MODULE_9 10 + +#define UART_MODULE_COUNT 4 +//EOF UART + +//SPI +#define SPI0_MISO_P100_AF6 +#define SPI0_MISO_P410_AF6 +#define SPI0_MOSI_P101_AF6 +#define SPI0_MOSI_P411_AF6 +#define SPI0_SCK_P102_AF6 +#define SPI0_SCK_P412_AF6 +#define SPI1_MISO_P110_AF6 +#define SPI1_MISO_P202_AF6 +#define SPI1_MOSI_P109_AF6 +#define SPI1_MOSI_P203_AF6 +#define SPI1_SCK_P111_AF6 +#define SPI1_SCK_P204_AF6 + +#define SPI_MODULE_0 1 +#define SPI_MODULE_1 2 + +#define SPI_MODULE_COUNT 2 +//EOF SPI + +//TIM +#define TIM0_P106_CHB_AF3 +#define TIM0_P107_CHA_AF3 +#define TIM0_P108_CHB_AF3 +#define TIM0_P212_CHB_AF3 +#define TIM0_P213_CHA_AF3 +#define TIM0_P300_CHA_AF3 +#define TIM0_P414_CHB_AF3 +#define TIM0_P415_CHA_AF3 +#define TIM1_P104_CHB_AF3 +#define TIM1_P105_CHA_AF3 +#define TIM1_P109_CHA_AF3 +#define TIM1_P110_CHB_AF3 +#define TIM1_P405_CHA_AF3 +#define TIM1_P406_CHB_AF3 +#define TIM2_P102_CHB_AF3 +#define TIM2_P103_CHA_AF3 +#define TIM2_P113_CHA_AF3 +#define TIM2_P114_CHB_AF3 +#define TIM2_P500_CHA_AF3 +#define TIM2_P501_CHB_AF3 +#define TIM3_P111_CHA_AF3 +#define TIM3_P112_CHB_AF3 +#define TIM3_P403_CHA_AF3 +#define TIM3_P404_CHB_AF3 +#define TIM3_P502_CHB_AF3 +#define TIM4_P115_CHA_AF3 +#define TIM4_P204_CHB_AF3 +#define TIM4_P205_CHA_AF3 +#define TIM4_P301_CHB_AF3 +#define TIM4_P302_CHA_AF3 +#define TIM4_P608_CHB_AF3 +#define TIM5_P100_CHB_AF3 +#define TIM5_P101_CHA_AF3 +#define TIM5_P202_CHB_AF3 +#define TIM5_P203_CHA_AF3 +#define TIM5_P408_CHB_AF3 +#define TIM5_P409_CHA_AF3 +#define TIM5_P609_CHA_AF3 +#define TIM5_P610_CHB_AF3 +#define TIM6_P400_CHA_AF3 +#define TIM6_P401_CHB_AF3 +#define TIM6_P410_CHB_AF3 +#define TIM6_P411_CHA_AF3 +#define TIM6_P600_CHB_AF3 +#define TIM6_P601_CHA_AF3 +#define TIM7_P303_CHB_AF3 +#define TIM7_P304_CHA_AF3 +#define TIM7_P602_CHB_AF3 +#define TIM7_P603_CHA_AF3 + +#define TIM_MODULE_0 1 +#define TIM_MODULE_1 2 +#define TIM_MODULE_2 3 +#define TIM_MODULE_3 4 +#define TIM_MODULE_4 5 +#define TIM_MODULE_5 6 +#define TIM_MODULE_6 7 +#define TIM_MODULE_7 8 + +#define TIM_MODULE_COUNT 8 +//EOF TIM + +//GPIO +#define __P000_CN +#define __P001_CN +#define __P002_CN +#define __P003_CN +#define __P004_CN +#define __P005_CN +#define __P006_CN +#define __P007_CN +#define __P008_CN +#define __P010_CN +#define __P011_CN +#define __P012_CN +#define __P013_CN +#define __P014_CN +#define __P015_CN +#define __P100_CN +#define __P101_CN +#define __P102_CN +#define __P103_CN +#define __P104_CN +#define __P105_CN +#define __P106_CN +#define __P107_CN +#define __P108_CN +#define __P109_CN +#define __P110_CN +#define __P111_CN +#define __P112_CN +#define __P113_CN +#define __P114_CN +#define __P115_CN +#define __P200_CN +#define __P201_CN +#define __P202_CN +#define __P203_CN +#define __P204_CN +#define __P205_CN +#define __P206_CN +#define __P212_CN +#define __P213_CN +#define __P214_CN +#define __P215_CN +#define __P300_CN +#define __P301_CN +#define __P302_CN +#define __P303_CN +#define __P304_CN +#define __P305_CN +#define __P306_CN +#define __P307_CN +#define __P400_CN +#define __P401_CN +#define __P402_CN +#define __P403_CN +#define __P404_CN +#define __P405_CN +#define __P406_CN +#define __P407_CN +#define __P408_CN +#define __P409_CN +#define __P410_CN +#define __P411_CN +#define __P412_CN +#define __P413_CN +#define __P414_CN +#define __P415_CN +#define __P500_CN +#define __P501_CN +#define __P502_CN +#define __P503_CN +#define __P504_CN +#define __P505_CN +#define __P600_CN +#define __P601_CN +#define __P602_CN +#define __P603_CN +#define __P608_CN +#define __P609_CN +#define __P610_CN +#define __P708_CN +#define __P808_CN +#define __P809_CN +#define __P914_CN +#define __P915_CN + +#define __PORT_0_CN +#define __PORT_1_CN +#define __PORT_2_CN +#define __PORT_3_CN +#define __PORT_4_CN +#define __PORT_5_CN +#define __PORT_6_CN +#define __PORT_7_CN +#define __PORT_8_CN +#define __PORT_9_CN + +#define PORT_SIZE (16) +#define PORT_COUNT (10) +//EOF GPIO + +//IVT_TABLE +#define UART0_TXI_NVIC 0 +#define UART0_TXI_EVENT 0x99 +#define UART0_RXI_NVIC 1 +#define UART0_RXI_EVENT 0x98 +#define UART1_TXI_NVIC 2 +#define UART1_TXI_EVENT 0x9F +#define UART1_RXI_NVIC 3 +#define UART1_RXI_EVENT 0x9E +#define UART2_TXI_NVIC 4 +#define UART2_TXI_EVENT 0xA4 +#define UART2_RXI_NVIC 5 +#define UART2_RXI_EVENT 0xA3 +#define UART9_TXI_NVIC 18 +#define UART9_TXI_EVENT 0xA9 +#define UART9_RXI_NVIC 19 +#define UART9_RXI_EVENT 0xA8 +//EOF IVT_TABLE + + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFL/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFL/mcu_definitions.h new file mode 100644 index 0000000000..197ec8a89f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFL/mcu_definitions.h @@ -0,0 +1,225 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#include "mcu_reg_addresses.h" + +//ADC +#define ADC0_P000_AN000 +#define ADC0_P001_AN001 +#define ADC0_P002_AN002 +#define ADC0_P010_AN005 +#define ADC0_P011_AN006 +#define ADC0_P012_AN007 +#define ADC0_P013_AN008 +#define ADC0_P014_AN009 +#define ADC0_P015_AN010 +#define ADC0_P100_AN022 +#define ADC0_P101_AN021 +#define ADC0_P102_AN020 +#define ADC0_P103_AN019 +#define ADC0_P500_AN016 + +#define ADC_MODULE_0 1 + +#define ADC_MODULE_COUNT 1 +//EOF ADC + +//I2C +#define I2C0_SCL_P400_AF7 +#define I2C0_SCL_P408_AF7 +#define I2C0_SDA_P407_AF7 +#define I2C1_SCL_P100_AF7 +#define I2C1_SDA_P101_AF7 +#define I2C1_SDA_P206_AF7 + +#define I2C_MODULE_0 1 +#define I2C_MODULE_1 2 + +#define I2C_MODULE_COUNT 2 +//EOF I2C + +//UART +#define UART0_RX_P100_AF4 +#define UART0_RX_P104_AF4 +#define UART0_RX_P206_AF4 +#define UART0_TX_P101_AF4 +#define UART1_RX_P212_AF5 +#define UART1_TX_P213_AF5 +#define UART2_RX_P301_AF4 +#define UART2_TX_P102_AF4 +#define UART2_TX_P112_AF4 +#define UART2_TX_P302_AF4 +#define UART9_RX_P110_AF5 +#define UART9_RX_P408_AF5 +#define UART9_TX_P109_AF5 +#define UART9_TX_P409_AF5 + +#define UART_MODULE_0 1 +#define UART_MODULE_1 2 +#define UART_MODULE_2 3 +#define UART_MODULE_9 10 + +#define UART_MODULE_COUNT 4 +//EOF UART + +//SPI +#define SPI0_MISO_P100_AF6 +#define SPI0_MOSI_P101_AF6 +#define SPI0_SCK_P102_AF6 +#define SPI1_MISO_P110_AF6 +#define SPI1_MOSI_P109_AF6 +#define SPI1_SCK_P111_AF6 + +#define SPI_MODULE_0 1 +#define SPI_MODULE_1 2 + +#define SPI_MODULE_COUNT 2 +//EOF SPI + +//TIM +#define TIM0_P108_CHB_AF3 +#define TIM0_P212_CHB_AF3 +#define TIM0_P213_CHA_AF3 +#define TIM0_P300_CHA_AF3 +#define TIM1_P104_CHB_AF3 +#define TIM1_P109_CHA_AF3 +#define TIM1_P110_CHB_AF3 +#define TIM2_P102_CHB_AF3 +#define TIM2_P103_CHA_AF3 +#define TIM2_P500_CHA_AF3 +#define TIM3_P111_CHA_AF3 +#define TIM3_P112_CHB_AF3 +#define TIM4_P301_CHB_AF3 +#define TIM4_P302_CHA_AF3 +#define TIM5_P100_CHB_AF3 +#define TIM5_P101_CHA_AF3 +#define TIM5_P408_CHB_AF3 +#define TIM5_P409_CHA_AF3 +#define TIM6_P400_CHA_AF3 + +#define TIM_MODULE_0 1 +#define TIM_MODULE_1 2 +#define TIM_MODULE_2 3 +#define TIM_MODULE_3 4 +#define TIM_MODULE_4 5 +#define TIM_MODULE_5 6 +#define TIM_MODULE_6 7 + +#define TIM_MODULE_COUNT 7 +//EOF TIM + +//GPIO +#define __P000_CN +#define __P001_CN +#define __P002_CN +#define __P010_CN +#define __P011_CN +#define __P012_CN +#define __P013_CN +#define __P014_CN +#define __P015_CN +#define __P100_CN +#define __P101_CN +#define __P102_CN +#define __P103_CN +#define __P104_CN +#define __P108_CN +#define __P109_CN +#define __P110_CN +#define __P111_CN +#define __P112_CN +#define __P200_CN +#define __P201_CN +#define __P206_CN +#define __P212_CN +#define __P213_CN +#define __P214_CN +#define __P215_CN +#define __P300_CN +#define __P301_CN +#define __P302_CN +#define __P400_CN +#define __P407_CN +#define __P408_CN +#define __P409_CN +#define __P500_CN +#define __P914_CN +#define __P915_CN + +#define __PORT_0_CN +#define __PORT_1_CN +#define __PORT_2_CN +#define __PORT_3_CN +#define __PORT_4_CN +#define __PORT_5_CN +#define __PORT_9_CN + +#define PORT_SIZE (16) +#define PORT_COUNT (7) +//EOF GPIO + +//IVT_TABLE +#define UART0_TXI_NVIC 0 +#define UART0_TXI_EVENT 0x99 +#define UART0_RXI_NVIC 1 +#define UART0_RXI_EVENT 0x98 +#define UART1_TXI_NVIC 2 +#define UART1_TXI_EVENT 0x9F +#define UART1_RXI_NVIC 3 +#define UART1_RXI_EVENT 0x9E +#define UART2_TXI_NVIC 4 +#define UART2_TXI_EVENT 0xA4 +#define UART2_RXI_NVIC 5 +#define UART2_RXI_EVENT 0xA3 +#define UART9_TXI_NVIC 18 +#define UART9_TXI_EVENT 0xA9 +#define UART9_RXI_NVIC 19 +#define UART9_RXI_EVENT 0xA8 +//EOF IVT_TABLE + + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h new file mode 100644 index 0000000000..d116e5cab2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -0,0 +1,272 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#include "mcu_reg_addresses.h" + +//ADC +#define ADC0_P000_AN000 +#define ADC0_P001_AN001 +#define ADC0_P002_AN002 +#define ADC0_P003_AN003 +#define ADC0_P004_AN004 +#define ADC0_P010_AN005 +#define ADC0_P011_AN006 +#define ADC0_P012_AN007 +#define ADC0_P013_AN008 +#define ADC0_P014_AN009 +#define ADC0_P015_AN010 +#define ADC0_P100_AN022 +#define ADC0_P101_AN021 +#define ADC0_P102_AN020 +#define ADC0_P103_AN019 +#define ADC0_P500_AN016 +#define ADC0_P501_AN017 +#define ADC0_P502_AN018 + +#define ADC_MODULE_0 1 + +#define ADC_MODULE_COUNT 1 +//EOF ADC + +//I2C +#define I2C0_SCL_P204_AF7 +#define I2C0_SCL_P400_AF7 +#define I2C0_SCL_P408_AF7 +#define I2C0_SDA_P401_AF7 +#define I2C0_SDA_P407_AF7 +#define I2C1_SCL_P100_AF7 +#define I2C1_SCL_P205_AF7 +#define I2C1_SDA_P101_AF7 +#define I2C1_SDA_P206_AF7 + +#define I2C_MODULE_0 1 +#define I2C_MODULE_1 2 + +#define I2C_MODULE_COUNT 2 +//EOF I2C + +//UART +#define UART0_RX_P100_AF4 +#define UART0_RX_P104_AF4 +#define UART0_RX_P206_AF4 +#define UART0_RX_P410_AF4 +#define UART0_TX_P101_AF4 +#define UART0_TX_P205_AF4 +#define UART0_TX_P411_AF4 +#define UART1_RX_P212_AF5 +#define UART1_RX_P402_AF5 +#define UART1_RX_P502_AF5 +#define UART1_TX_P213_AF5 +#define UART1_TX_P401_AF5 +#define UART1_TX_P501_AF5 +#define UART2_RX_P301_AF4 +#define UART2_TX_P102_AF4 +#define UART2_TX_P112_AF4 +#define UART2_TX_P302_AF4 +#define UART9_RX_P110_AF5 +#define UART9_RX_P408_AF5 +#define UART9_TX_P109_AF5 +#define UART9_TX_P409_AF5 + +#define UART_MODULE_0 1 +#define UART_MODULE_1 2 +#define UART_MODULE_2 3 +#define UART_MODULE_9 10 + +#define UART_MODULE_COUNT 4 +//EOF UART + +//SPI +#define SPI0_MISO_P100_AF6 +#define SPI0_MISO_P410_AF6 +#define SPI0_MOSI_P101_AF6 +#define SPI0_MOSI_P411_AF6 +#define SPI0_SCK_P102_AF6 +#define SPI1_MISO_P110_AF6 +#define SPI1_MOSI_P109_AF6 +#define SPI1_SCK_P111_AF6 +#define SPI1_SCK_P204_AF6 + +#define SPI_MODULE_0 1 +#define SPI_MODULE_1 2 + +#define SPI_MODULE_COUNT 2 +//EOF SPI + +//TIM +#define TIM0_P106_CHB_AF3 +#define TIM0_P107_CHA_AF3 +#define TIM0_P108_CHB_AF3 +#define TIM0_P212_CHB_AF3 +#define TIM0_P213_CHA_AF3 +#define TIM0_P300_CHA_AF3 +#define TIM1_P104_CHB_AF3 +#define TIM1_P105_CHA_AF3 +#define TIM1_P109_CHA_AF3 +#define TIM1_P110_CHB_AF3 +#define TIM2_P102_CHB_AF3 +#define TIM2_P103_CHA_AF3 +#define TIM2_P113_CHA_AF3 +#define TIM2_P500_CHA_AF3 +#define TIM2_P501_CHB_AF3 +#define TIM3_P111_CHA_AF3 +#define TIM3_P112_CHB_AF3 +#define TIM3_P502_CHB_AF3 +#define TIM4_P204_CHB_AF3 +#define TIM4_P205_CHA_AF3 +#define TIM4_P301_CHB_AF3 +#define TIM4_P302_CHA_AF3 +#define TIM5_P100_CHB_AF3 +#define TIM5_P101_CHA_AF3 +#define TIM5_P408_CHB_AF3 +#define TIM5_P409_CHA_AF3 +#define TIM6_P400_CHA_AF3 +#define TIM6_P401_CHB_AF3 +#define TIM6_P410_CHB_AF3 +#define TIM6_P411_CHA_AF3 +#define TIM7_P303_CHB_AF3 +#define TIM7_P304_CHA_AF3 + +#define TIM_MODULE_0 1 +#define TIM_MODULE_1 2 +#define TIM_MODULE_2 3 +#define TIM_MODULE_3 4 +#define TIM_MODULE_4 5 +#define TIM_MODULE_5 6 +#define TIM_MODULE_6 7 +#define TIM_MODULE_7 8 + +#define TIM_MODULE_COUNT 8 +//EOF TIM + +//GPIO +#define __P000_CN +#define __P001_CN +#define __P002_CN +#define __P003_CN +#define __P004_CN +#define __P010_CN +#define __P011_CN +#define __P012_CN +#define __P013_CN +#define __P014_CN +#define __P015_CN +#define __P100_CN +#define __P101_CN +#define __P102_CN +#define __P103_CN +#define __P104_CN +#define __P105_CN +#define __P106_CN +#define __P107_CN +#define __P108_CN +#define __P109_CN +#define __P110_CN +#define __P111_CN +#define __P112_CN +#define __P113_CN +#define __P200_CN +#define __P201_CN +#define __P204_CN +#define __P205_CN +#define __P206_CN +#define __P212_CN +#define __P213_CN +#define __P214_CN +#define __P215_CN +#define __P300_CN +#define __P301_CN +#define __P302_CN +#define __P303_CN +#define __P304_CN +#define __P400_CN +#define __P401_CN +#define __P402_CN +#define __P407_CN +#define __P408_CN +#define __P409_CN +#define __P410_CN +#define __P411_CN +#define __P500_CN +#define __P501_CN +#define __P502_CN +#define __P914_CN +#define __P915_CN + +#define __PORT_0_CN +#define __PORT_1_CN +#define __PORT_2_CN +#define __PORT_3_CN +#define __PORT_4_CN +#define __PORT_5_CN +#define __PORT_9_CN + +#define PORT_SIZE (16) +#define PORT_COUNT (7) +//EOF GPIO + +//IVT_TABLE +#define UART0_TXI_NVIC 0 +#define UART0_TXI_EVENT 0x99 +#define UART0_RXI_NVIC 1 +#define UART0_RXI_EVENT 0x98 +#define UART1_TXI_NVIC 2 +#define UART1_TXI_EVENT 0x9F +#define UART1_RXI_NVIC 3 +#define UART1_RXI_EVENT 0x9E +#define UART2_TXI_NVIC 4 +#define UART2_TXI_EVENT 0xA4 +#define UART2_RXI_NVIC 5 +#define UART2_RXI_EVENT 0xA3 +#define UART9_TXI_NVIC 18 +#define UART9_TXI_EVENT 0xA9 +#define UART9_RXI_NVIC 19 +#define UART9_RXI_EVENT 0xA8 +//EOF IVT_TABLE + + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFP/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFP/mcu_definitions.h new file mode 100644 index 0000000000..d88846319b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFP/mcu_definitions.h @@ -0,0 +1,339 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#include "mcu_reg_addresses.h" + +//ADC +#define ADC0_P000_AN000 +#define ADC0_P001_AN001 +#define ADC0_P002_AN002 +#define ADC0_P003_AN003 +#define ADC0_P004_AN004 +#define ADC0_P005_AN011 +#define ADC0_P006_AN012 +#define ADC0_P007_AN013 +#define ADC0_P008_AN014 +#define ADC0_P010_AN005 +#define ADC0_P011_AN006 +#define ADC0_P012_AN007 +#define ADC0_P013_AN008 +#define ADC0_P014_AN009 +#define ADC0_P015_AN010 +#define ADC0_P100_AN022 +#define ADC0_P101_AN021 +#define ADC0_P102_AN020 +#define ADC0_P103_AN019 +#define ADC0_P500_AN016 +#define ADC0_P501_AN017 +#define ADC0_P502_AN018 +#define ADC0_P503_AN023 +#define ADC0_P504_AN024 +#define ADC0_P505_AN025 + +#define ADC_MODULE_0 1 + +#define ADC_MODULE_COUNT 1 +//EOF ADC + +//I2C +#define I2C0_SCL_P204_AF7 +#define I2C0_SCL_P400_AF7 +#define I2C0_SCL_P408_AF7 +#define I2C0_SDA_P401_AF7 +#define I2C0_SDA_P407_AF7 +#define I2C1_SCL_P100_AF7 +#define I2C1_SCL_P205_AF7 +#define I2C1_SDA_P101_AF7 +#define I2C1_SDA_P206_AF7 + +#define I2C_MODULE_0 1 +#define I2C_MODULE_1 2 + +#define I2C_MODULE_COUNT 2 +//EOF I2C + +//UART +#define UART0_RX_P100_AF4 +#define UART0_RX_P104_AF4 +#define UART0_RX_P206_AF4 +#define UART0_RX_P410_AF4 +#define UART0_TX_P101_AF4 +#define UART0_TX_P205_AF4 +#define UART0_TX_P411_AF4 +#define UART1_RX_P212_AF5 +#define UART1_RX_P402_AF5 +#define UART1_RX_P502_AF5 +#define UART1_RX_P708_AF5 +#define UART1_TX_P213_AF5 +#define UART1_TX_P401_AF5 +#define UART1_TX_P501_AF5 +#define UART2_RX_P301_AF4 +#define UART2_TX_P102_AF4 +#define UART2_TX_P112_AF4 +#define UART2_TX_P302_AF4 +#define UART9_RX_P110_AF5 +#define UART9_RX_P202_AF5 +#define UART9_RX_P408_AF5 +#define UART9_RX_P601_AF5 +#define UART9_TX_P109_AF5 +#define UART9_TX_P203_AF5 +#define UART9_TX_P409_AF5 +#define UART9_TX_P602_AF5 + +#define UART_MODULE_0 1 +#define UART_MODULE_1 2 +#define UART_MODULE_2 3 +#define UART_MODULE_9 10 + +#define UART_MODULE_COUNT 4 +//EOF UART + +//SPI +#define SPI0_MISO_P100_AF6 +#define SPI0_MISO_P410_AF6 +#define SPI0_MOSI_P101_AF6 +#define SPI0_MOSI_P411_AF6 +#define SPI0_SCK_P102_AF6 +#define SPI0_SCK_P412_AF6 +#define SPI1_MISO_P110_AF6 +#define SPI1_MISO_P202_AF6 +#define SPI1_MOSI_P109_AF6 +#define SPI1_MOSI_P203_AF6 +#define SPI1_SCK_P111_AF6 +#define SPI1_SCK_P204_AF6 + +#define SPI_MODULE_0 1 +#define SPI_MODULE_1 2 + +#define SPI_MODULE_COUNT 2 +//EOF SPI + +//TIM +#define TIM0_P106_CHB_AF3 +#define TIM0_P107_CHA_AF3 +#define TIM0_P108_CHB_AF3 +#define TIM0_P212_CHB_AF3 +#define TIM0_P213_CHA_AF3 +#define TIM0_P300_CHA_AF3 +#define TIM0_P414_CHB_AF3 +#define TIM0_P415_CHA_AF3 +#define TIM1_P104_CHB_AF3 +#define TIM1_P105_CHA_AF3 +#define TIM1_P109_CHA_AF3 +#define TIM1_P110_CHB_AF3 +#define TIM1_P405_CHA_AF3 +#define TIM1_P406_CHB_AF3 +#define TIM2_P102_CHB_AF3 +#define TIM2_P103_CHA_AF3 +#define TIM2_P113_CHA_AF3 +#define TIM2_P114_CHB_AF3 +#define TIM2_P500_CHA_AF3 +#define TIM2_P501_CHB_AF3 +#define TIM3_P111_CHA_AF3 +#define TIM3_P112_CHB_AF3 +#define TIM3_P403_CHA_AF3 +#define TIM3_P404_CHB_AF3 +#define TIM3_P502_CHB_AF3 +#define TIM4_P115_CHA_AF3 +#define TIM4_P204_CHB_AF3 +#define TIM4_P205_CHA_AF3 +#define TIM4_P301_CHB_AF3 +#define TIM4_P302_CHA_AF3 +#define TIM4_P608_CHB_AF3 +#define TIM5_P100_CHB_AF3 +#define TIM5_P101_CHA_AF3 +#define TIM5_P202_CHB_AF3 +#define TIM5_P203_CHA_AF3 +#define TIM5_P408_CHB_AF3 +#define TIM5_P409_CHA_AF3 +#define TIM5_P609_CHA_AF3 +#define TIM5_P610_CHB_AF3 +#define TIM6_P400_CHA_AF3 +#define TIM6_P401_CHB_AF3 +#define TIM6_P410_CHB_AF3 +#define TIM6_P411_CHA_AF3 +#define TIM6_P600_CHB_AF3 +#define TIM6_P601_CHA_AF3 +#define TIM7_P303_CHB_AF3 +#define TIM7_P304_CHA_AF3 +#define TIM7_P602_CHB_AF3 +#define TIM7_P603_CHA_AF3 + +#define TIM_MODULE_0 1 +#define TIM_MODULE_1 2 +#define TIM_MODULE_2 3 +#define TIM_MODULE_3 4 +#define TIM_MODULE_4 5 +#define TIM_MODULE_5 6 +#define TIM_MODULE_6 7 +#define TIM_MODULE_7 8 + +#define TIM_MODULE_COUNT 8 +//EOF TIM + +//GPIO +#define __P000_CN +#define __P001_CN +#define __P002_CN +#define __P003_CN +#define __P004_CN +#define __P005_CN +#define __P006_CN +#define __P007_CN +#define __P008_CN +#define __P010_CN +#define __P011_CN +#define __P012_CN +#define __P013_CN +#define __P014_CN +#define __P015_CN +#define __P100_CN +#define __P101_CN +#define __P102_CN +#define __P103_CN +#define __P104_CN +#define __P105_CN +#define __P106_CN +#define __P107_CN +#define __P108_CN +#define __P109_CN +#define __P110_CN +#define __P111_CN +#define __P112_CN +#define __P113_CN +#define __P114_CN +#define __P115_CN +#define __P200_CN +#define __P201_CN +#define __P202_CN +#define __P203_CN +#define __P204_CN +#define __P205_CN +#define __P206_CN +#define __P212_CN +#define __P213_CN +#define __P214_CN +#define __P215_CN +#define __P300_CN +#define __P301_CN +#define __P302_CN +#define __P303_CN +#define __P304_CN +#define __P305_CN +#define __P306_CN +#define __P307_CN +#define __P400_CN +#define __P401_CN +#define __P402_CN +#define __P403_CN +#define __P404_CN +#define __P405_CN +#define __P406_CN +#define __P407_CN +#define __P408_CN +#define __P409_CN +#define __P410_CN +#define __P411_CN +#define __P412_CN +#define __P413_CN +#define __P414_CN +#define __P415_CN +#define __P500_CN +#define __P501_CN +#define __P502_CN +#define __P503_CN +#define __P504_CN +#define __P505_CN +#define __P600_CN +#define __P601_CN +#define __P602_CN +#define __P603_CN +#define __P608_CN +#define __P609_CN +#define __P610_CN +#define __P708_CN +#define __P808_CN +#define __P809_CN +#define __P914_CN +#define __P915_CN + +#define __PORT_0_CN +#define __PORT_1_CN +#define __PORT_2_CN +#define __PORT_3_CN +#define __PORT_4_CN +#define __PORT_5_CN +#define __PORT_6_CN +#define __PORT_7_CN +#define __PORT_8_CN +#define __PORT_9_CN + +#define PORT_SIZE (16) +#define PORT_COUNT (10) +//EOF GPIO + +//IVT_TABLE +#define UART0_TXI_NVIC 0 +#define UART0_TXI_EVENT 0x99 +#define UART0_RXI_NVIC 1 +#define UART0_RXI_EVENT 0x98 +#define UART1_TXI_NVIC 2 +#define UART1_TXI_EVENT 0x9F +#define UART1_RXI_NVIC 3 +#define UART1_RXI_EVENT 0x9E +#define UART2_TXI_NVIC 4 +#define UART2_TXI_EVENT 0xA4 +#define UART2_RXI_NVIC 5 +#define UART2_RXI_EVENT 0xA3 +#define UART9_TXI_NVIC 18 +#define UART9_TXI_EVENT 0xA9 +#define UART9_RXI_NVIC 19 +#define UART9_RXI_EVENT 0xA8 +//EOF IVT_TABLE + + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNB/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNB/mcu_definitions.h new file mode 100644 index 0000000000..d116e5cab2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNB/mcu_definitions.h @@ -0,0 +1,272 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#include "mcu_reg_addresses.h" + +//ADC +#define ADC0_P000_AN000 +#define ADC0_P001_AN001 +#define ADC0_P002_AN002 +#define ADC0_P003_AN003 +#define ADC0_P004_AN004 +#define ADC0_P010_AN005 +#define ADC0_P011_AN006 +#define ADC0_P012_AN007 +#define ADC0_P013_AN008 +#define ADC0_P014_AN009 +#define ADC0_P015_AN010 +#define ADC0_P100_AN022 +#define ADC0_P101_AN021 +#define ADC0_P102_AN020 +#define ADC0_P103_AN019 +#define ADC0_P500_AN016 +#define ADC0_P501_AN017 +#define ADC0_P502_AN018 + +#define ADC_MODULE_0 1 + +#define ADC_MODULE_COUNT 1 +//EOF ADC + +//I2C +#define I2C0_SCL_P204_AF7 +#define I2C0_SCL_P400_AF7 +#define I2C0_SCL_P408_AF7 +#define I2C0_SDA_P401_AF7 +#define I2C0_SDA_P407_AF7 +#define I2C1_SCL_P100_AF7 +#define I2C1_SCL_P205_AF7 +#define I2C1_SDA_P101_AF7 +#define I2C1_SDA_P206_AF7 + +#define I2C_MODULE_0 1 +#define I2C_MODULE_1 2 + +#define I2C_MODULE_COUNT 2 +//EOF I2C + +//UART +#define UART0_RX_P100_AF4 +#define UART0_RX_P104_AF4 +#define UART0_RX_P206_AF4 +#define UART0_RX_P410_AF4 +#define UART0_TX_P101_AF4 +#define UART0_TX_P205_AF4 +#define UART0_TX_P411_AF4 +#define UART1_RX_P212_AF5 +#define UART1_RX_P402_AF5 +#define UART1_RX_P502_AF5 +#define UART1_TX_P213_AF5 +#define UART1_TX_P401_AF5 +#define UART1_TX_P501_AF5 +#define UART2_RX_P301_AF4 +#define UART2_TX_P102_AF4 +#define UART2_TX_P112_AF4 +#define UART2_TX_P302_AF4 +#define UART9_RX_P110_AF5 +#define UART9_RX_P408_AF5 +#define UART9_TX_P109_AF5 +#define UART9_TX_P409_AF5 + +#define UART_MODULE_0 1 +#define UART_MODULE_1 2 +#define UART_MODULE_2 3 +#define UART_MODULE_9 10 + +#define UART_MODULE_COUNT 4 +//EOF UART + +//SPI +#define SPI0_MISO_P100_AF6 +#define SPI0_MISO_P410_AF6 +#define SPI0_MOSI_P101_AF6 +#define SPI0_MOSI_P411_AF6 +#define SPI0_SCK_P102_AF6 +#define SPI1_MISO_P110_AF6 +#define SPI1_MOSI_P109_AF6 +#define SPI1_SCK_P111_AF6 +#define SPI1_SCK_P204_AF6 + +#define SPI_MODULE_0 1 +#define SPI_MODULE_1 2 + +#define SPI_MODULE_COUNT 2 +//EOF SPI + +//TIM +#define TIM0_P106_CHB_AF3 +#define TIM0_P107_CHA_AF3 +#define TIM0_P108_CHB_AF3 +#define TIM0_P212_CHB_AF3 +#define TIM0_P213_CHA_AF3 +#define TIM0_P300_CHA_AF3 +#define TIM1_P104_CHB_AF3 +#define TIM1_P105_CHA_AF3 +#define TIM1_P109_CHA_AF3 +#define TIM1_P110_CHB_AF3 +#define TIM2_P102_CHB_AF3 +#define TIM2_P103_CHA_AF3 +#define TIM2_P113_CHA_AF3 +#define TIM2_P500_CHA_AF3 +#define TIM2_P501_CHB_AF3 +#define TIM3_P111_CHA_AF3 +#define TIM3_P112_CHB_AF3 +#define TIM3_P502_CHB_AF3 +#define TIM4_P204_CHB_AF3 +#define TIM4_P205_CHA_AF3 +#define TIM4_P301_CHB_AF3 +#define TIM4_P302_CHA_AF3 +#define TIM5_P100_CHB_AF3 +#define TIM5_P101_CHA_AF3 +#define TIM5_P408_CHB_AF3 +#define TIM5_P409_CHA_AF3 +#define TIM6_P400_CHA_AF3 +#define TIM6_P401_CHB_AF3 +#define TIM6_P410_CHB_AF3 +#define TIM6_P411_CHA_AF3 +#define TIM7_P303_CHB_AF3 +#define TIM7_P304_CHA_AF3 + +#define TIM_MODULE_0 1 +#define TIM_MODULE_1 2 +#define TIM_MODULE_2 3 +#define TIM_MODULE_3 4 +#define TIM_MODULE_4 5 +#define TIM_MODULE_5 6 +#define TIM_MODULE_6 7 +#define TIM_MODULE_7 8 + +#define TIM_MODULE_COUNT 8 +//EOF TIM + +//GPIO +#define __P000_CN +#define __P001_CN +#define __P002_CN +#define __P003_CN +#define __P004_CN +#define __P010_CN +#define __P011_CN +#define __P012_CN +#define __P013_CN +#define __P014_CN +#define __P015_CN +#define __P100_CN +#define __P101_CN +#define __P102_CN +#define __P103_CN +#define __P104_CN +#define __P105_CN +#define __P106_CN +#define __P107_CN +#define __P108_CN +#define __P109_CN +#define __P110_CN +#define __P111_CN +#define __P112_CN +#define __P113_CN +#define __P200_CN +#define __P201_CN +#define __P204_CN +#define __P205_CN +#define __P206_CN +#define __P212_CN +#define __P213_CN +#define __P214_CN +#define __P215_CN +#define __P300_CN +#define __P301_CN +#define __P302_CN +#define __P303_CN +#define __P304_CN +#define __P400_CN +#define __P401_CN +#define __P402_CN +#define __P407_CN +#define __P408_CN +#define __P409_CN +#define __P410_CN +#define __P411_CN +#define __P500_CN +#define __P501_CN +#define __P502_CN +#define __P914_CN +#define __P915_CN + +#define __PORT_0_CN +#define __PORT_1_CN +#define __PORT_2_CN +#define __PORT_3_CN +#define __PORT_4_CN +#define __PORT_5_CN +#define __PORT_9_CN + +#define PORT_SIZE (16) +#define PORT_COUNT (7) +//EOF GPIO + +//IVT_TABLE +#define UART0_TXI_NVIC 0 +#define UART0_TXI_EVENT 0x99 +#define UART0_RXI_NVIC 1 +#define UART0_RXI_EVENT 0x98 +#define UART1_TXI_NVIC 2 +#define UART1_TXI_EVENT 0x9F +#define UART1_RXI_NVIC 3 +#define UART1_RXI_EVENT 0x9E +#define UART2_TXI_NVIC 4 +#define UART2_TXI_EVENT 0xA4 +#define UART2_RXI_NVIC 5 +#define UART2_RXI_EVENT 0xA3 +#define UART9_TXI_NVIC 18 +#define UART9_TXI_EVENT 0xA9 +#define UART9_RXI_NVIC 19 +#define UART9_RXI_EVENT 0xA8 +//EOF IVT_TABLE + + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNE/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNE/mcu_definitions.h new file mode 100644 index 0000000000..197ec8a89f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNE/mcu_definitions.h @@ -0,0 +1,225 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#include "mcu_reg_addresses.h" + +//ADC +#define ADC0_P000_AN000 +#define ADC0_P001_AN001 +#define ADC0_P002_AN002 +#define ADC0_P010_AN005 +#define ADC0_P011_AN006 +#define ADC0_P012_AN007 +#define ADC0_P013_AN008 +#define ADC0_P014_AN009 +#define ADC0_P015_AN010 +#define ADC0_P100_AN022 +#define ADC0_P101_AN021 +#define ADC0_P102_AN020 +#define ADC0_P103_AN019 +#define ADC0_P500_AN016 + +#define ADC_MODULE_0 1 + +#define ADC_MODULE_COUNT 1 +//EOF ADC + +//I2C +#define I2C0_SCL_P400_AF7 +#define I2C0_SCL_P408_AF7 +#define I2C0_SDA_P407_AF7 +#define I2C1_SCL_P100_AF7 +#define I2C1_SDA_P101_AF7 +#define I2C1_SDA_P206_AF7 + +#define I2C_MODULE_0 1 +#define I2C_MODULE_1 2 + +#define I2C_MODULE_COUNT 2 +//EOF I2C + +//UART +#define UART0_RX_P100_AF4 +#define UART0_RX_P104_AF4 +#define UART0_RX_P206_AF4 +#define UART0_TX_P101_AF4 +#define UART1_RX_P212_AF5 +#define UART1_TX_P213_AF5 +#define UART2_RX_P301_AF4 +#define UART2_TX_P102_AF4 +#define UART2_TX_P112_AF4 +#define UART2_TX_P302_AF4 +#define UART9_RX_P110_AF5 +#define UART9_RX_P408_AF5 +#define UART9_TX_P109_AF5 +#define UART9_TX_P409_AF5 + +#define UART_MODULE_0 1 +#define UART_MODULE_1 2 +#define UART_MODULE_2 3 +#define UART_MODULE_9 10 + +#define UART_MODULE_COUNT 4 +//EOF UART + +//SPI +#define SPI0_MISO_P100_AF6 +#define SPI0_MOSI_P101_AF6 +#define SPI0_SCK_P102_AF6 +#define SPI1_MISO_P110_AF6 +#define SPI1_MOSI_P109_AF6 +#define SPI1_SCK_P111_AF6 + +#define SPI_MODULE_0 1 +#define SPI_MODULE_1 2 + +#define SPI_MODULE_COUNT 2 +//EOF SPI + +//TIM +#define TIM0_P108_CHB_AF3 +#define TIM0_P212_CHB_AF3 +#define TIM0_P213_CHA_AF3 +#define TIM0_P300_CHA_AF3 +#define TIM1_P104_CHB_AF3 +#define TIM1_P109_CHA_AF3 +#define TIM1_P110_CHB_AF3 +#define TIM2_P102_CHB_AF3 +#define TIM2_P103_CHA_AF3 +#define TIM2_P500_CHA_AF3 +#define TIM3_P111_CHA_AF3 +#define TIM3_P112_CHB_AF3 +#define TIM4_P301_CHB_AF3 +#define TIM4_P302_CHA_AF3 +#define TIM5_P100_CHB_AF3 +#define TIM5_P101_CHA_AF3 +#define TIM5_P408_CHB_AF3 +#define TIM5_P409_CHA_AF3 +#define TIM6_P400_CHA_AF3 + +#define TIM_MODULE_0 1 +#define TIM_MODULE_1 2 +#define TIM_MODULE_2 3 +#define TIM_MODULE_3 4 +#define TIM_MODULE_4 5 +#define TIM_MODULE_5 6 +#define TIM_MODULE_6 7 + +#define TIM_MODULE_COUNT 7 +//EOF TIM + +//GPIO +#define __P000_CN +#define __P001_CN +#define __P002_CN +#define __P010_CN +#define __P011_CN +#define __P012_CN +#define __P013_CN +#define __P014_CN +#define __P015_CN +#define __P100_CN +#define __P101_CN +#define __P102_CN +#define __P103_CN +#define __P104_CN +#define __P108_CN +#define __P109_CN +#define __P110_CN +#define __P111_CN +#define __P112_CN +#define __P200_CN +#define __P201_CN +#define __P206_CN +#define __P212_CN +#define __P213_CN +#define __P214_CN +#define __P215_CN +#define __P300_CN +#define __P301_CN +#define __P302_CN +#define __P400_CN +#define __P407_CN +#define __P408_CN +#define __P409_CN +#define __P500_CN +#define __P914_CN +#define __P915_CN + +#define __PORT_0_CN +#define __PORT_1_CN +#define __PORT_2_CN +#define __PORT_3_CN +#define __PORT_4_CN +#define __PORT_5_CN +#define __PORT_9_CN + +#define PORT_SIZE (16) +#define PORT_COUNT (7) +//EOF GPIO + +//IVT_TABLE +#define UART0_TXI_NVIC 0 +#define UART0_TXI_EVENT 0x99 +#define UART0_RXI_NVIC 1 +#define UART0_RXI_EVENT 0x98 +#define UART1_TXI_NVIC 2 +#define UART1_TXI_EVENT 0x9F +#define UART1_RXI_NVIC 3 +#define UART1_RXI_EVENT 0x9E +#define UART2_TXI_NVIC 4 +#define UART2_TXI_EVENT 0xA4 +#define UART2_RXI_NVIC 5 +#define UART2_RXI_EVENT 0xA3 +#define UART9_TXI_NVIC 18 +#define UART9_TXI_EVENT 0xA9 +#define UART9_RXI_NVIC 19 +#define UART9_RXI_EVENT 0xA8 +//EOF IVT_TABLE + + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNF/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNF/mcu_definitions.h new file mode 100644 index 0000000000..1cecb5eb30 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNF/mcu_definitions.h @@ -0,0 +1,200 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#include "mcu_reg_addresses.h" + +//ADC +#define ADC0_P000_AN000 +#define ADC0_P001_AN001 +#define ADC0_P010_AN005 +#define ADC0_P011_AN006 +#define ADC0_P012_AN007 +#define ADC0_P013_AN008 +#define ADC0_P014_AN009 +#define ADC0_P015_AN010 +#define ADC0_P100_AN022 +#define ADC0_P101_AN021 +#define ADC0_P102_AN020 + +#define ADC_MODULE_0 1 + +#define ADC_MODULE_COUNT 1 +//EOF ADC + +//I2C +#define I2C0_SCL_P408_AF7 +#define I2C0_SDA_P407_AF7 +#define I2C1_SCL_P100_AF7 +#define I2C1_SDA_P101_AF7 + +#define I2C_MODULE_0 1 +#define I2C_MODULE_1 2 + +#define I2C_MODULE_COUNT 2 +//EOF I2C + +//UART +#define UART0_RX_P100_AF4 +#define UART0_TX_P101_AF4 +#define UART1_RX_P212_AF5 +#define UART1_TX_P213_AF5 +#define UART2_RX_P301_AF4 +#define UART2_TX_P102_AF4 +#define UART2_TX_P112_AF4 +#define UART9_RX_P110_AF5 +#define UART9_RX_P408_AF5 +#define UART9_TX_P109_AF5 + +#define UART_MODULE_0 1 +#define UART_MODULE_1 2 +#define UART_MODULE_2 3 +#define UART_MODULE_9 10 + +#define UART_MODULE_COUNT 4 +//EOF UART + +//SPI +#define SPI0_MISO_P100_AF6 +#define SPI0_MOSI_P101_AF6 +#define SPI0_SCK_P102_AF6 +#define SPI1_MISO_P110_AF6 +#define SPI1_MOSI_P109_AF6 +#define SPI1_SCK_P111_AF6 + +#define SPI_MODULE_0 1 +#define SPI_MODULE_1 2 + +#define SPI_MODULE_COUNT 2 +//EOF SPI + +//TIM +#define TIM0_P108_CHB_AF3 +#define TIM0_P212_CHB_AF3 +#define TIM0_P213_CHA_AF3 +#define TIM0_P300_CHA_AF3 +#define TIM1_P109_CHA_AF3 +#define TIM1_P110_CHB_AF3 +#define TIM2_P102_CHB_AF3 +#define TIM3_P111_CHA_AF3 +#define TIM3_P112_CHB_AF3 +#define TIM4_P301_CHB_AF3 +#define TIM5_P100_CHB_AF3 +#define TIM5_P101_CHA_AF3 +#define TIM5_P408_CHB_AF3 + +#define TIM_MODULE_0 1 +#define TIM_MODULE_1 2 +#define TIM_MODULE_2 3 +#define TIM_MODULE_3 4 +#define TIM_MODULE_4 5 +#define TIM_MODULE_5 6 + +#define TIM_MODULE_COUNT 6 +//EOF TIM + +//GPIO +#define __P000_CN +#define __P001_CN +#define __P010_CN +#define __P011_CN +#define __P012_CN +#define __P013_CN +#define __P014_CN +#define __P015_CN +#define __P100_CN +#define __P101_CN +#define __P102_CN +#define __P108_CN +#define __P109_CN +#define __P110_CN +#define __P111_CN +#define __P112_CN +#define __P200_CN +#define __P201_CN +#define __P212_CN +#define __P213_CN +#define __P214_CN +#define __P215_CN +#define __P300_CN +#define __P301_CN +#define __P407_CN +#define __P408_CN +#define __P914_CN +#define __P915_CN + +#define __PORT_0_CN +#define __PORT_1_CN +#define __PORT_2_CN +#define __PORT_3_CN +#define __PORT_4_CN +#define __PORT_9_CN + +#define PORT_SIZE (16) +#define PORT_COUNT (6) +//EOF GPIO + +//IVT_TABLE +#define UART0_TXI_NVIC 0 +#define UART0_TXI_EVENT 0x99 +#define UART0_RXI_NVIC 1 +#define UART0_RXI_EVENT 0x98 +#define UART1_TXI_NVIC 2 +#define UART1_TXI_EVENT 0x9F +#define UART1_RXI_NVIC 3 +#define UART1_RXI_EVENT 0x9E +#define UART2_TXI_NVIC 4 +#define UART2_TXI_EVENT 0xA4 +#define UART2_RXI_NVIC 5 +#define UART2_RXI_EVENT 0xA3 +#define UART9_TXI_NVIC 18 +#define UART9_TXI_EVENT 0xA9 +#define UART9_RXI_NVIC 19 +#define UART9_RXI_EVENT 0xA8 +//EOF IVT_TABLE + + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/RENESAS/R7FA4M1AB3CFM/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/RENESAS/R7FA4M1AB3CFM/mcu_reg_addresses.h new file mode 100644 index 0000000000..e69de29bb2 diff --git a/targets/arm/mikroe/core/CMakeLists.txt b/targets/arm/mikroe/core/CMakeLists.txt index 6167c2ab16..1a8e145ef2 100644 --- a/targets/arm/mikroe/core/CMakeLists.txt +++ b/targets/arm/mikroe/core/CMakeLists.txt @@ -37,6 +37,13 @@ elseif(${MCU_NAME} MATCHES "^TM4C.*") set(chip_vendor "tiva") list(APPEND hal_ll_core_def_list ${chip_vendor}) set(hal_ll_core_source "m4") +elseif(${MCU_NAME} MATCHES "^R7.*") + set(chip_vendor "renesas") + list(APPEND hal_ll_core_def_list ${chip_vendor}) + if((${CORE_NAME} MATCHES "M4EF") OR (${CORE_NAME} MATCHES "M4DSP")) + set(hal_ll_core_source "m4") + list(APPEND hal_ll_core_def_list __cortex_m4__) + endif() elseif(${MCU_NAME} MATCHES "^(AT)?SAM.*") set(chip_vendor "sam") list(APPEND hal_ll_core_def_list ${chip_vendor}) diff --git a/targets/arm/mikroe/core/src/renesas/m4/hal_ll_core_port.c b/targets/arm/mikroe/core/src/renesas/m4/hal_ll_core_port.c new file mode 100644 index 0000000000..5f0094ac60 --- /dev/null +++ b/targets/arm/mikroe/core/src/renesas/m4/hal_ll_core_port.c @@ -0,0 +1,56 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_core_port.c + * @brief This file contains all low level function definitions for chip specific core functionality. + * @note Refers to all M4 cortex chips. + */ + +#include "hal_ll_core_defines.h" +#include "hal_ll_bit_control.h" + +void hal_ll_core_port_nvic_enable_irq( uint8_t IRQn ) +{} + +void hal_ll_core_port_nvic_disable_irq( uint8_t IRQn ) +{} + +void hal_ll_core_port_nvic_set_priority_irq( uint8_t IRQn, uint8_t IRQn_priority ) +{} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/CMakeLists.txt b/targets/arm/mikroe/renesas/CMakeLists.txt new file mode 100644 index 0000000000..c0cce131d5 --- /dev/null +++ b/targets/arm/mikroe/renesas/CMakeLists.txt @@ -0,0 +1,39 @@ +## ./targets/arm/mikroe/renesas/CMakeLists.txt +# ALL MODULES +add_subdirectory(src/hal_ll) + +# SEPARATE MODULES +set(module_list "") +set(module_list_supported "") +set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") + +if (msdk_adc IN_LIST module_list_supported) + add_subdirectory(src/adc) +endif() +if (msdk_gpio_in IN_LIST module_list_supported) + add_subdirectory(src/gpio) +endif() +if (msdk_i2c_master IN_LIST module_list_supported) + add_subdirectory(src/i2c) +endif() +if (msdk_pwm IN_LIST module_list_supported) + add_subdirectory(src/tim) +endif() +if (msdk_spi_master IN_LIST module_list_supported) + add_subdirectory(src/spi_master) +endif() +if (msdk_uart IN_LIST module_list_supported) + add_subdirectory(src/uart) +endif() +if (msdk_onewire IN_LIST module_list_supported) + add_subdirectory(src/one_wire) +endif() +if (msdk_can IN_LIST module_list_supported) + add_subdirectory(src/can) +endif() +if (msdk_dma IN_LIST module_list_supported) + add_subdirectory(src/dma) +endif() +if (msdk_rtc IN_LIST module_list_supported) + add_subdirectory(src/rtc) +endif() diff --git a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc.h b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc.h new file mode 100644 index 0000000000..4980973df7 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc.h @@ -0,0 +1,228 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.h + * @brief This file contains all the functions prototypes for the ADC library. + */ + +#ifndef HAL_LL_ADC_H +#define HAL_LL_ADC_H + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" + +#define HAL_ADC_6BIT_RES_VAL (0x003FU) +#define HAL_ADC_8BIT_RES_VAL (0x00FFU) +#define HAL_ADC_10BIT_RES_VAL (0x03FFU) +#define HAL_ADC_12BIT_RES_VAL (0x0FFFU) +#define HAL_ADC_14BIT_RES_VAL (0x3FFFU) +#define HAL_ADC_16BIT_RES_VAL (0xFFFFU) + +/** + * @brief ADC low level handle. + * + * The context for storing low level object handler. + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + handle_t *hal_ll_adc_handle; + handle_t *hal_drv_adc_handle; + bool init_ll_state; +} hal_ll_adc_handle_register_t; + + +/** + * ADC VREF. + */ +typedef enum +{ + HAL_LL_ADC_VREF_EXTERNAL = 0, + HAL_LL_ADC_VREF_INTERNAL, + HAL_LL_ADC_VREF_DEFAULT = HAL_LL_ADC_VREF_INTERNAL +} hal_ll_adc_voltage_reference_t; + +/** + * ADC resolution. + */ +typedef enum +{ + HAL_LL_ADC_RESOLUTION_NOT_SET = 0, + HAL_LL_ADC_RESOLUTION_6_BIT, /**< 6 bit resolution */ + HAL_LL_ADC_RESOLUTION_8_BIT, /**< 8 bit resolution */ + HAL_LL_ADC_RESOLUTION_10_BIT, /**< 10 bit resolution */ + HAL_LL_ADC_RESOLUTION_12_BIT, /**< 12 bit resolution */ + HAL_LL_ADC_RESOLUTION_14_BIT, /**< 14 bit resolution */ + HAL_LL_ADC_RESOLUTION_16_BIT, /**< 16 bit resolution */ + + /*!< Default resolution. */ + HAL_LL_ADC_RESOLUTION_DEFAULT = HAL_LL_ADC_RESOLUTION_CMAKE +} hal_ll_adc_resolution_t; + +/** + * @brief ADC low level specific structure. + * + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_adc_voltage_reference_t vref_input; + float vref_value; + uint32_t resolution; + uint8_t channel; +} hal_ll_adc_hw_specifics_map_t; + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ); + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] *handle HAL context object handle. + * @param[in] pin Analog input pin. + * @param[in] vref_input Voltage reference source. + * @param[in] resolution Analog data resolution. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id); + +/** + * @brief Sets ADC resolution. + * + * Sets specified ADC resolution for module. + * Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param[in] *handle HAL context object handle. + * @param[in] resolution ADC resolution. + * + * @return hal_ll_err_t Module specific error or success. + */ +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution); + +/** + * @brief Sets ADC reference voltage source. + * + * Sets ADC reference voltage source for specified + * object. Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param[in] *handle HAL context object handle. + * @param[in] vref_input ADC reference voltage source. + * + * @return hal_ll_err_t Module specific error or success. + */ +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input); + +/** + * @brief Sets ADC reference voltage value. + * + * Sets ADC reference voltage value for specified + * object. + * + * @param[in] *handle HAL context object handle. + * @param[in] vref_input ADC reference voltage value. + * + * @return void None. + */ +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value); + +/** + * @brief Executes data read via ADC module. + * + * Function shall read raw unsigned analog value. + * + * @param handle ADC handle. + * @param *readDatabuf Data buffer where read data + * shall be placed. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_adc_read(handle_t *handle, uint16_t *readDatabuf ); + +/** + * @brief Closes ADC HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_adc_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // HAL_LL_ADC_H +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h new file mode 100644 index 0000000000..6f4af094a4 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h @@ -0,0 +1,195 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Macro defining `weak` attribute */ +#define __weak __attribute__((weak)) + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/*!< ADC module base addresses. */ +#ifdef ADC_MODULE_0 +static const hal_ll_base_addr_t HAL_LL_ADC0_BASE_ADDR = ( hal_ll_base_addr_t ) 0x4005C000; +#endif + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + uint8_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint8_t channel; +} hal_ll_pin_channel_list_t; + +static const hal_ll_pin_channel_list_t hal_ll_analog_in_register_list[] = +{ + #ifdef ADC0_P000_AN000 + {GPIO_P000, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_0}, + #endif + #ifdef ADC0_P001_AN001 + {GPIO_P001, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC0_P010_AN005 + {GPIO_P010, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC0_P011_AN006 + {GPIO_P011, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC0_P012_AN007 + {GPIO_P012, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC0_P013_AN008 + {GPIO_P013, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC0_P014_AN009 + {GPIO_P014, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC0_P015_AN010 + {GPIO_P015, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC0_P100_AN022 + {GPIO_P100, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_22}, + #endif + #ifdef ADC0_P101_AN021 + {GPIO_P101, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_21}, + #endif + #ifdef ADC0_P102_AN020 + {GPIO_P102, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_20}, + #endif + #ifdef ADC0_P002_AN002 + {GPIO_P002, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC0_P003_AN003 + {GPIO_P003, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC0_P004_AN004 + {GPIO_P004, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC0_P103_AN019 + {GPIO_P103, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_19}, + #endif + #ifdef ADC0_P500_AN016 + {GPIO_P500, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC0_P501_AN017 + {GPIO_P501, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC0_P502_AN018 + {GPIO_P502, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_18}, + #endif + #ifdef ADC0_P005_AN011 + {GPIO_P005, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC0_P006_AN012 + {GPIO_P006, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC0_P007_AN013 + {GPIO_P007, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC0_P008_AN014 + {GPIO_P008, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC0_P503_AN023 + {GPIO_P503, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_23}, + #endif + #ifdef ADC0_P504_AN024 + {GPIO_P504, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_24}, + #endif + #ifdef ADC0_P505_AN025 + {GPIO_P505, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_25}, + #endif + + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h new file mode 100644 index 0000000000..33a4528631 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h @@ -0,0 +1,276 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio.h + * @brief This file contains all the functions prototypes for the GPIO library. + */ + +#ifndef _HAL_LL_GPIO_H_ +#define _HAL_LL_GPIO_H_ + +#include "hal_ll_gpio_port.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief Function configures pin. + * + * Configures pin to digital output or digital input. + * Sets only the pin defined by pin mask in + * hal_ll_gpio_pin_t structure. + * + * @param *pin Pin object context. + * Configured during this functions process. + * @param name Pin name -- GPIO_PA0, GPIO_PA1... + * @param direction Pin direction. + * HAL_LL_GPIO_DIGITAL_INPUT + * HAL_LL_GPIO_DIGITAL_OUTPUT + * + * @return None. + */ +void hal_ll_gpio_configure_pin(hal_ll_gpio_pin_t *pin, hal_ll_pin_name_t name, hal_ll_gpio_direction_t direction); + +/** + * @brief Read pin input. + * + * Checks pin data input register value and + * returns logical state. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return uint8_t Pin logical state. + * 1/true -- pin high state -- 1.8V or more detected + * 0/false -- pin low state -- 1.8V or less detected + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_pin_input(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) == 0) ? \ + (0) : (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->pidr & ((hal_ll_gpio_pin_t *)_handle)->mask) ? \ + (1) : (0)) +#else +uint8_t hal_ll_gpio_read_pin_input(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Read pin output. + * + * Checks pin data output register value and + * returns logical state. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return uint8_t Pin logical state. + * 1/true -- pin high state -- 1.8V or more detected + * 0/false -- pin low state -- 1.8V or less detected + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) == 0) ? \ + (0) : (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr & ((hal_ll_gpio_pin_t *)_handle)->mask) ? \ + (1) : (0)) +#else +uint8_t hal_ll_gpio_read_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Writes pin output state. + * + * Sets single pin logical state. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * @param value Pin logical state. + * 1/true -- sets pin high state -- over 1.8V + * 0/false -- sets pin low state -- less than 1.8V + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_write_pin_output(_handle,_value) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + ((_value > 0) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr |= ((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr &= ~((hal_ll_gpio_pin_t *)_handle)->mask)) : \ + (0)) +#else +void hal_ll_gpio_write_pin_output(hal_ll_gpio_pin_t *pin, uint8_t value); +#endif + +/** + * @brief Toggles pin logical state. + * + * Checks current state of pin + * and toggles it. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_toggle_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + ((((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr & ((hal_ll_gpio_pin_t *)_handle)->mask))) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr &= ~((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr |= ((hal_ll_gpio_pin_t *)_handle)->mask)) : \ + (0)) +#else +void hal_ll_gpio_toggle_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Sets pin logical state. + * + * Sets pin logical state to high. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_set_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr |= ((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (0)) +#else +void hal_ll_gpio_set_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Sets pin logical state. + * + * Sets pin logical state to low. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_clear_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr &= ~((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (0)) +#else +void hal_ll_gpio_clear_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Configures port. + * + * Configures port according to specified + * direction. Takes into consideration only + * pins defined by mask. + * + * @param *port Port object context. + * Configured during this functions process. + * @param name Port name. + * @param mask Port pin mask. + * @param direction Port pin direction. + * HAL_LL_GPIO_DIGITAL_INPUT + * HAL_LL_GPIO_DIGITAL_OUTPUT + * + * @return None + */ +void hal_ll_gpio_configure_port(hal_ll_gpio_port_t *port, hal_ll_port_name_t name, hal_ll_gpio_mask_t mask, hal_ll_gpio_direction_t direction); + +/** + * @brief Read port input value. + * + * Checks port data input register value and + * returns it. + * + * @param *port Port object context. + * Configured during hal_ll_gpio_configure_port. + * + * @return hal_ll_port_size_t Port input data register value. + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_port_input(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ + ((hal_ll_port_size_t)(((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->pidr) & (((hal_ll_gpio_port_t *)_handle)->mask)) : \ + (0)) +#else +hal_ll_port_size_t hal_ll_gpio_read_port_input(hal_ll_gpio_port_t *port); +#endif + +/** + * @brief Read port output value. + * + * Checks port data output register value and + * returns it. + * + * @param *port Port object context. + * Configured during hal_ll_gpio_configure_port. + * @return hal_ll_port_size_t Port output data register value. + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_port_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ + ((hal_ll_port_size_t)(((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->podr) & (((hal_ll_gpio_port_t *)_handle)->mask)) : \ + (0)) +#else +hal_ll_port_size_t hal_ll_gpio_read_port_output(hal_ll_gpio_port_t *port); +#endif + +/** + * @brief Set port state. + * + * Sets port output state. + * Will take into consideration only + * port pins defined by mask in + * port object context. + * + * @param *port Port object context. + * Configured during hal_ll_gpio_configure_port. + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_write_port_output(_handle,_value) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->podr = \ + ((hal_ll_gpio_port_t *)_handle)->mask & (hal_ll_port_size_t)_value) : \ + (0)) +#else +void hal_ll_gpio_write_port_output(hal_ll_gpio_port_t *port, hal_ll_port_size_t value); +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_constants.h b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_constants.h new file mode 100644 index 0000000000..ab4fe47a1f --- /dev/null +++ b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_constants.h @@ -0,0 +1,79 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#define GPIO_CFG_PORT_OUTPUT_HIGH (0x00000001UL) // Sets the output level to HIGH (only valid for output pins) +#define GPIO_CFG_PORT_OUTPUT_LOW (0x00000000UL) // Sets the output level to LOW (only valid for output pins) +#define GPIO_CFG_PORT_DIRECTION_OUTPUT (0x00000004UL) // Configures the pin direction as OUTPUT +#define GPIO_CFG_PORT_DIRECTION_INPUT (0x00000000UL) // Configures the pin direction as INPUT +#define GPIO_CFG_PORT_PULL_UP_ENABLE (0x00000010UL) // Enables the internal pull-up resistor +#define GPIO_CFG_NMOS_OPEN_DRAIN_ENABLE (0x00000040UL) // Enables NMOS open-drain output (drives low or floats) +#define GPIO_CFG_PORT_LOW_DRIVE (0x00000000UL) // Sets the output drive strength to LOW +#define GPIO_CFG_PORT_MIDDLE_DRIVE (0x00000400UL) // Sets the output drive strength to MIDDLE +#define GPIO_CFG_PORT_MIDDLE_DRIVE_P408 (0x00000800UL) // Sets the output drive strength to MIDDLE for IIC Fast-mode +#define GPIO_CFG_EVENT_RISING_EDGE (0x00001000UL) // Configures the pin to trigger an event on rising edge +#define GPIO_CFG_EVENT_FALLING_EDGE (0x00002000UL) // Configures the pin to trigger an event on falling edge +#define GPIO_CFG_EVENT_BOTH_EDGES (0x00003000UL) // Configures the pin to trigger an event on both edges +#define GPIO_CFG_IRQ_ENABLE (0x00004000UL) // Enables interrupt generation for this pin +#define GPIO_CFG_ANALOG_ENABLE (0x00008000UL) // Configures the pin to operate in analog mode +#define GPIO_CFG_PERIPHERAL_PIN (0x00010000UL) // Configures the pin for peripheral function (not GPIO) + +#define GPIO_PRV_PFS_PSEL_OFFSET (24) // Bit offset for Peripheral Function Selection (PSEL) +#define GPIO_PRV_PFS_PSEL_MASK (0x1F000000UL) // Bit mask for Peripheral Function Selection (PSEL) + +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_ANALOG_ENABLE | GPIO_CFG_PORT_DIRECTION_INPUT ) +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_PORT_DIRECTION_OUTPUT ) +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_PORT_DIRECTION_INPUT ) + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h new file mode 100644 index 0000000000..d7a1c87d34 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h @@ -0,0 +1,249 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio.h + * @brief This file contains all the functions prototypes for the GPIO library. + */ + +#ifndef _HAL_LL_GPIO_PORT_H_ +#define _HAL_LL_GPIO_PORT_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" +#include "hal_ll_gpio_constants.h" + +/** + * Helper macros for GPIO HAL + */ +#define GPIO_MODULE_STRUCT_END (-1) +#define GPIO_PIN_NAME_MASK (0xFFUL) +#define GPIO_AF_OFFSET 8 +#define VALUE(pin, func) (pin | (func << GPIO_AF_OFFSET)) + +/** + * GPIO module struct defining pins and proprietary functions + */ +typedef struct +{ + union { + uint32_t pcntr1; + struct { + uint16_t podr; + uint16_t pdr; + }; + }; + union { + uint32_t pcntr2; + struct { + uint16_t eidr; // PORT1-4 only + uint16_t pidr; + }; + }; + union { + uint32_t pcntr3; + struct { + uint16_t porr; + uint16_t posr; + }; + }; + union { + uint32_t pcntr4; // PORT1-4 only + struct { + uint16_t eorr; // PORT1-4 only + uint16_t eosr; // PORT1-4 only + }; + }; +} hal_ll_gpio_base_handle_t; + +/** + * GPIO module struct defining pins and proprietary functions + */ +typedef struct +{ + uint32_t pins[13]; + uint32_t configs[13]; + uint32_t gpio_remap; +} module_struct; + +/** + * @brief Pin Function Select Register (PmnPFS) structure. + * + * Represents the configuration settings for a single pin using the + * Port Function Select (PFS) register. This includes direction, mode, + * drive strength, and peripheral selection. + */ +typedef struct +{ + union + { + volatile uint32_t pmnpfs; + + struct + { + volatile uint32_t podr : 1; /**< Output data. */ + volatile uint32_t pidr : 1; /**< Input data. */ + volatile uint32_t pdr : 1; /**< Direction (0: input, 1: output). */ + uint32_t : 1; /**< Reserved. */ + volatile uint32_t pcr : 1; /**< Pull-up control (0: disabled, 1: enabled). */ + uint32_t : 1; /**< Reserved. */ + volatile uint32_t ncodr : 1; /**< N-ch open-drain control (0: CMOS, 1: NMOS open-drain). */ + uint32_t : 3; /**< Reserved. */ + volatile uint32_t dscr : 2; /**< Drive capacity control. */ + volatile uint32_t eofr : 2; /**< Event on falling/rising edge. */ + volatile uint32_t isel : 1; /**< IRQ input select (0: disabled, 1: enabled). */ + volatile uint32_t asel : 1; /**< Analog select (0: digital, 1: analog). */ + volatile uint32_t pmr : 1; /**< Peripheral mode select (0: GPIO, 1: peripheral). */ + uint32_t : 7; /**< Reserved. */ + volatile uint32_t psel : 5; /**< Peripheral function select. */ + uint32_t : 3; /**< Reserved. */ + } pmnpfs_b; + }; +} hal_ll_gpio_pfs_pin_t; + +/** + * @brief Port-level PFS register map. + * + * Represents the PFS register set for all 16 pins of a given port. + */ +typedef struct +{ + volatile hal_ll_gpio_pfs_pin_t pin[16]; /**< PFS configuration for pins 0 to 15. */ +} hal_ll_gpio_pfs_port_t; + +/** + * @brief Entire PFS register map for all ports. + * + * Represents all available ports in the microcontroller that support + * Port Function Select configuration. + */ +typedef struct +{ + volatile hal_ll_gpio_pfs_port_t port[10]; /**< Port array supporting PFS. */ +} hal_ll_gpio_pfs_t; + +/** + * Handle and mask types. + */ +typedef handle_t hal_ll_gpio_base_t; + +/** + * Enum used for pin direction selection. + */ +typedef enum +{ + HAL_LL_GPIO_DIGITAL_INPUT = 0, + HAL_LL_GPIO_DIGITAL_OUTPUT = 1 +} hal_ll_gpio_direction_t; + +/** + * Enum used for pin direction selection. + */ +typedef struct hal_ll_gpio_t +{ + hal_ll_gpio_base_t base; + hal_ll_gpio_mask_t mask; +}; + +/** + * Pin and port data types. + */ +typedef struct hal_ll_gpio_t hal_ll_gpio_pin_t; +typedef struct hal_ll_gpio_t hal_ll_gpio_port_t; + +/** + * @brief Get pins port index within a list of available ports + * @param name - desired pin + * @return uint8_t value from 0 to PORT_COUNT-1 + */ +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ); + +/** + * @brief Get pin mask of provided pin within proprietery port + * @param name - desired pin + * @return uint32_t + */ +uint16_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ); + +/** + * @brief Get base address of ports registers + * @param name - desired port + * @return uint32_t address of first regsiter + */ +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ); + +/** + * @brief Set pin as analog input + * @param port - port base address acquired from hal_gpio_ll_port_base + * @param pin_mask - pin mask acquired from hal_gpio_ll_pin_mask + * @return none + */ +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ); + +/** + * @brief Set pin as digital input + * @param port - port base address acquired from hal_gpio_ll_port_base + * @param pin_mask - pin mask acquired from hal_gpio_ll_pin_mask + * @return none + */ +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ); + +/** + * @brief Set pin as digital output + * @param port - port base address acquired from hal_gpio_ll_port_base + * @param pin_mask - pin mask acquired from hal_gpio_ll_pin_mask + * @return none + */ +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ); + +/** + * @brief Initialize structure of pins associated to specific peripheral + * @param module - desired module pins structure + * @return none + */ +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_PORT_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h b/targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h new file mode 100644 index 0000000000..1fdc2f3dea --- /dev/null +++ b/targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h @@ -0,0 +1,108 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_mstpcr.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_MSTPCR_H_ +#define _HAL_LL_MSTPCR_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _MSTPCRA ( uint32_t * )0x4001E01C +#define _MSTPCRB ( uint32_t * )0x40047000 +#define _MSTPCRC ( uint32_t * )0x40047004 +#define _MSTPCRD ( uint32_t * )0x40047008 + +#define MSTPCRA_MSTPA0_POS 0 // SRAM0 +#define MSTPCRA_MSTPA6_POS 6 // ECCSRAM +#define MSTPCRA_MSTPA22_POS 22 // DMA/DTC +#define MSTPCRB_MSTPB2_POS 2 // CAN0 +#define MSTPCRB_MSTPB8_POS 8 // I2C1 +#define MSTPCRB_MSTPB9_POS 9 // I2C0 +#define MSTPCRB_MSTPB11_POS 11 // USBFS +#define MSTPCRB_MSTPB18_POS 18 // SPI1 +#define MSTPCRB_MSTPB19_POS 19 // SPI0 +#define MSTPCRB_MSTPB22_POS 22 // SCI9 +#define MSTPCRB_MSTPB29_POS 29 // SCI2 +#define MSTPCRB_MSTPB30_POS 30 // SCI1 +#define MSTPCRB_MSTPB31_POS 31 // SCI0 +#define MSTPCRC_MSTPC0_POS 0 // CAC +#define MSTPCRC_MSTPC1_POS 1 // CRC +#define MSTPCRC_MSTPC3_POS 3 // CTSU +#define MSTPCRC_MSTPC4_POS 4 // SLCDC +#define MSTPCRC_MSTPC8_POS 8 // SSIE0 +#define MSTPCRC_MSTPC13_POS 13 // DOC +#define MSTPCRC_MSTPC14_POS 14 // ELC +#define MSTPCRC_MSTPC31_POS 31 // SCE5 +#define MSTPCRD_MSTPD2_POS 2 // AGT1 +#define MSTPCRD_MSTPD3_POS 3 // AGT0 +#define MSTPCRD_MSTPD5_POS 5 // GPT321 to GPT320 +#define MSTPCRD_MSTPD6_POS 6 // GPT167 to GPT162 +#define MSTPCRD_MSTPD14_POS 14 // POEG +#define MSTPCRD_MSTPD16_POS 16 // ADC140 +#define MSTPCRD_MSTPD19_POS 19 // DAC8 +#define MSTPCRD_MSTPD20_POS 20 // DAC12 +#define MSTPCRD_MSTPD29_POS 29 // ACMPLP +#define MSTPCRD_MSTPD31_POS 31 // OPAMP + +typedef struct +{ + uint32_t iclk; // System clock frequency in Hz + uint32_t pclka; // PCLKA clock frequency in Hz + uint32_t pclkb; // PCLKB clock frequency in Hz + uint32_t pclkc; // PCLKC clock frequency in Hz + uint32_t pclkd; // PCLKD clock frequency in Hz + uint32_t fclk; // Flash interface clock frequency in Hz +} system_clocks_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_MSTPCR_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h b/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h new file mode 100644 index 0000000000..d608a109ba --- /dev/null +++ b/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h @@ -0,0 +1,850 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_pin_names.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_PIN_NAMES_H_ +#define _HAL_LL_PIN_NAMES_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "mcu_definitions.h" +#include "hal_ll_target_names.h" + +#define GPIO_FEATURE_8BIT_PORT + +#ifdef __PORT_A_CN +#define GPIO_FEATURE_GROUP_1 +#endif +#ifdef __PORT_B_CN +#define GPIO_FEATURE_GROUP_2 +#endif +#ifdef __PORT_C_CN +#define GPIO_FEATURE_GROUP_3 +#endif +#ifdef __PORT_D_CN +#define GPIO_FEATURE_GROUP_4 +#endif +#ifdef __PORT_E_CN +#define GPIO_FEATURE_GROUP_5 +#endif +#ifdef __PORT_F_CN +#define GPIO_FEATURE_GROUP_6 +#endif +#ifdef __PORT_G_CN +#define GPIO_FEATURE_GROUP_7 +#endif +#ifdef __PORT_H_CN +#define GPIO_FEATURE_GROUP_8 +#endif +#ifdef __PORT_J_CN +#define GPIO_FEATURE_GROUP_9 +#endif +#ifdef __PORT_K_CN +#define GPIO_FEATURE_GROUP_10 +#endif +#ifdef __PORT_L_CN +#define GPIO_FEATURE_GROUP_11 +#endif +#ifdef __PORT_M_CN +#define GPIO_FEATURE_GROUP_12 +#endif +#ifdef __PORT_N_CN +#define GPIO_FEATURE_GROUP_13 +#endif +#ifdef __PORT_P_CN +#define GPIO_FEATURE_GROUP_14 +#endif +#ifdef __PORT_Q_CN +#define GPIO_FEATURE_GROUP_15 +#endif +#ifdef __PORT_R_CN +#define GPIO_FEATURE_GROUP_16 +#endif +#ifdef __PORT_S_CN +#define GPIO_FEATURE_GROUP_17 +#endif +#ifdef __PORT_T_CN +#define GPIO_FEATURE_GROUP_18 +#endif + +// PORT 0 +#ifdef __P000_CN +#define GPIO_P000 (0x00) +#define P000 GPIO_P000 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P000! +#endif +#ifdef __P001_CN +#define GPIO_P001 (0x01) +#define P001 GPIO_P001 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P001! +#endif +#ifdef __P002_CN +#define GPIO_P002 (0x02) +#define P002 GPIO_P002 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P002! +#endif +#ifdef __P003_CN +#define GPIO_P003 (0x03) +#define P003 GPIO_P003 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P003! +#endif +#ifdef __P004_CN +#define GPIO_P004 (0x04) +#define P004 GPIO_P004 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P004! +#endif +#ifdef __P005_CN +#define GPIO_P005 (0x05) +#define P005 GPIO_P005 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P005! +#endif +#ifdef __P006_CN +#define GPIO_P006 (0x06) +#define P006 GPIO_P006 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P006! +#endif +#ifdef __P007_CN +#define GPIO_P007 (0x07) +#define P007 GPIO_P007 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P007! +#endif +#ifdef __P008_CN +#define GPIO_P008 (0x08) +#define P008 GPIO_P008 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P008! +#endif +#ifdef __P009_CN +#define GPIO_P009 (0x09) +#define P009 GPIO_P009 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P009! +#endif +#ifdef __P010_CN +#define GPIO_P010 (0x0A) +#define P010 GPIO_P010 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P010! +#endif +#ifdef __P011_CN +#define GPIO_P011 (0x0B) +#define P011 GPIO_P011 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P011! +#endif +#ifdef __P012_CN +#define GPIO_P012 (0x0C) +#define P012 GPIO_P012 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P012! +#endif +#ifdef __P013_CN +#define GPIO_P013 (0x0D) +#define P013 GPIO_P013 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P013! +#endif +#ifdef __P014_CN +#define GPIO_P014 (0x0E) +#define P014 GPIO_P014 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P014! +#endif +#ifdef __P015_CN +#define GPIO_P015 (0x0F) +#define P015 GPIO_P015 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P015! +#endif + +// PORT 1 +#ifdef __P100_CN +#define GPIO_P100 (0x10) +#define P100 GPIO_P100 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P100! +#endif +#ifdef __P101_CN +#define GPIO_P101 (0x11) +#define P101 GPIO_P101 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P101! +#endif +#ifdef __P102_CN +#define GPIO_P102 (0x12) +#define P102 GPIO_P102 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P102! +#endif +#ifdef __P103_CN +#define GPIO_P103 (0x13) +#define P103 GPIO_P103 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P103! +#endif +#ifdef __P104_CN +#define GPIO_P104 (0x14) +#define P104 GPIO_P104 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P104! +#endif +#ifdef __P105_CN +#define GPIO_P105 (0x15) +#define P105 GPIO_P105 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P105! +#endif +#ifdef __P106_CN +#define GPIO_P106 (0x16) +#define P106 GPIO_P106 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P106! +#endif +#ifdef __P107_CN +#define GPIO_P107 (0x17) +#define P107 GPIO_P107 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P107! +#endif +#ifdef __P108_CN +#define GPIO_P108 (0x18) +#define P108 GPIO_P108 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P108! +#endif +#ifdef __P109_CN +#define GPIO_P109 (0x19) +#define P109 GPIO_P109 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P109! +#endif +#ifdef __P110_CN +#define GPIO_P110 (0x1A) +#define P110 GPIO_P110 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P110! +#endif +#ifdef __P111_CN +#define GPIO_P111 (0x1B) +#define P111 GPIO_P111 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P111! +#endif +#ifdef __P112_CN +#define GPIO_P112 (0x1C) +#define P112 GPIO_P112 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P112! +#endif +#ifdef __P113_CN +#define GPIO_P113 (0x1D) +#define P113 GPIO_P113 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P113! +#endif +#ifdef __P114_CN +#define GPIO_P114 (0x1E) +#define P114 GPIO_P114 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P114! +#endif +#ifdef __P115_CN +#define GPIO_P115 (0x1F) +#define P115 GPIO_P115 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P115! +#endif + +// PORT 2 +#ifdef __P200_CN +#define GPIO_P200 (0x20) +#define P200 GPIO_P200 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P200! +#endif +#ifdef __P201_CN +#define GPIO_P201 (0x21) +#define P201 GPIO_P201 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P201! +#endif +#ifdef __P202_CN +#define GPIO_P202 (0x22) +#define P202 GPIO_P202 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P202! +#endif +#ifdef __P203_CN +#define GPIO_P203 (0x23) +#define P203 GPIO_P203 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P203! +#endif +#ifdef __P204_CN +#define GPIO_P204 (0x24) +#define P204 GPIO_P204 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P204! +#endif +#ifdef __P205_CN +#define GPIO_P205 (0x25) +#define P205 GPIO_P205 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P205! +#endif +#ifdef __P206_CN +#define GPIO_P206 (0x26) +#define P206 GPIO_P206 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P206! +#endif +#ifdef __P207_CN +#define GPIO_P207 (0x27) +#define P207 GPIO_P207 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P207! +#endif +#ifdef __P208_CN +#define GPIO_P208 (0x28) +#define P208 GPIO_P208 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P208! +#endif +#ifdef __P209_CN +#define GPIO_P209 (0x29) +#define P209 GPIO_P209 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P209! +#endif +#ifdef __P210_CN +#define GPIO_P210 (0x2A) +#define P210 GPIO_P210 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P210! +#endif +#ifdef __P211_CN +#define GPIO_P211 (0x2B) +#define P211 GPIO_P211 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P211! +#endif +#ifdef __P212_CN +#define GPIO_P212 (0x2C) +#define P212 GPIO_P212 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P212! +#endif +#ifdef __P213_CN +#define GPIO_P213 (0x2D) +#define P213 GPIO_P213 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P213! +#endif +#ifdef __P214_CN +#define GPIO_P214 (0x2E) +#define P214 GPIO_P214 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P214! +#endif +#ifdef __P215_CN +#define GPIO_P215 (0x2F) +#define P215 GPIO_P215 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P215! +#endif + +// PORT 3 +#ifdef __P300_CN +#define GPIO_P300 (0x30) +#define P300 GPIO_P300 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P300! +#endif +#ifdef __P301_CN +#define GPIO_P301 (0x31) +#define P301 GPIO_P301 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P301! +#endif +#ifdef __P302_CN +#define GPIO_P302 (0x32) +#define P302 GPIO_P302 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P302! +#endif +#ifdef __P303_CN +#define GPIO_P303 (0x33) +#define P303 GPIO_P303 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P303! +#endif +#ifdef __P304_CN +#define GPIO_P304 (0x34) +#define P304 GPIO_P304 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P304! +#endif +#ifdef __P305_CN +#define GPIO_P305 (0x35) +#define P305 GPIO_P305 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P305! +#endif +#ifdef __P306_CN +#define GPIO_P306 (0x36) +#define P306 GPIO_P306 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P306! +#endif +#ifdef __P307_CN +#define GPIO_P307 (0x37) +#define P307 GPIO_P307 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P307! +#endif +#ifdef __P308_CN +#define GPIO_P308 (0x38) +#define P308 GPIO_P308 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P308! +#endif +#ifdef __P309_CN +#define GPIO_P309 (0x39) +#define P309 GPIO_P309 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P309! +#endif +#ifdef __P310_CN +#define GPIO_P310 (0x3A) +#define P310 GPIO_P310 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P310! +#endif +#ifdef __P311_CN +#define GPIO_P311 (0x3B) +#define P311 GPIO_P311 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P311! +#endif +#ifdef __P312_CN +#define GPIO_P312 (0x3C) +#define P312 GPIO_P312 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P312! +#endif +#ifdef __P313_CN +#define GPIO_P313 (0x3D) +#define P313 GPIO_P313 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P313! +#endif +#ifdef __P314_CN +#define GPIO_P314 (0x3E) +#define P314 GPIO_P314 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P314! +#endif +#ifdef __P315_CN +#define GPIO_P315 (0x3F) +#define P315 GPIO_P315 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P315! +#endif + +// PORT 4 +#ifdef __P400_CN +#define GPIO_P400 (0x40) +#define P400 GPIO_P400 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P400! +#endif +#ifdef __P401_CN +#define GPIO_P401 (0x41) +#define P401 GPIO_P401 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P401! +#endif +#ifdef __P402_CN +#define GPIO_P402 (0x42) +#define P402 GPIO_P402 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P402! +#endif +#ifdef __P403_CN +#define GPIO_P403 (0x43) +#define P403 GPIO_P403 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P403! +#endif +#ifdef __P404_CN +#define GPIO_P404 (0x44) +#define P404 GPIO_P404 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P404! +#endif +#ifdef __P405_CN +#define GPIO_P405 (0x45) +#define P405 GPIO_P405 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P405! +#endif +#ifdef __P406_CN +#define GPIO_P406 (0x46) +#define P406 GPIO_P406 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P406! +#endif +#ifdef __P407_CN +#define GPIO_P407 (0x47) +#define P407 GPIO_P407 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P407! +#endif +#ifdef __P408_CN +#define GPIO_P408 (0x48) +#define P408 GPIO_P408 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P408! +#endif +#ifdef __P409_CN +#define GPIO_P409 (0x49) +#define P409 GPIO_P409 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P409! +#endif +#ifdef __P410_CN +#define GPIO_P410 (0x4A) +#define P410 GPIO_P410 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P410! +#endif +#ifdef __P411_CN +#define GPIO_P411 (0x4B) +#define P411 GPIO_P411 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P411! +#endif +#ifdef __P412_CN +#define GPIO_P412 (0x4C) +#define P412 GPIO_P412 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P412! +#endif +#ifdef __P413_CN +#define GPIO_P413 (0x4D) +#define P413 GPIO_P413 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P413! +#endif +#ifdef __P414_CN +#define GPIO_P414 (0x4E) +#define P414 GPIO_P414 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P414! +#endif +#ifdef __P415_CN +#define GPIO_P415 (0x4F) +#define P415 GPIO_P415 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P415! +#endif + +// PORT 5 +#ifdef __P500_CN +#define GPIO_P500 (0x50) +#define P500 GPIO_P500 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P500! +#endif +#ifdef __P501_CN +#define GPIO_P501 (0x51) +#define P501 GPIO_P501 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P501! +#endif +#ifdef __P502_CN +#define GPIO_P502 (0x52) +#define P502 GPIO_P502 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P502! +#endif +#ifdef __P503_CN +#define GPIO_P503 (0x53) +#define P503 GPIO_P503 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P503! +#endif +#ifdef __P504_CN +#define GPIO_P504 (0x54) +#define P504 GPIO_P504 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P504! +#endif +#ifdef __P505_CN +#define GPIO_P505 (0x55) +#define P505 GPIO_P505 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P505! +#endif +#ifdef __P506_CN +#define GPIO_P506 (0x56) +#define P506 GPIO_P506 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P506! +#endif +#ifdef __P507_CN +#define GPIO_P507 (0x57) +#define P507 GPIO_P507 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P507! +#endif +#ifdef __P508_CN +#define GPIO_P508 (0x58) +#define P508 GPIO_P508 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P508! +#endif +#ifdef __P509_CN +#define GPIO_P509 (0x59) +#define P509 GPIO_P509 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P509! +#endif +#ifdef __P510_CN +#define GPIO_P510 (0x5A) +#define P510 GPIO_P510 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P510! +#endif +#ifdef __P511_CN +#define GPIO_P511 (0x5B) +#define P511 GPIO_P511 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P511! +#endif +#ifdef __P512_CN +#define GPIO_P512 (0x5C) +#define P512 GPIO_P512 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P512! +#endif +#ifdef __P513_CN +#define GPIO_P513 (0x5D) +#define P513 GPIO_P513 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P513! +#endif +#ifdef __P514_CN +#define GPIO_P514 (0x5E) +#define P514 GPIO_P514 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P514! +#endif +#ifdef __P515_CN +#define GPIO_P515 (0x5F) +#define P515 GPIO_P515 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P515! +#endif + +// PORT 6 +#ifdef __P600_CN +#define GPIO_P600 (0x60) +#define P600 GPIO_P600 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P600! +#endif +#ifdef __P601_CN +#define GPIO_P601 (0x61) +#define P601 GPIO_P601 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P601! +#endif +#ifdef __P602_CN +#define GPIO_P602 (0x62) +#define P602 GPIO_P602 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P602! +#endif +#ifdef __P603_CN +#define GPIO_P603 (0x63) +#define P603 GPIO_P603 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P603! +#endif +#ifdef __P604_CN +#define GPIO_P604 (0x64) +#define P604 GPIO_P604 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P604! +#endif +#ifdef __P605_CN +#define GPIO_P605 (0x65) +#define P605 GPIO_P605 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P605! +#endif +#ifdef __P606_CN +#define GPIO_P606 (0x66) +#define P606 GPIO_P606 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P606! +#endif +#ifdef __P607_CN +#define GPIO_P607 (0x67) +#define P607 GPIO_P607 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P607! +#endif +#ifdef __P608_CN +#define GPIO_P608 (0x68) +#define P608 GPIO_P608 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P608! +#endif +#ifdef __P609_CN +#define GPIO_P609 (0x69) +#define P609 GPIO_P609 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P609! +#endif +#ifdef __P610_CN +#define GPIO_P610 (0x6A) +#define P610 GPIO_P610 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P610! +#endif +#ifdef __P611_CN +#define GPIO_P611 (0x6B) +#define P611 GPIO_P611 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P611! +#endif +#ifdef __P612_CN +#define GPIO_P612 (0x6C) +#define P612 GPIO_P612 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P612! +#endif +#ifdef __P613_CN +#define GPIO_P613 (0x6D) +#define P613 GPIO_P613 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P613! +#endif +#ifdef __P614_CN +#define GPIO_P614 (0x6E) +#define P614 GPIO_P614 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P614! +#endif +#ifdef __P615_CN +#define GPIO_P615 (0x6F) +#define P615 GPIO_P615 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P615! +#endif + +// PORT 7 +#ifdef __P700_CN +#define GPIO_P700 (0x70) +#define P700 GPIO_P700 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P700! +#endif +#ifdef __P701_CN +#define GPIO_P701 (0x71) +#define P701 GPIO_P701 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P701! +#endif +#ifdef __P702_CN +#define GPIO_P702 (0x72) +#define P702 GPIO_P702 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P702! +#endif +#ifdef __P703_CN +#define GPIO_P703 (0x73) +#define P703 GPIO_P703 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P703! +#endif +#ifdef __P704_CN +#define GPIO_P704 (0x74) +#define P704 GPIO_P704 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P704! +#endif +#ifdef __P705_CN +#define GPIO_P705 (0x75) +#define P705 GPIO_P705 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P705! +#endif +#ifdef __P706_CN +#define GPIO_P706 (0x76) +#define P706 GPIO_P706 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P706! +#endif +#ifdef __P707_CN +#define GPIO_P707 (0x77) +#define P707 GPIO_P707 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P707! +#endif +#ifdef __P708_CN +#define GPIO_P708 (0x78) +#define P708 GPIO_P708 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P708! +#endif +#ifdef __P709_CN +#define GPIO_P709 (0x79) +#define P709 GPIO_P709 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P709! +#endif +#ifdef __P710_CN +#define GPIO_P710 (0x7A) +#define P710 GPIO_P710 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P710! +#endif +#ifdef __P711_CN +#define GPIO_P711 (0x7B) +#define P711 GPIO_P711 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P711! +#endif +#ifdef __P712_CN +#define GPIO_P712 (0x7C) +#define P712 GPIO_P712 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P712! +#endif +#ifdef __P713_CN +#define GPIO_P713 (0x7D) +#define P713 GPIO_P713 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P713! +#endif +#ifdef __P714_CN +#define GPIO_P714 (0x7E) +#define P714 GPIO_P714 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P714! +#endif +#ifdef __P715_CN +#define GPIO_P715 (0x7F) +#define P715 GPIO_P715 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P715! +#endif + +// PORT 8 +#ifdef __P800_CN +#define GPIO_P800 (0x80) +#define P800 GPIO_P800 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P800! +#endif +#ifdef __P801_CN +#define GPIO_P801 (0x81) +#define P801 GPIO_P801 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P801! +#endif +#ifdef __P802_CN +#define GPIO_P802 (0x82) +#define P802 GPIO_P802 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P802! +#endif +#ifdef __P803_CN +#define GPIO_P803 (0x83) +#define P803 GPIO_P803 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P803! +#endif +#ifdef __P804_CN +#define GPIO_P804 (0x84) +#define P804 GPIO_P804 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P804! +#endif +#ifdef __P805_CN +#define GPIO_P805 (0x85) +#define P805 GPIO_P805 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P805! +#endif +#ifdef __P806_CN +#define GPIO_P806 (0x86) +#define P806 GPIO_P806 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P806! +#endif +#ifdef __P807_CN +#define GPIO_P807 (0x87) +#define P807 GPIO_P807 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P807! +#endif +#ifdef __P808_CN +#define GPIO_P808 (0x88) +#define P808 GPIO_P808 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P808! +#endif +#ifdef __P809_CN +#define GPIO_P809 (0x89) +#define P809 GPIO_P809 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P809! +#endif +#ifdef __P810_CN +#define GPIO_P810 (0x8A) +#define P810 GPIO_P810 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P810! +#endif +#ifdef __P811_CN +#define GPIO_P811 (0x8B) +#define P811 GPIO_P811 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P811! +#endif +#ifdef __P812_CN +#define GPIO_P812 (0x8C) +#define P812 GPIO_P812 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P812! +#endif +#ifdef __P813_CN +#define GPIO_P813 (0x8D) +#define P813 GPIO_P813 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P813! +#endif +#ifdef __P814_CN +#define GPIO_P814 (0x8E) +#define P814 GPIO_P814 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P814! +#endif +#ifdef __P815_CN +#define GPIO_P815 (0x8F) +#define P815 GPIO_P815 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P815! +#endif + +// PORT 9 +#ifdef __P900_CN +#define GPIO_P900 (0x90) +#define P900 GPIO_P900 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P900! +#endif +#ifdef __P901_CN +#define GPIO_P901 (0x91) +#define P901 GPIO_P901 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P901! +#endif +#ifdef __P902_CN +#define GPIO_P902 (0x92) +#define P902 GPIO_P902 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P902! +#endif +#ifdef __P903_CN +#define GPIO_P903 (0x93) +#define P903 GPIO_P903 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P903! +#endif +#ifdef __P904_CN +#define GPIO_P904 (0x94) +#define P904 GPIO_P904 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P904! +#endif +#ifdef __P905_CN +#define GPIO_P905 (0x95) +#define P905 GPIO_P905 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P905! +#endif +#ifdef __P906_CN +#define GPIO_P906 (0x96) +#define P906 GPIO_P906 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P906! +#endif +#ifdef __P907_CN +#define GPIO_P907 (0x97) +#define P907 GPIO_P907 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P907! +#endif +#ifdef __P908_CN +#define GPIO_P908 (0x98) +#define P908 GPIO_P908 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P908! +#endif +#ifdef __P909_CN +#define GPIO_P909 (0x99) +#define P909 GPIO_P909 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P909! +#endif +#ifdef __P910_CN +#define GPIO_P910 (0x9A) +#define P910 GPIO_P910 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P910! +#endif +#ifdef __P911_CN +#define GPIO_P911 (0x9B) +#define P911 GPIO_P911 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P911! +#endif +#ifdef __P912_CN +#define GPIO_P912 (0x9C) +#define P912 GPIO_P912 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P912! +#endif +#ifdef __P913_CN +#define GPIO_P913 (0x9D) +#define P913 GPIO_P913 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P913! +#endif +#ifdef __P914_CN +#define GPIO_P914 (0x9E) +#define P914 GPIO_P914 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P914! +#endif +#ifdef __P915_CN +#define GPIO_P915 (0x9F) +#define P915 GPIO_P915 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P915! +#endif + +#define GPIO_PIN_0 (0x00) +#define PIN_0 GPIO_PIN_0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_0! +#define GPIO_PIN_1 (0x01) +#define PIN_1 GPIO_PIN_1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_1! +#define GPIO_PIN_2 (0x02) +#define PIN_2 GPIO_PIN_2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_2! +#define GPIO_PIN_3 (0x03) +#define PIN_3 GPIO_PIN_3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_3! +#define GPIO_PIN_4 (0x04) +#define PIN_4 GPIO_PIN_4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_4! +#define GPIO_PIN_5 (0x05) +#define PIN_5 GPIO_PIN_5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_5! +#define GPIO_PIN_6 (0x06) +#define PIN_6 GPIO_PIN_6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_6! +#define GPIO_PIN_7 (0x07) +#define PIN_7 GPIO_PIN_7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_7! +#define GPIO_PIN_8 (0x08) +#define PIN_8 GPIO_PIN_8 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_8! +#define GPIO_PIN_9 (0x09) +#define PIN_9 GPIO_PIN_9 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_9! +#define GPIO_PIN_10 (0x10) +#define PIN_10 GPIO_PIN_10 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_10! +#define GPIO_PIN_11 (0x11) +#define PIN_11 GPIO_PIN_11 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_11! +#define GPIO_PIN_12 (0x12) +#define PIN_12 GPIO_PIN_12 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_12! +#define GPIO_PIN_13 (0x13) +#define PIN_13 GPIO_PIN_13 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_13! +#define GPIO_PIN_14 (0x14) +#define PIN_14 GPIO_PIN_14 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_14! +#define GPIO_PIN_15 (0x15) +#define PIN_15 GPIO_PIN_15 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_15! + +#ifdef __PORT_0_CN +#define GPIO_PORT_0 (0x00) +#define PORT_0 GPIO_PORT_0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_0! +#endif +#ifdef __PORT_1_CN +#define GPIO_PORT_1 (0x01) +#define PORT_1 GPIO_PORT_1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_1! +#endif +#ifdef __PORT_2_CN +#define GPIO_PORT_2 (0x02) +#define PORT_2 GPIO_PORT_2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_2! +#endif +#ifdef __PORT_3_CN +#define GPIO_PORT_3 (0x03) +#define PORT_3 GPIO_PORT_3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_3! +#endif +#ifdef __PORT_4_CN +#define GPIO_PORT_4 (0x04) +#define PORT_4 GPIO_PORT_4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_4! +#endif +#ifdef __PORT_5_CN +#define GPIO_PORT_5 (0x05) +#define PORT_5 GPIO_PORT_5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_5! +#endif +#ifdef __PORT_6_CN +#define GPIO_PORT_6 (0x06) +#define PORT_6 GPIO_PORT_6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_6! +#endif +#ifdef __PORT_7_CN +#define GPIO_PORT_7 (0x07) +#define PORT_7 GPIO_PORT_7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_7! +#endif +#ifdef __PORT_8_CN +#define GPIO_PORT_8 (0x08) +#define PORT_8 GPIO_PORT_8 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_8! +#endif +#ifdef __PORT_9_CN +#define GPIO_PORT_9 (0x09) +#define PORT_9 GPIO_PORT_9 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_9! +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_PIN_NAMES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/hal_ll_target.h b/targets/arm/mikroe/renesas/include/hal_ll_target.h new file mode 100644 index 0000000000..40b76d92e2 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/hal_ll_target.h @@ -0,0 +1,67 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_target.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_TARGET_H_ +#define _HAL_LL_TARGET_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" +#include "hal_ll_bit_control.h" +#include "assembly.h" +#include "common_macros.h" +#include "common_types.h" + +#define HAL_LL_MODULE_ERROR (hal_ll_base_addr_t)(0xFFFFFFFF) +#define HAL_LL_CHANNEL_ERROR (hal_ll_base_addr_t)(0xFFFFFF) +#define HAL_LL_PIN_NC (hal_ll_pin_name_t)(0xFFFF) +#define HAL_LL_PORT_NC (hal_ll_port_name_t)(0xFF) + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TARGET_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/hal_ll_target_names.h b/targets/arm/mikroe/renesas/include/hal_ll_target_names.h new file mode 100644 index 0000000000..559ced4f2a --- /dev/null +++ b/targets/arm/mikroe/renesas/include/hal_ll_target_names.h @@ -0,0 +1,72 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_target_names.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_TARGET_NAMES_H_ +#define _HAL_LL_TARGET_NAMES_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include +#include +#include +#include + +typedef uintptr_t handle_t; +typedef uint16_t hal_ll_gpio_mask_t; +typedef uint8_t hal_ll_pin_name_t; +typedef uint8_t hal_ll_port_name_t; +typedef uint16_t hal_ll_port_size_t; +typedef uint32_t hal_ll_base_addr_t; +typedef uint8_t hal_ll_channel_t; + +typedef int32_t hal_ll_err_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TARGET_NAMES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_master.h b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_master.h new file mode 100644 index 0000000000..02c683f928 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_master.h @@ -0,0 +1,245 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.h + * @brief API for I2C master HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_I2C_MASTER_H_ +#define _HAL_LL_I2C_MASTER_H_ + +#include "hal_ll_target.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief I2C master low level pins config structure. + * + * The context structure for storing low level pin configuration + * for both SCL and SDA pins. + * + */ +typedef struct +{ + hal_ll_pin_af_t pin_scl; + hal_ll_pin_af_t pin_sda; +} hal_ll_i2c_pins_t; + +/** + * @brief I2C master low level handle. + * + * The context for storing low level object handler. + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + handle_t *hal_ll_i2c_master_handle; + handle_t *hal_drv_i2c_master_handle; + bool init_ll_state; +} hal_ll_i2c_master_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] scl I2C SCL pin. + * @param[in] sda I2C SDA pin. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ); + +/** + * @brief Sets I2C slave address. + * + * Registers I2C slave address for specified + * object. + * + * @param[in] *handle HAL context object handle. + * @param[in] addr I2C slave address. + * + * @return void None. + */ +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ); + +/** + * @brief Sets I2C module speed. + * + * Sets specified speed for module. + * Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param[in] *handle HAL context object handle. + * @param[in] speed Desired speed value. + * + * @return hal_ll_err_t Module specific error. + * + * Returns value of speed the module was + * initialized to, or module specific error if + * initialization failed. + * When using from low level directly, + * speed can be set to any desired value, + * but take into consideration that not all values + * will work, as this is chip specific. + * Speed value is declared in kbit/s. + */ +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ); + +/** + * @brief Sets I2C timeout value. + * + * Registers I2C timeout value in number of retries. + * Module shall retry any given operation + * `timeout` number of times before aborting operation. + * + * @param[in] *handle HAL context object handle. + * @param[in] timeout I2C timeout value. + * + * @return void None. + */ +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ); + +/** + * @brief Executes low level data read on I2C bus. + * + * Function shall generate a START signal, + * followed by lenReadData number of reads + * on the bus. Ends with a STOP signal. + * + * @param handle I2C handle. + * @param *readDatabuf Data buffer where read data + * shall be placed. + * @param lenReadData Number of bytes to read. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ); + +/** + * @brief Executes low level data write on I2C bus. + * + * Function shall generate a START signal, + * followed by lenWriteData number of writes + * on the bus. Ends with a STOP signal. + * + * @param handle I2C handle. + * @param *WriteDatabuf Data buffer where data to + * be written is located. + * @param lenWriteData Number of bytes to send. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ); + +/** + * @brief Perform a low level write followed by a low level read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation followed by a + * read operation on the bus. + * The operation consists of a start signal followed by lenWriteData number + * of write operations, a restart signal followed by lenReadData number + * of read operations finishing with a stop signal. + * + * @param handle I2C handle. + * @param[in] *writeDatabuf - Pointer to write data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @param[in] *readDatabuf - Pointer to read data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, + uint8_t *write_data_buf, + size_t len_write_data, + uint8_t *read_data_buf, + size_t len_read_data ); + +/** + * @brief Closes I2C master HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_i2c_master_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_MASTER_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h new file mode 100644 index 0000000000..8ca61d04ff --- /dev/null +++ b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h @@ -0,0 +1,117 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Macro defining `weak` attribute */ +#define __weak __attribute__((weak)) +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +#ifdef I2C_MODULE_0 +static const hal_ll_base_addr_t HAL_LL_I2C0_BASE_ADDR = 0x40053000UL; +#endif +#ifdef I2C_MODULE_1 +static const hal_ll_base_addr_t HAL_LL_I2C1_BASE_ADDR = 0x40053100UL; +#endif + +/*!< @brief I2C pin structure. */ +typedef struct { + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +/*!< I2C SCL Pins. */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = { + #ifdef I2C0_SCL_P408_AF7 + {GPIO_P408, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, + #endif + #ifdef I2C1_SCL_P100_AF7 + {GPIO_P100, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, + #endif + #ifdef I2C0_SCL_P204_AF7 + {GPIO_P204, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, + #endif + #ifdef I2C0_SCL_P400_AF7 + {GPIO_P400, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, + #endif + #ifdef I2C1_SCL_P205_AF7 + {GPIO_P205, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, + #endif + + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< I2C SDA Pins. */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = { + #ifdef I2C0_SDA_P407_AF7 + {GPIO_P407, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, + #endif + #ifdef I2C1_SDA_P101_AF7 + {GPIO_P101, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, + #endif + #ifdef I2C0_SDA_P401_AF7 + {GPIO_P401, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, + #endif + #ifdef I2C1_SDA_P206_AF7 + {GPIO_P206, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, + #endif + + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/one_wire/hal_ll_one_wire.h b/targets/arm/mikroe/renesas/include/one_wire/hal_ll_one_wire.h new file mode 100644 index 0000000000..274f6c1f7e --- /dev/null +++ b/targets/arm/mikroe/renesas/include/one_wire/hal_ll_one_wire.h @@ -0,0 +1,231 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_one_wire.h + * @brief API for One Wire HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_ONE_WIRE_H_ +#define _HAL_LL_ONE_WIRE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_gpio.h" + +/** + * @brief Structure for storing One Wire device address. + * @details Unique One Wire address used for device addressing. + */ +typedef struct { + uint8_t address[8]; /*!< One Wire address buffer. */ +} hal_ll_one_wire_rom_address_t; + +/** + * @brief One Wire HAL Low Level context structure. + * @details The context structure for storing driver internal state. The contents of the + * context structure are used by the module and must not be altered. Reading or + * writing data directly from a control structure by user should be avoided. + */ +typedef struct { + hal_ll_pin_name_t data_pin; // One Wire data pin. + volatile uint32_t direction; // Register for altering GPIO pin direction. + volatile uint32_t output_set; // Register for GPIO port bit set. + volatile uint32_t output_clear; // Register for GPIO port bit reset. + volatile uint32_t input; // Register for reading current GPIO pin state. +} hal_ll_one_wire_local_t; + +/** + * @brief One Wire HAL Low Level initialization configuration structure. + * + * @details + * - data_pin value - to be configured as desired. + * - state value - NOTE must not be altered (it is supposed to be set automatically in Low Level Layer). + */ +typedef struct { + hal_ll_pin_name_t data_pin; /*!< One Wire pin - user is to configure it as desired. */ + bool state; /*!< State of a pin. NOTE must not be altered. */ +} hal_ll_one_wire_t; + +/** + * @details Enum containing predefined module return values. + */ +typedef enum { + HAL_LL_ONE_WIRE_SUCCESS = 0, /*!< Success. */ + HAL_LL_ONE_WIRE_ERROR = (-1) /*!< Error. */ +} hal_ll_one_wire_err_t; + +/** + * @brief Opens One Wire HAL Low Level object. + * @details Opens One Wire HAL Low Level object on selected pin. + * Enables appropriate PORT clock, configures pin to have digital output functionality, + * makes sure that HIGH voltage state is applied on pin before any One Wire actions. + * @param[in,out] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @return None. + * @pre Make sure that \p LowLevel structure has been adequately + * populated beforehand. + * @note It is recommended to check return value for error. + */ +void hal_ll_one_wire_open( hal_ll_one_wire_t *obj ); + +/** + * @brief Reset One Wire bus. + * @details Host shall send reset sequence and devices shall go into reset state. + * @param[in,out] *handle One Wire HAL Low Level object. + * See #hal_one_wire_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_reset( hal_ll_one_wire_t *obj ); + +/** + * @brief Reads device's ROM information. + * @details Allows the host to read eight-bit family code, + * 48-bit serial number, and eight-bit CRC. + * + * @important THIS FUNCTION IS TO BE ISSUED ONLY IF WE ARE DEALING WITH + * ONE DEVICE ONLY. THIS FUNCTION AUTOMATICALLY RESETS ONE WIRE BUS. + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_one_wire_t structure definition for detailed explanation. + * @param[out] *device_rom_address Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + */ +hal_ll_err_t hal_ll_one_wire_read_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ); + +/** + * @brief Access device's level functions without transmitting ROM information. + * @details Allows the host to access device functions without + * providing the 64-bit ROM identification number. + * + * @important THIS FUNCTION IS TO BE ISSUED ONLY IF WE ARE DEALING WITH + * ONE DEVICE ONLY. THIS FUNCTION AUTOMATICALLY RESETS ONE WIRE BUS. + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_one_wire_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + */ +hal_ll_err_t hal_ll_one_wire_skip_rom( hal_ll_one_wire_t *obj ); + +/** + * @brief Selects a specific One Wire capable device on bus. + * @details Select a One Wire device with specific ID. + * + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @param[in] device_rom_address Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_match_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ); + +/** + * @brief Search One Wire capable device on bus. + * @details Search and list 1st device that is One Wire capable. + * + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @param[out] *one_wire_device_list Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_search_first_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ); + +/** + * @brief Search One Wire capable devices on bus. + * @details Search devices that is One Wire capable. + * + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @param[out] *one_wire_device_list Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_search_next_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ); + +/** + * @brief Writes byte to One Wire bus. + * @details Writes byte to One Wire bus. + * @param[in] *write_data_buffer Data transmit buffer. + * @param[in] write_data_length Number of bytes to write from data transmit buffer. + * @return None. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +void hal_ll_one_wire_write_byte( uint8_t *write_data_buffer, size_t write_data_length ); + +/** + * @brief Reads byte from One Wire bus. + * @details Reads byte from One Wire bus. + * @param[out] *read_data_buffer Data receive buffer. + * @param[in] read_data_length Number of bytes to be read. + * @return None. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +void hal_ll_one_wire_read_byte( uint8_t *read_data_buffer, size_t read_data_length ); + +/** + * @brief Reconfigures One Wire pin settings. + * @details Enables appropriate PORT clock, configures pin to have digital output functionality, + * makes sure that HIGH voltage state is applied on pin before any One Wire actions. + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @return None. + * @pre Before calling this function, + * the user is expected to call #hal_one_wire_open function. + */ +void hal_ll_one_wire_reconfigure( hal_ll_one_wire_t *obj ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ONE_WIRE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h new file mode 100644 index 0000000000..bba04635fb --- /dev/null +++ b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h @@ -0,0 +1,260 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.h + * @brief API for SPI master HAL LOW LEVEL layer. + */ + +#ifndef HAL_LL_SPI_MASTER_H +#define HAL_LL_SPI_MASTER_H + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" +#include "hal_ll_gpio.h" + +/** + * @brief SPI configuration pins structure. + */ +typedef struct { + hal_ll_pin_af_t sck; + hal_ll_pin_af_t miso; + hal_ll_pin_af_t mosi; +} hal_ll_spi_master_pins_t; + +/** + * @brief SPI master HAL low lever configuration structure. + */ +typedef struct { + uint8_t default_write_data; + hal_ll_pin_name_t sck; + hal_ll_pin_name_t miso; + hal_ll_pin_name_t mosi; + uint32_t speed; +} hal_ll_spi_master_config_t; + +/** + * @brief Enum containing predefined module mode values. + * + * Enum values: + * + * HAL_LL_SPI_MASTER_MODE_0 -- CPO = 0, CPH = 0 + * HAL_LL_SPI_MASTER_MODE_1 -- CPO = 0, CPH = 1 + * HAL_LL_SPI_MASTER_MODE_2 -- CPO = 1, CPH = 0 + * HAL_LL_SPI_MASTER_MODE_3 -- CPO = 1, CPH = 1 + */ +typedef enum { + HAL_LL_SPI_MASTER_MODE_0 = 0, + HAL_LL_SPI_MASTER_MODE_1, + HAL_LL_SPI_MASTER_MODE_2, + HAL_LL_SPI_MASTER_MODE_3, + + HAL_LL_SPI_MASTER_MODE_DEFAULT = HAL_LL_SPI_MASTER_MODE_0 +} hal_ll_spi_master_mode_t; + +/** + * @brief SPI master HAL low lever handle register. + */ +typedef struct { + handle_t *hal_ll_spi_master_handle; + handle_t *hal_drv_spi_master_handle; + bool init_ll_state; +} hal_ll_spi_master_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] *handle HAL context object handle. + * @param[in] sck SPI sck pin. + * @param[in] miso SPI miso pin. + * @param[in] mosi SPI mosi pin. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_register_handle( hal_ll_pin_name_t sck, + hal_ll_pin_name_t miso, + hal_ll_pin_name_t mosi, + hal_ll_spi_master_handle_register_t *handle_map, + uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_spi( handle_t *handle ); + +/** + * @brief Sets SPI Master configuration dummy data. + * @param config[IN] SPI Master module configuration. + * @param config[IN] user-defined dummy data. + */ +void hal_ll_spi_master_set_default_write_data( handle_t *handle, uint8_t dummy_data ); + +/** + * @brief Sets SPI Master configuration dummy data. + * @param config[IN] SPI Master module configuration. + * @param config[IN] user-defined SPI Master baud rate value. + */ +uint32_t hal_ll_spi_master_set_speed( handle_t *handle, uint32_t speed ); + +/** + * @brief Sets SPI Master configuration dummy data. + * @param[in] *handle HAL context object handle. + * @param[in] mode SPI Master de-facto mode selection. + */ +hal_ll_err_t hal_ll_spi_master_set_mode( handle_t *handle, hal_ll_spi_master_mode_t mode ); + +/** + * @brief Executes low level data write on SPI bus. + * + * Function shall generate a START signal, + * followed by write_data_buffer number of writes + * on the bus. + * + * @param *handle HAL context object handle. + * @param *write_data_buffer Data buffer where data to be written is located. + * @param length_data Number of bytes to send. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write( handle_t *handle, uint8_t *write_data_buffer, size_t length_data); + +/** + * @brief Executes low level data read on SPI bus. + * + * @param handle I2C handle. + * @param *read_data_buffer Data buffer where read data shall be placed. + * @param length_data Number of bytes to read. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_read( handle_t *handle, uint8_t *read_data_buffer, size_t length_data); + +/** + * @brief Perform a low level write followed by a low level read on the SPI bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation followed by a + * read operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to write data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to read data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, + uint8_t *write_data_buffer, + size_t length_write_data, + uint8_t *read_data_buffer, + size_t length_read_data ); + +/** + * @brief Performs simultaneous write and read on SPI bus. + * + * Executes a full-duplex SPI transfer. While writing `write_data_buffer`, + * the incoming bytes from the SPI slave are placed into `read_data_buffer`. + * This function is suitable for devices that require simultaneous + * transmission and reception. + * + * @param[in] handle HAL context object handle. + * @param[in] write_data_buffer Pointer to data to be written to the bus. + * @param[out] read_data_buffer Pointer to buffer where read data will be stored. + * @param[in] data_length Number of bytes to transfer. + * + * @return hal_ll_err_t Returns #HAL_LL_SPI_MASTER_SUCCESS on success, + * otherwise returns #HAL_LL_SPI_MASTER_MODULE_ERROR + * if handle is invalid or data_length is 0. + * + * @note This function assumes the SPI module is already initialized via + * #hal_ll_spi_master_register_handle and #hal_ll_module_configure_spi. + */ +hal_ll_err_t hal_ll_spi_master_transfer( handle_t *handle, + uint8_t *write_data_buffer, + uint8_t *read_data_buffer, + size_t data_length ); + +/** + * @brief Closes SPI Master HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_spi_master_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // HAL_LL_SPI_MASTER_H +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h new file mode 100644 index 0000000000..6fbe0597c0 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h @@ -0,0 +1,136 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Macro defining `weak` attribute */ +#define __weak __attribute__((weak)) +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) + +/*!< SPI module base addresses. */ +#ifdef SPI_MODULE_0 +static const hal_ll_base_addr_t HAL_LL_SPI0_MASTER_BASE_ADDR = 0x40072000UL; +#endif +#ifdef SPI_MODULE_1 +static const hal_ll_base_addr_t HAL_LL_SPI1_MASTER_BASE_ADDR = 0x40072100UL; +#endif +#ifdef SPI_MODULE_2 +static const hal_ll_base_addr_t HAL_LL_SPI2_MASTER_BASE_ADDR = 0x40072200UL; +#endif + +/*!< @brief SPI pin structure. */ +typedef struct { + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint8_t af; +} hal_ll_spi_master_pin_map_t; + +/*!< SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_sck_map[] = { + #ifdef SPI0_SCK_P102_AF6 + {GPIO_P102, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_0 ), 6}, + #endif + #ifdef SPI1_SCK_P111_AF6 + {GPIO_P111, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_1 ), 6}, + #endif + #ifdef SPI1_SCK_P204_AF6 + {GPIO_P204, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_1 ), 6}, + #endif + #ifdef SPI0_SCK_P412_AF6 + {GPIO_P412, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_0 ), 6}, + #endif + + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_miso_map[] = { + #ifdef SPI0_MISO_P100_AF6 + {GPIO_P100, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_0 ), 6}, + #endif + #ifdef SPI1_MISO_P110_AF6 + {GPIO_P110, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_1 ), 6}, + #endif + #ifdef SPI0_MISO_P410_AF6 + {GPIO_P410, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_0 ), 6}, + #endif + #ifdef SPI1_MISO_P202_AF6 + {GPIO_P202, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_1 ), 6}, + #endif + + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_mosi_map[] = { + #ifdef SPI0_MOSI_P101_AF6 + {GPIO_P101, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_0 ), 6}, + #endif + #ifdef SPI1_MOSI_P109_AF6 + {GPIO_P109, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_1 ), 6}, + #endif + #ifdef SPI0_MOSI_P411_AF6 + {GPIO_P411, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_0 ), 6}, + #endif + #ifdef SPI1_MOSI_P203_AF6 + {GPIO_P203, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_1 ), 6}, + #endif + + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim.h b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim.h new file mode 100644 index 0000000000..aa8917ad30 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim.h @@ -0,0 +1,211 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.h + * @brief Brief file description. + */ + +#ifndef _HAL_LL_TIM_H_ +#define _HAL_LL_TIM_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" + +/** + * TIM modules + */ +typedef enum { + HAL_LL_TIM_MODULE_DEFAULT = 0xFF, + #if defined(TIM_MODULE_0) + HAL_LL_TIM_MODULE_0 = 0, + #endif + #if defined(TIM_MODULE_1) + HAL_LL_TIM_MODULE_1 = 1, + #endif + #if defined(TIM_MODULE_2) + HAL_LL_TIM_MODULE_2 = 2, + #endif + #if defined(TIM_MODULE_3) + HAL_LL_TIM_MODULE_3 = 3, + #endif + #if defined(TIM_MODULE_4) + HAL_LL_TIM_MODULE_4 = 4, + #endif + #if defined(TIM_MODULE_5) + HAL_LL_TIM_MODULE_5 = 5, + #endif + #if defined(TIM_MODULE_6) + HAL_LL_TIM_MODULE_6 = 6, + #endif + #if defined(TIM_MODULE_7) + HAL_LL_TIM_MODULE_7 = 7, + #endif + HAL_LL_TIM_MODULE_NONE +} hal_ll_tim_module_number_t; + +/** + * @brief TIMER HAL low lever handle register. + */ +typedef struct { + handle_t *hal_ll_tim_handle; + handle_t *hal_drv_tim_handle; + bool init_ll_state; +} hal_ll_tim_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] pin TIM pin. + * @param[out] handle_map HAL layer local handle map. + * @param[out] hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, + hal_ll_tim_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ); + +/** + * @brief Enables counter for TIM module. + * + * Initializes TIM module on hardware level, if not already initialized and + * starts TIM module. + * + * @param[in] handle TIM handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_start( handle_t *handle ); + +/** + * @brief Stops counter for TIM module. + * + * The TIM Module needs to be initialized so that + * the stop can be done. + * + * @param[in] handle TIM handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ); + +/** + * @brief Set TIM frequency in Hertz. + * + * This function is used to set the TIM frequency, it + * stops TIM module and sets duty_cycle on 0. + * Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param[in] handle TIM handle. + * @param[in] freq_hz TIM frequency in hz. + * + * @return This function returns the frequency value in hz, + * to which the PWM module is set. + * + * @note If the frequency value is less than allowed, + * the frequency will be set to the lowest possible value for the specified TIM. + */ +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ); + +/** + * @brief Set TIM duty cycle in percentages. + * + * The user should enter the duty_ratio in percentages. + * The dut_ratio value should be between 0 and 1 + * (where 0 represents 0% and 1 represents 100%). + * + * @param[in] handle TIM handle. + * @param[in] duty_ratio TIM duty ratio in percentages. + * + * @return hal_ll_err_t Module specific error. + * + * @note Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ); + +/** + * @brief Closes TIM master HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] handle TIM handle. + * + * @return void None. + */ +void hal_ll_tim_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h new file mode 100644 index 0000000000..759b753669 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h @@ -0,0 +1,274 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Macro defining `weak` attribute */ +#define __weak __attribute__((weak)) +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief TIMER module base addresses. */ +#ifdef TIM_MODULE_0 +static const hal_ll_base_addr_t HAL_LL_TIM0_BASE_ADDR = 0x40078000UL; +#endif +#ifdef TIM_MODULE_1 +static const hal_ll_base_addr_t HAL_LL_TIM1_BASE_ADDR = 0x40078100UL; +#endif +#ifdef TIM_MODULE_2 +static const hal_ll_base_addr_t HAL_LL_TIM2_BASE_ADDR = 0x40078200UL; +#endif +#ifdef TIM_MODULE_3 +static const hal_ll_base_addr_t HAL_LL_TIM3_BASE_ADDR = 0x40078300UL; +#endif +#ifdef TIM_MODULE_4 +static const hal_ll_base_addr_t HAL_LL_TIM4_BASE_ADDR = 0x40078400UL; +#endif +#ifdef TIM_MODULE_5 +static const hal_ll_base_addr_t HAL_LL_TIM5_BASE_ADDR = 0x40078500UL; +#endif +#ifdef TIM_MODULE_6 +static const hal_ll_base_addr_t HAL_LL_TIM6_BASE_ADDR = 0x40078600UL; +#endif +#ifdef TIM_MODULE_7 +static const hal_ll_base_addr_t HAL_LL_TIM7_BASE_ADDR = 0x40078700UL; +#endif +#ifdef TIM_MODULE_8 +static const hal_ll_base_addr_t HAL_LL_TIM8_BASE_ADDR = 0x40078800UL; +#endif +#ifdef TIM_MODULE_9 +static const hal_ll_base_addr_t HAL_LL_TIM9_BASE_ADDR = 0x40078900UL; +#endif +#ifdef TIM_MODULE_10 +static const hal_ll_base_addr_t HAL_LL_TIM10_BASE_ADDR = 0x40078A00UL; +#endif +#ifdef TIM_MODULE_11 +static const hal_ll_base_addr_t HAL_LL_TIM11_BASE_ADDR = 0x40078B00UL; +#endif +#ifdef TIM_MODULE_12 +static const hal_ll_base_addr_t HAL_LL_TIM12_BASE_ADDR = 0x40078C00UL; +#endif +#ifdef TIM_MODULE_13 +static const hal_ll_base_addr_t HAL_LL_TIM13_BASE_ADDR = 0x40078D00UL; +#endif + +typedef enum { + HAL_LL_TIM_PIN_A = 0, + HAL_LL_TIM_PIN_B +} hal_ll_tim_pin_type_t; + +/*!< @brief TIM pin structure. */ +typedef struct { + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t af; + hal_ll_pin_name_t module_index; + hal_ll_tim_pin_type_t pin_type; +} hal_ll_tim_pin_map_t; + +/*!< TIM pins. */ +static const hal_ll_tim_pin_map_t hal_ll_tim_pin_map[] = { + #ifdef TIM0_P108_CHB_AF3 + {GPIO_P108, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM0_P212_CHB_AF3 + {GPIO_P212, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM0_P213_CHA_AF3 + {GPIO_P213, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM0_P300_CHA_AF3 + {GPIO_P300, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM1_P109_CHA_AF3 + {GPIO_P109, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM1_P110_CHB_AF3 + {GPIO_P110, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM2_P102_CHB_AF3 + {GPIO_P102, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM3_P111_CHA_AF3 + {GPIO_P111, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM3_P112_CHB_AF3 + {GPIO_P112, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM4_P301_CHB_AF3 + {GPIO_P301, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM5_P100_CHB_AF3 + {GPIO_P100, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM5_P101_CHA_AF3 + {GPIO_P101, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM5_P408_CHB_AF3 + {GPIO_P408, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM0_P106_CHB_AF3 + {GPIO_P106, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM0_P107_CHA_AF3 + {GPIO_P107, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM1_P104_CHB_AF3 + {GPIO_P104, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM1_P105_CHA_AF3 + {GPIO_P105, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM2_P103_CHA_AF3 + {GPIO_P103, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM2_P113_CHA_AF3 + {GPIO_P113, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM2_P500_CHA_AF3 + {GPIO_P500, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM2_P501_CHB_AF3 + {GPIO_P501, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM3_P502_CHB_AF3 + {GPIO_P502, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM4_P204_CHB_AF3 + {GPIO_P204, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM4_P205_CHA_AF3 + {GPIO_P205, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM4_P302_CHA_AF3 + {GPIO_P302, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM5_P409_CHA_AF3 + {GPIO_P409, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM6_P400_CHA_AF3 + {GPIO_P400, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM6_P401_CHB_AF3 + {GPIO_P401, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM6_P410_CHB_AF3 + {GPIO_P410, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM6_P411_CHA_AF3 + {GPIO_P411, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM7_P303_CHB_AF3 + {GPIO_P303, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM7_P304_CHA_AF3 + {GPIO_P304, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM0_P414_CHB_AF3 + {GPIO_P414, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM0_P415_CHA_AF3 + {GPIO_P415, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM1_P405_CHA_AF3 + {GPIO_P405, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM1_P406_CHB_AF3 + {GPIO_P406, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM2_P114_CHB_AF3 + {GPIO_P114, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM3_P403_CHA_AF3 + {GPIO_P403, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM3_P404_CHB_AF3 + {GPIO_P404, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM4_P115_CHA_AF3 + {GPIO_P115, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM4_P608_CHB_AF3 + {GPIO_P608, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM5_P202_CHB_AF3 + {GPIO_P202, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM5_P203_CHA_AF3 + {GPIO_P203, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM5_P609_CHA_AF3 + {GPIO_P609, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM5_P610_CHB_AF3 + {GPIO_P610, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM6_P600_CHB_AF3 + {GPIO_P600, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM6_P601_CHA_AF3 + {GPIO_P601, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM7_P602_CHB_AF3 + {GPIO_P602, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM7_P603_CHA_AF3 + {GPIO_P603, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_A}, + #endif + + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h new file mode 100644 index 0000000000..b94cda84fe --- /dev/null +++ b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h @@ -0,0 +1,329 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.h + * @brief API for UART HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_UART_H_ +#define _HAL_LL_UART_H_ + +#include "hal_ll_target.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief Interrupt request type enum. + */ +typedef enum +{ + HAL_LL_UART_IRQ_RX, /**< RX INT */ + HAL_LL_UART_IRQ_TX /**< TX INT */ +} hal_ll_uart_irq_t; + +/** + * @brief Pointer to interrupt handler function. + */ +typedef void ( *hal_ll_uart_isr_t )( handle_t handle, hal_ll_uart_irq_t event ); + +/** + * @brief Predefined enum values for parity selection. + */ +typedef enum +{ + HAL_LL_UART_PARITY_NONE = 0, + HAL_LL_UART_PARITY_EVEN, + HAL_LL_UART_PARITY_ODD, + + HAL_LL_UART_PARITY_DEFAULT = HAL_LL_UART_PARITY_NONE +} hal_ll_uart_parity_t; + +/** + * @brief Predefined enum values for stop bit selection. + */ +typedef enum +{ + HAL_LL_UART_STOP_BITS_HALF = 0, + HAL_LL_UART_STOP_BITS_ONE, + HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF, + HAL_LL_UART_STOP_BITS_TWO, + + HAL_LL_UART_STOP_BITS_DEFAULT = HAL_LL_UART_STOP_BITS_ONE +} hal_ll_uart_stop_bits_t; + +/** + * @brief Predefined enum values for data bit selection. + */ +typedef enum +{ + HAL_LL_UART_DATA_BITS_5 = -2, + HAL_LL_UART_DATA_BITS_6, + HAL_LL_UART_DATA_BITS_7, + HAL_LL_UART_DATA_BITS_8, + HAL_LL_UART_DATA_BITS_9, + + HAL_LL_UART_DATA_BITS_DEFAULT = HAL_LL_UART_DATA_BITS_8 +} hal_ll_uart_data_bits_t; + +/** + * @brief UART low level pins config structure. + * + * The context structure for storing low level pin configuration + * for both TX and RX pins. + * + */ +typedef struct +{ + hal_ll_pin_af_t tx_pin; + hal_ll_pin_af_t rx_pin; +} hal_ll_uart_pins_t; + +/** + * @brief UART low level handle. + * + * The context for storing low level object handler. + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + handle_t *hal_ll_uart_handle; + handle_t *hal_drv_uart_handle; + bool init_ll_state; +} hal_ll_uart_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] tx_pin UART TX pin. + * @param[in] rx_pin UART RX pin. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, + hal_ll_pin_name_t rx_pin, + hal_ll_uart_handle_register_t *handle_map, + uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ); + +/** + * @brief Registers interrupt handlers for future use. + * + * Registers low level interrupt handlers + * for use with appropriate functions. + * + * @param[in] handle HAL context object handle. + * @param[in] handler Predefined pointer function. + * @param[in] obj HAL context handle address. + + * @return None. + */ +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ); + +/** + * @brief Sets desired baud rate. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] handle HAL context object handle. + * @param[in] baud Desired baud rate value in Bits/s. + * + * @return Actual baud rate value the hw module was initialized to, + * or module specific error value if init failed. + */ +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ); + +/** + * @brief Sets desired parity. + * + * Initializes module with specified parity value. + * + * @param[in] handle HAL context object handle. + * @param[in] parity One of pre-defined values. + * + * @return Re-init module state. If neccessary. + */ +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module with specified stop bits value. + * + * @param[in] handle HAL context object handle. + * @param[in] stop_bit One of pre-defined values. + * + * @return Re-init module state. If neccessary. + */ +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ); + +/** + * @brief Sets desired data bits. + * + * Initializes module with specified data bits value. + * + * @param[in] handle HAL context object handle. + * @param[in] data_bit One of pre-defined values. + * + * @return Re-init module state. If neccessary. + */ +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ); + +/** + * @brief Enables module specific interrupt. + * + * Enables module specific interrupt and registers + * interrupt on hardware level and enables it. + * + * @param[in] handle HAL context object handle. + * @param[in] irq Chip interrupt IRQ value. + * + * @return void None. + */ +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ); + +/** + * @brief Disables module specific interrupt. + * + * Disables module specific interrupt. + * + * @param[in] handle HAL context object handle. + * @param[in] irq Chip interrupt IRQ value. + * + * @return void None. + */ +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ); + +/** + * @brief Performs read operation. + * + * Reads one byte on a hardware level. + * + * @param[in] handle HAL context object handle. + * + * @return uint8_t Data read from hw register. + */ +uint8_t hal_ll_uart_read( handle_t *handle ); + +/** + * @brief Performs read operation in polling mode. + * + * Reads one byte on a hardware level. + * + * @param[in] handle HAL context object handle. + * + * @return uint8_t Data read from hw register. + */ +uint8_t hal_ll_uart_read_polling( handle_t *handle ); + +/** + * @brief Performs write operation. + * + * Accesses hardware data registers and + * writes data directly to it. + * + * @param[in] handle HAL context object handle. + * @param[in] wr_data Data to be written. + * + * @return void None. + */ +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data); + +/** + * @brief Performs write operation in polling mode. + * + * Accesses hardware data registers and + * writes data directly to it. + * + * @param[in] handle HAL context object handle. + * @param[in] wr_data Data to be written. + * + * @return void None. + */ +void hal_ll_uart_write_polling( handle_t *handle, uint8_t wr_data); + +/** + * @brief Closes UART HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_uart_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h new file mode 100644 index 0000000000..b70aa4f0df --- /dev/null +++ b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h @@ -0,0 +1,194 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Macro defining `weak` attribute */ +#define __weak __attribute__((weak)) +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) + +/*!< @brief UART module base addresses */ +#ifdef UART_MODULE_0 +static const hal_ll_base_addr_t HAL_LL_UART0_BASE_ADDRESS = 0x40070000UL; +#endif +#ifdef UART_MODULE_1 +static const hal_ll_base_addr_t HAL_LL_UART1_BASE_ADDRESS = 0x40070020UL; +#endif +#ifdef UART_MODULE_2 +static const hal_ll_base_addr_t HAL_LL_UART2_BASE_ADDRESS = 0x40070040UL; +#endif +#ifdef UART_MODULE_3 +static const hal_ll_base_addr_t HAL_LL_UART3_BASE_ADDRESS = 0x40070060UL; +#endif +#ifdef UART_MODULE_4 +static const hal_ll_base_addr_t HAL_LL_UART4_BASE_ADDRESS = 0x40070080UL; +#endif +#ifdef UART_MODULE_5 +static const hal_ll_base_addr_t HAL_LL_UART5_BASE_ADDRESS = 0x400700A0UL; +#endif +#ifdef UART_MODULE_6 +static const hal_ll_base_addr_t HAL_LL_UART6_BASE_ADDRESS = 0x400700C0UL; +#endif +#ifdef UART_MODULE_7 +static const hal_ll_base_addr_t HAL_LL_UART7_BASE_ADDRESS = 0x400700E0UL; +#endif +#ifdef UART_MODULE_8 +static const hal_ll_base_addr_t HAL_LL_UART8_BASE_ADDRESS = 0x40070100UL; +#endif +#ifdef UART_MODULE_9 +static const hal_ll_base_addr_t HAL_LL_UART9_BASE_ADDRESS = 0x40070120UL; +#endif + + +/*!< @brief UART pin structure. */ +typedef struct { + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t af; +} hal_ll_uart_pin_map_t; + +/*!< UART TX Pins. */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { + #ifdef UART0_TX_P101_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P101, HAL_LL_UART0_BASE_ADDRESS, 4}, + #endif + #ifdef UART1_TX_P213_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P213, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif + #ifdef UART2_TX_P102_AF4 + {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P102, HAL_LL_UART2_BASE_ADDRESS, 4}, + #endif + #ifdef UART2_TX_P112_AF4 + {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P112, HAL_LL_UART2_BASE_ADDRESS, 4}, + #endif + #ifdef UART9_TX_P109_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P109, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif + #ifdef UART0_TX_P205_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P205, HAL_LL_UART0_BASE_ADDRESS, 4}, + #endif + #ifdef UART0_TX_P411_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P411, HAL_LL_UART0_BASE_ADDRESS, 4}, + #endif + #ifdef UART1_TX_P401_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P401, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif + #ifdef UART1_TX_P501_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P501, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif + #ifdef UART2_TX_P302_AF4 + {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P302, HAL_LL_UART2_BASE_ADDRESS, 4}, + #endif + #ifdef UART9_TX_P409_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P409, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif + #ifdef UART9_TX_P203_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P203, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif + #ifdef UART9_TX_P602_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P602, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +/*!< UART RX Pins. */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = { + #ifdef UART0_RX_P100_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P100, HAL_LL_UART0_BASE_ADDRESS, 4}, + #endif + #ifdef UART1_RX_P212_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P212, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif + #ifdef UART2_RX_P301_AF4 + {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P301, HAL_LL_UART2_BASE_ADDRESS, 4}, + #endif + #ifdef UART9_RX_P110_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P110, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif + #ifdef UART9_RX_P408_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P408, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif + #ifdef UART0_RX_P104_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P104, HAL_LL_UART0_BASE_ADDRESS, 4}, + #endif + #ifdef UART0_RX_P206_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P206, HAL_LL_UART0_BASE_ADDRESS, 4}, + #endif + #ifdef UART0_RX_P410_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P410, HAL_LL_UART0_BASE_ADDRESS, 4}, + #endif + #ifdef UART1_RX_P402_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P402, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif + #ifdef UART1_RX_P502_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P502, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif + #ifdef UART1_RX_P708_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P708, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif + #ifdef UART9_RX_P202_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P202, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif + #ifdef UART9_RX_P601_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P601, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt b/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt new file mode 100644 index 0000000000..7ce0824264 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt @@ -0,0 +1,62 @@ +## ./targets/arm/mikroe/renesas/src/adc/CMakeLists.txt +set(hal_ll_def_list "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +# BEGIN ADC +list(APPEND hal_ll_def_list "MACRO_USAGE_ADC") +list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +set(adc_subimplementation "implementation_1/hal_ll_adc.c") +set(adc_pin_map "hal_ll_adc_pin_map/implementation_1") +# END ADC + +mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC + ${adc_subimplementation} + ../../include/hal_ll_mstpcr.h + ../../include/hal_ll_target.h +#BEGIN ADC + ../../include/adc/hal_ll_adc.h + ../../include/adc/${adc_pin_map}/hal_ll_adc_pin_map.h +#END ADC +) + +target_compile_definitions(lib_hal_ll_adc PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_adc PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_adc + PRIVATE + ../../include + ../../include/gpio + #BEGINADC + ../../include/adc + ../../include/adc/${adc_pin_map} + #ENDADC + INTERFACE + $ + $ + $ + $ + + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.ADC) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.ADC ../../include/adc/hal_ll_adc.h) diff --git a/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c new file mode 100644 index 0000000000..d33d03225d --- /dev/null +++ b/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c @@ -0,0 +1,471 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" +#include "hal_ll_mstpcr.h" + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base + +/*!< @brief Helper macro for getting adequate module index number. */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_ADCER_ADPCR_MASK (0x6UL) +#define HAL_LL_ADC_ADCER_ADPCR_12_bit (0) +#define HAL_LL_ADC_ADCER_ADPCR_14_bit (3) +#define HAL_LL_ADC_ADCSR_ADCS_MASK (0x6000UL) +#define HAL_LL_ADC_ADCSR_ADCS_SINGLE_SCAN (0) +#define HAL_LL_ADC_ADCSR_ADST (15) +#define HAL_LL_ADC0_ADHVREFCNT_HVSEL_MASK (0x3UL) +#define HAL_LL_ADC0_ADHVREFCNT_HVSEL_VREFH0 (0x1UL) +#define HAL_LL_ADC0_ADHVREFCNT_HVSEL_INTERNAL (0x2UL) + +#define HAL_LL_ADC0_ADHVREFCNT_REG_ADDR ((uint8_t *)0x4005C08AUL) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list. */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ ADC_MODULE_COUNT ] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/*!< @brief ADC register structure. */ +typedef struct { + volatile uint16_t adcsr; + volatile uint8_t adref; + volatile uint8_t adexref; + volatile uint16_t adansa[2]; + volatile uint16_t adads[2]; + volatile uint8_t adadc; + volatile uint8_t reserved; + volatile uint16_t adcer; + volatile uint16_t adstrgr; + volatile uint16_t adexicr; + volatile uint16_t adansb[2]; + volatile uint16_t addbldr; + volatile uint16_t adtsdr; + volatile uint16_t adocdr; + volatile uint16_t adrd; + volatile uint16_t addr[29]; + // Other registers may be present, but are not used in this implementation. +} hal_ll_adc_base_handle_t; + +/** + * Return values. + */ +typedef enum { + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +/*!< @brief ADC hw specific module values. */ +typedef struct { + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +// ---------------------------------------------------------- PRIVATE VARIABLES +/** + * @brief Array of maps holding information for configuring hardware. + */ +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[ADC_MODULE_COUNT + 1] = { + #ifdef ADC_MODULE_0 + {HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_PIN_NC, + HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, + 0, HAL_LL_ADC_RESOLUTION_DEFAULT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Check if pins are adequate. + * @Details Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, + hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * @details Maps pin name, register address and channel from + * analog register list to module in hardware specific map. + * @param[in] module_index ADC HW module index -- 0,1,2... Index in hal_ll_adc_hw_specifics_map, + * destination of copying. + * @param[in] index Pointer with ADC pin map index value. Index in hal_ll_analog_in_register_list + * source of copying information + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Get local hardware specific map. + * @details Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array element. + * @param[in] handle - Object specific context handler. + * @return address of a member in hal_ll_adc_hw_specifics_map, either a correct member + * or an 'error' terminating member in map. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Initialize hardware ADC module. + * @details ADC hardware initialization. + * @param *map - ADC module local map, pointer to a + * member in hal_ll_adc_hw_specifics_map global array. + * @return None + */ +static void hal_ll_adc_hw_init(hal_ll_adc_hw_specifics_map_t *map); + +/** + * @brief Initialize ADC module @p map. + * @details from @p map, uses pin information to set it as analog & sets + * @param[in] *map - ADC module local map, pointer to a + * member in hal_ll_adc_hw_specifics_map global array. + * @return None. + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, + hal_ll_adc_voltage_reference_t vref_input, + hal_ll_adc_resolution_t resolution, + hal_ll_adc_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + uint16_t pin_check_result; + hal_ll_adc_pin_id index = { HAL_LL_PIN_NC }; + + if (( pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + } + + switch ( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_ADC_12BIT_RES_VAL; + break; + case HAL_LL_ADC_RESOLUTION_14_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_ADC_14BIT_RES_VAL; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_EXTERNAL; + break; + case HAL_LL_ADC_VREF_INTERNAL: + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_INTERNAL; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[ pin_check_result ].pin != pin ) { + hal_ll_adc_map_pin( pin_check_result, &index ); + handle_map[ pin_check_result ].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_adc_handle = + ( handle_t* )&hal_ll_adc_hw_specifics_map[ pin_check_result ].base; + handle_map[ pin_check_result ].hal_ll_adc_handle = + ( handle_t* )&hal_ll_module_state[ pin_check_result ].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) { + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_adc_handle = + ( handle_t* )&hal_ll_adc_hw_specifics_map[ pin_check_result ].base; + + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution( handle_t *handle, hal_ll_adc_resolution_t resolution ) { + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); + + if( NULL == low_level_handle->hal_ll_adc_handle ) { + return HAL_LL_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + switch ( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_ADC_12BIT_RES_VAL; + break; + case HAL_LL_ADC_RESOLUTION_14_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_ADC_16BIT_RES_VAL; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input( handle_t *handle, hal_ll_adc_voltage_reference_t vref_input ) { + hal_ll_adc_handle_register_t *low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); + + if( low_level_handle->hal_ll_adc_handle == NULL ) { + return HAL_LL_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_EXTERNAL; + break; + case HAL_LL_ADC_VREF_INTERNAL: + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_INTERNAL; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value( handle_t *handle, float vref_value ) { + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); + + if( low_level_handle->hal_ll_adc_handle != NULL ) { + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; + } +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) { + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base; + + if( NULL == low_level_handle->hal_ll_adc_handle ) { + return HAL_LL_MODULE_ERROR; + } + + // Single scan mode. + base->adcsr &= ~HAL_LL_ADC_ADCSR_ADCS_MASK; + base->adcsr |= HAL_LL_ADC_ADCSR_ADCS_SINGLE_SCAN; + + // Start conversion. + set_reg_bit( &base->adcsr, HAL_LL_ADC_ADCSR_ADST); + + *readDatabuf = ( uint16_t )base->addr[ hal_ll_adc_hw_specifics_map_local->channel ]; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) { + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = + hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, + hal_ll_adc_pin_id *index, + hal_ll_adc_handle_register_t *handle_map ) { + static const uint16_t adc_map_size = + ( sizeof( hal_ll_analog_in_register_list ) / sizeof( hal_ll_pin_channel_list_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == hal_ll_analog_in_register_list[pin_index].pin ) + { + // Get module number + hal_ll_module_id = hal_ll_analog_in_register_list[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = + hal_ll_analog_in_register_list[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = + hal_ll_analog_in_register_list[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = + sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_adc_handle_register_t )); + static uint8_t hal_ll_module_error = + sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_adc_handle_register_t )); + + while( hal_ll_module_count-- ) { + if ( hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[ hal_ll_module_count ].base ) { + return &hal_ll_adc_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_adc_hw_specifics_map[ hal_ll_module_error ]; +} + +static void hal_ll_adc_hw_init( hal_ll_adc_hw_specifics_map_t *map ) { + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t* )hal_ll_adc_get_base_struct( map->base ); + + // Select channel. + if( 0 <= map->channel && 14 >= map->channel ) + set_reg_bit( &base->adansa[0], map->channel ); + else if( 16 <= map->channel && 25 >= map->channel ) + set_reg_bit( &base->adansa[1], map->channel - 16 ); + + // Resolution settings. NOTE: The only supported resolutions are 12-bit and 14-bit. + base->adcer &= ~HAL_LL_ADC_ADCER_ADPCR_MASK; + if( HAL_ADC_12BIT_RES_VAL == map->resolution ) + base->adcer |= HAL_LL_ADC_ADCER_ADPCR_12_bit; + else if( HAL_ADC_14BIT_RES_VAL == map->resolution ) + base->adcer |= HAL_LL_ADC_ADCER_ADPCR_14_bit; + + // Voltage reference settings. + clear_reg_bits( HAL_LL_ADC0_ADHVREFCNT_REG_ADDR, HAL_LL_ADC0_ADHVREFCNT_HVSEL_MASK); + if( HAL_LL_ADC_VREF_EXTERNAL == map->vref_input ) + set_reg_bits( HAL_LL_ADC0_ADHVREFCNT_REG_ADDR, HAL_LL_ADC0_ADHVREFCNT_HVSEL_VREFH0 ); + else if( HAL_LL_ADC_VREF_INTERNAL == map->vref_input ) { + set_reg_bits( HAL_LL_ADC0_ADHVREFCNT_REG_ADDR, HAL_LL_ADC0_ADHVREFCNT_HVSEL_MASK ); + Delay_us(5); // Documentation specifies a small delay is required. + set_reg_bits( HAL_LL_ADC0_ADHVREFCNT_REG_ADDR, HAL_LL_ADC0_ADHVREFCNT_HVSEL_INTERNAL ); + } +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + // Enable ADC operation. + clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD16_POS ); + + hal_ll_adc_hw_init( map ); +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt b/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt new file mode 100644 index 0000000000..c82627ab60 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt @@ -0,0 +1,63 @@ +## ./targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt +set(hal_ll_def_list "") +set(MCU_NAME_FIRST_7 "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) +string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) +list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +# BEGIN GPIO +list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") +set(gpio_subimplementation "implementation_1/hal_ll_gpio_port.c") +# END GPIO + +mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO + # BEGIN GPIO + hal_ll_gpio.c + ${gpio_subimplementation} + # END GPIO + ../../include/hal_ll_target.h + ../../include/hal_ll_pin_names.h + # BEGIN GPIO + ../../include/gpio/hal_ll_gpio.h + ../../include/gpio/hal_ll_gpio_port.h + ../../include/gpio/hal_ll_gpio_constants.h + # END GPIO +) + +target_compile_definitions(lib_hal_ll_gpio PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_gpio PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_gpio + PRIVATE + ../../include + # BEGIN GPIO + ../../include/gpio + # END GPIO + + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.GPIO) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) diff --git a/targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c b/targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c new file mode 100644 index 0000000000..641f8ae6a1 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c @@ -0,0 +1,167 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio.c + * @brief GPIO HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio_port.h" + +/******************************************************************************* + * + */ +void hal_ll_gpio_configure_pin(hal_ll_gpio_pin_t *pin, hal_ll_pin_name_t name, hal_ll_gpio_direction_t direction) { + pin->base = (hal_ll_gpio_base_t)hal_ll_gpio_port_base(hal_ll_gpio_port_index(name)); + pin->mask = hal_ll_gpio_pin_mask(name); + + if ( direction == HAL_LL_GPIO_DIGITAL_INPUT) + hal_ll_gpio_digital_input(&pin->base, pin->mask); + else + hal_ll_gpio_digital_output(&pin->base, pin->mask); +} + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +uint8_t hal_ll_gpio_read_pin_input(hal_ll_gpio_pin_t *pin) { + uint8_t gpio_data_value; + + gpio_data_value = ((hal_ll_gpio_base_handle_t *)(pin->base))->pidr; + return (gpio_data_value & pin->mask) ? 0x01 : 0x00; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +uint8_t hal_ll_gpio_read_pin_output(hal_ll_gpio_pin_t *pin) { + uint8_t gpio_data_value; + + gpio_data_value = ((hal_ll_gpio_base_handle_t *)(pin->base))->podr; + return (gpio_data_value & pin->mask) ? 0x01 : 0x00; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_write_pin_output(hal_ll_gpio_pin_t *pin, uint8_t value) { + if (value) + ((hal_ll_gpio_base_handle_t *)(pin->base))->podr |= pin->mask; + else + ((hal_ll_gpio_base_handle_t *)(pin->base))->podr &= ~pin->mask; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_toggle_pin_output(hal_ll_gpio_pin_t *pin) { + uint8_t gpio_data_value = hal_ll_gpio_read_pin_output(pin); + hal_ll_gpio_write_pin_output(pin, !gpio_data_value); +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_set_pin_output(hal_ll_gpio_pin_t *pin) { + ((hal_ll_gpio_base_handle_t *)(pin->base))->podr |= pin->mask; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_clear_pin_output(hal_ll_gpio_pin_t *pin) { + ((hal_ll_gpio_base_handle_t *)(pin->base))->podr &= ~pin->mask; +} +#endif + +/******************************************************************************* + * + */ +void hal_ll_gpio_configure_port(hal_ll_gpio_port_t *port, hal_ll_port_name_t name, + hal_ll_gpio_mask_t mask, hal_ll_gpio_direction_t direction) { + port->base = hal_ll_gpio_port_base(name); + port->mask = mask; + + if (direction == HAL_LL_GPIO_DIGITAL_INPUT) + hal_ll_gpio_digital_input(&port->base, port->mask); + else + hal_ll_gpio_digital_output(&port->base, port->mask); +} + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +hal_ll_port_size_t hal_ll_gpio_read_port_input(hal_ll_gpio_port_t *port) { + uint8_t gpio_data_value; + return ((hal_ll_gpio_base_handle_t *)(port->base))->pidr & port->mask; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +hal_ll_port_size_t hal_ll_gpio_read_port_output(hal_ll_gpio_port_t *port) { + uint8_t gpio_data_value; + return ((hal_ll_gpio_base_handle_t *)(port->base))->podr & port->mask; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_write_port_output(hal_ll_gpio_port_t *port, hal_ll_port_size_t value) { + hal_ll_gpio_base_handle_t *base_reg = (hal_ll_gpio_base_handle_t *)port->base; + base_reg->podr = (uint32_t)(port->mask & value); +} +#endif + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c new file mode 100644 index 0000000000..064143f082 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c @@ -0,0 +1,333 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" + +#define hal_ll_gpio_port_get_pin_index(__index) ( ( uint8_t )__index & 0xF ) + +#define hal_ll_gpio_port_get_port_index(__index) ( ( uint8_t )( __index & 0xF0 ) >> 4 ) + +#ifdef GPIO_PORT_0 +#define GPIO_PORT0_BASE (0x40040000UL) +#endif +#ifdef GPIO_PORT_1 +#define GPIO_PORT1_BASE (0x40040020UL) +#endif +#ifdef GPIO_PORT_2 +#define GPIO_PORT2_BASE (0x40040040UL) +#endif +#ifdef GPIO_PORT_3 +#define GPIO_PORT3_BASE (0x40040060UL) +#endif +#ifdef GPIO_PORT_4 +#define GPIO_PORT4_BASE (0x40040080UL) +#endif +#ifdef GPIO_PORT_5 +#define GPIO_PORT5_BASE (0x400400A0UL) +#endif +#ifdef GPIO_PORT_6 +#define GPIO_PORT6_BASE (0x400400C0UL) +#endif +#ifdef GPIO_PORT_7 +#define GPIO_PORT7_BASE (0x400400E0UL) +#endif +#ifdef GPIO_PORT_8 +#define GPIO_PORT8_BASE (0x40040100UL) +#endif +#ifdef GPIO_PORT_9 +#define GPIO_PORT9_BASE (0x40040120UL) +#endif +#ifdef GPIO_PORT_PORT10 +#define GPIO_PORT10_BASE (0x40040140UL) +#endif +#ifdef GPIO_PORT_PORT11 +#define GPIO_PORT11_BASE (0x40040160UL) +#endif +#ifdef GPIO_PORT_PORT12 +#define GPIO_PORT12_BASE (0x40040180UL) +#endif +#ifdef GPIO_PORT_PORT13 +#define GPIO_PORT13_BASE (0x400401A0UL) +#endif +#ifdef GPIO_PORT_PORT14 +#define GPIO_PORT14_BASE (0x400401C0UL) +#endif + +#define PWPR_REGISTER_BASE (* ( volatile uint8_t * )0x40040D03UL) +#define PFS_REGISTER_ADDR (0x40040800UL) +#define PFS_PSEL_MASK (0x1F000000UL) + +/*!< @brief GPIO PORT array */ +static const uint32_t hal_ll_gpio_port_base_arr[] = +{ + #ifdef GPIO_PORT0_BASE + GPIO_PORT0_BASE, + #endif + #ifdef GPIO_PORT1_BASE + GPIO_PORT1_BASE, + #endif + #ifdef GPIO_PORT2_BASE + GPIO_PORT2_BASE, + #endif + #ifdef GPIO_PORT3_BASE + GPIO_PORT3_BASE, + #endif + #ifdef GPIO_PORT4_BASE + GPIO_PORT4_BASE, + #endif + #ifdef GPIO_PORT5_BASE + GPIO_PORT5_BASE, + #endif + #ifdef GPIO_PORT6_BASE + GPIO_PORT6_BASE, + #endif + #ifdef GPIO_PORT7_BASE + GPIO_PORT7_BASE, + #endif + #ifdef GPIO_PORT8_BASE + GPIO_PORT8_BASE, + #endif + #ifdef GPIO_PORT9_BASE + GPIO_PORT9_BASE, + #endif + #ifdef GPIO_PORT10_BASE + GPIO_PORT10_BASE, + #endif + #ifdef GPIO_PORT11_BASE + GPIO_PORT11_BASE, + #endif + #ifdef GPIO_PORT12_BASE + GPIO_PORT12_BASE, + #endif + #ifdef GPIO_PORT13_BASE + GPIO_PORT13_BASE, + #endif + #ifdef GPIO_PORT14_BASE + GPIO_PORT14_BASE + #endif +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +/** + * @brief Retrieve the index of the + * provided pin + * @param hal_ll_pin_name_t - pin + * @return uint8_t - the index of the pin + */ +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) { + uint16_t ret; + ret = hal_ll_gpio_port_get_port_index( name ); + return ret; +} + +uint16_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) { + uint16_t ret; + ret = ( 1UL << hal_ll_gpio_pin_index( name ) ); + return ret; +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) { + return hal_ll_gpio_port_base_arr[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) { + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) { + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) { + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) { + int32_t index = 0; + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +// ------------------------------------------------ STATIC FUNCTION DEFINITIONS + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) { + return hal_ll_gpio_port_get_pin_index( name ); +} + +static uint32_t hal_ll_gpio_get_port_number(uint32_t base_addr) +{ + for (int i = 0; i < sizeof(hal_ll_gpio_port_base_arr) / sizeof(hal_ll_gpio_port_base_arr[0]); i++) { + if (hal_ll_gpio_port_base_arr[i] == base_addr) { + return i; // Port number. + } + } + return -1; // Not found. +} + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) { + uint32_t pin_index = ( pin_mask == 0xFFFF ) ? 0xFFFF : __builtin_ctz(pin_mask); + hal_ll_port_name_t port_index; + port_index = hal_ll_gpio_get_port_number( *port ); + hal_ll_gpio_pfs_t *port_pfs_ptr = PFS_REGISTER_ADDR; + hal_ll_gpio_base_handle_t *port_ptr = (hal_ll_gpio_base_handle_t *) *port; + + // Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register. + PWPR_REGISTER_BASE &= ~0x80; // Clear B0WI bit + // Set 1 to the PFSWE bit in the PWPR register. This enables writing to the PmnPFS register. + PWPR_REGISTER_BASE |= 0x40; // Set PFSWE bit + + if ( pin_mask == 0xFFFF ) { + if ( config & GPIO_CFG_DIGITAL_OUTPUT ) + port_ptr->pdr = pin_mask; + else + port_ptr->pdr = 0; + } else { + // Clear the Port Mode Control bit in the PMR for the target pin to select the general I/O port. + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pmr = 0; + // Specify the input/output function for the pin through the PSEL[4:0] bit settings in the PmnPFS register. + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.psel = 0; + + if( config & GPIO_CFG_ANALOG_INPUT ) { + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pmr = 0; + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pdr = 0; + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.asel = 1; + } else if ( config & GPIO_CFG_DIGITAL_OUTPUT ) { + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pdr = 1; + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.asel = 0; + } else if ( config & GPIO_CFG_DIGITAL_INPUT ) { + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pdr = 0; + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.asel = 0; + } + + if( config & GPIO_CFG_PORT_PULL_UP_ENABLE ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pcr = 1; + + if( config & GPIO_CFG_NMOS_OPEN_DRAIN_ENABLE ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.ncodr = 1; + + if( config & GPIO_CFG_PORT_MIDDLE_DRIVE ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.dscr = 1; + + if( config & GPIO_CFG_EVENT_RISING_EDGE ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.eofr = 1; + + if( config & GPIO_CFG_EVENT_FALLING_EDGE ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.eofr = 2; + + if( config & GPIO_CFG_EVENT_BOTH_EDGES ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.eofr = 3; + + if( config & GPIO_CFG_IRQ_ENABLE ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.isel = 1; + + if( config & GPIO_CFG_PERIPHERAL_PIN ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pmr = 1; + + // Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register. + PWPR_REGISTER_BASE &= ~0x40; // Set PFSWE bit + // Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register + PWPR_REGISTER_BASE |= 0x80; // Set B0WI bit + } +} + +static void hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) { + uint8_t pin_index; + hal_ll_pin_name_t pin_name; + hal_ll_port_name_t port_name; + hal_ll_gpio_pfs_t *port_ptr = PFS_REGISTER_ADDR; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + pin_index = hal_ll_gpio_pin_index( pin_name ); + + port_name = hal_ll_gpio_port_index( module_pin & 0xFF ); + + hal_ll_gpio_config( (uint32_t *)&port_ptr, hal_ll_gpio_pin_mask( pin_index ), module_config ); + + // Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register. + PWPR_REGISTER_BASE &= ~0x80; // Clear B0WI bit + // Set 1 to the PFSWE bit in the PWPR register. This enables writing to the PmnPFS register. + PWPR_REGISTER_BASE |= 0x40; // Set PFSWE bit + + if ( true == state ) { + port_ptr->port[port_name].pin[pin_index].pmnpfs_b.psel = (( module_pin & 0xFF00 ) >> 8 ); + port_ptr->port[port_name].pin[pin_index].pmnpfs_b.pmr = 1; // Peripheral mode + } else { + port_ptr->port[port_name].pin[pin_index].pmnpfs_b.psel &= 0; + } + + // Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register. + PWPR_REGISTER_BASE &= ~0x40; // Set PFSWE bit + // Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register + PWPR_REGISTER_BASE |= 0x80; // Set B0WI bit +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt b/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt new file mode 100644 index 0000000000..79a55e1dfd --- /dev/null +++ b/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt @@ -0,0 +1,15 @@ +## ./targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt +add_library(lib_hal_ll INTERFACE) + +add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) + +set(module_list "") +set(module_list_supported "") +set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") + +target_link_libraries(lib_hal_ll INTERFACE + ${module_list} +) + +mikrosdk_install(MikroSDK.HalLowLevel) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_mstpcr.h ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) diff --git a/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt b/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt new file mode 100644 index 0000000000..1e0c7de59c --- /dev/null +++ b/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt @@ -0,0 +1,72 @@ +## ./targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +## BEGIN I2C +list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") +set(i2c_subimplementation "implementation_1/hal_ll_i2c_master.c") +set(i2c_pin_map "hal_ll_i2c_pin_map/implementation_1") +## END I2C + +# TSC2003 Special case +if (NOT DEFINED _MSDK_TFT_TP_) + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") +else() + if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") + list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") + else() + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") + endif() +endif() + +mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master + ${i2c_subimplementation} + + ../../include/hal_ll_mstpcr.h + ../../include/hal_ll_target.h +# BEGIN I2C + ../../include/i2c/hal_ll_i2c_master.h + ../../include/i2c/${i2c_pin_map}/hal_ll_i2c_pin_map.h +# END I2C +) + +target_compile_definitions(lib_hal_ll_i2c_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_i2c_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_i2c_master + PRIVATE + ../../include + ../../include/gpio + # BEGIN I2C + ../../include/i2c + ../../include/i2c/${i2c_pin_map} + # END I2C + + INTERFACE + $ + $ + $ + $ + $ + $ + ) + +mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h) diff --git a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c new file mode 100644 index 0000000000..397c6da9fc --- /dev/null +++ b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c @@ -0,0 +1,912 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" +#include "hal_ll_mstpcr.h" +#include "delays.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_PORT_PULL_UP_ENABLE |\ + GPIO_CFG_DIGITAL_OUTPUT |\ + GPIO_CFG_NMOS_OPEN_DRAIN_ENABLE |\ + GPIO_CFG_PERIPHERAL_PIN) + +/*!< @brief Bit positions and masks */ +#define HAL_LL_I2C_ICCR1_IICRST (6) +#define HAL_LL_I2C_ICCR1_ICE (7) +#define HAL_LL_I2C_ICCR2_BBSY (7) +#define HAL_LL_I2C_ICCR2_ST (1) +#define HAL_LL_I2C_ICCR2_SP (3) +#define HAL_LL_I2C_ICSR2_TDRE (7) +#define HAL_LL_I2C_ICSR2_NACKF (4) +#define HAL_LL_I2C_ICSR2_TEND (6) +#define HAL_LL_I2C_ICSR2_STOP (3) +#define HAL_LL_I2C_ICSR2_RDRF (5) +#define HAL_LL_I2C_ICMR3_WAIT (6) +#define HAL_LL_I2C_ICMR3_ACKBT (3) +#define HAL_LL_I2C_ICMR3_ACKWP (4) +#define HAL_LL_I2C_ICFER_SCLE (6) +#define HAL_LL_I2C_ICFER_NFE (5) +#define HAL_LL_I2C_ICMR1_CKS (4) +#define HAL_LL_I2C_ICMR1_CKS_DIV_1 (0) +#define HAL_LL_I2C_ICMR1_CKS_DIV_2 (1) +#define HAL_LL_I2C_ICMR1_CKS_DIV_4 (2) +#define HAL_LL_I2C_ICMR1_CKS_DIV_8 (3) +#define HAL_LL_I2C_ICMR1_CKS_DIV_16 (4) +#define HAL_LL_I2C_ICMR1_CKS_DIV_32 (5) +#define HAL_LL_I2C_ICMR1_CKS_DIV_64 (6) +#define HAL_LL_I2C_ICMR1_CKS_DIV_128 (7) + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K (100000UL) +#define HAL_LL_I2C_MASTER_SPEED_400K (400000UL) +#define HAL_LL_I2C_MASTER_SPEED_1M (1000000UL) +#define HAL_LL_I2C_MASTER_SPEED_3M2 (3200000UL) + +#define HAL_LL_I2C_DEFAULT_PASS_COUNT (10000) + +/*!< @brief I2C register structure */ +typedef struct { + uint8_t iccr1; + uint8_t iccr2; + uint8_t icmr1; + uint8_t icmr2; + uint8_t icmr3; + uint8_t icfer; + uint8_t icser; + uint8_t icier; + uint8_t icsr1; + uint8_t icsr2; + uint8_t sarl[3]; + uint8_t saru[3]; + uint8_t icbrl; + uint8_t icbrh; + uint8_t icdrt; + uint8_t icdrr; + uint8_t reserved[2]; + uint8_t icwur; + uint8_t icwur2; +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct { + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct { + uint32_t pin_scl; + uint32_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C end mode selection values */ +typedef enum { + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C hw specific error values */ +typedef enum { + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C timeout error values */ +typedef enum { + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT, + HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE +} hal_ll_i2c_master_timeout_t; + +/*!< @brief Enum containing predefined module standard speed values */ +typedef enum { + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[ I2C_MODULE_COUNT + 1 ] = { + #ifdef I2C_MODULE_0 + {HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), + {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 10000}, + HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), + {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 10000}, + HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, + {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @return None + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return None + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, + bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, + hal_ll_pin_name_t sda, + hal_ll_i2c_pin_id *index_list, + hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Waits until device is free to operate. + * + * Polls I2C busy bit value and waits until device has finished any + * on-going operation. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + */ +static hal_ll_err_t hal_ll_i2c_master_wait_for_idle( hal_ll_i2c_hw_specifics_map_t *map ) ; + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( uint32_t bit_rate ); + +/** + * @brief Set I2C speed registers based on clock and bit rate. + * + * Sets ICMR1, ICBRL, and ICBRH values based on the PCLKB clock + * and desired I2C speed (100kHz, 400kHz, or 1MHz). + * + * @param[in] *map - I2C hardware context. + * + * @note Supports only 24MHz and 32MHz PCLKB. + */ +static void hal_ll_i2c_calculate_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, + uint8_t *read_data_buf, + size_t len_read_data, + hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, + uint8_t *write_data_buf, + size_t len_write_data, + hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, + hal_ll_pin_name_t sda, + hal_ll_i2c_master_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = + (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = + (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_i2c_master_handle = + ( handle_t * )&hal_ll_i2c_hw_specifics_map[ pin_check_result ].base; + + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + + low_level_handle->init_ll_state = false; + hal_ll_i2c_hw_specifics_map_local->speed = hal_ll_i2c_get_speed( speed ); + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( HAL_LL_MODULE_ERROR != hal_ll_i2c_hw_specifics_map_local->base ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( HAL_LL_MODULE_ERROR != hal_ll_i2c_hw_specifics_map_local->base ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, + read_data_buf, + len_read_data, + HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, + write_data_buf, + len_write_data, + HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, + uint8_t *write_data_buf, + size_t len_write_data, + uint8_t *read_data_buf, + size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + + if( NULL != hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, + write_data_buf, + len_write_data, + HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( NULL != hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, + read_data_buf, + len_read_data, + HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( NULL != low_level_handle->hal_ll_i2c_master_handle ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, + uint8_t *write_data_buf, + size_t len_write_data, + hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + uint16_t time_counter = map->timeout; + + if( HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE == hal_ll_i2c_master_wait_for_idle( map )) { + return HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE; + } + + set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_ST ); + + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + write_reg( &hal_ll_hw_reg->icdrt, map->address << 1 ); + + time_counter = map->timeout; + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if( check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_NACKF )) + set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_SP ); + + time_counter = map->timeout; + for( uint8_t i = 0; i < len_write_data; i++ ) { + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + write_reg( &hal_ll_hw_reg->icdrt, write_data_buf[i] ); + } + + time_counter = map->timeout; + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TEND )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); + set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_SP ); + + time_counter = map->timeout; + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + set_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_NACKF ); + clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, + uint8_t *read_data_buf, + size_t len_read_data, + hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + uint16_t time_counter = map->timeout; + uint8_t dummy_read; + + if( HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE == hal_ll_i2c_master_wait_for_idle( map )) { + return HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE; + } + + set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_ST ); + + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + + write_reg( &hal_ll_hw_reg->icdrt, ( map->address << 1 ) | 1 ); + + time_counter = map->timeout; + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + + if( check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_NACKF )) { + // Error + clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); + set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_SP ); + dummy_read = read_reg( &hal_ll_hw_reg->icdrr ); + } else { + dummy_read = read_reg( &hal_ll_hw_reg->icdrr ); + if( 1 != len_read_data ) { + for( uint8_t i = 0; i < len_read_data - 2; i++ ) { + time_counter = map->timeout; + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[i] = read_reg( &hal_ll_hw_reg->icdrr ); + } + + time_counter = map->timeout; + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + + set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_ACKWP ); + set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_ACKBT ); + clear_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_ACKWP ); + set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_WAIT ); + + read_data_buf[len_read_data - 2] = read_reg( &hal_ll_hw_reg->icdrr ); + } + + time_counter = map->timeout; + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + + clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); + set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_SP ); + + read_data_buf[len_read_data - 1] = read_reg( &hal_ll_hw_reg->icdrr ); + clear_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_WAIT ); + } + + time_counter = map->timeout; + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + + clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_NACKF ); + clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, + bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = + hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = + hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, + // hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = + hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = + hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static uint32_t hal_ll_i2c_get_speed( uint32_t bit_rate ) { + if ( bit_rate <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( bit_rate <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + return HAL_LL_I2C_MASTER_SPEED_100K; + } else if ( bit_rate <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + return HAL_LL_I2C_MASTER_SPEED_400K; + } else if ( bit_rate <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + return HAL_LL_I2C_MASTER_SPEED_1M; + } else { + return HAL_LL_I2C_MASTER_SPEED_100K; + } + } else { + if ( bit_rate <= HAL_LL_I2C_MASTER_SPEED_100K ) { + return HAL_LL_I2C_MASTER_SPEED_100K; + } else if ( bit_rate <= HAL_LL_I2C_MASTER_SPEED_400K ) { + return HAL_LL_I2C_MASTER_SPEED_400K; + } else if ( bit_rate <= HAL_LL_I2C_MASTER_SPEED_1M ) { + return HAL_LL_I2C_MASTER_SPEED_1M; + } else { + return HAL_LL_I2C_MASTER_SPEED_1M; + } + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / + (sizeof( hal_ll_i2c_master_handle_register_t )); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / + (sizeof( hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if ( hal_ll_i2c_get_base_from_hal_handle == + hal_ll_i2c_hw_specifics_map[ hal_ll_module_count ].base ) { + return &hal_ll_i2c_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_i2c_hw_specifics_map[ hal_ll_module_error ]; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, + hal_ll_pin_name_t sda, + hal_ll_i2c_pin_id *index_list, + hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = + ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = + ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == + hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_err_t hal_ll_i2c_master_wait_for_idle( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + uint16_t time_counter = map->timeout; + + while( check_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_BBSY )) { + if( map->timeout ) { + if( !time_counter-- ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE; + } + } + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_calculate_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + + system_clocks_t system_clocks; + SYSTEM_GetClocksFrequency( &system_clocks ); + + uint32_t i2c_source_clock = system_clocks.pclkb; + + set_reg_bit( &hal_ll_hw_reg->icfer, HAL_LL_I2C_ICFER_SCLE ); + set_reg_bit( &hal_ll_hw_reg->icfer, HAL_LL_I2C_ICFER_NFE ); + + // TODO: Add bit rate calculation based on the formulas. + if ( 32000000 == i2c_source_clock ) { + if ( HAL_LL_I2C_MASTER_SPEED_1M == map->speed ) { + // 32MHz on PCLKB, 1Mbps I2C + write_reg( &hal_ll_hw_reg->icmr1, + ( HAL_LL_I2C_ICMR1_CKS_DIV_2 << HAL_LL_I2C_ICMR1_CKS )); + write_reg( &hal_ll_hw_reg->icbrl, 0xE3 ); + write_reg( &hal_ll_hw_reg->icbrh, 0xE4 ); + } else if ( HAL_LL_I2C_MASTER_SPEED_400K == map->speed ) { + // 32MHz on PCLKB, 400kbps I2C + write_reg( &hal_ll_hw_reg->icmr1, + ( HAL_LL_I2C_ICMR1_CKS_DIV_2 << HAL_LL_I2C_ICMR1_CKS )); + write_reg( &hal_ll_hw_reg->icbrl, 0xF0 ); + write_reg( &hal_ll_hw_reg->icbrh, 0xEF ); + } else { + // 32MHz on PCLKB, 100kbps I2C + write_reg( &hal_ll_hw_reg->icmr1, + ( HAL_LL_I2C_ICMR1_CKS_DIV_8 << HAL_LL_I2C_ICMR1_CKS )); + write_reg( &hal_ll_hw_reg->icbrl, 0xF2 ); + write_reg( &hal_ll_hw_reg->icbrh, 0xF0 ); + } + } else if ( 24000000 == i2c_source_clock ) { + if ( HAL_LL_I2C_MASTER_SPEED_1M == map->speed ) { + // 24MHz on PCLKB, 1Mbps I2C + write_reg( &hal_ll_hw_reg->icmr1, + ( HAL_LL_I2C_ICMR1_CKS_DIV_2 << HAL_LL_I2C_ICMR1_CKS )); + write_reg( &hal_ll_hw_reg->icbrl, 0xE2 ); + write_reg( &hal_ll_hw_reg->icbrh, 0xE2 ); + } else if ( HAL_LL_I2C_MASTER_SPEED_400K == map->speed ) { + // 24MHz on PCLKB, 400kbps I2C + write_reg( &hal_ll_hw_reg->icmr1, + ( HAL_LL_I2C_ICMR1_CKS_DIV_2 << HAL_LL_I2C_ICMR1_CKS )); + write_reg( &hal_ll_hw_reg->icbrl, 0xEA ); + write_reg( &hal_ll_hw_reg->icbrh, 0xEB ); + } else { + // 24MHz on PCLKB, 100kbps I2C + write_reg( &hal_ll_hw_reg->icmr1, + ( HAL_LL_I2C_ICMR1_CKS_DIV_4 << HAL_LL_I2C_ICMR1_CKS )); + write_reg( &hal_ll_hw_reg->icbrl, 0xFA ); + write_reg( &hal_ll_hw_reg->icbrh, 0xFB ); + } + } +} + +static void hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + + // I2C initialization + // Set the ICCR1.ICE bit set to 0 to set the SCLn and SDAn pins to the inactive state. + clear_reg_bit( &hal_ll_hw_reg->iccr1, HAL_LL_I2C_ICCR1_ICE ); + // Set the ICCR1.IICRST bit to 1 to initiate IIC reset. + set_reg_bit( &hal_ll_hw_reg->iccr1, HAL_LL_I2C_ICCR1_IICRST ); + // Set the ICCR1.ICE bit to 1 to initiate internal reset. + set_reg_bit( &hal_ll_hw_reg->iccr1, HAL_LL_I2C_ICCR1_ICE ); + + clear_reg( &hal_ll_hw_reg->icser ); +} + +static void hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + + // Enable IIC peripheral + if( hal_ll_i2c_module_num( I2C_MODULE_0 ) == map->module_index ) + clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB9_POS ); + else if( hal_ll_i2c_module_num( I2C_MODULE_1 ) == map->module_index ) + clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB8_POS ); + + hal_ll_i2c_hw_init( map ); + + hal_ll_i2c_calculate_speed( map ); + + // When the required register settings are complete, + // set the ICCR1.IICRST bit to 0 to release the IIC reset. + clear_reg_bit( &hal_ll_hw_reg->iccr1, HAL_LL_I2C_ICCR1_IICRST ); +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/one_wire/CMakeLists.txt b/targets/arm/mikroe/renesas/src/one_wire/CMakeLists.txt new file mode 100644 index 0000000000..0b7820f611 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/one_wire/CMakeLists.txt @@ -0,0 +1,31 @@ +## ./targets/arm/mikroe/renesas/src/one_wire/CMakeLists.txt +set(hal_ll_def_list "") +list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") + +mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire + hal_ll_one_wire.c + + ../../include/one_wire/hal_ll_one_wire.h) + +target_compile_definitions(lib_hal_ll_one_wire PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_one_wire PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.GPIO + MikroSDK.HalLowLevelCommon +) + +target_include_directories(lib_hal_ll_one_wire + PRIVATE + ../../include/one_wire + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.OneWire) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) diff --git a/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c b/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c new file mode 100644 index 0000000000..a7a4c8d7e8 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c @@ -0,0 +1,558 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_one_wire.c + * @brief One Wire HAL LOW LEVEL layer implementation. + */ +#include "hal_ll_one_wire.h" +#include "delays.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro getting minimum bits per transfer. */ +#define HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER (8) + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief Static array for selecting One Wire data bits. */ +static const uint8_t hal_ll_one_wire_selected_bit[ HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ] = { + 1, 2, 4, 8, 16, 32, 64, 128 +}; + +/*!< @brief Helper macro for starting to enumerate device ID(s). */ +static uint8_t hal_ll_one_wire_search_rom_command = ONE_WIRE_CMD_ROM_SEARCH; + +/*!< @brief Helper macro for reading a device ID. */ +static uint8_t hal_ll_one_wire_read_rom_command_legacy = ONE_WIRE_CMD_ROM_READ_LEGACY; +static uint8_t hal_ll_one_wire_read_rom_command = ONE_WIRE_CMD_ROM_READ; + +/*!< @brief Helper macro for ignoring a device ID. */ +static uint8_t hal_ll_one_wire_skip_rom_command = ONE_WIRE_CMD_ROM_SKIP; + +/*!< @brief Helper macro for selecting a device with specific ID. */ +static uint8_t hal_ll_one_wire_match_rom_command = ONE_WIRE_CMD_ROM_MATCH; + +/*!< @brief Helper flag if One Wire device is the last one left on the bus. */ +static uint8_t last_device_flag = 0; + +/*!< @brief Helper flag for last discrepancy. */ +static uint8_t last_discrepancy = 0; + +/*!< @brief Helper flag for last family discrepancy. */ +static uint8_t last_family_discrepancy = 0; + +/*!< @brief Helper instance consisting of hardware specifics. */ +static hal_ll_one_wire_local_t one_wire_handle; + +__weak void one_wire_timing_value_a( void ) { + Delay_6us(); +} + +__weak void one_wire_timing_value_b( void ) { + Delay_64us(); +} + +__weak void one_wire_timing_value_c( void ) { + Delay_60us(); +} + +__weak void one_wire_timing_value_d( void ) { + Delay_10us(); +} + +__weak void one_wire_timing_value_e( void ) { + Delay_9us(); +} + +__weak void one_wire_timing_value_f( void ) { + Delay_55us(); +} + +__weak void one_wire_timing_value_h( void ) { + Delay_480us(); +} + +__weak void one_wire_timing_value_i( void ) { + Delay_70us(); +} + +__weak void one_wire_timing_value_j( void ) { + Delay_410us(); +} +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Writes bit to One Wire bus. + * @details Writes bit to One Wire bus. + * @param[in] write_data_buffer Data transmit buffer. + */ +static void hal_ll_one_wire_write_bit( uint8_t write_data_buffer ); + +/** + * @brief Reads bit from One Wire bus. + * @details Reads bit from One Wire bus. + * @param[in] write_data_buffer Data receive buffer. + */ +static void hal_ll_one_wire_read_bit( uint8_t *read_data_buffer ); + +/** + * @brief Search One Wire capable device on bus. + * @details Search One Wire capable device on bus. + * + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @param[out] *one_wire_device_list Buffer for One Wire device ROM information. + */ +static hal_ll_err_t hal_ll_one_wire_search( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +void hal_ll_one_wire_open( hal_ll_one_wire_t *obj ) { + // Local instance of One Wire pin. + hal_ll_gpio_pin_t one_wire_pin; + + // Enable appropriate PORT clock, set pin to be digital output. + hal_ll_gpio_configure_pin( &one_wire_pin, obj->data_pin, HAL_LL_GPIO_DIGITAL_OUTPUT ); + + /* Enables appropriate PORT clock, configures pin to have digital output functionality, + * makes sure that HIGH voltage state is applied on pin before any One Wire actions. */ + hal_ll_one_wire_reconfigure( obj ); +} + +hal_ll_err_t hal_ll_one_wire_reset( hal_ll_one_wire_t *obj ) { + /* Variable for checking whether there are device(s) on + * One Wire data pin (0) or there aren't any devices at all (1). */ + uint16_t device_response = 1; + + // One Wire data pin mask. + uint16_t bit_location = 1ul << one_wire_handle.data_pin; + + // Make sure that pin has output capability. + *(uint16_t *)one_wire_handle.direction |= bit_location; + + // Set pin to LOW voltage level. + *(uint16_t *)one_wire_handle.output_clear |= bit_location; + + // Timing value for reset of One Wire bus - LOW voltage level. + one_wire_timing_value_h(); + + // Release pin ( pull-up resistor will do the rest (pull the data line up) ). + *(uint16_t *)one_wire_handle.direction &= ~(bit_location); + + // Timing value for reset of One Wire bus - Master sample pulse. + one_wire_timing_value_i(); + + // Check whether there are devices on One Wire data pin. + device_response = *(uint16_t *)one_wire_handle.input & bit_location; + + // Provide enough time for power injection into internal power logic of devices that are present. + one_wire_timing_value_j(); + + // Return final result of device response. + return device_response; +} + +hal_ll_err_t hal_ll_one_wire_read_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ) { + // Initiate Reset sequence. + if ( hal_ll_one_wire_reset( obj ) ) { + return HAL_LL_ONE_WIRE_ERROR; + } + + // Initiate "Read ROM" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_read_rom_command, 1 ); + + // Read ROM address. + hal_ll_one_wire_read_byte( &device_rom_address->address[0], 8 ); + + return HAL_LL_ONE_WIRE_SUCCESS; +} + +hal_ll_err_t hal_ll_one_wire_skip_rom( hal_ll_one_wire_t *obj ) { + // Initiate Reset sequence. + if ( hal_ll_one_wire_reset( obj ) ) { + return HAL_LL_ONE_WIRE_ERROR; + } + + // Initiate "Skip ROM" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_skip_rom_command, 1 ); + + return HAL_LL_ONE_WIRE_SUCCESS; +} + +hal_ll_err_t hal_ll_one_wire_match_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ) { + // Initiate Reset sequence. + if ( hal_ll_one_wire_reset( obj ) ) { + return HAL_LL_ONE_WIRE_ERROR; + } + + // Initiate "Match" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_match_rom_command, 1 ); + + // Send ROM address. + hal_ll_one_wire_write_byte( (uint32_t)device_rom_address, 8 ); + + return HAL_LL_ONE_WIRE_SUCCESS; +} + +static hal_ll_err_t hal_ll_one_wire_search( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) { + // Final search result variable. + uint8_t search_result = 0; + + // Initialize variables for search method. + uint8_t rom_byte_number = 0; + uint8_t rom_byte_mask = 1; + uint8_t id_bit_number = 1; + uint8_t last_zero = 0; + + // The first bit read in a bit search sequence. + // ( logical AND of all of the id_bit_number bits of the devices that are still participating in the search ). + uint8_t id_bit = 0; + + // The complement of id_bit. + // ( logical AND of the complement of all id_bit_number bits of the devices that are still participating in the search ). + uint8_t cmp_id_bit = 0; + + // Search direction ( bit-per-bit search ). + uint8_t search_direction = 0; + + // If the last call was not the last one... + if ( !last_device_flag ) { + + // If there were no any device while executing One Wire reset sequence... + if ( hal_ll_one_wire_reset( obj ) ) { + + // Reset all the important variables. + last_device_flag = 0; + last_discrepancy = 0; + last_family_discrepancy = 0; + + // Stop searching because there are no any One Wire capable devices. + return HAL_LL_ONE_WIRE_ERROR; + } + + // If device(s) has(have) been found, initiate "Search" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_search_rom_command, 1 ); + + // Iterate until all 64 bits (8 bytes) of unique ROM 'registration' numbers have not been found. + do { + // Read a bit. + hal_ll_one_wire_read_bit( &id_bit ); + + // Then, read its complement. + hal_ll_one_wire_read_bit( &cmp_id_bit ); + + // Check whether no devices participating in current search. + if ( ( id_bit == 1 ) && ( cmp_id_bit == 1 ) ) { + break; + // Proceed, because we have found some device(s). + } else { + // We are going to check once again whether read bit and + // its complement of all the devices on the One Wire grid are not the same. + // If they are not the same, we are going to start our search with non-complement bit. + if ( id_bit != cmp_id_bit ) { + search_direction = id_bit; // Bit write value for search. + + // Otherwise, there are both binary zeros and ones in the current + // bit position of the participating ROM numbers. This is a discrepancy. + } else { + if ( id_bit_number < last_discrepancy ) { + search_direction = ( ( one_wire_device_list->address[ rom_byte_number ] & rom_byte_mask ) > 0 ); + } else { + search_direction = ( id_bit_number == last_discrepancy ); + } + + // If 0 is picked, save its position. + if ( search_direction == 0) { + last_zero = id_bit_number; + + // Check for last discrepancy in family. + if ( last_zero < 9 ) { + last_family_discrepancy = last_zero; + } + } + } + + // Set or clear bit in the ROM byte rom_byte_number with mask rom_byte_mask. + if ( search_direction == 1 ) { + one_wire_device_list->address[ rom_byte_number ] |= rom_byte_mask; + } else { + one_wire_device_list->address[ rom_byte_number ] &= ~rom_byte_mask; + } + + // Search number search direction write bit. + hal_ll_one_wire_write_bit( search_direction ); + + // Increment the byte counter "id_bit_number", and shift the mask "rom_byte_mask". + id_bit_number++; + rom_byte_mask <<= 1; + + // If the mask is zero, then go to new "serial_num" byte, "rom_byte_number" and "reset_mask". + if ( rom_byte_mask == 0 ) { + rom_byte_number++; + rom_byte_mask = 1; + } + } + } while ( rom_byte_number < HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ); + + // If the search was successful then... + if ( !( id_bit_number < 65 ) ) { + + last_discrepancy = last_zero; + + // Check for last device. + if ( last_discrepancy == 0 ) { + last_device_flag = 1; + } + search_result = 1; + } + } + // If no device found then reset counters so next "search" will be like a first. + if ( !search_result || !one_wire_device_list->address[0] ) { + last_discrepancy = 0; + last_family_discrepancy = 0; + last_device_flag = 0; + search_result = 0; + } + + // Return info whether we have found some device ID or not. + return search_result; +} + +hal_ll_err_t hal_ll_one_wire_search_first_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) { + // Reset the search state. + last_discrepancy = 0; + last_device_flag = 0; + last_family_discrepancy = 0; + + // Initiate search algorithm, in order to get first device on One Wire grid. + hal_ll_one_wire_search( obj, one_wire_device_list ); + + return HAL_LL_ONE_WIRE_SUCCESS; +} + +hal_ll_err_t hal_ll_one_wire_search_next_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) { + // Initiate search algorithm, in order to get first device on One Wire grid. + hal_ll_one_wire_search( obj, one_wire_device_list ); + + return HAL_LL_ONE_WIRE_SUCCESS; +} + +void hal_ll_one_wire_write_byte( uint8_t *write_data_buffer, size_t write_data_length ) { + // Local instance of One Wire pin. + hal_ll_gpio_pin_t one_wire_pin; + uint32_t bit_location = 1ul << one_wire_handle.data_pin; + + size_t local_byte_checker = 0; + uint8_t local_bit_checker = 0; + + // For every byte to be sent... + while ( local_byte_checker != write_data_length ) { + + // ...restart bit checker... + local_bit_checker = 0; + + // For every bit in byte to be sent... + while ( local_bit_checker != HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ) { + // Set pin to be digital output. + *(uint16_t *)one_wire_handle.direction |= bit_location; + + // Set pin to LOW voltage level. + *(uint16_t *)one_wire_handle.output_clear |= bit_location; + + // Check whether a bit is binary one. + if ( write_data_buffer[ local_byte_checker ] & hal_ll_one_wire_selected_bit[ local_bit_checker ] ) { + // Timing value "a" for writing logical '1' - LOW voltage level. + one_wire_timing_value_a(); + // Else, bit is binary zero. + } else { + // Timing value "c" for writing logical '0' - LOW voltage level. + one_wire_timing_value_c(); + } + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint16_t *)one_wire_handle.direction &= ~bit_location; + + // Recommended timing after writing 1's or 0's. + if ( write_data_buffer[ local_byte_checker ] & hal_ll_one_wire_selected_bit[ local_bit_checker ] ) { + // Timing value "b" for writing logical '1' - LOW voltage level. + one_wire_timing_value_b(); + } else { + // Timing value "d" for writing logical '0' - HIGH voltage level. + one_wire_timing_value_d(); + } + // Increment so we could send another bit. + ++local_bit_checker; + } + // Increment so we could send another byte. + ++local_byte_checker; + } +} + +void hal_ll_one_wire_read_byte( uint8_t *read_data_buffer, size_t read_data_length ) { + size_t local_byte_checker = 0; + uint8_t local_bit_checker = 0; + uint32_t bit_location = 1ul << one_wire_handle.data_pin; + uint8_t local_buffer = 0; + + // For every byte to be read... + while ( local_byte_checker != read_data_length ) { + + // ...restart bit checker and buffer... + local_bit_checker = 0; + local_buffer = 0; + + // For every bit in byte to be read... + while ( local_bit_checker != HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ) { + // Set pin to be digital output. + *(uint16_t*)one_wire_handle.direction |= bit_location; + + // Set pin to LOW voltage level. + *(uint16_t*)one_wire_handle.output_clear |= bit_location; + + // Timing value "a" for bit reading - LOW voltage level. + one_wire_timing_value_a(); + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint16_t*)one_wire_handle.direction &= ~bit_location; + + // Timing value "e" for sampling read information. + one_wire_timing_value_e(); + + // Read bit. + local_buffer += ( (*(uint32_t*)one_wire_handle.input & bit_location)?(1):(0) ) << local_bit_checker; + + // Timing value "f" for the rest of the read operation. + one_wire_timing_value_f(); + + // Increment so we could send another bit. + ++local_bit_checker; + } + // Send back one logical level up a byte of data that has been just read. + read_data_buffer[local_byte_checker++] = local_buffer; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static void hal_ll_one_wire_write_bit( uint8_t write_data_buffer ) { + uint32_t bit_location = 1ul << one_wire_handle.data_pin; + + // Set pin to be digital output. + *(uint16_t *)one_wire_handle.direction |= bit_location; + + // Set pin to LOW voltage level. + *(uint16_t *)one_wire_handle.output_clear |= bit_location; + + // Check whether a bit is binary one. + if ( write_data_buffer & 1 ) { + // Timing value "a" for writing logical '1' - LOW voltage level. + one_wire_timing_value_a(); + // Else, bit is binary zero. + } else { + // Timing value "c" for writing logical '0' - LOW voltage level. + one_wire_timing_value_c(); + } + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint16_t *)one_wire_handle.direction &= ~bit_location; + + // Recommended timing after writing 1's or 0's. + if ( write_data_buffer & 1 ) { + // Timing value "b" for writing logical '1' - LOW voltage level. + one_wire_timing_value_b(); + } else { + // Timing value "d" for writing logical '0' - HIGH voltage level. + one_wire_timing_value_d(); + } +} + +static void hal_ll_one_wire_read_bit( uint8_t *read_data_buffer ) { + uint16_t bit_location = 1ul << one_wire_handle.data_pin; + + // Set pin to be digital output. + *(uint16_t *)one_wire_handle.direction |= bit_location; + + // Set pin to LOW voltage level. + *(uint16_t *)one_wire_handle.output_clear |= bit_location; + + // Timing value "a" for bit reading - LOW voltage level. + one_wire_timing_value_a(); + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint16_t *)one_wire_handle.direction &= ~bit_location; + + // Timing value "e" for sampling read information. + one_wire_timing_value_e(); + + // Read bit. + read_data_buffer[ 0 ] = ( *(uint32_t *)one_wire_handle.input & bit_location ) ? 0x01 : 0x00; + + // Timing value "f" for the rest of the read operation. + one_wire_timing_value_f(); +} + +void hal_ll_one_wire_reconfigure( hal_ll_one_wire_t *obj ) { + // Local instance of One Wire pin. + hal_ll_gpio_pin_t one_wire_pin; + + one_wire_pin.base = (hal_ll_gpio_base_t)hal_ll_gpio_port_base(hal_ll_gpio_port_index(obj->data_pin)); + one_wire_pin.mask = hal_ll_gpio_pin_mask(obj->data_pin); + + // The idle state for the One Wire bus is HIGH. + do { + // Make sure that we have HIGH voltage state before any actions. + hal_ll_gpio_write_pin_output( &one_wire_pin, 1 ); + + // Make sure that pin is at HIGH voltage state. + } while ( !hal_ll_gpio_read_pin_output( &one_wire_pin ) ); + + // Memorize info about pin number (for future use). + one_wire_handle.data_pin = obj->data_pin % PORT_SIZE; + + // Memorize info about register whose main task is to alter GPIO pin direction. + hal_ll_gpio_base_handle_t *gpio_ptr = (hal_ll_gpio_base_handle_t *)one_wire_pin.base; + + // Pin direction registers. + one_wire_handle.direction = (uint32_t)&gpio_ptr->pdr; + one_wire_handle.input = (uint32_t)&gpio_ptr->pidr; + + // GPIO pin set/reset registers. + one_wire_handle.output_clear = (uint32_t)&gpio_ptr->porr; + one_wire_handle.output_set = (uint32_t)&gpio_ptr->posr; + + // Set object state to true. + obj->state = true; +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt b/targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt new file mode 100644 index 0000000000..e4bc45ed41 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt @@ -0,0 +1,64 @@ +## ./targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt +set(hal_ll_def_list "") +set(MCU_NAME_FIRST_7 "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) +string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) +list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +# BEGIN SPI +list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") + +set( spi_subimplementation "implementation_1/hal_ll_spi_master.c" ) +set( spi_pin_map "hal_ll_spi_master_pin_map/implementation_1" ) +# END SPI + +mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master + ${spi_subimplementation} + + ../../include/hal_ll_target.h + # BEGIN SPI + ../../include/spi_master/hal_ll_spi_master.h + ../../include/spi_master/${spi_pin_map}/hal_ll_spi_master_pin_map.h + # END SPI +) + +target_compile_definitions(lib_hal_ll_spi_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_spi_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_spi_master + PRIVATE + ../../include + ../../include/gpio + # BEGIN SPI + ../../include/spi_master + ../../include/spi_master/${spi_pin_map} + # END SPI + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h) diff --git a/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c b/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c new file mode 100644 index 0000000000..cff46c96fb --- /dev/null +++ b/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c @@ -0,0 +1,824 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" +#include "hal_ll_gpio_port.h" +#include "hal_ll_mstpcr.h" +#include "mcu.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[ SPI_MODULE_COUNT ] = { ( handle_t * )NULL, ( handle_t * )NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ( ( hal_ll_spi_master_handle_register_t * )*handle ) +/*!< @brief Helper macro for getting module specific control register structure base address */ +#define hal_ll_spi_master_get_handle ( hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct( _handle ) ( ( hal_ll_spi_master_base_handle_t * )_handle ) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ( ( hal_ll_spi_master_hw_specifics_map_t * )( ( hal_ll_spi_master_handle_register_t * )\ + ( ( ( hal_ll_spi_master_handle_register_t * )( handle ) )->hal_ll_spi_master_handle ) )->hal_ll_spi_master_handle )->base + +// -------------------------------------------------------------- PRIVATE TYPES + +#define HAL_LL_SPI_SPSR_SPTEF (5) +#define HAL_LL_SPI_SPSR_SPRF (7) + +#define HAL_LL_SPI_SPDCR_SPBYT (6) + +#define HAL_LL_SPI_SPCR2_SCKASE (4) + +#define HAL_LL_SPI_SPCMD0_SPNDEN_MASK (1UL << 13) +#define HAL_LL_SPI_SPCMD0_SLNDEN_MASK (1UL << 14) +#define HAL_LL_SPI_SPCMD0_SCKDEN_MASK (1UL << 15) +#define HAL_LL_SPI_SPCMD0_SPB_8BIT_MASK (7UL << 8) +#define HAL_LL_SPI_SPCMD0_BRDV_MASK (3UL << 2) +#define HAL_LL_SPI_SPCMD0_BRDV (2) +#define HAL_LL_SPI_SPCMD0_CPHA (0) +#define HAL_LL_SPI_SPCMD0_CPOL (1) + +#define HAL_LL_SPI_SPCR_MSTR_MASK (1UL << 3) +#define HAL_LL_SPI_SPCR_SPE_MASK (1UL << 6) + + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +/*!< @brief SPI Master hw specific error values. */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +/*!< @brief SPI register structure. */ +typedef struct { + uint8_t spcr; + uint8_t sslp; + uint8_t sppcr; + uint8_t spsr; + union { + uint32_t spdr; + uint16_t spdr_ha; + uint8_t spdr_by; + }; + uint8_t spscr; + uint8_t spssr; + uint8_t spbr; + uint8_t spdcr; + uint8_t spckd; + uint8_t sslnd; + uint8_t spnd; + uint8_t spcr2; + uint16_t spcmd0; +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific module values. */ +typedef struct { + uint8_t pin_miso; + uint8_t pin_mosi; + uint8_t pin_sck; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hardware specific structure. */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions. */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +/*!< @brief SPI Master hardware specific info. */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[ SPI_MODULE_COUNT + 1 ] = { + #ifdef SPI_MODULE_0 + { HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), + { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, + HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT }, + #endif + + { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, 0, 0, 0 } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address. + * @param[out] *handle_map - Pointer to local handle list. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins( hal_ll_pin_name_t sck_pin, + hal_ll_pin_name_t miso_pin, + hal_ll_pin_name_t mosi_pin, + hal_ll_spi_pin_id *index_list, + hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Enable clock for SPI module on hardware level. + * + * Initializes SPI module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @return None + */ +static void hal_ll_spi_master_module_enable( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Set SPI Master bit rate. + * + * Calculates and sets the SPI bit rate by configuring the SPBR register, + * based on the system clock, desired speed, and BRDV setting. + * + * @param[in] *map Object-specific context handler. + * @return None + * + */ +static void hal_ll_spi_master_set_bit_rate( hal_ll_spi_master_hw_specifics_map_t *map ); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ); + +/** + * @brief Initialize hardware SPI module. + * + * @param[in] *map - Object specific context handler. + * @return None + * + */ +static void hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map ); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, + uint8_t *read_data, + size_t write_data_size ); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + */ +static void hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, + uint8_t *read_data_buffer, + size_t read_data_length, + uint8_t dummy_data ); + +/** + * @brief Perform a simultaneous write and read on the SPI Master bus. + * + * Function performs a full-duplex SPI transfer. Each written byte results in + * a received byte which is optionally stored in the read buffer. + * If the write buffer is NULL, the configured dummy byte will be transmitted. + * If the read buffer is NULL, the received data will be discarded. + * + * @param[in] *map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to write data buffer. + * If NULL, dummy data will be used. + * @param[out] *read_data_buffer - Pointer to read data buffer. + * If NULL, received data will be discarded. + * @param[in] data_length - Number of bytes to be transferred. + * + * @note TX FIFO is flushed and re-enabled on each byte transfer to ensure proper behavior. + * This implementation uses polling and is blocking. + */ +static void hal_ll_spi_master_transfer_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, + uint8_t *write_data_buffer, + uint8_t *read_data_buffer, + size_t data_length ); +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_t *map, + bool hal_ll_state ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * + * @return None + */ +static void hal_ll_spi_master_map_pins( uint8_t module_index, hal_ll_spi_pin_id *index_list ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_spi_master_register_handle( hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, + hal_ll_spi_master_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + hal_ll_spi_pin_id index_list[ SPI_MODULE_COUNT ] = { HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC }; + uint16_t pin_check_result; + + // Check user-defined pins. + if ( ( pin_check_result = hal_ll_spi_master_check_pins( sck, miso, mosi, &index_list, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ( ( hal_ll_spi_master_hw_specifics_map[ pin_check_result ].pins.sck.pin_name != sck ) || + ( hal_ll_spi_master_hw_specifics_map[ pin_check_result ].pins.miso.pin_name != miso ) || + ( hal_ll_spi_master_hw_specifics_map[ pin_check_result ].pins.mosi.pin_name != mosi ) ) { + + hal_ll_spi_master_alternate_functions_set_state( &hal_ll_spi_master_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_spi_master_map_pins( pin_check_result, &index_list ); + + hal_ll_spi_master_alternate_functions_set_state( &hal_ll_spi_master_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle = + ( handle_t * )&hal_ll_spi_master_hw_specifics_map[ pin_check_result ].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[ pin_check_result ].hal_ll_spi_master_handle = + ( handle_t* )&hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi( handle_t *handle ) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle = + ( handle_t * )&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data( handle_t *handle, uint8_t dummy_data ) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + if( hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write( handle_t *handle, uint8_t *write_data_buffer, size_t length_data ) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, + write_data_buffer, + length_data ); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read( handle_t *handle, uint8_t *read_data_buffer, size_t length_data ) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, + read_data_buffer, length_data, + hal_ll_spi_master_hw_specifics_map_local->dummy_data ); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, + uint8_t *write_data_buffer, + size_t length_write_data, + uint8_t *read_data_buffer, + size_t length_read_data ) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, + write_data_buffer, + length_write_data ); + + hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, + read_data_buffer, + length_read_data, + hal_ll_spi_master_hw_specifics_map_local->dummy_data ); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_transfer(handle_t *handle, + uint8_t *write_data_buffer, + uint8_t *read_data_buffer, + size_t data_length) { + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if (NULL == low_level_handle->hal_ll_spi_master_handle) { + return HAL_LL_SPI_MASTER_MODULE_ERROR; + } + + hal_ll_spi_master_transfer_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, + write_data_buffer, read_data_buffer, data_length ); + + if (!hal_ll_spi_master_hw_specifics_map_local || !data_length) { + return HAL_LL_SPI_MASTER_MODULE_ERROR; + } + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed( handle_t *handle, uint32_t speed ) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = + hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode( handle_t *handle, hal_ll_spi_master_mode_t mode ) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = + hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close( handle_t* handle ) { + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = + hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + if( low_level_handle->hal_ll_spi_master_handle != NULL ) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_module_enable( hal_ll_spi_master_hw_specifics_map_local, true ); + hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_local, false ); + hal_ll_spi_master_module_enable( hal_ll_spi_master_hw_specifics_map_local, false ); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, + uint8_t *write_data_buffer, size_t write_data_length ) { + while ( 0 < write_data_length-- ) { + // Wait until transmit buffer is empty + while ( !check_reg_bit( &hal_ll_hw_reg->spsr, HAL_LL_SPI_SPSR_SPTEF )); + + // Send byte from write buffer + write_reg( &hal_ll_hw_reg->spdr_by, ( uint8_t )( *write_data_buffer++ ) ); + + // Wait until receive is complete + while ( !check_reg_bit( &hal_ll_hw_reg->spsr, HAL_LL_SPI_SPSR_SPRF )); + + // Dummy read + volatile uint8_t temp = read_reg( &hal_ll_hw_reg->spdr_by ); + } +} + +static void hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, + uint8_t *read_data_buffer, size_t read_data_length, + uint8_t dummy_data ) { + while ( 0 < read_data_length-- ) { + // Wait until transmit buffer is empty + while ( !check_reg_bit( &hal_ll_hw_reg->spsr, HAL_LL_SPI_SPSR_SPTEF )); + + // Send dummy data + write_reg( &hal_ll_hw_reg->spdr_by, (uint8_t)(dummy_data)); + + // Wait until receive is complete + while ( !check_reg_bit( &hal_ll_hw_reg->spsr, HAL_LL_SPI_SPSR_SPRF )); + + // Read received byte and store if read buffer is provided + *read_data_buffer++ = (uint8_t)read_reg( &hal_ll_hw_reg->spdr_by ); + } +} + +static void hal_ll_spi_master_transfer_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, + uint8_t *write_data_buffer, + uint8_t *read_data_buffer, + size_t data_length ) { + while ( 0 < data_length-- ) { + // Wait until transmit buffer is empty + while ( !check_reg_bit( &hal_ll_hw_reg->spsr, HAL_LL_SPI_SPSR_SPTEF )); + + // Send byte from write buffer or dummy if NULL + uint8_t tx_data = ( write_data_buffer ) ? *write_data_buffer++ : 0xFF; + write_reg( &hal_ll_hw_reg->spdr_by, tx_data ); + + // Wait until receive is complete + while ( !check_reg_bit( &hal_ll_hw_reg->spsr, HAL_LL_SPI_SPSR_SPRF )); + + // Read received byte and store if read buffer is provided + uint8_t rx_data = (uint8_t)read_reg( &hal_ll_hw_reg->spdr_by ); + if ( read_data_buffer ) { + *read_data_buffer++ = rx_data; + } + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins( hal_ll_pin_name_t sck_pin, + hal_ll_pin_name_t miso_pin, + hal_ll_pin_name_t mosi_pin, + hal_ll_spi_pin_id *index_list, + hal_ll_spi_master_handle_register_t *handle_map ) { + static const uint16_t sck_map_size = + ( sizeof( hal_ll_spi_master_sck_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) ); + static const uint16_t miso_map_size = + ( sizeof( hal_ll_spi_master_miso_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) ); + static const uint16_t mosi_map_size = + ( sizeof( hal_ll_spi_master_mosi_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( ( HAL_LL_PIN_NC == sck_pin ) || ( HAL_LL_PIN_NC == miso_pin ) || ( HAL_LL_PIN_NC == mosi_pin ) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for ( sck_index = 0; sck_index < sck_map_size; sck_index++ ) { + if (hal_ll_spi_master_sck_map[ sck_index ].pin == sck_pin ) { + for ( miso_index = 0; miso_index < miso_map_size; miso_index++ ) { + if (hal_ll_spi_master_miso_map[ miso_index ].pin == miso_pin ) { + if (hal_ll_spi_master_sck_map[ sck_index ].module_index == + hal_ll_spi_master_miso_map[ miso_index ].module_index ) { + for ( mosi_index = 0; mosi_index < mosi_map_size; mosi_index++ ) { + if (hal_ll_spi_master_mosi_map[mosi_index ].pin == mosi_pin ) { + if (hal_ll_spi_master_sck_map[sck_index].module_index == + hal_ll_spi_master_mosi_map[ mosi_index ].module_index ) { + // Get module number + hal_ll_module_id =hal_ll_spi_master_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[ hal_ll_module_id ].pin_sck = sck_index; + index_list[ hal_ll_module_id ].pin_miso = miso_index; + index_list[ hal_ll_module_id ].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_spi_master_handle_register_t ) ); + + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_spi_master_handle_register_t ) ); + + while ( hal_ll_module_count-- ) { + if ( hal_ll_spi_master_get_base_from_hal_handle == + hal_ll_spi_master_hw_specifics_map[ hal_ll_module_count ].base ) { + return &hal_ll_spi_master_hw_specifics_map[ hal_ll_module_count ]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_map_pins( uint8_t module_index, hal_ll_spi_pin_id *index_list ) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.sck.pin_name = + hal_ll_spi_master_sck_map[ index_list[ module_index ].pin_sck ].pin; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.miso.pin_name = + hal_ll_spi_master_miso_map[ index_list[ module_index ].pin_miso ].pin; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.mosi.pin_name = + hal_ll_spi_master_mosi_map[ index_list[ module_index ].pin_mosi ].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.sck.pin_af = + hal_ll_spi_master_sck_map[ index_list[ module_index ].pin_sck ].af; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.miso.pin_af = + hal_ll_spi_master_miso_map[ index_list[ module_index ].pin_miso ].af; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.mosi.pin_af = + hal_ll_spi_master_mosi_map[ index_list[ module_index ].pin_mosi ].af; +} + +static void hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_t *map, + bool hal_ll_state ) { + module_struct module; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && + (map->pins.miso.pin_name != HAL_LL_PIN_NC) && + (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = GPIO_CFG_PORT_PULL_UP_ENABLE | GPIO_CFG_DIGITAL_OUTPUT | GPIO_CFG_PERIPHERAL_PIN; + module.configs[1] = GPIO_CFG_DIGITAL_INPUT | GPIO_CFG_PERIPHERAL_PIN; + module.configs[2] = GPIO_CFG_PORT_PULL_UP_ENABLE | GPIO_CFG_DIGITAL_OUTPUT | GPIO_CFG_PERIPHERAL_PIN; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static void hal_ll_spi_master_module_enable( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ) { + if ( true == hal_ll_state ) { + switch ( map->module_index ) { + #ifdef SPI_MODULE_0 + case hal_ll_spi_master_module_num(SPI_MODULE_0): + clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB19_POS ); + break; + #endif + #ifdef SPI_MODULE_1 + case hal_ll_spi_master_module_num(SPI_MODULE_1): + clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB18_POS ); + break; + #endif + + default: + break; + } + } else { + switch ( map->module_index ) { + #ifdef SPI_MODULE_0 + case hal_ll_spi_master_module_num(SPI_MODULE_0): + set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB19_POS ); + break; + #endif + #ifdef SPI_MODULE_1 + case hal_ll_spi_master_module_num(SPI_MODULE_1): + set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB18_POS ); + break; + #endif + + default: + break; + } + } +} + +static void hal_ll_spi_master_set_bit_rate( hal_ll_spi_master_hw_specifics_map_t *map ) { + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + static const int mul_table[] = { 2, 4, 8, 16 }; + uint8_t spbr, mul; + + system_clocks_t system_clocks; + SYSTEM_GetClocksFrequency( &system_clocks ); + + uint8_t brdv = ( read_reg( &hal_ll_hw_reg->spcmd0 ) & HAL_LL_SPI_SPCMD0_BRDV_MASK ) >> HAL_LL_SPI_SPCMD0_BRDV; + + mul = mul_table[brdv]; + + spbr = system_clocks.pclka / ( map->speed * mul ) - 1; + + write_reg( &hal_ll_hw_reg->spbr, spbr ); + + // TODO: Add support for highest and lowest possible bit rates, as well as deviation calculation. +} + +static void hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map ) { + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Disable loopback mode; set MOSI output value. + clear_reg( &hal_ll_hw_reg->sppcr ); + + // Set the desired bit rate. + hal_ll_spi_master_set_bit_rate( map ); + + // Byte access is used for SPDR. + set_reg_bit( &hal_ll_hw_reg->spdcr, HAL_LL_SPI_SPDCR_SPBYT ); + + clear_reg( &hal_ll_hw_reg->spckd ); // 1RSPCK delay + clear_reg( &hal_ll_hw_reg->sslnd ); // 1RSPCK delay + clear_reg( &hal_ll_hw_reg->spnd ); // 1RSPCK + 2PCLKA delay + + // Enable RSPCK auto-stop function. + set_reg_bit( &hal_ll_hw_reg->spcr2, HAL_LL_SPI_SPCR2_SCKASE ); + + // Use delays as defined in SPND, SSLND and SPCKD. + write_reg( &hal_ll_hw_reg->spcmd0, HAL_LL_SPI_SPCMD0_SPNDEN_MASK | + HAL_LL_SPI_SPCMD0_SLNDEN_MASK | + HAL_LL_SPI_SPCMD0_SCKDEN_MASK ); + + // 8 bit data length. + write_reg( &hal_ll_hw_reg->spcmd0, HAL_LL_SPI_SPCMD0_SPB_8BIT_MASK ); + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (HAL_LL_SPI_MASTER_MODE_1 >= map->mode ) { + clear_reg_bit( &hal_ll_hw_reg->spcmd0, HAL_LL_SPI_SPCMD0_CPOL ); + } else { + set_reg_bit(&( hal_ll_hw_reg->spcmd0), HAL_LL_SPI_SPCMD0_CPOL ); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if ( HAL_LL_SPI_MASTER_MODE_0 == map->mode || HAL_LL_SPI_MASTER_MODE_2 == map->mode ) { + clear_reg_bit( &hal_ll_hw_reg->spcmd0, HAL_LL_SPI_SPCMD0_CPHA ); + } else { + set_reg_bit( &hal_ll_hw_reg->spcmd0, HAL_LL_SPI_SPCMD0_CPHA ); + } + + // Enable SPI; Master mode + write_reg( &hal_ll_hw_reg->spcr, HAL_LL_SPI_SPCR_MSTR_MASK | HAL_LL_SPI_SPCR_SPE_MASK ); + + volatile uint8_t temp = read_reg( &hal_ll_hw_reg->spcr ); +} + +static void hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ) { + + hal_ll_spi_master_module_enable( map, true ); + + hal_ll_spi_master_alternate_functions_set_state( map, true ); + + hal_ll_spi_master_hw_init( map ); +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/tim/CMakeLists.txt b/targets/arm/mikroe/renesas/src/tim/CMakeLists.txt new file mode 100644 index 0000000000..1bcd6323b1 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/tim/CMakeLists.txt @@ -0,0 +1,63 @@ +## ./targets/arm/mikroe/renesas/src/tim/CMakeLists.txt +set(hal_ll_def_list "") +set(MCU_NAME_FIRST_7 "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) +string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) +list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +# BEGIN TIM +list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") +set( tim_subimplementation "implementation_1/hal_ll_tim.c" ) +set( tim_pin_map "hal_ll_tim_pin_map/implementation_1" ) +# END TIM + +mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM + ${tim_subimplementation} + + ../../include/hal_ll_target.h + # BEGIN TIM + ../../include/tim/hal_ll_tim.h + ../../include/tim/${tim_pin_map}/hal_ll_tim_pin_map.h + # END TIM +) + +target_compile_definitions(lib_hal_ll_tim PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_tim PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_tim + PRIVATE + ../../include + ../../include/gpio + # BEGIN TIM + ../../include/tim + ../../include/tim/${tim_pin_map} + # END TIM + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.TIM) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h) diff --git a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c new file mode 100644 index 0000000000..b6681ac296 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c @@ -0,0 +1,600 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" +#include "hal_ll_mstpcr.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< Register defs. */ +#define HAL_LL_TIM_GTCR_CST (0) +#define HAL_LL_TIM_GTCR_MD_MASK (0x70000UL) + +#define HAL_LL_TIM_GTBER_PR_MASK (0x300000UL) +#define HAL_LL_TIM_GTBER_PR_SINGLE_BUFFER (0x100000UL) +#define HAL_LL_TIM_GTBER_CCRA_MASK (0x30000UL) +#define HAL_LL_TIM_GTBER_CCRA_SINGLE_BUFFER (0x10000UL) +#define HAL_LL_TIM_GTBER_CCRB_MASK (0xC0000UL) +#define HAL_LL_TIM_GTBER_CCRB_SINGLE_BUFFER (0x40000UL) + +#define HAL_LL_TIM_GTUDDTYC_UD (0) + +#define HAL_LL_TIM_GTIOR_GTIOA_MASK (0x1FUL) +#define HAL_LL_TIM_GTIOR_GTIOB_MASK (0x1FUL << 16) +#define HAL_LL_TIM_GTIOR_GTIOA_9 (0x9) +#define HAL_LL_TIM_GTIOR_GTIOB_9 (0x9UL << 16) +#define HAL_LL_TIM_GTIOR_OAE (8) +#define HAL_LL_TIM_GTIOR_OBE (24) + +#define HAL_LL_TIM_AF_CONFIG (GPIO_CFG_DIGITAL_OUTPUT | GPIO_CFG_PORT_PULL_UP_ENABLE) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t gtwp; + uint32_t gtstr; + uint32_t gtstp; + uint32_t gtclr; + uint32_t gtssr; + uint32_t gtpsr; + uint32_t gtcsr; + uint32_t gtupsr; + uint32_t gtdnsr; + uint32_t gticasr; + uint32_t gticbsr; + uint32_t gtcr; + uint32_t gtuddtyc; + uint32_t gtior; + uint32_t gtintad; + uint32_t gtst; + uint32_t gtber; + uint32_t gtitc; + uint32_t gtcnt; + uint32_t gtccr[6]; + uint32_t gtpr; + uint32_t gtpbr; + uint32_t gtpdbr; + uint32_t gtadtra; + uint32_t gtadtbra; + uint32_t gtadtdbra; + uint32_t gtadtrb; + uint32_t gtadtbrb; + uint32_t gtdtcr; + uint32_t gtdvu; +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_tim_pin_type_t pin_type; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_0 + {HAL_LL_TIM0_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM_MODULE_4 + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM_MODULE_5 + {HAL_LL_TIM5_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM_MODULE_6 + {HAL_LL_TIM6_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_6)}, + #endif + #ifdef TIM_MODULE_7 + {HAL_LL_TIM7_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_7)}, + #endif + + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void hal_ll_tim_module_enable( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @return uint32_t - clock source + */ +static uint32_t hal_ll_tim_clock_source(); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return uint32_t - Set period. + * + */ +static uint32_t hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return uint32_t - Set period. + * + */ +static uint32_t hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, + hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, + bool hal_ll_state ); + +/** + * @brief Set TIM frequency register values. + * + * Calculates and writes values to the period registers + * based on the peripheral clock and desired frequency. + * + * @param[in] map - Object specific context handler. + * @return uint32_t - Set period + * + */ +static uint32_t hal_ll_tim_set_freq_bare_metal( hal_ll_tim_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result].config.pin != pin ) { + hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_tim_map_pin( pin_check_result, index ); + + hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = + ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = + ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = + (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + uint16_t local_freq = 0; + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + uint32_t period; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + period = hal_ll_tim_init(hal_ll_tim_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Memorize information about the max period available (PWM duty cycle is dependant of this information). + return ( hal_ll_tim_hw_specifics_map_local->max_period = period ); +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + hal_ll_tim_pin_type_t pin_type = hal_ll_tim_hw_specifics_map_local->config.pin_type; + + uint32_t pclkd = hal_ll_tim_clock_source(); + + if ( check_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST )) { + write_reg( &hal_ll_hw_reg->gtccr[(HAL_LL_TIM_PIN_A == pin_type) ? 2 : 3], + (( uint32_t )( hal_ll_tim_hw_specifics_map_local->max_period + 1 ) * duty_ratio - 1 ) ); + } else { + write_reg( &hal_ll_hw_reg->gtccr[(HAL_LL_TIM_PIN_A == pin_type) ? 0 : 1], + (( uint32_t )( hal_ll_tim_hw_specifics_map_local->max_period + 1 ) * duty_ratio - 1 ) ); + + if( HAL_LL_TIM_PIN_A == pin_type ) { + write_reg( &hal_ll_hw_reg->gtccr[2], read_reg( &hal_ll_hw_reg->gtccr[0] )); + } else { + write_reg( &hal_ll_hw_reg->gtccr[3], read_reg( &hal_ll_hw_reg->gtccr[1] )); + } + } + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + hal_ll_tim_pin_type_t pin_type = hal_ll_tim_hw_specifics_map_local->config.pin_type; + + if( read_reg( &hal_ll_hw_reg->gtpr ) && read_reg( &hal_ll_hw_reg->gtccr[(HAL_LL_TIM_PIN_A == pin_type) ? 0 : 1])) + set_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST ); // Start operation. + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + clear_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST ); + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + hal_ll_tim_module_enable( hal_ll_tim_hw_specifics_map_local, true ); + hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + hal_ll_tim_module_enable( hal_ll_tim_hw_specifics_map_local, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.pin_type = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, + hal_ll_tim_handle_register_t *handle_map ) { + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( hal_ll_tim_pin_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( hal_ll_tim_pin_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = hal_ll_tim_pin_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void hal_ll_tim_module_enable( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + if ( true == hal_ll_state ) { + if ( 1 >= map->module_index ) + clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD5_POS ); + else if ( 7 >= map->module_index ) + clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD6_POS ); + } else { + if ( 1 >= map->module_index ) + set_reg_bit( _MSTPCRD, MSTPCRD_MSTPD5_POS ); + else if ( 7 >= map->module_index ) + set_reg_bit( _MSTPCRD, MSTPCRD_MSTPD6_POS ); + } +} + +static uint32_t hal_ll_tim_clock_source() { + system_clocks_t system_clocks; + + SYSTEM_GetClocksFrequency( &system_clocks ); + + return system_clocks.pclkd; +} + +static void hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + // Map new pin. + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = hal_ll_tim_pin_map[ index ].pin; + hal_ll_tim_hw_specifics_map[ module_index ].config.pin_type = hal_ll_tim_pin_map[ index ].pin_type; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = hal_ll_tim_pin_map[ index ].af; +} + +static void hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( map->config.pin != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->config.pin, map->config.af ); + module.pins[1] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_TIM_AF_CONFIG; + module.configs[1] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_tim_set_freq_bare_metal( hal_ll_tim_hw_specifics_map_t *map ) { + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + uint32_t period; + + uint32_t pclkd = hal_ll_tim_clock_source(); + + period = pclkd / map->freq_hz - 1; + + // When using modules GPT2 - GPT7, the minimum possible frequency with PCKLD = 48MHz is ~732Hz. + if ( 7 >= map->module_index && 1 < map->module_index ) + if ( 0xFFFF < period ) + period = 0xFFFF; + + write_reg( &hal_ll_hw_reg->gtpr, ( uint32_t ) period ); + write_reg( &hal_ll_hw_reg->gtpbr, ( uint32_t ) period ); + + return period; +} + +static uint32_t hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + hal_ll_tim_pin_type_t pin_type = map->config.pin_type; + uint32_t period; + + hal_ll_tim_module_enable( map, true ); + + clear_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST ); // Stop operation first. + clear_reg_bits( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_MD_MASK ); // PWM mode. + set_reg_bit( &hal_ll_hw_reg->gtuddtyc, HAL_LL_TIM_GTUDDTYC_UD ); // Count up. + clear_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_PR_MASK ); + set_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_PR_SINGLE_BUFFER ); // Single buffer operation. + + // Frequency settings + period = hal_ll_tim_set_freq_bare_metal( map ); + + clear_reg( &hal_ll_hw_reg->gtcnt ); + + if( HAL_LL_TIM_PIN_A == map->config.pin_type ) { + // A + // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end). + clear_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOA_MASK ); + set_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOA_9 ); + set_reg_bit( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_OAE ); // Enable GTIOC pin output. + clear_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRA_MASK ); + set_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRA_SINGLE_BUFFER ); + } else { + // B + // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end). + clear_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOB_MASK ); + set_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOB_9 ); + set_reg_bit( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_OBE ); // Enable GTIOC pin output. + clear_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRB_MASK ); + set_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRB_SINGLE_BUFFER ); + } + + return period; +} + +static uint32_t hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + hal_ll_tim_module_enable( map->base, true ); + + hal_ll_tim_alternate_functions_set_state( map, true ); + + return hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/uart/CMakeLists.txt b/targets/arm/mikroe/renesas/src/uart/CMakeLists.txt new file mode 100644 index 0000000000..cbfd69b57d --- /dev/null +++ b/targets/arm/mikroe/renesas/src/uart/CMakeLists.txt @@ -0,0 +1,60 @@ +## ./targets/arm/mikroe/renesas/src/uart/CMakeLists.txt +set(hal_ll_def_list "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +# BEGIN UART +list(APPEND hal_ll_def_list "MACRO_USAGE_UART") +set(uart_subimplementation "implementation_1/hal_ll_uart.c") +set(uart_pin_map "hal_ll_uart_pin_map/implementation_1") +# END UART + +mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART + ${uart_subimplementation} + + ../../include/hal_ll_target.h + # BEGIN UART + ../../include/uart/hal_ll_uart.h + ../../include/uart/${uart_pin_map}/hal_ll_uart_pin_map.h + # END UART +) + +target_compile_definitions(lib_hal_ll_uart PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_uart PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_uart + PRIVATE + ../../include + ../../include/gpio + # BEGIN UART + ../../include/uart + ../../include/uart/${uart_pin_map} + # END UART + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.UART) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h) diff --git a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c new file mode 100644 index 0000000000..35361aac39 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c @@ -0,0 +1,1308 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_mstpcr.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[ UART_MODULE_COUNT ] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address. */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address. */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure. */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle. */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value. */ + + +/*!< @brief Macro used for status registed flag check. + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->mis & _flag) + +/*!< @brief Macro used for status registed flag clearing. + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit(&(((hal_ll_uart_base_handle_t *)_handle)->icr), _flag)) + +/*!< @brief Macro used for picking the divisors for the source clock. + * if is_base_16 == true: + * Skip this calculation for divisors that are not achievable with 16 base clk cycles per bit. + * if is_base_16 == false: + * Skip this calculation for divisors that are only achievable without 16 base clk cycles per bit. + */ +#define hal_ll_sci_brr_assert_divisors(is_base_16, i) \ + (is_base_16 ^ (g_async_baud[i].abcs | g_async_baud[i].abcse)) + +/*!< @brief Macro used for calculating BRR register value. + * BRR = (PCLKA / (div_coefficient * baud)) - 1 + */ +#define hal_ll_sci_brr_calculate(baud, pclka, i) (pclka / (g_div_coefficient[i] * baud)) + +/*!< @brief Macro used for calculating the baud rate error. + * error[%] = {(PCLKA / (baud * div_coefficient * (BRR + 1)) - 1} x 100 + * Promoting to 64 bits for calculation, but the final value can never be more than 32 bits, as + * described below, so this cast is safe. + * 1. Larger frequencies yield larger bit errors (absolute value). As the frequency grows, + * the current_error approaches -100000, so: + * 0 >= current_error >= -100000 + * 2. current_error is between -100000 and 0. This entire range fits in an int32_t type, so the cast + * to (int32_t) is safe. + */ +#define hal_ll_sci_brr_get_error(brr, pclka, baud, i) \ + (int32_t)(((((int64_t)pclka) * HAL_LL_SCI_BRR_ERROR_REFERENCE) / \ + (g_div_coefficient[i] * baud * (brr + 1))) - HAL_LL_SCI_BRR_ERROR_REFERENCE) + +/*!< @brief Macro used for getting the real baudrate. + * baud = PCLKA / ((BRR + 1) * div_coefficient) + */ +#define hal_ll_sci_get_baud_rate(pclka, brr, i) (pclka / ((brr + 1) * g_div_coefficient[i])) + +/*!< @brief Macros defining bit location. */ +#define HAL_LL_SCI_SEMR_BRME 2 +#define HAL_LL_SCI_SEMR_ABCSE 3 +#define HAL_LL_SCI_SMR_STOP 3 +#define HAL_LL_SCI_SEMR_ABCS 4 +#define HAL_LL_SCI_SCMR_CHR1 4 +#define HAL_LL_SCI_SMR_PM 4 +#define HAL_LL_SCI_SCR_RE 4 +#define HAL_LL_SCI_SCR_TE 5 +#define HAL_LL_SCI_SMR_PE 5 +#define HAL_LL_SCI_SMR_CHR 6 +#define HAL_LL_SCI_SSR_RDRF 6 +#define HAL_LL_SCI_SEMR_BGDM 6 +#define HAL_LL_SCI_SSR_TDRE 7 + +/*!< @brief Macros defining register bit values. */ +#define HAL_LL_SCI_CLOCK_EXTERNAL 0x3 +#define HAL_LL_SCI_SEMR_CONFIGURE(bgdm, abcs, abcse) \ + (bgdm << HAL_LL_SCI_SEMR_BGDM) | \ + (abcs << HAL_LL_SCI_SEMR_ABCS) | \ + (abcse << HAL_LL_SCI_SEMR_ABCSE) + +/*!< @brief Macros used for baudrate calculations. */ +#define HAL_LL_SCI_NUM_DIVISORS 13 +#define HAL_LL_SCI_BRR_MAX 256 +#define HAL_LL_SCI_BRR_ERROR_ACCEPTABLE 1000UL +#define HAL_LL_SCI_BRR_ERROR_REFERENCE 100000UL + +/*!< @brief Structures used for baudrate calculations. */ +typedef struct st_baud_setting_const_t +{ + uint8_t bgdm; /**< BGDM value to get divisor */ + uint8_t abcs; /**< ABCS value to get divisor */ + uint8_t abcse; /**< ABCSE value to get divisor */ + uint8_t cks; /**< CKS value to get divisor (CKS = N) */ +} baud_setting_const_t; + +/*!< @brief Baud rate bit divisor information structure. */ +static const baud_setting_const_t g_async_baud[ HAL_LL_SCI_NUM_DIVISORS ] = +{ + {0U, 0U, 1U, 0U}, /* BGDM, ABCS, ABCSE, n */ + {1U, 1U, 0U, 0U}, + {1U, 0U, 0U, 0U}, + {0U, 0U, 1U, 1U}, + {0U, 0U, 0U, 0U}, + {1U, 0U, 0U, 1U}, + {0U, 0U, 1U, 2U}, + {0U, 0U, 0U, 1U}, + {1U, 0U, 0U, 2U}, + {0U, 0U, 1U, 3U}, + {0U, 0U, 0U, 2U}, + {1U, 0U, 0U, 3U}, + {0U, 0U, 0U, 3U} +}; + +/*!< @brief Baud rate divisor information structure. */ +static const uint16_t g_div_coefficient[ HAL_LL_SCI_NUM_DIVISORS ] = +{ + 6U, 8U, 16U, 24U, 32U, 64U, 96U, 128U, 256U, 384U, 512U, 1024U, 2048U, +}; + +/*!< @brief UART HW register structure. */ +typedef struct { + uint8_t smr; // Serial Mode Register. + uint8_t brr; // Bit Rate Register. + uint8_t scr; // Serial Control Register. + uint8_t tdr; // Transmit Data Register. + uint8_t ssr; // Serial Status Register. + uint8_t rdr; // Receive Data Register. + uint8_t scmr; // Smart Card Mode Register. + uint8_t semr; // Serial Extended Mode Register. +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure. */ +typedef struct { + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure. */ +typedef struct { + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific error values. */ +typedef enum { + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART hw specific module values. */ +typedef struct { + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART module state selection. */ +typedef enum { + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info. */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[ UART_MODULE_COUNT + 1 ] = { + #ifdef UART_MODULE_0 + {HAL_LL_UART0_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_0 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_1 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_2 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_3 + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_3 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_4 + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_4 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_5 + {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_5 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_6 + {HAL_LL_UART6_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_6 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_7 + {HAL_LL_UART7_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_7 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_8 + {HAL_LL_UART8_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_8 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_9 + {HAL_LL_UART9_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_9 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; +/*!< @brief UART hardware specific info. */ + +/*!< @brief Global handle variables used in functions. */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions. */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed for UART module. + * + * @return uint32_t UART source clock speed in Hz. + */ +static uint32_t hal_ll_uart_get_clock_speed( void ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid. + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + hal_ll_uart_handle_register_t *hal_handle = ( hal_ll_uart_handle_register_t * )*handle; + uint8_t pin_check_result = hal_ll_uart_hw_specifics_map_local->module_index; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = ( handle_t * )&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + + // Chips using this implementation do not support 7 bit data. + if ( ( data_bit < HAL_LL_UART_DATA_BITS_7 ) || ( data_bit > HAL_LL_UART_DATA_BITS_9 ) ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_local, true ); + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable( handle, HAL_LL_UART_IRQ_RX ); + hal_ll_uart_irq_disable( handle, HAL_LL_UART_IRQ_TX ); + + hal_ll_uart_clear_regs( hal_ll_uart_hw_specifics_map_local->base ); + hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ){ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + // TODO + break; + case HAL_LL_UART_IRQ_TX: + // TODO + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) { + #if defined( UART_MODULE_0 ) && defined( UART0_NVIC ) + case hal_ll_uart_module_num( UART_MODULE_0 ): + hal_ll_core_enable_irq( UART0_NVIC ); + break; + #endif + #if defined( UART_MODULE_1 ) && defined( UART1_NVIC ) + case hal_ll_uart_module_num( UART_MODULE_1 ): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + #if defined( UART_MODULE_2 ) && defined( UART2_NVIC ) + case hal_ll_uart_module_num( UART_MODULE_2 ): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + #if defined( UART_MODULE_3 ) && defined( UART3_NVIC ) + case hal_ll_uart_module_num( UART_MODULE_3 ): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + #endif + #if defined( UART_MODULE_4 ) && defined( UART4_NVIC ) + case hal_ll_uart_module_num( UART_MODULE_4 ): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + #endif + #if defined( UART_MODULE_5 ) && defined( UART5_NVIC ) + case hal_ll_uart_module_num( UART_MODULE_5 ): + hal_ll_core_enable_irq( UART5_NVIC ); + break; + #endif + #if defined( UART_MODULE_6 ) && defined( UART6_NVIC ) + case hal_ll_uart_module_num( UART_MODULE_6 ): + hal_ll_core_enable_irq( UART6_NVIC ); + break; + #endif + #if defined(UART_MODULE_7) && defined(UART7_NVIC) + case hal_ll_uart_module_num( UART_MODULE_7 ): + hal_ll_core_enable_irq( UART7_NVIC ); + break; + #endif + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + // TODO + break; + case HAL_LL_UART_IRQ_TX: + // TODO + break; + + default: + break; + } + + /* Check if module interrupt flags are set or not. + * ATTENTION This is a very important part in the code. + * Interrupts should be disabled ONLY in case we have + * both TX and RX interrupts disabled. + */ + if ( + // ( !check_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_RXIM_BIT ) ) && + // ( !check_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_TXIM_BIT ) ) + 1 // TODO + ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) { + #if defined( UART_MODULE_0 ) && defined( UART0_NVIC ) + case hal_ll_uart_module_num( UART_MODULE_0 ): + hal_ll_core_disable_irq( UART0_NVIC ); + break; + #endif + #if defined( UART_MODULE_1 ) && defined( UART1_NVIC ) + case hal_ll_uart_module_num( UART_MODULE_1 ): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + #if defined( UART_MODULE_2 ) && defined( UART2_NVIC ) + case hal_ll_uart_module_num( UART_MODULE_2 ): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + #if defined( UART_MODULE_3 ) && defined( UART3_NVIC ) + case hal_ll_uart_module_num( UART_MODULE_3 ): + hal_ll_core_disable_irq( UART3_NVIC ); + break; + #endif + #if defined( UART_MODULE_4 ) && defined( UART4_NVIC ) + case hal_ll_uart_module_num( UART_MODULE_4 ): + hal_ll_core_disable_irq( UART4_NVIC ); + break; + #endif + #if defined( UART_MODULE_5 ) && defined( UART5_NVIC ) + case hal_ll_uart_module_num( UART_MODULE_5 ): + hal_ll_core_disable_irq( UART5_NVIC ); + break; + #endif + #if defined( UART_MODULE_6 ) && defined( UART6_NVIC ) + case hal_ll_uart_module_num( UART_MODULE_6 ): + hal_ll_core_disable_irq( UART6_NVIC ); + break; + #endif + #if defined( UART_MODULE_7 ) && defined( UART7_NVIC ) + case hal_ll_uart_module_num( UART_MODULE_7 ): + hal_ll_core_disable_irq( UART7_NVIC ); + break; + #endif + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +void hal_ll_uart_write_polling( handle_t *handle, uint8_t wr_data ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t * )hal_ll_uart_hw_specifics_map_local->base; + + // Wait until transmit data register is empty. + while ( !( check_reg_bit( &hal_ll_hw_reg->ssr, HAL_LL_SCI_SSR_TDRE ))); + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t * )hal_ll_uart_hw_specifics_map_local->base; + + return hal_ll_hw_reg->rdr; +} + +uint8_t hal_ll_uart_read_polling( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + // Wait until there is data in the receive data register. + while ( !( check_reg_bit( &hal_ll_hw_reg->ssr, HAL_LL_SCI_SSR_RDRF ))); + + return hal_ll_hw_reg->rdr; +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS +#if defined( UART_MODULE_0 ) && defined( UART0_NVIC ) +void MARK_AS_IRQ_HANDLER UART0_IRQHandler( void ) MIKROC_IV( UART0_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART0_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART0_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_0 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART0_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART0_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_0 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined( UART_MODULE_1 ) && defined( UART1_NVIC ) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler( void ) MIKROC_IV( UART1_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_1 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_1 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined( UART_MODULE_2 ) && defined( UART2_NVIC ) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler( void ) MIKROC_IV( UART2_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_2 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_2 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined( UART_MODULE_3 ) && defined( UART3_NVIC ) +void MARK_AS_IRQ_HANDLER UART3_IRQHandler( void ) MIKROC_IV( UART3_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_3 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_3 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined( UART_MODULE_4 ) && defined( UART4_NVIC ) +void MARK_AS_IRQ_HANDLER UART4_IRQHandler( void ) MIKROC_IV( UART4_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_4 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_4 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined( UART_MODULE_5 ) && defined( UART5_NVIC ) +void MARK_AS_IRQ_HANDLER UART5_IRQHandler( void ) MIKROC_IV( UART5_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_5 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_5 )], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined( UART_MODULE_6 ) && defined( UART6_NVIC ) +void MARK_AS_IRQ_HANDLER UART6_IRQHandler( void ) MIKROC_IV( UART6_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART6_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART6_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_6 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART6_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART6_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_6 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined( UART_MODULE_7 ) && defined( UART7_NVIC ) +void MARK_AS_IRQ_HANDLER UART7_IRQHandler( void ) MIKROC_IV( UART7_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART7_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART7_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_7 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART7_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART7_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_7 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined( UART_MODULE_8 ) && defined( UART8_NVIC ) +void MARK_AS_IRQ_HANDLER UART8_IRQHandler( void ) MIKROC_IV( UART8_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART8_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART8_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_8 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART8_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART8_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_8 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined( UART_MODULE_9 ) && defined( UART9_NVIC ) +void MARK_AS_IRQ_HANDLER UART9_IRQHandler( void ) MIKROC_IV( UART9_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART9_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART9_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_9 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART9_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART9_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_9 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if (( HAL_LL_PIN_NC == tx_pin ) || ( HAL_LL_PIN_NC == rx_pin )) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number. + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names. + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken. + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_uart_handle_register_t )); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_uart_handle_register_t )); + + while( hal_ll_module_count-- ) { + if ( hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base ) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) { + #ifdef UART_MODULE_0 + case ( hal_ll_uart_module_num( UART_MODULE_0 )): + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB31_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB31_POS )); + break; + #endif + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num( UART_MODULE_1 )): + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB30_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB30_POS )); + break; + #endif + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num( UART_MODULE_2 )): + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB29_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB29_POS )); + break; + #endif + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num( UART_MODULE_3 )): + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB28_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB28_POS )); + break; + #endif + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num( UART_MODULE_4 )): + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB27_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB27_POS )); + break; + #endif + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num( UART_MODULE_5 )): + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB26_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB26_POS )); + break; + #endif + #ifdef UART_MODULE_6 + case ( hal_ll_uart_module_num( UART_MODULE_6 )): + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB25_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB25_POS )); + break; + #endif + #ifdef UART_MODULE_7 + case ( hal_ll_uart_module_num( UART_MODULE_7 )): + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB24_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB24_POS )); + break; + #endif + #ifdef UART_MODULE_8 + case ( hal_ll_uart_module_num( UART_MODULE_8 )): + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB23_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB23_POS )); + break; + #endif + #ifdef UART_MODULE_9 + case ( hal_ll_uart_module_num( UART_MODULE_9 )): + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB22_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB22_POS )); + break; + #endif + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins. + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[index_list[module_index].pin_tx].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[index_list[module_index].pin_rx].pin; + // TX and RX could have different alternate function settings, hence save both AF values. + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[index_list[module_index].pin_tx].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[index_list[module_index].pin_rx].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + uint32_t uart_config = 0; + + if (( map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) && + ( map->pins.tx_pin.pin_name != HAL_LL_PIN_NC )) + { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = uart_config; + module.configs[ 1 ] = uart_config; + module.configs[ 2 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base ); + + /* Find the best BRR (bit rate register) value. + * In table g_async_baud, divisor values are stored for BGDM, ABCS, ABCSE and N values. Each set of divisors + * is tried, and the settings with the lowest bit rate error are stored. The formula to calculate BRR is as + * follows and it must be 255 or less: + * BRR = (PCLKA / (div_coefficient * baud)) - 1 + */ + uint32_t error = HAL_LL_SCI_BRR_ERROR_REFERENCE; + uint32_t temp_brr, divisor = 0U; + uint8_t abcse, abcs, bgdm, brr, cks; + int32_t err_divisor, current_error; + uint32_t source_clock = hal_ll_uart_get_clock_speed( ); + + for ( uint8_t select_16_base_clk_cycles = 0U; + (( 1 >= select_16_base_clk_cycles ) && ( HAL_LL_SCI_BRR_ERROR_ACCEPTABLE < error )); + select_16_base_clk_cycles++ ) + { + for ( uint8_t i = 0U; HAL_LL_SCI_NUM_DIVISORS > i ; i++ ) + { + if ( hal_ll_sci_brr_assert_divisors( select_16_base_clk_cycles, i )) + { + continue; + } + + temp_brr = hal_ll_sci_brr_calculate( map->baud_rate.baud, source_clock, i ); + + if (( HAL_LL_SCI_BRR_MAX ) >= temp_brr ) + { + while ( temp_brr-- > 0U ) + { + current_error = hal_ll_sci_brr_get_error( temp_brr, source_clock, map->baud_rate.baud, i ); + + /* Take the absolute value of the bit rate error. */ + if ( current_error < 0 ) + { + current_error = -current_error; + } + + /* If the absolute value of the bit rate error is less than the previous lowest absolute value of + * bit rate error, then store these settings as the best value. + */ + if ( current_error < error ) + { + bgdm = g_async_baud[i].bgdm; + abcs = g_async_baud[i].abcs; + abcse = g_async_baud[i].abcse; + cks = g_async_baud[i].cks; + brr = ( uint8_t ) temp_brr; + error = current_error; + map->baud_rate.real_baud = hal_ll_sci_get_baud_rate( source_clock, brr ,i ); + } + } + } + } + } + + set_reg_bits( &hal_ll_hw_reg->semr, HAL_LL_SCI_SEMR_CONFIGURE( bgdm, abcs, abcse )); + set_reg_bits( &hal_ll_hw_reg->smr, cks ); + write_reg( &hal_ll_hw_reg->brr, brr ); +} + +static uint32_t hal_ll_uart_get_clock_speed( void ) { + system_clocks_t system_clocks; + + SYSTEM_GetClocksFrequency( &system_clocks ); + return system_clocks.pclka; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base ); + + switch ( map->stop_bit ) { + case HAL_LL_UART_STOP_BITS_ONE: + clear_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_STOP ); + break; + case HAL_LL_UART_STOP_BITS_TWO: + set_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_STOP ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base ); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + set_reg_bit( &hal_ll_hw_reg->scmr, HAL_LL_SCI_SCMR_CHR1 ); + set_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_CHR ); + break; + case HAL_LL_UART_DATA_BITS_8: + set_reg_bit( &hal_ll_hw_reg->scmr, HAL_LL_SCI_SCMR_CHR1 ); + clear_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_CHR ); + break; + case HAL_LL_UART_DATA_BITS_9: + clear_reg_bit( &hal_ll_hw_reg->scmr, HAL_LL_SCI_SCMR_CHR1 ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base ); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + clear_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_PE ); + break; + case HAL_LL_UART_PARITY_EVEN: + set_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_PE ); + break; + case HAL_LL_UART_PARITY_ODD: + set_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_PE ); + set_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_PM ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + /* SCI module doesn't have any specific bitfield for enabling it, but + * we disable UART work by switching source clock to external as this implementation + * doesn't support the use of external clock for SCI module. + */ + case HAL_LL_UART_DISABLE: + set_reg_bits( &hal_ll_hw_reg->scr, HAL_LL_SCI_CLOCK_EXTERNAL ); + break; + + case HAL_LL_UART_ENABLE: + clear_reg_bits( &hal_ll_hw_reg->scr, HAL_LL_SCI_CLOCK_EXTERNAL ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &hal_ll_hw_reg->scr, HAL_LL_SCI_SCR_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &hal_ll_hw_reg->scr, HAL_LL_SCI_SCR_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &hal_ll_hw_reg->scr, HAL_LL_SCI_SCR_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &hal_ll_hw_reg->scr, HAL_LL_SCI_SCR_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + clear_reg( &hal_ll_hw_reg->scr ); + while ( read_reg( &hal_ll_hw_reg->scr )); + clear_reg( &hal_ll_hw_reg->smr ); + clear_reg( &hal_ll_hw_reg->ssr ); +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} + +// ------------------------------------------------------------------------- END diff --git a/tests/gpio/CMakeLists.txt b/tests/gpio/CMakeLists.txt index adc9b73f37..1ec26c4d6a 100644 --- a/tests/gpio/CMakeLists.txt +++ b/tests/gpio/CMakeLists.txt @@ -6,7 +6,7 @@ string(SUBSTRING ${MCU_NAME} 0 4 MCU_NAME_FIRST_4) string(SUBSTRING ${MCU_NAME} 0 5 MCU_NAME_FIRST_5) string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) -if ( ( ${MCU_NAME_FIRST_7} STREQUAL "PIC32MZ" ) OR ( ${MCU_NAME_FIRST_7} STREQUAL "PIC32MX" ) OR ( ${MCU_NAME_FIRST_5} STREQUAL "STM32" ) OR ( ${MCU_NAME} MATCHES "GD32VF103" ) OR ( ${MCU_NAME} MATCHES "^(ds)?PIC(24|30|33).*" ) ) +if ( ( ${MCU_NAME_FIRST_7} STREQUAL "PIC32MZ" ) OR ( ${MCU_NAME_FIRST_7} STREQUAL "PIC32MX" ) OR ( ${MCU_NAME_FIRST_5} STREQUAL "STM32" ) OR ( ${MCU_NAME} MATCHES "GD32VF103" ) OR ( ${MCU_NAME} MATCHES "^(ds)?PIC(24|30|33).*" ) OR ( ${MCU_NAME_FIRST_2} STREQUAL "R7" ) ) list(APPEND gpio_def_list "port_count_size=16") elseif( ( ${MCU_NAME_FIRST_5} STREQUAL "PIC18" ) OR ( ${MCU_NAME_FIRST_4} STREQUAL "TM4C" ) OR ( ${MCU_NAME_FIRST_2} STREQUAL "AT" ) ) list(APPEND gpio_def_list "port_count_size=8")