From 9a0fcf806df221bdb41f847a6a0f45ce8d2573ea Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Tue, 3 Jun 2025 10:54:26 +0200 Subject: [PATCH 01/62] Renesas addition initial --- cmake/utils.cmake | 2 + hal/interface/CMakeLists.txt | 2 + .../lcd/lib/include/drivers/lcd_controllers.h | 2 +- targets/arm/mikroe/CMakeLists.txt | 2 + targets/arm/mikroe/common/CMakeLists.txt | 3 + .../arm/mikroe/common/include/flatten_me.h | 71 + .../RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 212 +++ .../RENESAS/R7FA4M1AB3CFM/mcu_reg_addresses.h | 0 targets/arm/mikroe/core/CMakeLists.txt | 7 + .../core/src/renesas/m4/hal_ll_core_port.c | 56 + targets/arm/mikroe/renesas/CMakeLists.txt | 39 + .../mikroe/renesas/include/adc/hal_ll_adc.h | 229 +++ .../implementation_1/hal_ll_adc_pin_map.h | 349 +++++ .../mikroe/renesas/include/can/hal_ll_can.h | 426 ++++++ .../hal_ll_can_pin_map/hal_ll_can_pin_map.h | 151 ++ .../mikroe/renesas/include/dma/hal_ll_dma.h | 311 ++++ .../mikroe/renesas/include/gpio/hal_ll_gpio.h | 276 ++++ .../include/gpio/hal_ll_gpio_constants.h | 102 ++ .../renesas/include/gpio/hal_ll_gpio_port.h | 194 +++ .../mikroe/renesas/include/hal_ll_pin_names.h | 800 ++++++++++ .../arm/mikroe/renesas/include/hal_ll_rcc.h | 70 + .../mikroe/renesas/include/hal_ll_target.h | 67 + .../renesas/include/hal_ll_target_names.h | 72 + .../renesas/include/i2c/hal_ll_i2c_master.h | 241 +++ .../implementation_1/hal_ll_i2c_pin_map.h | 318 ++++ .../include/one_wire/hal_ll_one_wire.h | 229 +++ .../mikroe/renesas/include/rtc/hal_ll_rtc.h | 152 ++ .../include/spi_master/hal_ll_spi_master.h | 228 +++ .../hal_ll_spi_master_pin_map.h | 232 +++ .../mikroe/renesas/include/tim/hal_ll_tim.h | 211 +++ .../implementation_1/hal_ll_tim_pin_map.h | 423 ++++++ .../mikroe/renesas/include/uart/hal_ll_uart.h | 325 +++++ .../implementation_1/hal_ll_uart_pin_map.h | 278 ++++ .../arm/mikroe/renesas/src/adc/CMakeLists.txt | 62 + .../src/adc/implementation_1/hal_ll_adc.c | 224 +++ .../arm/mikroe/renesas/src/can/CMakeLists.txt | 54 + .../src/can/implementation_1/hal_ll_can.c | 1017 +++++++++++++ .../arm/mikroe/renesas/src/dma/CMakeLists.txt | 56 + .../src/dma/implementation_1/hal_ll_dma.c | 759 ++++++++++ .../mikroe/renesas/src/gpio/CMakeLists.txt | 63 + .../arm/mikroe/renesas/src/gpio/hal_ll_gpio.c | 166 +++ .../gpio/implementation_1/hal_ll_gpio_port.c | 614 ++++++++ .../mikroe/renesas/src/hal_ll/CMakeLists.txt | 15 + .../arm/mikroe/renesas/src/i2c/CMakeLists.txt | 72 + .../i2c/implementation_1/hal_ll_i2c_master.c | 453 ++++++ .../renesas/src/one_wire/CMakeLists.txt | 31 + .../renesas/src/one_wire/hal_ll_one_wire.c | 557 +++++++ .../arm/mikroe/renesas/src/rtc/CMakeLists.txt | 39 + .../src/rtc/implementation_1/hal_ll_rtc.c | 276 ++++ .../src/rtc/implementation_2/hal_ll_rtc.c | 265 ++++ .../renesas/src/spi_master/CMakeLists.txt | 65 + .../implementation_1/hal_ll_spi_master.c | 784 ++++++++++ .../arm/mikroe/renesas/src/tim/CMakeLists.txt | 64 + .../src/tim/implementation_1/hal_ll_tim.c | 1056 ++++++++++++++ .../mikroe/renesas/src/uart/CMakeLists.txt | 61 + .../src/uart/implementation_1/hal_ll_uart.c | 1286 +++++++++++++++++ tests/CMakeLists.txt | 1 + tests/renesas/CMakeLists.txt | 10 + tests/renesas/ReadMe.txt | 9 + tests/renesas/src/main.c | 61 + 60 files changed, 14199 insertions(+), 1 deletion(-) create mode 100644 targets/arm/mikroe/common/include/flatten_me.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_reg_addresses/RENESAS/R7FA4M1AB3CFM/mcu_reg_addresses.h create mode 100644 targets/arm/mikroe/core/src/renesas/m4/hal_ll_core_port.c create mode 100644 targets/arm/mikroe/renesas/CMakeLists.txt create mode 100644 targets/arm/mikroe/renesas/include/adc/hal_ll_adc.h create mode 100644 targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h create mode 100644 targets/arm/mikroe/renesas/include/can/hal_ll_can.h create mode 100644 targets/arm/mikroe/renesas/include/can/hal_ll_can_pin_map/hal_ll_can_pin_map.h create mode 100644 targets/arm/mikroe/renesas/include/dma/hal_ll_dma.h create mode 100644 targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h create mode 100644 targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_constants.h create mode 100644 targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h create mode 100644 targets/arm/mikroe/renesas/include/hal_ll_pin_names.h create mode 100644 targets/arm/mikroe/renesas/include/hal_ll_rcc.h create mode 100644 targets/arm/mikroe/renesas/include/hal_ll_target.h create mode 100644 targets/arm/mikroe/renesas/include/hal_ll_target_names.h create mode 100644 targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_master.h create mode 100644 targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h create mode 100644 targets/arm/mikroe/renesas/include/one_wire/hal_ll_one_wire.h create mode 100644 targets/arm/mikroe/renesas/include/rtc/hal_ll_rtc.h create mode 100644 targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h create mode 100644 targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h create mode 100644 targets/arm/mikroe/renesas/include/tim/hal_ll_tim.h create mode 100644 targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h create mode 100644 targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h create mode 100644 targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h create mode 100644 targets/arm/mikroe/renesas/src/adc/CMakeLists.txt create mode 100644 targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c create mode 100644 targets/arm/mikroe/renesas/src/can/CMakeLists.txt create mode 100644 targets/arm/mikroe/renesas/src/can/implementation_1/hal_ll_can.c create mode 100644 targets/arm/mikroe/renesas/src/dma/CMakeLists.txt create mode 100644 targets/arm/mikroe/renesas/src/dma/implementation_1/hal_ll_dma.c create mode 100644 targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt create mode 100644 targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c create mode 100644 targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c create mode 100644 targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt create mode 100644 targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt create mode 100644 targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c create mode 100644 targets/arm/mikroe/renesas/src/one_wire/CMakeLists.txt create mode 100644 targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c create mode 100644 targets/arm/mikroe/renesas/src/rtc/CMakeLists.txt create mode 100644 targets/arm/mikroe/renesas/src/rtc/implementation_1/hal_ll_rtc.c create mode 100644 targets/arm/mikroe/renesas/src/rtc/implementation_2/hal_ll_rtc.c create mode 100644 targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt create mode 100644 targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c create mode 100644 targets/arm/mikroe/renesas/src/tim/CMakeLists.txt create mode 100644 targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c create mode 100644 targets/arm/mikroe/renesas/src/uart/CMakeLists.txt create mode 100644 targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c create mode 100644 tests/renesas/CMakeLists.txt create mode 100644 tests/renesas/ReadMe.txt create mode 100644 tests/renesas/src/main.c diff --git a/cmake/utils.cmake b/cmake/utils.cmake index a44c579aea..5611427fb5 100644 --- a/cmake/utils.cmake +++ b/cmake/utils.cmake @@ -175,6 +175,8 @@ function(find_chip_architecture _chip_architecture) set(${_chip_architecture} "arm" PARENT_SCOPE) elseif(${MCU_NAME} MATCHES "^(AT)?SAM.*") set(${_chip_architecture} "arm" PARENT_SCOPE) + elseif(${MCU_NAME} MATCHES "^R7.*") + set(${_chip_architecture} "arm" PARENT_SCOPE) else() set(${_chip_architecture} "UNSUPPORTED_CHIP_SELECTED_FOR_FOLLOWING_IMPLEMENTATION" PARENT_SCOPE) endif() diff --git a/hal/interface/CMakeLists.txt b/hal/interface/CMakeLists.txt index 6359a32a8d..3489cb9932 100644 --- a/hal/interface/CMakeLists.txt +++ b/hal/interface/CMakeLists.txt @@ -25,6 +25,8 @@ elseif(${MCU_NAME} MATCHES "(^MK(.+)$)") set(vendor_id "nxp") elseif(${MCU_NAME} MATCHES "(^TM4C1(.+)$)") set(vendor_id "tiva") +elseif(${MCU_NAME} MATCHES "(^R7(.+)$)") + set(vendor_id "renesas") elseif(${MCU_NAME} MATCHES "(^PIC32(.+)$)") set(vendor_id "pic32") elseif(${MCU_NAME} MATCHES "(^PIC18(.+)$)") diff --git a/middleware/lcd/lib/include/drivers/lcd_controllers.h b/middleware/lcd/lib/include/drivers/lcd_controllers.h index 6b02056877..3f224978ce 100644 --- a/middleware/lcd/lib/include/drivers/lcd_controllers.h +++ b/middleware/lcd/lib/include/drivers/lcd_controllers.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Copyright (C) MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** Commercial License Usage diff --git a/targets/arm/mikroe/CMakeLists.txt b/targets/arm/mikroe/CMakeLists.txt index 904a304b76..49e9ea0197 100644 --- a/targets/arm/mikroe/CMakeLists.txt +++ b/targets/arm/mikroe/CMakeLists.txt @@ -6,6 +6,8 @@ elseif(${MCU_NAME} MATCHES "(^MK(.+)$)") elseif(${MCU_NAME} MATCHES "(^TM4C1(.+)$)") ## TIVA has only the 71 MCUs already implemented set(vendor_id "tiva") +elseif(${MCU_NAME} MATCHES "(^R7(.+)$)") + set(vendor_id "renesas") elseif(${MCU_NAME} MATCHES "(^(AT)?SAM(.+)$)") set(vendor_id "sam") else() diff --git a/targets/arm/mikroe/common/CMakeLists.txt b/targets/arm/mikroe/common/CMakeLists.txt index 810529ad29..c65778c1bc 100644 --- a/targets/arm/mikroe/common/CMakeLists.txt +++ b/targets/arm/mikroe/common/CMakeLists.txt @@ -41,6 +41,9 @@ elseif(${MCU_NAME} MATCHES "(^ATSAM(.+)$)") elseif(${MCU_NAME} MATCHES "(^TM4C1(.+)$)") set(architecture_macro "TIVA") set(architecture "TIVA") +elseif(${MCU_NAME} MATCHES "(^R7(.+)$)") + set(architecture_macro "RENESAS") + set(architecture "RENESAS") endif() set(header_files "") diff --git a/targets/arm/mikroe/common/include/flatten_me.h b/targets/arm/mikroe/common/include/flatten_me.h new file mode 100644 index 0000000000..446641823e --- /dev/null +++ b/targets/arm/mikroe/common/include/flatten_me.h @@ -0,0 +1,71 @@ +/**************************************************************************** +** +** Copyright (C) MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file flatten_me.h + * @brief mikroSDK code flattener level selection. + */ + +#ifndef __FLATTEN_ME_H__ +#define __FLATTEN_ME_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Flattening levels. + * @ref FLATTEN_ME_LEVEL_NONE - no code flattening done. + * @ref FLATTEN_ME_LEVEL_LOW - flatten only HAL_LL APIs. + * @ref FLATTEN_ME_LEVEL_MID - flatten only HAL_LL and HAL APIs. + * @ref FLATTEN_ME_LEVEL_HIGH - flatten all layered APIs (HAL_LL, HAL and DRV). + */ +#define FLATTEN_ME_LEVEL_NONE (0) +#define FLATTEN_ME_LEVEL_LOW (1) +#define FLATTEN_ME_LEVEL_MID (2) +#define FLATTEN_ME_LEVEL_HIGH (3) + +// Flatten code or not? +#define FLATTEN_ME + +// Flatten level selection. +#define FLATTEN_ME_LEVEL FLATTEN_ME_LEVEL_HIGH + +#ifdef __cplusplus +} +#endif + +#endif // __FLATTEN_ME_H__ diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h new file mode 100644 index 0000000000..8947d45758 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -0,0 +1,212 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + + +//ADC + +#define ADC_MODULE_COUNT 3 +//EOF ADC + +//I2C + +#define I2C_MODULE_COUNT 3 +//EOF I2C + +//UART + +//EOF UART + +//USART + +#define UART_MODULE_COUNT 8 +//EOF USART + +//SPI + +#define SPI_MODULE_COUNT 6 +//EOF SPI + +//TIM + +#define TIM_MODULE_COUNT 12 +//EOF TIM + +//GPIO +#define __PH1_CN +#define __PH0_CN +#define __PG9_CN +#define __PG8_CN +#define __PG7_CN +#define __PG6_CN +#define __PG5_CN +#define __PG4_CN +#define __PG3_CN +#define __PG2_CN +#define __PG15_CN +#define __PG14_CN +#define __PG13_CN +#define __PG12_CN +#define __PG11_CN +#define __PG10_CN +#define __PG1_CN +#define __PG0_CN +#define __PF9_CN +#define __PF8_CN +#define __PF7_CN +#define __PF6_CN +#define __PF5_CN +#define __PF4_CN +#define __PF3_CN +#define __PF2_CN +#define __PF15_CN +#define __PF14_CN +#define __PF13_CN +#define __PF12_CN +#define __PF11_CN +#define __PF10_CN +#define __PF1_CN +#define __PF0_CN +#define __PE9_CN +#define __PE8_CN +#define __PE7_CN +#define __PE6_CN +#define __PE5_CN +#define __PE4_CN +#define __PE3_CN +#define __PE2_CN +#define __PE15_CN +#define __PE14_CN +#define __PE13_CN +#define __PE12_CN +#define __PE11_CN +#define __PE10_CN +#define __PE1_CN +#define __PE0_CN +#define __PD9_CN +#define __PD8_CN +#define __PD7_CN +#define __PD6_CN +#define __PD5_CN +#define __PD4_CN +#define __PD3_CN +#define __PD2_CN +#define __PD15_CN +#define __PD14_CN +#define __PD13_CN +#define __PD12_CN +#define __PD11_CN +#define __PD10_CN +#define __PD1_CN +#define __PD0_CN +#define __PC9_CN +#define __PC8_CN +#define __PC7_CN +#define __PC6_CN +#define __PC5_CN +#define __PC4_CN +#define __PC3_CN +#define __PC2_CN +#define __PC15_CN +#define __PC14_CN +#define __PC13_CN +#define __PC12_CN +#define __PC11_CN +#define __PC10_CN +#define __PC1_CN +#define __PC0_CN +#define __PB9_CN +#define __PB8_CN +#define __PB7_CN +#define __PB6_CN +#define __PB5_CN +#define __PB4_CN +#define __PB3_CN +#define __PB2_CN +#define __PB15_CN +#define __PB14_CN +#define __PB13_CN +#define __PB12_CN +#define __PB11_CN +#define __PB10_CN +#define __PB1_CN +#define __PB0_CN +#define __PA9_CN +#define __PA8_CN +#define __PA7_CN +#define __PA6_CN +#define __PA5_CN +#define __PA4_CN +#define __PA3_CN +#define __PA2_CN +#define __PA15_CN +#define __PA14_CN +#define __PA13_CN +#define __PA12_CN +#define __PA11_CN +#define __PA10_CN +#define __PA1_CN +#define __PA0_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN +#define __PORT_H_CN + +#define PORT_SIZE (32) +#define PORT_COUNT (8) +//EOF GPIO + +//IVT_TABLE + +//EOF IVT_TABLE + + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/RENESAS/R7FA4M1AB3CFM/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/RENESAS/R7FA4M1AB3CFM/mcu_reg_addresses.h new file mode 100644 index 0000000000..e69de29bb2 diff --git a/targets/arm/mikroe/core/CMakeLists.txt b/targets/arm/mikroe/core/CMakeLists.txt index 6167c2ab16..1a8e145ef2 100644 --- a/targets/arm/mikroe/core/CMakeLists.txt +++ b/targets/arm/mikroe/core/CMakeLists.txt @@ -37,6 +37,13 @@ elseif(${MCU_NAME} MATCHES "^TM4C.*") set(chip_vendor "tiva") list(APPEND hal_ll_core_def_list ${chip_vendor}) set(hal_ll_core_source "m4") +elseif(${MCU_NAME} MATCHES "^R7.*") + set(chip_vendor "renesas") + list(APPEND hal_ll_core_def_list ${chip_vendor}) + if((${CORE_NAME} MATCHES "M4EF") OR (${CORE_NAME} MATCHES "M4DSP")) + set(hal_ll_core_source "m4") + list(APPEND hal_ll_core_def_list __cortex_m4__) + endif() elseif(${MCU_NAME} MATCHES "^(AT)?SAM.*") set(chip_vendor "sam") list(APPEND hal_ll_core_def_list ${chip_vendor}) diff --git a/targets/arm/mikroe/core/src/renesas/m4/hal_ll_core_port.c b/targets/arm/mikroe/core/src/renesas/m4/hal_ll_core_port.c new file mode 100644 index 0000000000..5f0094ac60 --- /dev/null +++ b/targets/arm/mikroe/core/src/renesas/m4/hal_ll_core_port.c @@ -0,0 +1,56 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_core_port.c + * @brief This file contains all low level function definitions for chip specific core functionality. + * @note Refers to all M4 cortex chips. + */ + +#include "hal_ll_core_defines.h" +#include "hal_ll_bit_control.h" + +void hal_ll_core_port_nvic_enable_irq( uint8_t IRQn ) +{} + +void hal_ll_core_port_nvic_disable_irq( uint8_t IRQn ) +{} + +void hal_ll_core_port_nvic_set_priority_irq( uint8_t IRQn, uint8_t IRQn_priority ) +{} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/CMakeLists.txt b/targets/arm/mikroe/renesas/CMakeLists.txt new file mode 100644 index 0000000000..c0cce131d5 --- /dev/null +++ b/targets/arm/mikroe/renesas/CMakeLists.txt @@ -0,0 +1,39 @@ +## ./targets/arm/mikroe/renesas/CMakeLists.txt +# ALL MODULES +add_subdirectory(src/hal_ll) + +# SEPARATE MODULES +set(module_list "") +set(module_list_supported "") +set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") + +if (msdk_adc IN_LIST module_list_supported) + add_subdirectory(src/adc) +endif() +if (msdk_gpio_in IN_LIST module_list_supported) + add_subdirectory(src/gpio) +endif() +if (msdk_i2c_master IN_LIST module_list_supported) + add_subdirectory(src/i2c) +endif() +if (msdk_pwm IN_LIST module_list_supported) + add_subdirectory(src/tim) +endif() +if (msdk_spi_master IN_LIST module_list_supported) + add_subdirectory(src/spi_master) +endif() +if (msdk_uart IN_LIST module_list_supported) + add_subdirectory(src/uart) +endif() +if (msdk_onewire IN_LIST module_list_supported) + add_subdirectory(src/one_wire) +endif() +if (msdk_can IN_LIST module_list_supported) + add_subdirectory(src/can) +endif() +if (msdk_dma IN_LIST module_list_supported) + add_subdirectory(src/dma) +endif() +if (msdk_rtc IN_LIST module_list_supported) + add_subdirectory(src/rtc) +endif() diff --git a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc.h b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc.h new file mode 100644 index 0000000000..8bc6da174e --- /dev/null +++ b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc.h @@ -0,0 +1,229 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.h + * @brief This file contains all the functions prototypes for the ADC library. + */ + +#ifndef HAL_LL_ADC_H +#define HAL_LL_ADC_H + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" +#include "hal_ll_rcc.h" + +#define HAL_ADC_6BIT_RES_VAL (0x003FU) +#define HAL_ADC_8BIT_RES_VAL (0x00FFU) +#define HAL_ADC_10BIT_RES_VAL (0x03FFU) +#define HAL_ADC_12BIT_RES_VAL (0x0FFFU) +#define HAL_ADC_14BIT_RES_VAL (0x3FFFU) +#define HAL_ADC_16BIT_RES_VAL (0xFFFFU) + +/** + * @brief ADC low level handle. + * + * The context for storing low level object handler. + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + handle_t *hal_ll_adc_handle; + handle_t *hal_drv_adc_handle; + bool init_ll_state; +} hal_ll_adc_handle_register_t; + + +/** + * ADC VREF. + */ +typedef enum +{ + HAL_LL_ADC_VREF_EXTERNAL = 0, + HAL_LL_ADC_VREF_INTERNAL, + HAL_LL_ADC_VREF_DEFAULT = HAL_LL_ADC_VREF_INTERNAL +} hal_ll_adc_voltage_reference_t; + +/** + * ADC resolution. + */ +typedef enum +{ + HAL_LL_ADC_RESOLUTION_NOT_SET = 0, + HAL_LL_ADC_RESOLUTION_6_BIT, /**< 6 bit resolution */ + HAL_LL_ADC_RESOLUTION_8_BIT, /**< 8 bit resolution */ + HAL_LL_ADC_RESOLUTION_10_BIT, /**< 10 bit resolution */ + HAL_LL_ADC_RESOLUTION_12_BIT, /**< 12 bit resolution */ + HAL_LL_ADC_RESOLUTION_14_BIT, /**< 14 bit resolution */ + HAL_LL_ADC_RESOLUTION_16_BIT, /**< 16 bit resolution */ + + /*!< Default resolution. */ + HAL_LL_ADC_RESOLUTION_DEFAULT = HAL_LL_ADC_RESOLUTION_CMAKE +} hal_ll_adc_resolution_t; + +/** + * @brief ADC low level specific structure. + * + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_adc_voltage_reference_t vref_input; + float vref_value; + uint32_t resolution; + uint8_t channel; +} hal_ll_adc_hw_specifics_map_t; + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ); + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] *handle HAL context object handle. + * @param[in] pin Analog input pin. + * @param[in] vref_input Voltage reference source. + * @param[in] resolution Analog data resolution. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id); + +/** + * @brief Sets ADC resolution. + * + * Sets specified ADC resolution for module. + * Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param[in] *handle HAL context object handle. + * @param[in] resolution ADC resolution. + * + * @return hal_ll_err_t Module specific error or success. + */ +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution); + +/** + * @brief Sets ADC reference voltage source. + * + * Sets ADC reference voltage source for specified + * object. Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param[in] *handle HAL context object handle. + * @param[in] vref_input ADC reference voltage source. + * + * @return hal_ll_err_t Module specific error or success. + */ +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input); + +/** + * @brief Sets ADC reference voltage value. + * + * Sets ADC reference voltage value for specified + * object. + * + * @param[in] *handle HAL context object handle. + * @param[in] vref_input ADC reference voltage value. + * + * @return void None. + */ +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value); + +/** + * @brief Executes data read via ADC module. + * + * Function shall read raw unsigned analog value. + * + * @param handle ADC handle. + * @param *readDatabuf Data buffer where read data + * shall be placed. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_adc_read(handle_t *handle, uint16_t *readDatabuf ); + +/** + * @brief Closes ADC HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_adc_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // HAL_LL_ADC_H +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h new file mode 100644 index 0000000000..75ed529fac --- /dev/null +++ b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h @@ -0,0 +1,349 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Macro defining `weak` attribute */ +#define __weak __attribute__((weak)) + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/*!< ADC module base addresses. */ +#ifdef ADC_MODULE_0 +static const hal_ll_base_addr_t ADC0_BASE_ADDR = 0x40038000; +#endif +#ifdef ADC_MODULE_1 +static const hal_ll_base_addr_t ADC1_BASE_ADDR = 0x40039000; +#endif + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + uint8_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint8_t channel; +} hal_ll_pin_channel_list_t; + +static const hal_ll_pin_channel_list_t hal_ll_analog_in_register_list[] = +{ + #ifdef ADC0_PE3_AIN0 + {GPIO_PE3, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_0}, + #endif + #ifdef ADC1_PE3_AIN0 + {GPIO_PE3, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0}, + #endif + #ifdef ADC0_PE2_AIN1 + {GPIO_PE2, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PE2_AIN1 + {GPIO_PE2, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC0_PE1_AIN2 + {GPIO_PE1, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PE1_AIN2 + {GPIO_PE1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC0_PE0_AIN3 + {GPIO_PE0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PE0_AIN3 + {GPIO_PE0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC0_PD3_AIN4 + {GPIO_PD3, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PD3_AIN4 + {GPIO_PD3, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC0_PD2_AIN5 + {GPIO_PD2, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PD2_AIN5 + {GPIO_PD2, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC0_PD1_AIN6 + {GPIO_PD1, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PD1_AIN6 + {GPIO_PD1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC0_PD0_AIN7 + {GPIO_PD0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PD0_AIN7 + {GPIO_PD0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC0_PE5_AIN8 + {GPIO_PE5, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PE5_AIN8 + {GPIO_PE5, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC0_PE4_AIN9 + {GPIO_PE4, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC1_PE4_AIN9 + {GPIO_PE4, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC0_PB4_AIN10 + {GPIO_PB4, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC1_PB4_AIN10 + {GPIO_PB4, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC0_PB5_AIN11 + {GPIO_PB5, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PB5_AIN11 + {GPIO_PB5, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC0_PD7_AIN4 + {GPIO_PD7, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PD7_AIN4 + {GPIO_PD7, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC0_PD6_AIN5 + {GPIO_PD6, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PD6_AIN5 + {GPIO_PD6, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC0_PD5_AIN6 + {GPIO_PD5, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PD5_AIN6 + {GPIO_PD5, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC0_PD4_AIN7 + {GPIO_PD4, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PD4_AIN7 + {GPIO_PD4, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC0_PD3_AIN12 + {GPIO_PD3, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC1_PD3_AIN12 + {GPIO_PD3, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC0_PD2_AIN13 + {GPIO_PD2, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC1_PD2_AIN13 + {GPIO_PD2, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC0_PD1_AIN14 + {GPIO_PD1, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC1_PD1_AIN14 + {GPIO_PD1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC0_PD0_AIN15 + {GPIO_PD0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PD0_AIN15 + {GPIO_PD0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC0_PH0_AIN16 + {GPIO_PH0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC1_PH0_AIN16 + {GPIO_PH0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC0_PH1_AIN17 + {GPIO_PH1, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC1_PH1_AIN17 + {GPIO_PH1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC0_PH2_AIN18 + {GPIO_PH2, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_18}, + #endif + #ifdef ADC1_PH2_AIN18 + {GPIO_PH2, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_18}, + #endif + #ifdef ADC0_PH3_AIN19 + {GPIO_PH3, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_19}, + #endif + #ifdef ADC1_PH3_AIN19 + {GPIO_PH3, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_19}, + #endif + #ifdef ADC0_PE7_AIN20 + {GPIO_PE7, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_20}, + #endif + #ifdef ADC1_PE7_AIN20 + {GPIO_PE7, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_20}, + #endif + #ifdef ADC0_PE6_AIN21 + {GPIO_PE6, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_21}, + #endif + #ifdef ADC1_PE6_AIN21 + {GPIO_PE6, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_21}, + #endif + #ifdef ADC0_PK0_AIN16 + {GPIO_PK0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC1_PK0_AIN16 + {GPIO_PK0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC0_PK1_AIN17 + {GPIO_PK1, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC1_PK1_AIN17 + {GPIO_PK1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC0_PK2_AIN18 + {GPIO_PK2, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_18}, + #endif + #ifdef ADC1_PK2_AIN18 + {GPIO_PK2, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_18}, + #endif + #ifdef ADC0_PK3_AIN19 + {GPIO_PK3, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_19}, + #endif + #ifdef ADC1_PK3_AIN19 + {GPIO_PK3, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_19}, + #endif + #ifdef ADC0_PP1_AIN22 + {GPIO_PP1, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_22}, + #endif + #ifdef ADC1_PP1_AIN22 + {GPIO_PP1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_22}, + #endif + #ifdef ADC0_PP0_AIN23 + {GPIO_PP0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_23}, + #endif + #ifdef ADC1_PP0_AIN23 + {GPIO_PP0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_23}, + #endif + #ifdef ADC0_PN1_AIN22 + {GPIO_PN1, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_22}, + #endif + #ifdef ADC1_PN1_AIN22 + {GPIO_PN1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_22}, + #endif + #ifdef ADC0_PN0_AIN23 + {GPIO_PN0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_23}, + #endif + #ifdef ADC1_PN0_AIN23 + {GPIO_PN0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_23}, + #endif + #ifdef ADC0_PE6_AIN20 + {GPIO_PE6, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_20}, + #endif + #ifdef ADC1_PE6_AIN20 + {GPIO_PE6, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_20}, + #endif + #ifdef ADC0_PE7_AIN21 + {GPIO_PE7, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_21}, + #endif + #ifdef ADC1_PE7_AIN21 + {GPIO_PE7, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_21}, + #endif + #ifdef ADC0_PP7_AIN22 + {GPIO_PP7, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_22}, + #endif + #ifdef ADC1_PP7_AIN22 + {GPIO_PP7, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_22}, + #endif + #ifdef ADC0_PP6_AIN23 + {GPIO_PP6, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_23}, + #endif + #ifdef ADC1_PP6_AIN23 + {GPIO_PP6, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_23}, + #endif + + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR } + //------------ END +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/can/hal_ll_can.h b/targets/arm/mikroe/renesas/include/can/hal_ll_can.h new file mode 100644 index 0000000000..0d87e37119 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/can/hal_ll_can.h @@ -0,0 +1,426 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can.h + * @brief API for CAN HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_CAN_H_ +#define _HAL_LL_CAN_H_ + +#include "hal_ll_target.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief CAN low level pins config structure. + * + * The context structure for storing low level pin configuration + * for both TX and RX pins. + * + */ +typedef struct +{ + hal_ll_pin_af_t tx_pin; + hal_ll_pin_af_t rx_pin; +} hal_ll_can_pins_t; + +/** + * @details CAN modes. + */ +typedef enum +{ + /* Universal Modes. */ + HAL_LL_CAN_MODE_NORMAL = 0, /*!< Mode for normal operation. */ + HAL_LL_CAN_MODE_LOOPBACK, /*!< Mode for testing communication internally with sending TX data frames to other nodes. */ + HAL_LL_CAN_MODE_DISABLE, /*!< Mode for ignoring TX and RX data frames. */ + /* STM32 and RISC-V Modes. */ + HAL_LL_CAN_MODE_SILENT, /*!< Mode for only receiving messages. */ + HAL_LL_CAN_MODE_LOOPBACK_SILENT, /*!< Mode for testing communication internally without sending TX data frames to other nodes. */ + /* NXP Modes. */ + HAL_LL_CAN_MODE_LISTENONLY, /*!< Mode for only receiving messages. */ + HAL_LL_CAN_MODE_DOZE, /*!< Mode for acknowledging system low-power mode. */ + HAL_LL_CAN_MODE_STOP, /*!< Mode for acknowledging system clock stop. */ + HAL_LL_CAN_MODE_FREEZE, /*!< Mode for ignoring TX and RX data frames. */ + /* dsPIC Modes. */ + HAL_LL_CAN_MODE_LISTENALL, /*!< Mode for receiving data frames without filter configs. */ + /* PIC/PIC32 Modes. */ + HAL_LL_CAN_MODE_CONFIGURATION /*!< Mode for configuring CAN module. */ +} hal_ll_can_mode_t; + +/** + * @details CAN data frame formats. + */ +typedef enum +{ + HAL_LL_CAN_FRAME_FORMAT_STANDARD_11BITS = 0, /*!< Standard format identifier. */ + HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS /*!< Extended format identifier. */ +} hal_ll_can_frame_format_t; + +/** + * @details CAN data frame types. + */ +typedef enum +{ + HAL_LL_CAN_FRAME_TYPE_DATA = 0, /*!< Data frame. */ + HAL_LL_CAN_FRAME_TYPE_RTR /*!< Remote frame. */ +} hal_ll_can_frame_type_t; + +/** + * @details CAN filter mode. + */ +typedef enum +{ + HAL_LL_CAN_FILTER_MODE_IDMASK = 0, /*!< Identifier mask mode. */ + HAL_LL_CAN_FILTER_MODE_IDLIST /*!< Identifier list mode. */ +} hal_ll_can_filter_mode_t; + +/** + * @details CAN filter scale. + */ +typedef enum +{ + HAL_LL_CAN_FILTER_SCALE_16BIT = 0, /*!< Two 16-bit filters. */ + HAL_LL_CAN_FILTER_SCALE_32BIT /*!< One 32-bit filter. */ +} hal_ll_can_filter_scale_t; + +/** + * @details CAN filter FIFO. + */ +typedef enum +{ + HAL_LL_CAN_FILTER_FIFO0 = 0, /*!< Filter mapped to FIFO0. */ + HAL_LL_CAN_FILTER_FIFO1, /*!< Filter mapped to FIFO1. */ + HAL_LL_CAN_FILTER_FIFO2, /*!< Filter mapped to FIFO2. */ + HAL_LL_CAN_FILTER_FIFO3, /*!< Filter mapped to FIFO3. */ + HAL_LL_CAN_FILTER_FIFO4, /*!< Filter mapped to FIFO4. */ + HAL_LL_CAN_FILTER_FIFO5, /*!< Filter mapped to FIFO5. */ + HAL_LL_CAN_FILTER_FIFO6, /*!< Filter mapped to FIFO6. */ + HAL_LL_CAN_FILTER_FIFO7, /*!< Filter mapped to FIFO7. */ + HAL_LL_CAN_FILTER_FIFO8, /*!< Filter mapped to FIFO8. */ + HAL_LL_CAN_FILTER_FIFO9, /*!< Filter mapped to FIFO9. */ + HAL_LL_CAN_FILTER_FIFO10, /*!< Filter mapped to FIFO10. */ + HAL_LL_CAN_FILTER_FIFO11, /*!< Filter mapped to FIFO11. */ + HAL_LL_CAN_FILTER_FIFO12, /*!< Filter mapped to FIFO12. */ + HAL_LL_CAN_FILTER_FIFO13, /*!< Filter mapped to FIFO13. */ + HAL_LL_CAN_FILTER_FIFO14, /*!< Filter mapped to FIFO14. */ + HAL_LL_CAN_FILTER_FIFO15, /*!< Filter mapped to FIFO15. */ + HAL_LL_CAN_FILTER_FIFO16, /*!< Filter mapped to FIFO16. */ + HAL_LL_CAN_FILTER_FIFO17, /*!< Filter mapped to FIFO17. */ + HAL_LL_CAN_FILTER_FIFO18, /*!< Filter mapped to FIFO18. */ + HAL_LL_CAN_FILTER_FIFO19, /*!< Filter mapped to FIFO19. */ + HAL_LL_CAN_FILTER_FIFO20, /*!< Filter mapped to FIFO20. */ + HAL_LL_CAN_FILTER_FIFO21, /*!< Filter mapped to FIFO21. */ + HAL_LL_CAN_FILTER_FIFO22, /*!< Filter mapped to FIFO22. */ + HAL_LL_CAN_FILTER_FIFO23, /*!< Filter mapped to FIFO23. */ + HAL_LL_CAN_FILTER_FIFO24, /*!< Filter mapped to FIFO24. */ + HAL_LL_CAN_FILTER_FIFO25, /*!< Filter mapped to FIFO25. */ + HAL_LL_CAN_FILTER_FIFO26, /*!< Filter mapped to FIFO26. */ + HAL_LL_CAN_FILTER_FIFO27, /*!< Filter mapped to FIFO27. */ + HAL_LL_CAN_FILTER_FIFO28, /*!< Filter mapped to FIFO28. */ + HAL_LL_CAN_FILTER_FIFO29, /*!< Filter mapped to FIFO29. */ + HAL_LL_CAN_FILTER_FIFO30, /*!< Filter mapped to FIFO30. */ + HAL_LL_CAN_FILTER_FIFO31 /*!< Filter mapped to FIFO31. */ +} hal_ll_can_filter_fifo_t; + +/*< @brief Default FIFO number and filter bank used for CAN implementation */ +#define HAL_LL_CAN_FILTER_FIFO_DEFAULT HAL_LL_CAN_FILTER_FIFO2 +#define HAL_LL_CAN_FILTER_BANK_DEFAULT (0) + +/** + * @details CAN filter activation. + */ +typedef enum +{ + HAL_LL_CAN_FILTER_DISABLE = 0, /*!< CAN filter disable. */ + HAL_LL_CAN_FILTER_ENABLE /*!< CAN filter enable. */ +} hal_ll_can_filter_activation_t; + +/** + * @details CAN filter config structure. + */ +typedef struct +{ + union { + struct { + uint16_t can_filter_id_low; /*!< 16-bit Filter ID. */ + uint16_t can_filter_id_high; /*!< 16-bit Filter ID. */ + }; + uint32_t can_filter_id; /*!< 32-bit Filter ID. */ + }; + union { + struct { + uint16_t can_filter_mask_id_low; /*!< 16-bit Filter ID or Filter Mask. */ + uint16_t can_filter_mask_id_high; /*!< 16-bit Filter ID or Filter Mask. */ + }; + uint32_t can_filter_mask_id; /*!< 32-bit Filter ID or Filter Mask. */ + }; + uint8_t can_filter_bank; /*!< Filter bank. */ + hal_ll_can_frame_type_t can_filter_frame_type[4]; /*!< Type of frame, data or remote. */ + hal_ll_can_filter_activation_t can_filter_enable; /*!< Filter activation status. */ + hal_ll_can_filter_mode_t can_filter_mode; /*!< Filter mode. */ + hal_ll_can_filter_scale_t can_filter_scale; /*!< Filter scale. */ + hal_ll_can_filter_fifo_t can_filter_fifo; /*!< Filter-to-FIFO mapping. */ +} hal_ll_can_filter_config_t; + +/** + * @details CAN module config structure. + */ +typedef struct +{ + hal_ll_pin_name_t tx_pin; /*!< Tx pin. */ + hal_ll_pin_name_t rx_pin; /*!< Rx pin. */ + hal_ll_can_mode_t mode; /*!< CAN mode. */ + uint32_t frequency; /*!< CAN frequency. */ +} hal_ll_can_config_t; + +/** + * @details Message structure. + */ +typedef struct +{ + union { + struct { + uint16_t std_id; /*!< Standard format frame identifier. */ + uint16_t ext_id; /*!< Extended format frame identifier. */ + }; + uint32_t message_id; + }; + hal_ll_can_frame_format_t frame_format; /*!< Format of frame, standard or extended format. */ + hal_ll_can_frame_type_t frame_type; /*!< Type of frame, data or remote. */ + uint8_t data_len; /*!< Data length. */ + uint8_t message_data[8]; /*!< Data. */ +} hal_ll_can_message_t; + +/** + * @details CAN HAL low level transmit message structure. + */ +typedef struct +{ + hal_ll_can_message_t message; /* CAN message structure. */ +} hal_ll_can_transmit_message_struct; + +/** + * @details CAN HAL low level receive message structure. + */ +typedef struct +{ + hal_ll_can_message_t message; /* CAN message structure. */ + uint8_t rx_fifo_number; /* Receive FIFO number. */ +} hal_ll_can_receive_message_struct; + +/** + * @brief CAN low level handle. + * + * The context for storing low level object handler. + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + handle_t *hal_ll_can_handle; /*!< CAN HAL low level handle */ + handle_t *hal_drv_can_handle; /*!< CAN DRV level handle */ + bool init_ll_state; /*!< CAN HAL low level object init state */ +} hal_ll_can_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] tx_pin CAN TX pin. + * @param[in] rx_pin CAN RX pin. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_can_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, + hal_ll_can_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Initializes specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] handle HAL context object handle. + * @param[in] config HAL low level config structure. + * @param[in] filter_config HAL low level filter config structure. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_can_init( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ); + +/** + * @brief Sets filter parameters. + * + * Initializes module with specified filter parameters. + * + * @param[in] handle HAL context object handle. + * @param[in] config HAL low level config structure. + * @param[in] filter_config HAL low level filter config structure. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_can_set_filter( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ); + +/** + * @brief Sets adequate bit timing parameters for desired frequency. + * + * @note: Setting parameters that result in a baud rate that + * differs from the desired value is not acceptable. + * If two devices communicate over CAN, their baud + * rates need to be exactly the same. + * + * @param[in] handle HAL context object handle. + * @param[in] config HAL low level config structure. + * @param[in] filter_config HAL low level filter config structure. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_can_set_frequency( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ); + +/** + * @brief Gets CAN frequency. + * + * Gets the currently configured CAN frequency. + * + * @param[in] handle HAL context object handle. + * + * Returns CAN frequency. + */ +hal_ll_err_t hal_ll_can_get_frequency( handle_t *handle ); + +/** + * @brief Sets desired CAN operating mode. + * + * Initializes module with specified CAN mode. + * + * @param[in] handle HAL context object handle. + * @param[in] config HAL low level config structure. + * @param[in] filter_config HAL low level filter config structure. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_can_set_mode( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ); + +/** + * @brief Gets CAN mode. + * + * Gets the currently configured CAN mode. + * + * @param[in] handle HAL context object handle. + * + * Returns CAN mode. + */ +hal_ll_err_t hal_ll_can_get_mode( handle_t *handle ); + +/** + * @brief Performs transmit operation. + * + * Accesses hardware transmit registers and + * writes parameters and data directly to them. + * + * @param[in] handle HAL context object handle. + * @param[in] transmit_message Transmit message structure. + * + * Returns one of pre-defined values. + */ +hal_ll_err_t hal_ll_can_transmit( handle_t *handle, hal_ll_can_transmit_message_struct *transmit_message ); + +/** + * @brief Stops transmit operation. + * + * Accesses hardware transmit registers and stops data transmission. + * + * @param[in] handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_can_transmission_stop( handle_t *handle ); + +/** + * @brief Performs receive operation. + * + * Accesses hardware receive registers and + * reads parameters and data directly from them. + * + * @param[in] handle HAL context object handle. + * @param[in] receive_message Receive message structure. + * + * Returns one of pre-defined values. + */ +hal_ll_err_t hal_ll_can_receive( handle_t *handle, hal_ll_can_receive_message_struct *receive_message ); + +/** + * @brief Closes CAN HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * Returns one of pre-defined values. + */ +hal_ll_err_t hal_ll_can_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_CAN_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/can/hal_ll_can_pin_map/hal_ll_can_pin_map.h b/targets/arm/mikroe/renesas/include/can/hal_ll_can_pin_map/hal_ll_can_pin_map.h new file mode 100644 index 0000000000..1253ba173b --- /dev/null +++ b/targets/arm/mikroe/renesas/include/can/hal_ll_can_pin_map/hal_ll_can_pin_map.h @@ -0,0 +1,151 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can_pin_map.h + * @brief CAN HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_CAN_PIN_MAP_H_ +#define _HAL_LL_CAN_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_can_module_num(_module_num) (_module_num - 1) + +/*!< @brief Macro defining `weak` attribute */ +#define __weak __attribute__((weak)) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_can_pin_map_t; + +/*!< @brief CAN RX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_rx_map[] = +{ + //------------ BEGIN RX + #ifdef CAN0_RX_PF0_AF3 + {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PF0, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF3}, + #endif + #ifdef CAN0_RX_PE4_AF8 + {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PE4, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF8}, + #endif + #ifdef CAN0_RX_PB4_AF8 + {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PB4, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF8}, + #endif + #ifdef CAN0_RX_PN0_AF1 + {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PN0, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF1}, + #endif + #ifdef CAN1_RX_PA0_AF8 + {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PA0, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF8}, + #endif + #ifdef CAN1_RX_PE6_AF8 + {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PE6, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF8}, + #endif + #ifdef CAN0_RX_PA0_AF7 + {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PA0, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF7}, + #endif + #ifdef CAN1_RX_PB0_AF7 + {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PB0, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF7}, + #endif + #ifdef CAN1_RX_PT2_AF7 + {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PT2, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF7}, + #endif + #ifdef CAN0_RX_PT0_AF7 + {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PT0, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF7}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +/*!< @brief CAN TX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_tx_map[] = +{ + //------------ BEGIN TX + #ifdef CAN0_TX_PE5_AF8 + {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PE5, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF8}, + #endif + #ifdef CAN0_TX_PB5_AF8 + {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PB5, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF8}, + #endif + #ifdef CAN0_TX_PF3_AF3 + {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PF3, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF3}, + #endif + #ifdef CAN0_TX_PN1_AF1 + {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PN1, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF1}, + #endif + #ifdef CAN1_TX_PA1_AF8 + {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PA1, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF8}, + #endif + #ifdef CAN1_TX_PE7_AF8 + {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PE7, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF8}, + #endif + #ifdef CAN1_TX_PB1_AF7 + {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PB1, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF7}, + #endif + #ifdef CAN0_TX_PA1_AF7 + {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PA1, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF7}, + #endif + #ifdef CAN1_TX_PT3_AF7 + {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PT3, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF7}, + #endif + #ifdef CAN0_TX_PT1_AF7 + {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PT1, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF7}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_CAN_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/dma/hal_ll_dma.h b/targets/arm/mikroe/renesas/include/dma/hal_ll_dma.h new file mode 100644 index 0000000000..40767116ad --- /dev/null +++ b/targets/arm/mikroe/renesas/include/dma/hal_ll_dma.h @@ -0,0 +1,311 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.h + * @brief API for DMA HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_DMA_H_ +#define _HAL_LL_DMA_H_ + +#include "hal_ll_target.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @details Return values. + */ +typedef enum +{ + HAL_LL_DMA_SUCCESS = 0, /*!< Success. */ + HAL_LL_DMA_ERROR = (-1) /*!< Error. */ +} hal_ll_dma_err_t; + +/** + * @details Module state values. + */ +typedef enum +{ + HAL_LL_DMA_STATE_FREE = 0, /*!< DMA object is free for use. */ + HAL_LL_DMA_STATE_ALLOCATED /*!< DMA object has been allocated - not free for use. */ +} hal_ll_dma_state_t; + +/** + * @details Source address memory region. + */ +typedef enum +{ + HAL_LL_DMA_SOURCE_MEMORY_REGION_RAM = 0, /*!< DMA source address is in RAM section. */ + HAL_LL_DMA_SOURCE_MEMORY_REGION_PFM = 1, /*!< DMA source address is in Program Flash Memory section. */ + HAL_LL_DMA_SOURCE_MEMORY_REGION_DEEPROM = 2 /*!< DMA source address is in Data EEPROM section. */ +} hal_ll_dma_source_memory_region_t; + +/** + * @details Module direction values. + */ +typedef enum +{ + HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY = 0, /*!< M2M */ + HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH, /*!< M2P */ + HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY, /*!< P2M */ + HAL_LL_DMA_DIRECTION_PERIPH_TO_PERIPH, /*!< P2P */ + + HAL_LL_DMA_DIRECTION_DEFAULT = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Default value is M2M. */ +} hal_ll_dma_direction_t; + +/** + * @details Module data alignment values. + */ +typedef enum +{ + HAL_LL_DMA_DATA_ALIGN_BYTES_1 = 0, /*!< Align data to byte (uint8_t). */ + HAL_LL_DMA_DATA_ALIGN_BYTES_2, /*!< Align data to half word (uint16_t). */ + HAL_LL_DMA_DATA_ALIGN_BYTES_3, /*!< Align data to 3 bytes (uint24_t). */ + HAL_LL_DMA_DATA_ALIGN_BYTES_4, /*!< Align data to word (uint32_t). */ + + HAL_LL_DMA_DATA_ALIGN_DEFAULT = HAL_LL_DMA_DATA_ALIGN_BYTES_1 /*!< Default data alignment of byte (uint8_t). */ +} hal_ll_dma_data_align_t; + +/** + * @details Module mode values. + */ +typedef enum +{ + HAL_LL_DMA_MODE_NORMAL = 0, /*!< Normal mode. */ + HAL_LL_DMA_MODE_CIRCULAR, /*!< Circular mode. */ + + HAL_LL_DMA_MODE_DEFAULT = HAL_LL_DMA_MODE_NORMAL /*!< Default mode set to normal. */ +} hal_ll_dma_mode_t; + +/** + * @details Module priority levels. + */ +typedef enum +{ + HAL_LL_DMA_PRIORITY_LOW = 0, /*!< Sets priority level to low. */ + HAL_LL_DMA_PRIORITY_MEDIUM, /*!< Sets priority level to medium. */ + HAL_LL_DMA_PRIORITY_HIGH, /*!< Sets priority level to high. */ + HAL_LL_DMA_PRIORITY_VERY_HIGH, /*!< Sets priority level to very high. */ + + HAL_LL_DMA_PRIORITY_DEFAULT = HAL_LL_DMA_PRIORITY_MEDIUM /*!< Default priority level set to medium. */ +} hal_ll_dma_priority_t; + +/** + * @details Module burst increment size. + */ +typedef enum +{ + HAL_LL_DMA_BURST_SIZE_INCREMENT_1 = 0, /*!< Dma module burst increment size set to 1 byte. */ + HAL_LL_DMA_BURST_SIZE_INCREMENT_2, /*!< Dma module burst increment size set to 2 bytes. */ + HAL_LL_DMA_BURST_SIZE_INCREMENT_4, /*!< Dma module burst increment size set to 4 bytes. */ + HAL_LL_DMA_BURST_SIZE_INCREMENT_8, /*!< Dma module burst increment size set to 8 bytes. */ + HAL_LL_DMA_BURST_SIZE_INCREMENT_16, /*!< Dma module burst increment size set to 16 bytes. */ + HAL_LL_DMA_BURST_SIZE_INCREMENT_32, /*!< Dma module burst increment size set to 32 bytes. */ + + HAL_LL_DMA_BURST_SIZE_INCREMENT_DEFAULT = HAL_LL_DMA_BURST_SIZE_INCREMENT_1 /*!< Default burst increment size set to 1 byte. */ +} hal_ll_dma_burst_size_t; + +/** + * @brief HAL LL DMA Configuration Structure prototype. + */ +typedef struct +{ + uint8_t module; /*!< Specifies the module. */ + uint8_t stream; /*!< Specifies the stream. */ + uint8_t channel; /*!< Specifies the channel used for the specified stream. */ + hal_ll_dma_direction_t direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory, from peripheral to memory, or from + peripheral to peripheral. + This parameter can be a value of @ref hal_ll_dma_direction_t */ + hal_ll_dma_mode_t mode; /*!< Specifies the operation mode of the DMA Stream. + This parameter can be a value of @ref hal_ll_dma_mode_t */ + bool src_inc; /*!< Specifies whether the Source address register should be incremented or not. */ + hal_ll_dma_data_align_t data_align_source; /*!< Specifies the Source data width. + This parameter can be a value of @ref hal_ll_dma_data_align_t */ + hal_ll_dma_burst_size_t burst_size_source; /*!< Specifies the Burst transfer configuration for the source transfers. + It specifies the amount of data to be transferred in a single non interruptable + transaction. + This parameter can be a value of @ref hal_ll_dma_burst_size_t + @note The burst mode is possible only if the address increment mode is enabled. */ + bool dst_inc; /*!< Specifies whether the Destination address register should be incremented or not. */ + hal_ll_dma_data_align_t data_align_destination; /*!< Specifies the Destination data width. + This parameter can be a value of @ref hal_ll_dma_data_align_t */ + hal_ll_dma_burst_size_t burst_size_destination; /*!< Specifies the Burst transfer configuration for the destination transfers. + It specifies the amount of data to be transferred in a single non interruptable + transaction. + This parameter can be a value of @ref hal_ll_dma_burst_size_t + @note The burst mode is possible only if the address increment mode is enabled. */ + hal_ll_dma_priority_t priority; /*!< Specifies the software priority for the DMA Stream. + This parameter can be a value of @ref hal_ll_dma_priority_t */ + uint32_t addr_src; /*!< Address to transfer from. */ + uint32_t addr_dst; /*!< Address to transfer to. */ + size_t transfer_length; /*!< Number of bytes to transfer. */ +} hal_ll_dma_config_t; + +/** + * @brief HAL DMA Handle prototype. + * @details DMA hal context structure, used by every other function later on. + */ +typedef struct +{ + handle_t handle; /*!< DMA HAL LL handle. */ + hal_ll_dma_config_t config; /*!< DMA HAL LL configuration structure. */ + uint8_t module; /*!< Specifies the module. */ + uint8_t stream; /*!< Specifies the stream. */ + uint8_t channel; /*!< Specifies the channel used for the specified stream. */ + hal_ll_dma_state_t allocated; /*!< Is the object allocated or not? */ + bool initialized; /*!< Is the object initialized or not? */ +} hal_ll_dma_t; + +/** + * @brief Initializes the DMA module. + * @details Enables module clock and initializes to values set in + * @b hal_ll_dma_t->hal_ll_dma_config_t + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ); + +/** + * @brief Set the DMA mode. + * @details Sets DMA mode to be used by the DMA HAL LL. + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @param[in] mode DMA mode. + * See #hal_ll_dma_mode_t for valid values. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ); + +/** + * @brief Set the DMA direction. + * @details Sets DMA direction to be used by the DMA HAL LL. + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @param[in] direction DMA direction. + * See #hal_ll_dma_direction_t for valid values. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ); + +/** + * @brief Set the DMA priority. + * @details Sets DMA priority level to be used by the DMA HAL LL. + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @param[in] priority DMA priority level. + * See #hal_ll_dma_priority_t for valid values. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ); + +/** + * @brief Configure the DMA transfer. + * @details Configures initialized DMA stream for transfer. + * @param[in,out] obj DMA HAL LL object. + * See #hal_dma_t structure definition for detailed explanation. + * @param[in] addr_src Source address for transfer. + * @param[in] addr_dst Destination address for transfer. + * @param[in] transfer_size Number of bytes to transfer. + * @param[in] src_mem_type Source address memory region. + * @return Nothing. + */ +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ); + +/** + * @brief Initializes the DMA transfer. + * @details Starts previously configured DMA transfer by enabling stream. + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ); + +/** + * @brief Stops the DMA transfer. + * @details Stops an active DMA transfer by disabling stream. + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ); + +/** + * @brief Aborts a DMA transfer. + * @details Aborts any ongoing DMA transfers and disables stream. + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ); + +/** + * @brief De-initializes the DMA module. + * @details Disables module clock and de-initializes module. + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *dma_obj ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_DMA_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h new file mode 100644 index 0000000000..224c946d1a --- /dev/null +++ b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h @@ -0,0 +1,276 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio.h + * @brief This file contains all the functions prototypes for the GPIO library. + */ + +#ifndef _HAL_LL_GPIO_H_ +#define _HAL_LL_GPIO_H_ + +#include "hal_ll_gpio_port.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief Function configures pin. + * + * Configures pin to digital output or digital input. + * Sets only the pin defined by pin mask in + * hal_ll_gpio_pin_t structure. + * + * @param *pin Pin object context. + * Configured during this functions process. + * @param name Pin name -- GPIO_PA0, GPIO_PA1... + * @param direction Pin direction. + * HAL_LL_GPIO_DIGITAL_INPUT + * HAL_LL_GPIO_DIGITAL_OUTPUT + * + * @return None. + */ +void hal_ll_gpio_configure_pin(hal_ll_gpio_pin_t *pin, hal_ll_pin_name_t name, hal_ll_gpio_direction_t direction); + +/** + * @brief Read pin input. + * + * Checks pin data input register value and + * returns logical state. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return uint8_t Pin logical state. + * 1/true -- pin high state -- 1.8V or more detected + * 0/false -- pin low state -- 1.8V or less detected + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_pin_input(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) == 0) ? \ + (0) : (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata & ((hal_ll_gpio_pin_t *)_handle)->mask) ? \ + (1) : (0)) +#else +uint8_t hal_ll_gpio_read_pin_input(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Read pin output. + * + * Checks pin data output register value and + * returns logical state. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return uint8_t Pin logical state. + * 1/true -- pin high state -- 1.8V or more detected + * 0/false -- pin low state -- 1.8V or less detected + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) == 0) ? \ + (0) : (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata & ((hal_ll_gpio_pin_t *)_handle)->mask) ? \ + (1) : (0)) +#else +uint8_t hal_ll_gpio_read_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Writes pin output state. + * + * Sets single pin logical state. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * @param value Pin logical state. + * 1/true -- sets pin high state -- over 1.8V + * 0/false -- sets pin low state -- less than 1.8V + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_write_pin_output(_handle,_value) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + ((_value > 0) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata |= ((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata &= ~((hal_ll_gpio_pin_t *)_handle)->mask)) : \ + (0)) +#else +void hal_ll_gpio_write_pin_output(hal_ll_gpio_pin_t *pin, uint8_t value); +#endif + +/** + * @brief Toggles pin logical state. + * + * Checks current state of pin + * and toggles it. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_toggle_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + ((((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata & ((hal_ll_gpio_pin_t *)_handle)->mask))) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata &= ~((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata |= ((hal_ll_gpio_pin_t *)_handle)->mask)) : \ + (0)) +#else +void hal_ll_gpio_toggle_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Sets pin logical state. + * + * Sets pin logical state to high. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_set_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata |= ((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (0)) +#else +void hal_ll_gpio_set_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Sets pin logical state. + * + * Sets pin logical state to low. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_clear_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata &= ~((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (0)) +#else +void hal_ll_gpio_clear_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Configures port. + * + * Configures port according to specified + * direction. Takes into consideration only + * pins defined by mask. + * + * @param *port Port object context. + * Configured during this functions process. + * @param name Port name. + * @param mask Port pin mask. + * @param direction Port pin direction. + * HAL_LL_GPIO_DIGITAL_INPUT + * HAL_LL_GPIO_DIGITAL_OUTPUT + * + * @return None + */ +void hal_ll_gpio_configure_port(hal_ll_gpio_port_t *port, hal_ll_port_name_t name, hal_ll_gpio_mask_t mask, hal_ll_gpio_direction_t direction); + +/** + * @brief Read port input value. + * + * Checks port data input register value and + * returns it. + * + * @param *port Port object context. + * Configured during hal_ll_gpio_configure_port. + * + * @return hal_ll_port_size_t Port input data register value. + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_port_input(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ + ((hal_ll_port_size_t)(((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->gpiodata) & (((hal_ll_gpio_port_t *)_handle)->mask)) : \ + (0)) +#else +hal_ll_port_size_t hal_ll_gpio_read_port_input(hal_ll_gpio_port_t *port); +#endif + +/** + * @brief Read port output value. + * + * Checks port data output register value and + * returns it. + * + * @param *port Port object context. + * Configured during hal_ll_gpio_configure_port. + * @return hal_ll_port_size_t Port output data register value. + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_port_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ + ((hal_ll_port_size_t)(((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->gpiodata) & (((hal_ll_gpio_port_t *)_handle)->mask)) : \ + (0)) +#else +hal_ll_port_size_t hal_ll_gpio_read_port_output(hal_ll_gpio_port_t *port); +#endif + +/** + * @brief Set port state. + * + * Sets port output state. + * Will take into consideration only + * port pins defined by mask in + * port object context. + * + * @param *port Port object context. + * Configured during hal_ll_gpio_configure_port. + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_write_port_output(_handle,_value) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->gpiodata = \ + ((hal_ll_gpio_port_t *)_handle)->mask & (hal_ll_port_size_t)_value) : \ + (0)) +#else +void hal_ll_gpio_write_port_output(hal_ll_gpio_port_t *port, hal_ll_port_size_t value); +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_constants.h b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_constants.h new file mode 100644 index 0000000000..0585eb08a4 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_constants.h @@ -0,0 +1,102 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#define GPIO_CFG_MODE_INPUT 0x0UL +#define GPIO_CFG_MODE_OUTPUT 0x1UL + +#define GPIO_DIR_INPUT 0 +#define GPIO_DIR_OUTPUT 1 + +#define GPIO_CFG_PULL_UP 0x1UL +#define GPIO_CFG_PULL_DOWN 0x2UL + +#define GPIO_CFG_OPEN_DRAIN 0x8UL +#define GPIO_CFG_DRIVE_2mA 0x10UL +#define GPIO_CFG_DRIVE_4mA 0x20UL +#define GPIO_CFG_DRIVE_8mA 0x40UL +#define GPIO_CFG_SLEW_RATE 0x80UL +#define GPIO_CFG_DIGITAL_ENABLE 0x100UL +#define GPIO_CFG_ISOLATION_DISABLE 0x200UL +#define GPIO_CFG_ALT_FUNCTION 0x400UL +#define GPIO_CFG_ADC_SRC_TRIGGER 0x800UL +#define GPIO_CFG_DRIVE_6mA 0x1000UL +#define GPIO_CFG_DRIVE_10mA 0x2000UL +#define GPIO_CFG_DRIVE_12mA 0x4000UL + +#define GPIO_CFG_ADV_AIN ( GPIO_CFG_ALT_FUNCTION | GPIO_CFG_ISOLATION_DISABLE ) + +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_DIR_OUTPUT | GPIO_CFG_DIGITAL_ENABLE | GPIO_CFG_DRIVE_8mA ) +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_DIR_INPUT | GPIO_CFG_DIGITAL_ENABLE | GPIO_CFG_DRIVE_8mA ) +#define GPIO_CFG_ANALOG_INPUT ( GPIO_DIR_INPUT | GPIO_CFG_ADV_AIN ) + +#define _HAL_GPIO_DIR_OFFSET ( 0x400UL / 4 ) +#define _HAL_GPIO_GPIOPC_OFFSET ( 0xFC4UL / 4 ) +#define _HAL_GPIO_GPIOODR_OFFSET ( 0x50CUL / 4 ) +#define _HAL_GPIO_GPIOPUR_OFFSET ( 0x510UL / 4 ) +#define _HAL_GPIO_GPIOPDR_OFFSET ( 0x514UL / 4 ) +#define _HAL_GPIO_GPIOSLR_OFFSET ( 0x518UL / 4 ) +#define _HAL_GPIO_GPIODEN_OFFSET ( 0x518UL / 4 ) +#define _HAL_GPIO_GPIODR2R_OFFSET ( 0x500UL / 4 ) +#define _HAL_GPIO_GPIODR4R_OFFSET ( 0x504UL / 4 ) +#define _HAL_GPIO_GPIODR8R_OFFSET ( 0x508UL / 4 ) +#define _HAL_GPIO_GPIODR12R_OFFSET ( 0x53CUL / 4 ) +#define _HAL_GPIO_GPIOAMSEL_OFFSET ( 0x528UL / 4 ) +#define _HAL_GPIO_GPIOAFSEL_OFFSET ( 0x420UL / 4 ) +#define _HAL_GPIO_GPIOADCCTL_OFFSET ( 0x530UL / 4 ) + +#define GPIO_PIN_NAME_MASK ( uint32_t )0xFF +#define GPIO_AF_MASK 0x0F + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h new file mode 100644 index 0000000000..6fb710bf2d --- /dev/null +++ b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h @@ -0,0 +1,194 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio.h + * @brief This file contains all the functions prototypes for the GPIO library. + */ + +#ifndef _HAL_LL_GPIO_PORT_H_ +#define _HAL_LL_GPIO_PORT_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" +#include "hal_ll_gpio_constants.h" + +/** + * Helper macros for GPIO HAL + */ +#define GPIO_MODULE_STRUCT_END (-1) +#define GPIO_AF_OFFSET 8 +#define VALUE(pin, func) (pin | (func << GPIO_AF_OFFSET)) + +/** + * GPIO module struct defining pins and proprietary functions + */ +typedef struct +{ + hal_ll_base_addr_t pins[13]; + uint32_t configs[13]; +} module_struct; + +/** + * GPIO module registers access structure + */ +typedef struct +{ + hal_ll_base_addr_t gpiodata; + hal_ll_base_addr_t gpiodir; + hal_ll_base_addr_t gpiois; + hal_ll_base_addr_t gpioibe; + hal_ll_base_addr_t gpioiev; + hal_ll_base_addr_t gpioim; + hal_ll_base_addr_t gpioris; + hal_ll_base_addr_t gpiomis; + hal_ll_base_addr_t gpioicr; + hal_ll_base_addr_t gpioafsel; + hal_ll_base_addr_t gpio_reserved[55]; + hal_ll_base_addr_t gpiodr2r; + hal_ll_base_addr_t gpiodr4r; + hal_ll_base_addr_t gpiodr8r; + hal_ll_base_addr_t gpioodr; + hal_ll_base_addr_t gpiopur; + hal_ll_base_addr_t gpiopdr; + hal_ll_base_addr_t gpioslr; + hal_ll_base_addr_t gpioden; + hal_ll_base_addr_t gpiolock; + hal_ll_base_addr_t gpiocr; + hal_ll_base_addr_t gpioamsel; + hal_ll_base_addr_t gpiopctl; + hal_ll_base_addr_t gpioadcctl; + hal_ll_base_addr_t gpiodmactl; + hal_ll_base_addr_t gpiosi; + hal_ll_base_addr_t gpiodr12r; + hal_ll_base_addr_t gpiowakepen; + hal_ll_base_addr_t gpiowakestat; + hal_ll_base_addr_t gpiopp; + hal_ll_base_addr_t gpiopc; +} hal_ll_gpio_base_handle_t; + +/** + * Handle and mask types. + */ +typedef handle_t hal_ll_gpio_base_t; + +/** + * Enum used for pin direction selection. + */ +typedef enum +{ + HAL_LL_GPIO_DIGITAL_INPUT = 0, + HAL_LL_GPIO_DIGITAL_OUTPUT = 1 +} hal_ll_gpio_direction_t; + +/** + * Enum used for pin direction selection. + */ +typedef struct hal_ll_gpio_t +{ + hal_ll_gpio_base_t base; + hal_ll_gpio_mask_t mask; +}; + +/** + * Pin and port data types. + */ +typedef struct hal_ll_gpio_t hal_ll_gpio_pin_t; +typedef struct hal_ll_gpio_t hal_ll_gpio_port_t; + +/** + * @brief Get pins port index within a list of available ports + * @param name - desired pin + * @return uint8_t value from 0 to PORT_COUNT-1 + */ +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ); + +/** + * @brief Get pin mask of provided pin within proprietery port + * @param name - desired pin + * @return uint32_t + */ +uint8_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ); + +/** + * @brief Get base address of ports registers + * @param name - desired port + * @return uint32_t address of first regsiter + */ +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ); + +/** + * @brief Set pin as analog input + * @param port - port base address acquired from hal_gpio_ll_port_base + * @param pin_mask - pin mask acquired from hal_gpio_ll_pin_mask + * @return none + */ +void hal_ll_gpio_analog_input( uint32_t *port, uint8_t pin_mask ); + +/** + * @brief Set pin as digital input + * @param port - port base address acquired from hal_gpio_ll_port_base + * @param pin_mask - pin mask acquired from hal_gpio_ll_pin_mask + * @return none + */ +void hal_ll_gpio_digital_input( uint32_t *port, uint8_t pin_mask ); + +/** + * @brief Set pin as digital output + * @param port - port base address acquired from hal_gpio_ll_port_base + * @param pin_mask - pin mask acquired from hal_gpio_ll_pin_mask + * @return none + */ +void hal_ll_gpio_digital_output( uint32_t *port, uint8_t pin_mask ); + +/** + * @brief Initialize structure of pins associated to specific peripheral + * @param module - desired module pins structure + * @return none + */ +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_PORT_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h b/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h new file mode 100644 index 0000000000..297b95511d --- /dev/null +++ b/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h @@ -0,0 +1,800 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_pin_names.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_PIN_NAMES_H_ +#define _HAL_LL_PIN_NAMES_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "mcu_definitions.h" +#include "hal_ll_target_names.h" + +#define GPIO_FEATURE_8BIT_PORT + +#ifdef __PORT_A_CN +#define GPIO_FEATURE_GROUP_1 +#endif +#ifdef __PORT_B_CN +#define GPIO_FEATURE_GROUP_2 +#endif +#ifdef __PORT_C_CN +#define GPIO_FEATURE_GROUP_3 +#endif +#ifdef __PORT_D_CN +#define GPIO_FEATURE_GROUP_4 +#endif +#ifdef __PORT_E_CN +#define GPIO_FEATURE_GROUP_5 +#endif +#ifdef __PORT_F_CN +#define GPIO_FEATURE_GROUP_6 +#endif +#ifdef __PORT_G_CN +#define GPIO_FEATURE_GROUP_7 +#endif +#ifdef __PORT_H_CN +#define GPIO_FEATURE_GROUP_8 +#endif +#ifdef __PORT_J_CN +#define GPIO_FEATURE_GROUP_9 +#endif +#ifdef __PORT_K_CN +#define GPIO_FEATURE_GROUP_10 +#endif +#ifdef __PORT_L_CN +#define GPIO_FEATURE_GROUP_11 +#endif +#ifdef __PORT_M_CN +#define GPIO_FEATURE_GROUP_12 +#endif +#ifdef __PORT_N_CN +#define GPIO_FEATURE_GROUP_13 +#endif +#ifdef __PORT_P_CN +#define GPIO_FEATURE_GROUP_14 +#endif +#ifdef __PORT_Q_CN +#define GPIO_FEATURE_GROUP_15 +#endif +#ifdef __PORT_R_CN +#define GPIO_FEATURE_GROUP_16 +#endif +#ifdef __PORT_S_CN +#define GPIO_FEATURE_GROUP_17 +#endif +#ifdef __PORT_T_CN +#define GPIO_FEATURE_GROUP_18 +#endif + +#ifdef __PA0_CN +#define GPIO_PA0 (0x00) +#define PA0 GPIO_PA0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA0! +#endif +#ifdef __PA1_CN +#define GPIO_PA1 (0x01) +#define PA1 GPIO_PA1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA1! +#endif +#ifdef __PA2_CN +#define GPIO_PA2 (0x02) +#define PA2 GPIO_PA2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA2! +#endif +#ifdef __PA3_CN +#define GPIO_PA3 (0x03) +#define PA3 GPIO_PA3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA3! +#endif +#ifdef __PA4_CN +#define GPIO_PA4 (0x04) +#define PA4 GPIO_PA4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA4! +#endif +#ifdef __PA5_CN +#define GPIO_PA5 (0x05) +#define PA5 GPIO_PA5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA5! +#endif +#ifdef __PA6_CN +#define GPIO_PA6 (0x06) +#define PA6 GPIO_PA6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA6! +#endif +#ifdef __PA7_CN +#define GPIO_PA7 (0x07) +#define PA7 GPIO_PA7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA7! +#endif + +#ifdef __PB0_CN +#define GPIO_PB0 (0x08) +#define PB0 GPIO_PB0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB0! +#endif +#ifdef __PB1_CN +#define GPIO_PB1 (0x09) +#define PB1 GPIO_PB1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB1! +#endif +#ifdef __PB2_CN +#define GPIO_PB2 (0x0A) +#define PB2 GPIO_PB2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB2! +#endif +#ifdef __PB3_CN +#define GPIO_PB3 (0x0B) +#define PB3 GPIO_PB3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB3! +#endif +#ifdef __PB4_CN +#define GPIO_PB4 (0x0C) +#define PB4 GPIO_PB4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB4! +#endif +#ifdef __PB5_CN +#define GPIO_PB5 (0x0D) +#define PB5 GPIO_PB5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB5! +#endif +#ifdef __PB6_CN +#define GPIO_PB6 (0x0E) +#define PB6 GPIO_PB6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB6! +#endif +#ifdef __PB7_CN +#define GPIO_PB7 (0x0F) +#define PB7 GPIO_PB7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB7! +#endif + +#ifdef __PC0_CN +#define GPIO_PC0 (0x10) +#define PC0 GPIO_PC0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC0! +#endif +#ifdef __PC1_CN +#define GPIO_PC1 (0x11) +#define PC1 GPIO_PC1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC1! +#endif +#ifdef __PC2_CN +#define GPIO_PC2 (0x12) +#define PC2 GPIO_PC2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC2! +#endif +#ifdef __PC3_CN +#define GPIO_PC3 (0x13) +#define PC3 GPIO_PC3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC3! +#endif +#ifdef __PC4_CN +#define GPIO_PC4 (0x14) +#define PC4 GPIO_PC4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC4! +#endif +#ifdef __PC5_CN +#define GPIO_PC5 (0x15) +#define PC5 GPIO_PC5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC5! +#endif +#ifdef __PC6_CN +#define GPIO_PC6 (0x16) +#define PC6 GPIO_PC6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC6! +#endif +#ifdef __PC7_CN +#define GPIO_PC7 (0x17) +#define PC7 GPIO_PC7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC7! +#endif + +#ifdef __PD0_CN +#define GPIO_PD0 (0x18) +#define PD0 GPIO_PD0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD0! +#endif +#ifdef __PD1_CN +#define GPIO_PD1 (0x19) +#define PD1 GPIO_PD1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD1! +#endif +#ifdef __PD2_CN +#define GPIO_PD2 (0x1A) +#define PD2 GPIO_PD2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD2! +#endif +#ifdef __PD3_CN +#define GPIO_PD3 (0x1B) +#define PD3 GPIO_PD3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD3! +#endif +#ifdef __PD4_CN +#define GPIO_PD4 (0x1C) +#define PD4 GPIO_PD4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD4! +#endif +#ifdef __PD5_CN +#define GPIO_PD5 (0x1D) +#define PD5 GPIO_PD5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD5! +#endif +#ifdef __PD6_CN +#define GPIO_PD6 (0x1E) +#define PD6 GPIO_PD6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD6! +#endif +#ifdef __PD7_CN +#define GPIO_PD7 (0x1F) +#define PD7 GPIO_PD7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD7! +#endif + +#ifdef __PE0_CN +#define GPIO_PE0 (0x20) +#define PE0 GPIO_PE0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE0! +#endif +#ifdef __PE1_CN +#define GPIO_PE1 (0x21) +#define PE1 GPIO_PE1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE1! +#endif +#ifdef __PE2_CN +#define GPIO_PE2 (0x22) +#define PE2 GPIO_PE2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE2! +#endif +#ifdef __PE3_CN +#define GPIO_PE3 (0x23) +#define PE3 GPIO_PE3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE3! +#endif +#ifdef __PE4_CN +#define GPIO_PE4 (0x24) +#define PE4 GPIO_PE4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE4! +#endif +#ifdef __PE5_CN +#define GPIO_PE5 (0x25) +#define PE5 GPIO_PE5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE5! +#endif +#ifdef __PE6_CN +#define GPIO_PE6 (0x26) +#define PE6 GPIO_PE6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE6! +#endif +#ifdef __PE7_CN +#define GPIO_PE7 (0x27) +#define PE7 GPIO_PE7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE7! +#endif + +#ifdef __PF0_CN +#define GPIO_PF0 (0x28) +#define PF0 GPIO_PF0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF0! +#endif +#ifdef __PF1_CN +#define GPIO_PF1 (0x29) +#define PF1 GPIO_PF1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF1! +#endif +#ifdef __PF2_CN +#define GPIO_PF2 (0x2A) +#define PF2 GPIO_PF2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF2! +#endif +#ifdef __PF3_CN +#define GPIO_PF3 (0x2B) +#define PF3 GPIO_PF3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF3! +#endif +#ifdef __PF4_CN +#define GPIO_PF4 (0x2C) +#define PF4 GPIO_PF4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF4! +#endif +#ifdef __PF5_CN +#define GPIO_PF5 (0x2D) +#define PF5 GPIO_PF5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF5! +#endif +#ifdef __PF6_CN +#define GPIO_PF6 (0x2E) +#define PF6 GPIO_PF6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF6! +#endif +#ifdef __PF7_CN +#define GPIO_PF7 (0x2F) +#define PF7 GPIO_PF7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF7! +#endif + +#ifdef __PG0_CN +#define GPIO_PG0 (0x30) +#define PG0 GPIO_PG0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG0! +#endif +#ifdef __PG1_CN +#define GPIO_PG1 (0x31) +#define PG1 GPIO_PG1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG1! +#endif +#ifdef __PG2_CN +#define GPIO_PG2 (0x32) +#define PG2 GPIO_PG2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG2! +#endif +#ifdef __PG3_CN +#define GPIO_PG3 (0x33) +#define PG3 GPIO_PG3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG3! +#endif +#ifdef __PG4_CN +#define GPIO_PG4 (0x34) +#define PG4 GPIO_PG4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG4! +#endif +#ifdef __PG5_CN +#define GPIO_PG5 (0x35) +#define PG5 GPIO_PG5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG5! +#endif +#ifdef __PG6_CN +#define GPIO_PG6 (0x36) +#define PG6 GPIO_PG6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG6! +#endif +#ifdef __PG7_CN +#define GPIO_PG7 (0x37) +#define PG7 GPIO_PG7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG7! +#endif + +#ifdef __PH0_CN +#define GPIO_PH0 (0x38) +#define PH0 GPIO_PH0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH0! +#endif +#ifdef __PH1_CN +#define GPIO_PH1 (0x39) +#define PH1 GPIO_PH1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH1! +#endif +#ifdef __PH2_CN +#define GPIO_PH2 (0x3A) +#define PH2 GPIO_PH2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH2! +#endif +#ifdef __PH3_CN +#define GPIO_PH3 (0x3B) +#define PH3 GPIO_PH3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH3! +#endif +#ifdef __PH4_CN +#define GPIO_PH4 (0x3C) +#define PH4 GPIO_PH4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH4! +#endif +#ifdef __PH5_CN +#define GPIO_PH5 (0x3D) +#define PH5 GPIO_PH5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH5! +#endif +#ifdef __PH6_CN +#define GPIO_PH6 (0x3E) +#define PH6 GPIO_PH6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH6! +#endif +#ifdef __PH7_CN +#define GPIO_PH7 (0x3F) +#define PH7 GPIO_PH7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH7! +#endif + +#ifdef __PJ0_CN +#define GPIO_PJ0 (0x40) +#define PJ0 GPIO_PJ0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ0! +#endif +#ifdef __PJ1_CN +#define GPIO_PJ1 (0x41) +#define PJ1 GPIO_PJ1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ1! +#endif +#ifdef __PJ2_CN +#define GPIO_PJ2 (0x42) +#define PJ2 GPIO_PJ2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ2! +#endif +#ifdef __PJ3_CN +#define GPIO_PJ3 (0x43) +#define PJ3 GPIO_PJ3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ3! +#endif +#ifdef __PJ4_CN +#define GPIO_PJ4 (0x44) +#define PJ4 GPIO_PJ4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ4! +#endif +#ifdef __PJ5_CN +#define GPIO_PJ5 (0x45) +#define PJ5 GPIO_PJ5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ5! +#endif +#ifdef __PJ6_CN +#define GPIO_PJ6 (0x46) +#define PJ6 GPIO_PJ6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ6! +#endif +#ifdef __PJ7_CN +#define GPIO_PJ7 (0x47) +#define PJ7 GPIO_PJ7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ7! +#endif + +#ifdef __PK0_CN +#define GPIO_PK0 (0x48) +#define PK0 GPIO_PK0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK0! +#endif +#ifdef __PK1_CN +#define GPIO_PK1 (0x49) +#define PK1 GPIO_PK1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK1! +#endif +#ifdef __PK2_CN +#define GPIO_PK2 (0x4A) +#define PK2 GPIO_PK2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK2! +#endif +#ifdef __PK3_CN +#define GPIO_PK3 (0x4B) +#define PK3 GPIO_PK3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK3! +#endif +#ifdef __PK4_CN +#define GPIO_PK4 (0x4C) +#define PK4 GPIO_PK4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK4! +#endif +#ifdef __PK5_CN +#define GPIO_PK5 (0x4D) +#define PK5 GPIO_PK5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK5! +#endif +#ifdef __PK6_CN +#define GPIO_PK6 (0x4E) +#define PK6 GPIO_PK6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK6! +#endif +#ifdef __PK7_CN +#define GPIO_PK7 (0x4F) +#define PK7 GPIO_PK7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK7! +#endif + +#ifdef __PL0_CN +#define GPIO_PL0 (0x50) +#define PL0 GPIO_PL0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL0! +#endif +#ifdef __PL1_CN +#define GPIO_PL1 (0x51) +#define PL1 GPIO_PL1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL1! +#endif +#ifdef __PL2_CN +#define GPIO_PL2 (0x52) +#define PL2 GPIO_PL2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL2! +#endif +#ifdef __PL3_CN +#define GPIO_PL3 (0x53) +#define PL3 GPIO_PL3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL3! +#endif +#ifdef __PL4_CN +#define GPIO_PL4 (0x54) +#define PL4 GPIO_PL4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL4! +#endif +#ifdef __PL5_CN +#define GPIO_PL5 (0x55) +#define PL5 GPIO_PL5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL5! +#endif +#ifdef __PL6_CN +#define GPIO_PL6 (0x56) +#define PL6 GPIO_PL6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL6! +#endif +#ifdef __PL7_CN +#define GPIO_PL7 (0x57) +#define PL7 GPIO_PL7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL7! +#endif + +#ifdef __PM0_CN +#define GPIO_PM0 (0x58) +#define PM0 GPIO_PM0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM0! +#endif +#ifdef __PM1_CN +#define GPIO_PM1 (0x59) +#define PM1 GPIO_PM1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM1! +#endif +#ifdef __PM2_CN +#define GPIO_PM2 (0x5A) +#define PM2 GPIO_PM2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM2! +#endif +#ifdef __PM3_CN +#define GPIO_PM3 (0x5B) +#define PM3 GPIO_PM3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM3! +#endif +#ifdef __PM4_CN +#define GPIO_PM4 (0x5C) +#define PM4 GPIO_PM4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM4! +#endif +#ifdef __PM5_CN +#define GPIO_PM5 (0x5D) +#define PM5 GPIO_PM5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM5! +#endif +#ifdef __PM6_CN +#define GPIO_PM6 (0x5E) +#define PM6 GPIO_PM6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM6! +#endif +#ifdef __PM7_CN +#define GPIO_PM7 (0x5F) +#define PM7 GPIO_PM7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM7! +#endif + +#ifdef __PN0_CN +#define GPIO_PN0 (0x60) +#define PN0 GPIO_PN0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN0! +#endif +#ifdef __PN1_CN +#define GPIO_PN1 (0x61) +#define PN1 GPIO_PN1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN1! +#endif +#ifdef __PN2_CN +#define GPIO_PN2 (0x62) +#define PN2 GPIO_PN2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN2! +#endif +#ifdef __PN3_CN +#define GPIO_PN3 (0x63) +#define PN3 GPIO_PN3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN3! +#endif +#ifdef __PN4_CN +#define GPIO_PN4 (0x64) +#define PN4 GPIO_PN4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN4! +#endif +#ifdef __PN5_CN +#define GPIO_PN5 (0x65) +#define PN5 GPIO_PN5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN5! +#endif +#ifdef __PN6_CN +#define GPIO_PN6 (0x66) +#define PN6 GPIO_PN6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN6! +#endif +#ifdef __PN7_CN +#define GPIO_PN7 (0x67) +#define PN7 GPIO_PN7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN7! +#endif + +#ifdef __PP0_CN +#define GPIO_PP0 (0x68) +#define PP0 GPIO_PP0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP0! +#endif +#ifdef __PP1_CN +#define GPIO_PP1 (0x69) +#define PP1 GPIO_PP1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP1! +#endif +#ifdef __PP2_CN +#define GPIO_PP2 (0x6A) +#define PP2 GPIO_PP2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP2! +#endif +#ifdef __PP3_CN +#define GPIO_PP3 (0x6B) +#define PP3 GPIO_PP3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP3! +#endif +#ifdef __PP4_CN +#define GPIO_PP4 (0x6C) +#define PP4 GPIO_PP4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP4! +#endif +#ifdef __PP5_CN +#define GPIO_PP5 (0x6D) +#define PP5 GPIO_PP5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP5! +#endif +#ifdef __PP6_CN +#define GPIO_PP6 (0x6E) +#define PP6 GPIO_PP6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP6! +#endif +#ifdef __PP7_CN +#define GPIO_PP7 (0x6F) +#define PP7 GPIO_PP7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP7! +#endif + +#ifdef __PQ0_CN +#define GPIO_PQ0 (0x70) +#define PQ0 GPIO_PQ0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ0! +#endif +#ifdef __PQ1_CN +#define GPIO_PQ1 (0x71) +#define PQ1 GPIO_PQ1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ1! +#endif +#ifdef __PQ2_CN +#define GPIO_PQ2 (0x72) +#define PQ2 GPIO_PQ2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ2! +#endif +#ifdef __PQ3_CN +#define GPIO_PQ3 (0x73) +#define PQ3 GPIO_PQ3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ3! +#endif +#ifdef __PQ4_CN +#define GPIO_PQ4 (0x74) +#define PQ4 GPIO_PQ4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ4! +#endif +#ifdef __PQ5_CN +#define GPIO_PQ5 (0x75) +#define PQ5 GPIO_PQ5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ5! +#endif +#ifdef __PQ6_CN +#define GPIO_PQ6 (0x76) +#define PQ6 GPIO_PQ6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ6! +#endif +#ifdef __PQ7_CN +#define GPIO_PQ7 (0x77) +#define PQ7 GPIO_PQ7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ7! +#endif + +#ifdef __PR0_CN +#define GPIO_PR0 (0x78) +#define PR0 GPIO_PR0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR0! +#endif +#ifdef __PR1_CN +#define GPIO_PR1 (0x79) +#define PR1 GPIO_PR1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR1! +#endif +#ifdef __PR2_CN +#define GPIO_PR2 (0x7A) +#define PR2 GPIO_PR2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR2! +#endif +#ifdef __PR3_CN +#define GPIO_PR3 (0x7B) +#define PR3 GPIO_PR3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR3! +#endif +#ifdef __PR4_CN +#define GPIO_PR4 (0x7C) +#define PR4 GPIO_PR4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR4! +#endif +#ifdef __PR5_CN +#define GPIO_PR5 (0x7D) +#define PR5 GPIO_PR5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR5! +#endif +#ifdef __PR6_CN +#define GPIO_PR6 (0x7E) +#define PR6 GPIO_PR6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR6! +#endif +#ifdef __PR7_CN +#define GPIO_PR7 (0x7F) +#define PR7 GPIO_PR7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR7! +#endif + +#ifdef __PS0_CN +#define GPIO_PS0 (0x80) +#define PS0 GPIO_PS0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS0! +#endif +#ifdef __PS1_CN +#define GPIO_PS1 (0x81) +#define PS1 GPIO_PS1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS1! +#endif +#ifdef __PS2_CN +#define GPIO_PS2 (0x82) +#define PS2 GPIO_PS2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS2! +#endif +#ifdef __PS3_CN +#define GPIO_PS3 (0x83) +#define PS3 GPIO_PS3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS3! +#endif +#ifdef __PS4_CN +#define GPIO_PS4 (0x84) +#define PS4 GPIO_PS4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS4! +#endif +#ifdef __PS5_CN +#define GPIO_PS5 (0x85) +#define PS5 GPIO_PS5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS5! +#endif +#ifdef __PS6_CN +#define GPIO_PS6 (0x86) +#define PS6 GPIO_PS6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS6! +#endif +#ifdef __PS7_CN +#define GPIO_PS7 (0x87) +#define PS7 GPIO_PS7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS7! +#endif + +#ifdef __PT0_CN +#define GPIO_PT0 (0x88) +#define PT0 GPIO_PT0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT0! +#endif +#ifdef __PT1_CN +#define GPIO_PT1 (0x89) +#define PT1 GPIO_PT1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT1! +#endif +#ifdef __PT2_CN +#define GPIO_PT2 (0x8A) +#define PT2 GPIO_PT2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT2! +#endif +#ifdef __PT3_CN +#define GPIO_PT3 (0x8B) +#define PT3 GPIO_PT3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT3! +#endif +#ifdef __PT4_CN +#define GPIO_PT4 (0x8C) +#define PT4 GPIO_PT4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT4! +#endif +#ifdef __PT5_CN +#define GPIO_PT5 (0x8D) +#define PT5 GPIO_PT5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT5! +#endif +#ifdef __PT6_CN +#define GPIO_PT6 (0x8E) +#define PT6 GPIO_PT6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT6! +#endif +#ifdef __PT7_CN +#define GPIO_PT7 (0x8F) +#define PT7 GPIO_PT7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT7! +#endif + +#define GPIO_PIN_0 (0x00) +#define PIN_0 GPIO_PIN_0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_0! +#define GPIO_PIN_1 (0x01) +#define PIN_1 GPIO_PIN_1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_1! +#define GPIO_PIN_2 (0x02) +#define PIN_2 GPIO_PIN_2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_2! +#define GPIO_PIN_3 (0x03) +#define PIN_3 GPIO_PIN_3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_3! +#define GPIO_PIN_4 (0x04) +#define PIN_4 GPIO_PIN_4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_4! +#define GPIO_PIN_5 (0x05) +#define PIN_5 GPIO_PIN_5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_5! +#define GPIO_PIN_6 (0x06) +#define PIN_6 GPIO_PIN_6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_6! +#define GPIO_PIN_7 (0x07) +#define PIN_7 GPIO_PIN_7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_7! + +#ifdef __PORT_A_CN +#define GPIO_PORT_A (0x00) +#define PORT_A GPIO_PORT_A // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_A! +#endif +#ifdef __PORT_B_CN +#define GPIO_PORT_B (0x01) +#define PORT_B GPIO_PORT_B // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_B! +#endif +#ifdef __PORT_C_CN +#define GPIO_PORT_C (0x02) +#define PORT_C GPIO_PORT_C // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_C! +#endif +#ifdef __PORT_D_CN +#define GPIO_PORT_D (0x03) +#define PORT_D GPIO_PORT_D // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_D! +#endif +#ifdef __PORT_E_CN +#define GPIO_PORT_E (0x04) +#define PORT_E GPIO_PORT_E // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_E! +#endif +#ifdef __PORT_F_CN +#define GPIO_PORT_F (0x05) +#define PORT_F GPIO_PORT_F // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_F! +#endif +#ifdef __PORT_G_CN +#define GPIO_PORT_G (0x06) +#define PORT_G GPIO_PORT_G // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_G! +#endif +#ifdef __PORT_H_CN +#define GPIO_PORT_H (0x07) +#define PORT_H GPIO_PORT_H // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_H! +#endif +#ifdef __PORT_J_CN +#define GPIO_PORT_J (0x08) +#define PORT_J GPIO_PORT_J // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_J! +#endif +#ifdef __PORT_K_CN +#define GPIO_PORT_K (0x09) +#define PORT_K GPIO_PORT_K // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_K! +#endif +#ifdef __PORT_L_CN +#define GPIO_PORT_L (0x0A) +#define PORT_L GPIO_PORT_L // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_L! +#endif +#ifdef __PORT_M_CN +#define GPIO_PORT_M (0x0B) +#define PORT_M GPIO_PORT_M // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_M! +#endif +#ifdef __PORT_N_CN +#define GPIO_PORT_N (0x0C) +#define PORT_N GPIO_PORT_N // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_N! +#endif +#ifdef __PORT_P_CN +#define GPIO_PORT_P (0x0D) +#define PORT_P GPIO_PORT_P // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_P! +#endif +#ifdef __PORT_Q_CN +#define GPIO_PORT_Q (0x0E) +#define PORT_Q GPIO_PORT_Q // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_Q! +#endif +#ifdef __PORT_R_CN +#define GPIO_PORT_R (0x0F) +#define PORT_R GPIO_PORT_R // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_R! +#endif +#ifdef __PORT_S_CN +#define GPIO_PORT_S (0x10) +#define PORT_S GPIO_PORT_S // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_S! +#endif +#ifdef __PORT_T_CN +#define GPIO_PORT_T (0x11) +#define PORT_T GPIO_PORT_T // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_T! +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_PIN_NAMES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/hal_ll_rcc.h b/targets/arm/mikroe/renesas/include/hal_ll_rcc.h new file mode 100644 index 0000000000..33664d51c0 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/hal_ll_rcc.h @@ -0,0 +1,70 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source. + */ +#define _SYSCTL_RCGCGPIO ( uint32_t * )0x400FE608 +#define _SYSCTL_GPIOHBCTL ( uint32_t * )0x400FE06C +#define _SYSCTL_RCGCSSI ( uint32_t * )0x400FE61C +#define _SYSCTL_RCGCTIMER ( uint32_t * )0x400FE604 +#define _SYSCTL_RCGCUART ( uint32_t * )0x400FE618 +#define _SYSCTL_RCGCI2C ( uint32_t * )0x400FE620 +#define _SYSCTL_RCGCADC ( uint32_t * )0x400FE638 +#define _SYSCTL_RCGCCAN ( uint32_t * )0x400FE634 + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/hal_ll_target.h b/targets/arm/mikroe/renesas/include/hal_ll_target.h new file mode 100644 index 0000000000..40b76d92e2 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/hal_ll_target.h @@ -0,0 +1,67 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_target.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_TARGET_H_ +#define _HAL_LL_TARGET_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" +#include "hal_ll_bit_control.h" +#include "assembly.h" +#include "common_macros.h" +#include "common_types.h" + +#define HAL_LL_MODULE_ERROR (hal_ll_base_addr_t)(0xFFFFFFFF) +#define HAL_LL_CHANNEL_ERROR (hal_ll_base_addr_t)(0xFFFFFF) +#define HAL_LL_PIN_NC (hal_ll_pin_name_t)(0xFFFF) +#define HAL_LL_PORT_NC (hal_ll_port_name_t)(0xFF) + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TARGET_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/hal_ll_target_names.h b/targets/arm/mikroe/renesas/include/hal_ll_target_names.h new file mode 100644 index 0000000000..92a59537b9 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/hal_ll_target_names.h @@ -0,0 +1,72 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_target_names.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_TARGET_NAMES_H_ +#define _HAL_LL_TARGET_NAMES_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include +#include +#include +#include + +typedef uintptr_t handle_t; +typedef uint8_t hal_ll_gpio_mask_t; +typedef uint8_t hal_ll_pin_name_t; +typedef uint8_t hal_ll_port_name_t; +typedef uint8_t hal_ll_port_size_t; +typedef uint32_t hal_ll_base_addr_t; +typedef uint8_t hal_ll_channel_t; + +typedef int32_t hal_ll_err_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TARGET_NAMES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_master.h b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_master.h new file mode 100644 index 0000000000..2bb7db69e6 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_master.h @@ -0,0 +1,241 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.h + * @brief API for I2C master HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_I2C_MASTER_H_ +#define _HAL_LL_I2C_MASTER_H_ + +#include "hal_ll_target.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief I2C master low level pins config structure. + * + * The context structure for storing low level pin configuration + * for both SCL and SDA pins. + * + */ +typedef struct +{ + hal_ll_pin_af_t pin_scl; + hal_ll_pin_af_t pin_sda; +} hal_ll_i2c_pins_t; + +/** + * @brief I2C master low level handle. + * + * The context for storing low level object handler. + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + handle_t *hal_ll_i2c_master_handle; + handle_t *hal_drv_i2c_master_handle; + bool init_ll_state; +} hal_ll_i2c_master_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] scl I2C SCL pin. + * @param[in] sda I2C SDA pin. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ); + +/** + * @brief Sets I2C slave address. + * + * Registers I2C slave address for specified + * object. + * + * @param[in] *handle HAL context object handle. + * @param[in] addr I2C slave address. + * + * @return void None. + */ +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ); + +/** + * @brief Sets I2C module speed. + * + * Sets specified speed for module. + * Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param[in] *handle HAL context object handle. + * @param[in] speed Desired speed value. + * + * @return hal_ll_err_t Module specific error. + * + * Returns value of speed the module was + * initialized to, or module specific error if + * initialization failed. + * When using from low level directly, + * speed can be set to any desired value, + * but take into consideration that not all values + * will work, as this is chip specific. + * Speed value is declared in kbit/s. + */ +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ); + +/** + * @brief Sets I2C timeout value. + * + * Registers I2C timeout value in number of retries. + * Module shall retry any given operation + * `timeout` number of times before aborting operation. + * + * @param[in] *handle HAL context object handle. + * @param[in] timeout I2C timeout value. + * + * @return void None. + */ +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ); + +/** + * @brief Executes low level data read on I2C bus. + * + * Function shall generate a START signal, + * followed by lenReadData number of reads + * on the bus. Ends with a STOP signal. + * + * @param handle I2C handle. + * @param *readDatabuf Data buffer where read data + * shall be placed. + * @param lenReadData Number of bytes to read. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ); + +/** + * @brief Executes low level data write on I2C bus. + * + * Function shall generate a START signal, + * followed by lenWriteData number of writes + * on the bus. Ends with a STOP signal. + * + * @param handle I2C handle. + * @param *WriteDatabuf Data buffer where data to + * be written is located. + * @param lenWriteData Number of bytes to send. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ); + +/** + * @brief Perform a low level write followed by a low level read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation followed by a + * read operation on the bus. + * The operation consists of a start signal followed by lenWriteData number + * of write operations, a restart signal followed by lenReadData number + * of read operations finishing with a stop signal. + * + * @param handle I2C handle. + * @param[in] *writeDatabuf - Pointer to write data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @param[in] *readDatabuf - Pointer to read data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ); + +/** + * @brief Closes I2C master HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_i2c_master_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_MASTER_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h new file mode 100644 index 0000000000..3bccd109c5 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h @@ -0,0 +1,318 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Macro defining `weak` attribute */ +#define __weak __attribute__((weak)) +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +#ifdef I2C_MODULE_0 +static const hal_ll_base_addr_t HAL_LL_I2C0_BASE_ADDR = 0x40020000; +#endif +#ifdef I2C_MODULE_1 +static const hal_ll_base_addr_t HAL_LL_I2C1_BASE_ADDR = 0x40021000; +#endif +#ifdef I2C_MODULE_2 +static const hal_ll_base_addr_t HAL_LL_I2C2_BASE_ADDR = 0x40022000; +#endif +#ifdef I2C_MODULE_3 +static const hal_ll_base_addr_t HAL_LL_I2C3_BASE_ADDR = 0x40023000; +#endif +#ifdef I2C_MODULE_4 +static const hal_ll_base_addr_t HAL_LL_I2C4_BASE_ADDR = 0x400C0000; +#endif +#ifdef I2C_MODULE_5 +static const hal_ll_base_addr_t HAL_LL_I2C5_BASE_ADDR = 0x400C1000; +#endif +#ifdef I2C_MODULE_6 +static const hal_ll_base_addr_t HAL_LL_I2C6_BASE_ADDR = 0x400C2000; +#endif +#ifdef I2C_MODULE_7 +static const hal_ll_base_addr_t HAL_LL_I2C7_BASE_ADDR = 0x400C3000; +#endif +#ifdef I2C_MODULE_8 +static const hal_ll_base_addr_t HAL_LL_I2C8_BASE_ADDR = 0x400B8000; +#endif +#ifdef I2C_MODULE_9 +static const hal_ll_base_addr_t HAL_LL_I2C9_BASE_ADDR = 0x400B9000; +#endif + +/*!< @brief I2C pin structure. */ +typedef struct { + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +/*!< I2C SCL Pins. */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = { + #ifdef I2C0_SCL_PB2_AF3 + {GPIO_PB2, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_0), 3}, + #endif + #ifdef I2C1_SCL_PA6_AF3 + {GPIO_PA6, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 3}, + #endif + #ifdef I2C1_SCL_PG4_AF3 + {GPIO_PG4, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 3}, + #endif + #ifdef I2C2_SCL_PE4_AF3 + {GPIO_PE4, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 3}, + #endif + #ifdef I2C3_SCL_PD0_AF3 + {GPIO_PD0, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 3}, + #endif + #ifdef I2C3_SCL_PG0_AF3 + {GPIO_PG0, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 3}, + #endif + #ifdef I2C4_SCL_PG2_AF3 + {GPIO_PG2, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, + #endif + #ifdef I2C5_SCL_PB6_AF3 + {GPIO_PB6, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 3}, + #endif + #ifdef I2C2_SCL_PF6_AF3 + {GPIO_PF6, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 3}, + #endif + #ifdef I2C5_SCL_PG6_AF3 + {GPIO_PG6, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 3}, + #endif + #ifdef I2C0_SCL_PB2_AF2 + {GPIO_PB2, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_0), 2}, + #endif + #ifdef I2C1_SCL_PG0_AF2 + {GPIO_PG0, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 2}, + #endif + #ifdef I2C2_SCL_PG2_AF2 + {GPIO_PG2, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, + #endif + #ifdef I2C2_SCL_PL1_AF2 + {GPIO_PL1, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, + #endif + #ifdef I2C2_SCL_PN5_AF3 + {GPIO_PN5, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 3}, + #endif + #ifdef I2C2_SCL_PP5_AF2 + {GPIO_PP5, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, + #endif + #ifdef I2C3_SCL_PG4_AF2 + {GPIO_PG4, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, + #endif + #ifdef I2C3_SCL_PK4_AF2 + {GPIO_PK4, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, + #endif + #ifdef I2C4_SCL_PG6_AF2 + {GPIO_PG6, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 2}, + #endif + #ifdef I2C4_SCL_PK6_AF2 + {GPIO_PK6, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 2}, + #endif + #ifdef I2C5_SCL_PB0_AF2 + {GPIO_PB0, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 2}, + #endif + #ifdef I2C5_SCL_PB4_AF2 + {GPIO_PB4, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 2}, + #endif + #ifdef I2C6_SCL_PA6_AF2 + {GPIO_PA6, HAL_LL_I2C6_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_6), 2}, + #endif + #ifdef I2C7_SCL_PA4_AF2 + {GPIO_PA4, HAL_LL_I2C7_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_7), 2}, + #endif + #ifdef I2C7_SCL_PD0_AF2 + {GPIO_PD0, HAL_LL_I2C7_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_7), 2}, + #endif + #ifdef I2C8_SCL_PA2_AF2 + {GPIO_PA2, HAL_LL_I2C8_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_8), 2}, + #endif + #ifdef I2C8_SCL_PD2_AF2 + {GPIO_PD2, HAL_LL_I2C8_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_8), 2}, + #endif + #ifdef I2C9_SCL_PA0_AF2 + {GPIO_PA0, HAL_LL_I2C9_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_9), 2}, + #endif + #ifdef I2C1_SCL_PR0_AF2 + {GPIO_PR0, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 2}, + #endif + #ifdef I2C2_SCL_PR2_AF2 + {GPIO_PR2, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, + #endif + #ifdef I2C3_SCL_PR4_AF2 + {GPIO_PR4, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, + #endif + #ifdef I2C4_SCL_PR6_AF2 + {GPIO_PR6, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 2}, + #endif + #ifdef I2C6_SCL_PB6_AF2 + {GPIO_PB6, HAL_LL_I2C6_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_6), 2}, + #endif + #ifdef I2C9_SCL_PE6_AF2 + {GPIO_PE6, HAL_LL_I2C9_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_9), 2}, + #endif + + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< I2C SDA Pins. */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = { + #ifdef I2C0_SDA_PB3_AF3 + {GPIO_PB3, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_0), 3}, + #endif + #ifdef I2C1_SDA_PA7_AF3 + {GPIO_PA7, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 3}, + #endif + #ifdef I2C1_SDA_PG5_AF3 + {GPIO_PG5, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 3}, + #endif + #ifdef I2C2_SDA_PE5_AF3 + {GPIO_PE5, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 3}, + #endif + #ifdef I2C3_SDA_PD1_AF3 + {GPIO_PD1, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 3}, + #endif + #ifdef I2C3_SDA_PG1_AF3 + {GPIO_PG1, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 3}, + #endif + #ifdef I2C4_SDA_PG3_AF3 + {GPIO_PG3, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, + #endif + #ifdef I2C5_SDA_PB7_AF3 + {GPIO_PB7, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 3}, + #endif + #ifdef I2C2_SDA_PF7_AF3 + {GPIO_PF7, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 3}, + #endif + #ifdef I2C5_SDA_PG7_AF3 + {GPIO_PG7, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 3}, + #endif + #ifdef I2C0_SDA_PB3_AF2 + {GPIO_PB3, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_0), 2}, + #endif + #ifdef I2C1_SDA_PG1_AF2 + {GPIO_PG1, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 2}, + #endif + #ifdef I2C2_SDA_PG3_AF2 + {GPIO_PG3, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, + #endif + #ifdef I2C2_SDA_PL0_AF2 + {GPIO_PL0, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, + #endif + #ifdef I2C2_SDA_PN4_AF3 + {GPIO_PN4, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 3}, + #endif + #ifdef I2C3_SDA_PG5_AF2 + {GPIO_PG5, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, + #endif + #ifdef I2C3_SDA_PK5_AF2 + {GPIO_PK5, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, + #endif + #ifdef I2C4_SDA_PG7_AF2 + {GPIO_PG7, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 2}, + #endif + #ifdef I2C4_SDA_PK7_AF2 + {GPIO_PK7, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 2}, + #endif + #ifdef I2C5_SDA_PB1_AF2 + {GPIO_PB1, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 2}, + #endif + #ifdef I2C5_SDA_PB5_AF2 + {GPIO_PB5, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 2}, + #endif + #ifdef I2C6_SDA_PA7_AF2 + {GPIO_PA7, HAL_LL_I2C6_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_6), 2}, + #endif + #ifdef I2C7_SDA_PA5_AF2 + {GPIO_PA5, HAL_LL_I2C7_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_7), 2}, + #endif + #ifdef I2C7_SDA_PD1_AF2 + {GPIO_PD1, HAL_LL_I2C7_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_7), 2}, + #endif + #ifdef I2C8_SDA_PA3_AF2 + {GPIO_PA3, HAL_LL_I2C8_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_8), 2}, + #endif + #ifdef I2C8_SDA_PD3_AF2 + {GPIO_PD3, HAL_LL_I2C8_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_8), 2}, + #endif + #ifdef I2C9_SDA_PA1_AF2 + {GPIO_PA1, HAL_LL_I2C9_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_9), 2}, + #endif + #ifdef I2C1_SDA_PR1_AF2 + {GPIO_PR1, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 2}, + #endif + #ifdef I2C2_SDA_PP6_AF2 + {GPIO_PP6, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, + #endif + #ifdef I2C2_SDA_PR3_AF2 + {GPIO_PR3, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, + #endif + #ifdef I2C3_SDA_PR5_AF2 + {GPIO_PR5, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, + #endif + #ifdef I2C4_SDA_PR7_AF2 + {GPIO_PR7, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 2}, + #endif + #ifdef I2C6_SDA_PB7_AF2 + {GPIO_PB7, HAL_LL_I2C6_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_6), 2}, + #endif + #ifdef I2C9_SDA_PE7_AF2 + {GPIO_PE7, HAL_LL_I2C9_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_9), 2}, + #endif + + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/one_wire/hal_ll_one_wire.h b/targets/arm/mikroe/renesas/include/one_wire/hal_ll_one_wire.h new file mode 100644 index 0000000000..b68688316c --- /dev/null +++ b/targets/arm/mikroe/renesas/include/one_wire/hal_ll_one_wire.h @@ -0,0 +1,229 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_one_wire.h + * @brief API for One Wire HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_ONE_WIRE_H_ +#define _HAL_LL_ONE_WIRE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_gpio.h" + +/** + * @brief Structure for storing One Wire device address. + * @details Unique One Wire address used for device addressing. + */ +typedef struct { + uint8_t address[8]; /*!< One Wire address buffer. */ +} hal_ll_one_wire_rom_address_t; + +/** + * @brief One Wire HAL Low Level context structure. + * @details The context structure for storing driver internal state. The contents of the + * context structure are used by the module and must not be altered. Reading or + * writing data directly from a control structure by user should be avoided. + */ +typedef struct { + hal_ll_pin_name_t data_pin; // One Wire data pin. + volatile uint32_t direction; // Register for altering GPIO pin direction. + volatile uint32_t input_output; // Register for GPIO port bit set/reset and for reading current GPIO pin state. +} hal_ll_one_wire_local_t; + +/** + * @brief One Wire HAL Low Level initialization configuration structure. + * + * @details + * - data_pin value - to be configured as desired. + * - state value - NOTE must not be altered (it is supposed to be set automatically in Low Level Layer). + */ +typedef struct { + hal_ll_pin_name_t data_pin; /*!< One Wire pin - user is to configure it as desired. */ + bool state; /*!< State of a pin. NOTE must not be altered. */ +} hal_ll_one_wire_t; + +/** + * @details Enum containing predefined module return values. + */ +typedef enum { + HAL_LL_ONE_WIRE_SUCCESS = 0, /*!< Success. */ + HAL_LL_ONE_WIRE_ERROR = (-1) /*!< Error. */ +} hal_ll_one_wire_err_t; + +/** + * @brief Opens One Wire HAL Low Level object. + * @details Opens One Wire HAL Low Level object on selected pin. + * Enables appropriate PORT clock, configures pin to have digital output functionality, + * makes sure that HIGH voltage state is applied on pin before any One Wire actions. + * @param[in,out] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @return None. + * @pre Make sure that \p LowLevel structure has been adequately + * populated beforehand. + * @note It is recommended to check return value for error. + */ +void hal_ll_one_wire_open( hal_ll_one_wire_t *obj ); + +/** + * @brief Reset One Wire bus. + * @details Host shall send reset sequence and devices shall go into reset state. + * @param[in,out] *handle One Wire HAL Low Level object. + * See #hal_one_wire_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_reset( hal_ll_one_wire_t *obj ); + +/** + * @brief Reads device's ROM information. + * @details Allows the host to read eight-bit family code, + * 48-bit serial number, and eight-bit CRC. + * + * @important THIS FUNCTION IS TO BE ISSUED ONLY IF WE ARE DEALING WITH + * ONE DEVICE ONLY. THIS FUNCTION AUTOMATICALLY RESETS ONE WIRE BUS. + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_one_wire_t structure definition for detailed explanation. + * @param[out] *device_rom_address Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + */ +hal_ll_err_t hal_ll_one_wire_read_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ); + +/** + * @brief Access device's level functions without transmitting ROM information. + * @details Allows the host to access device functions without + * providing the 64-bit ROM identification number. + * + * @important THIS FUNCTION IS TO BE ISSUED ONLY IF WE ARE DEALING WITH + * ONE DEVICE ONLY. THIS FUNCTION AUTOMATICALLY RESETS ONE WIRE BUS. + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_one_wire_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + */ +hal_ll_err_t hal_ll_one_wire_skip_rom( hal_ll_one_wire_t *obj ); + +/** + * @brief Selects a specific One Wire capable device on bus. + * @details Select a One Wire device with specific ID. + * + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @param[in] device_rom_address Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_match_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ); + +/** + * @brief Search One Wire capable device on bus. + * @details Search and list 1st device that is One Wire capable. + * + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @param[out] *one_wire_device_list Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_search_first_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ); + +/** + * @brief Search One Wire capable devices on bus. + * @details Search devices that is One Wire capable. + * + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @param[out] *one_wire_device_list Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_search_next_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ); + +/** + * @brief Writes byte to One Wire bus. + * @details Writes byte to One Wire bus. + * @param[in] *write_data_buffer Data transmit buffer. + * @param[in] write_data_length Number of bytes to write from data transmit buffer. + * @return None. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +void hal_ll_one_wire_write_byte( uint8_t *write_data_buffer, size_t write_data_length ); + +/** + * @brief Reads byte from One Wire bus. + * @details Reads byte from One Wire bus. + * @param[out] *read_data_buffer Data receive buffer. + * @param[in] read_data_length Number of bytes to be read. + * @return None. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +void hal_ll_one_wire_read_byte( uint8_t *read_data_buffer, size_t read_data_length ); + +/** + * @brief Reconfigures One Wire pin settings. + * @details Enables appropriate PORT clock, configures pin to have digital output functionality, + * makes sure that HIGH voltage state is applied on pin before any One Wire actions. + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @return None. + * @pre Before calling this function, + * the user is expected to call #hal_one_wire_open function. + */ +void hal_ll_one_wire_reconfigure( hal_ll_one_wire_t *obj ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ONE_WIRE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/rtc/hal_ll_rtc.h b/targets/arm/mikroe/renesas/include/rtc/hal_ll_rtc.h new file mode 100644 index 0000000000..95ca553b1d --- /dev/null +++ b/targets/arm/mikroe/renesas/include/rtc/hal_ll_rtc.h @@ -0,0 +1,152 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rtc.h + * @brief API for RTC HAL LOW level layer. + */ + +#ifndef _HAL_LL_RTC_H +#define _HAL_LL_RTC_H + +#ifdef __cplusplus +extern "C"{ +#endif + +#ifdef __GNUC__ +#include "mcu.h" +#endif + +#include "hal_target.h" +#include "hal_ll_bit_control.h" + +/** + * @brief Structure representing the RTC time. + * @details This structure is used to hold the real-time clock information, including + * hour, minute, second and it follows a 24-hour format. + * @note Take into consideration that any value can be changed explicitly by the user. + */ +typedef struct +{ + uint8_t hour; // 2-digit format - supports values from 00 to 23 + uint8_t minute; // 2-digit format - supports values from 00 to 59 + uint8_t second; // 2-digit format - supports values from 00 to 59 +} hal_ll_rtc_time_t; + +/** + * @brief Initialize the RTC module. + * @details Initialize the RTC module. + * @param None. + */ +void hal_ll_rtc_init(); + +/** + * @brief Start the RTC module. + * @details Continue the RTC module count from the stored value in the count register. + * @param None. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + * @note It is recommended to check return value for error. + * @pre Before calling this function, the user is expected + * to have initialized RTC by using hal_ll_rtc_init() and have the RTC not counting. + */ +err_t hal_ll_rtc_start(); + +/** + * @brief Stop the RTC module. + * @details Stop the RTC module count. + * @param None. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + * @note It is recommended to check return value for error. + * @pre Before calling this function, the user is expected + * to have the RTC started. + */ +err_t hal_ll_rtc_stop(); + +/** + * @brief Reset the RTC module. + * @details Reset the RTC counter to the default values of 0h:0m:0s. + * @param None. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + * @note It is recommended to check return value for error. + * @pre Before calling this function, the user is expected + * to have the RTC started. + */ +err_t hal_ll_rtc_reset(); + +/** + * @brief Configure time of RTC module. + * @details Configure time registers with the values from hal_ll_rtc_time_t structure. + * @param time hal_ll_rtc_time_t structure. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + * @note It is recommended to check return value for error. + * @pre Before calling this function, the user is expected + * to have the RTC enabled. + */ +err_t hal_ll_rtc_set_time( hal_ll_rtc_time_t *time ); + +/** + * @brief Get time from RTC module. + * @details Configure hal_ll_rtc_time_t structure with the values from time registers. + * @param time hal_ll_rtc_time_t structure. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + * @note It is recommended to check return value for error. + * @pre Before calling this function, the user is expected + * to have the RTC enabled. + */ +err_t hal_ll_rtc_get_time( hal_ll_rtc_time_t *time ); + +/** + * @brief Preforms system reset. + * @details Resets the core and all on-chip peripherals except the Debug + * interface. + * @param None. + * @warning System reset affects core and periferals, + * depending on the architecture you will need to reconfigure opened modules. + */ +void hal_ll_rtc_system_reset(); + +#ifdef __cplusplus +} +#endif + +#endif // HAL_LL_RTC_H diff --git a/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h new file mode 100644 index 0000000000..24e926b0fc --- /dev/null +++ b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h @@ -0,0 +1,228 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.h + * @brief API for SPI master HAL LOW LEVEL layer. + */ + +#ifndef HAL_LL_SPI_MASTER_H +#define HAL_LL_SPI_MASTER_H + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" +#include "hal_ll_gpio.h" + +/** + * @brief SPI configuration pins structure. + */ +typedef struct { + hal_ll_pin_af_t sck; + hal_ll_pin_af_t miso; + hal_ll_pin_af_t mosi; +} hal_ll_spi_master_pins_t; + +/** + * @brief SPI master HAL low lever configuration structure. + */ +typedef struct { + uint8_t default_write_data; + hal_ll_pin_name_t sck; + hal_ll_pin_name_t miso; + hal_ll_pin_name_t mosi; + uint32_t speed; +} hal_ll_spi_master_config_t; + +/** + * @brief Enum containing predefined module mode values. + * + * Enum values: + * + * HAL_LL_SPI_MASTER_MODE_0 -- CPO = 0, CPH = 0 + * HAL_LL_SPI_MASTER_MODE_1 -- CPO = 0, CPH = 1 + * HAL_LL_SPI_MASTER_MODE_2 -- CPO = 1, CPH = 0 + * HAL_LL_SPI_MASTER_MODE_3 -- CPO = 1, CPH = 1 + */ +typedef enum { + HAL_LL_SPI_MASTER_MODE_0 = 0, + HAL_LL_SPI_MASTER_MODE_1, + HAL_LL_SPI_MASTER_MODE_2, + HAL_LL_SPI_MASTER_MODE_3, + + HAL_LL_SPI_MASTER_MODE_DEFAULT = HAL_LL_SPI_MASTER_MODE_0 +} hal_ll_spi_master_mode_t; + +/** + * @brief SPI master HAL low lever handle register. + */ +typedef struct { + handle_t *hal_ll_spi_master_handle; + handle_t *hal_drv_spi_master_handle; + bool init_ll_state; +} hal_ll_spi_master_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] *handle HAL context object handle. + * @param[in] sck SPI sck pin. + * @param[in] miso SPI miso pin. + * @param[in] mosi SPI mosi pin. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_register_handle( hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, + hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_spi( handle_t *handle ); + +/** + * @brief Sets SPI Master configuration dummy data. + * @param config[IN] SPI Master module configuration. + * @param config[IN] user-defined dummy data. + */ +void hal_ll_spi_master_set_default_write_data( handle_t *handle, uint8_t dummy_data ); + +/** + * @brief Sets SPI Master configuration dummy data. + * @param config[IN] SPI Master module configuration. + * @param config[IN] user-defined SPI Master baud rate value. + */ +uint32_t hal_ll_spi_master_set_speed( handle_t *handle, uint32_t speed ); + +/** + * @brief Sets SPI Master configuration dummy data. + * @param[in] *handle HAL context object handle. + * @param[in] mode SPI Master de-facto mode selection. + */ +hal_ll_err_t hal_ll_spi_master_set_mode( handle_t *handle, hal_ll_spi_master_mode_t mode ); + +/** + * @brief Executes low level data write on SPI bus. + * + * Function shall generate a START signal, + * followed by write_data_buffer number of writes + * on the bus. + * + * @param *handle HAL context object handle. + * @param *write_data_buffer Data buffer where data to be written is located. + * @param length_data Number of bytes to send. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write( handle_t *handle, uint8_t *write_data_buffer, size_t length_data); + +/** + * @brief Executes low level data read on SPI bus. + * + * @param handle I2C handle. + * @param *read_data_buffer Data buffer where read data shall be placed. + * @param length_data Number of bytes to read. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_read( handle_t *handle, uint8_t *read_data_buffer, size_t length_data); + +/** + * @brief Perform a low level write followed by a low level read on the SPI bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation followed by a + * read operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to write data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to read data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data ); + +/** + * @brief Closes SPI Master HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_spi_master_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // HAL_LL_SPI_MASTER_H +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h new file mode 100644 index 0000000000..feaa27b803 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h @@ -0,0 +1,232 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Macro defining `weak` attribute */ +#define __weak __attribute__((weak)) +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) + +/*!< SPI module base addresses. */ +#ifdef SPI_MODULE_0 +static const hal_ll_base_addr_t HAL_LL_SPI0_MASTER_BASE_ADDR = 0X40008000; +#endif +#ifdef SPI_MODULE_1 +static const hal_ll_base_addr_t HAL_LL_SPI1_MASTER_BASE_ADDR = 0X40009000; +#endif +#ifdef SPI_MODULE_2 +static const hal_ll_base_addr_t HAL_LL_SPI2_MASTER_BASE_ADDR = 0X4000A000; +#endif +#ifdef SPI_MODULE_3 +static const hal_ll_base_addr_t HAL_LL_SPI3_MASTER_BASE_ADDR = 0X4000B000; +#endif + +/*!< @brief SPI pin structure. */ +typedef struct { + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint8_t af; +} hal_ll_spi_master_pin_map_t; + +/*!< SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = { + #ifdef SPI0_SCK_PA2_AF2 + {GPIO_PA2, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 2}, + #endif + #ifdef SPI1_SCK_PD0_AF2 + {GPIO_PD0, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + #endif + #ifdef SPI1_SCK_PF2_AF2 + {GPIO_PF2, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + #endif + #ifdef SPI2_SCK_PB4_AF2 + {GPIO_PB4, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 2}, + #endif + #ifdef SPI3_SCK_PD0_AF1 + {GPIO_PD0, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 1}, + #endif + #ifdef SPI2_SCK_PH4_AF2 + {GPIO_PH4, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 2}, + #endif + #ifdef SPI3_SCK_PH0_AF2 + {GPIO_PH0, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 2}, + #endif + #ifdef SPI3_SCK_PK0_AF2 + {GPIO_PK0, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 2}, + #endif + #ifdef SPI0_SCK_PA2_AF15 + {GPIO_PA2, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 15}, + #endif + #ifdef SPI1_SCK_PB5_AF15 + {GPIO_PB5, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 15}, + #endif + #ifdef SPI2_SCK_PD3_AF15 + {GPIO_PD3, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 15}, + #endif + #ifdef SPI2_SCK_PG7_AF15 + {GPIO_PG7, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 15}, + #endif + #ifdef SPI3_SCK_PF2_AF14 + {GPIO_PF2, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 14}, + #endif + #ifdef SPI3_SCK_PF3_AF14 + {GPIO_PF3, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 14}, + #endif + #ifdef SPI3_SCK_PQ0_AF14 + {GPIO_PQ0, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 14}, + #endif + + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = { + #ifdef SPI0_MISO_PA4_AF2 + {GPIO_PA4, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 2}, + #endif + #ifdef SPI1_MISO_PD2_AF2 + {GPIO_PD2, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + #endif + #ifdef SPI1_MISO_PF0_AF2 + {GPIO_PF0, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + #endif + #ifdef SPI2_MISO_PB6_AF2 + {GPIO_PB6, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 2}, + #endif + #ifdef SPI3_MISO_PD2_AF1 + {GPIO_PD2, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 1}, + #endif + #ifdef SPI2_MISO_PH6_AF2 + {GPIO_PH6, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 2}, + #endif + #ifdef SPI3_MISO_PH2_AF2 + {GPIO_PH2, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 2}, + #endif + #ifdef SPI3_MISO_PK2_AF2 + {GPIO_PK2, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 2}, + #endif + #ifdef SPI0_MISO_PA5_AF15 + {GPIO_PA5, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 15}, + #endif + #ifdef SPI1_MISO_PE5_AF15 + {GPIO_PE5, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 15}, + #endif + #ifdef SPI2_MISO_PD0_AF15 + {GPIO_PD0, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 15}, + #endif + #ifdef SPI2_MISO_PG4_AF15 + {GPIO_PG4, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 15}, + #endif + #ifdef SPI3_MISO_PF0_AF14 + {GPIO_PF0, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 14}, + #endif + #ifdef SPI3_MISO_PQ3_AF14 + {GPIO_PQ3, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 14}, + #endif + + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = { + #ifdef SPI0_MOSI_PA5_AF2 + {GPIO_PA5, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 2}, + #endif + #ifdef SPI1_MOSI_PD3_AF2 + {GPIO_PD3, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + #endif + #ifdef SPI1_MOSI_PF1_AF2 + {GPIO_PF1, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + #endif + #ifdef SPI2_MOSI_PB7_AF2 + {GPIO_PB7, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 2}, + #endif + #ifdef SPI3_MOSI_PD3_AF1 + {GPIO_PD3, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 1}, + #endif + #ifdef SPI2_MOSI_PH7_AF2 + {GPIO_PH7, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 2}, + #endif + #ifdef SPI3_MOSI_PH3_AF2 + {GPIO_PH3, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 2}, + #endif + #ifdef SPI3_MOSI_PK3_AF2 + {GPIO_PK3, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 2}, + #endif + #ifdef SPI0_MOSI_PA4_AF15 + {GPIO_PA4, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 15}, + #endif + #ifdef SPI1_MOSI_PE4_AF15 + {GPIO_PE4, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 15}, + #endif + #ifdef SPI2_MOSI_PD1_AF15 + {GPIO_PD1, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 15}, + #endif + #ifdef SPI2_MOSI_PG5_AF15 + {GPIO_PG5, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 15}, + #endif + #ifdef SPI3_MOSI_PF1_AF14 + {GPIO_PF1, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 14}, + #endif + #ifdef SPI3_MOSI_PQ2_AF14 + {GPIO_PQ2, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 14}, + #endif + + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim.h b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim.h new file mode 100644 index 0000000000..aa8917ad30 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim.h @@ -0,0 +1,211 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.h + * @brief Brief file description. + */ + +#ifndef _HAL_LL_TIM_H_ +#define _HAL_LL_TIM_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" + +/** + * TIM modules + */ +typedef enum { + HAL_LL_TIM_MODULE_DEFAULT = 0xFF, + #if defined(TIM_MODULE_0) + HAL_LL_TIM_MODULE_0 = 0, + #endif + #if defined(TIM_MODULE_1) + HAL_LL_TIM_MODULE_1 = 1, + #endif + #if defined(TIM_MODULE_2) + HAL_LL_TIM_MODULE_2 = 2, + #endif + #if defined(TIM_MODULE_3) + HAL_LL_TIM_MODULE_3 = 3, + #endif + #if defined(TIM_MODULE_4) + HAL_LL_TIM_MODULE_4 = 4, + #endif + #if defined(TIM_MODULE_5) + HAL_LL_TIM_MODULE_5 = 5, + #endif + #if defined(TIM_MODULE_6) + HAL_LL_TIM_MODULE_6 = 6, + #endif + #if defined(TIM_MODULE_7) + HAL_LL_TIM_MODULE_7 = 7, + #endif + HAL_LL_TIM_MODULE_NONE +} hal_ll_tim_module_number_t; + +/** + * @brief TIMER HAL low lever handle register. + */ +typedef struct { + handle_t *hal_ll_tim_handle; + handle_t *hal_drv_tim_handle; + bool init_ll_state; +} hal_ll_tim_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] pin TIM pin. + * @param[out] handle_map HAL layer local handle map. + * @param[out] hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, + hal_ll_tim_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ); + +/** + * @brief Enables counter for TIM module. + * + * Initializes TIM module on hardware level, if not already initialized and + * starts TIM module. + * + * @param[in] handle TIM handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_start( handle_t *handle ); + +/** + * @brief Stops counter for TIM module. + * + * The TIM Module needs to be initialized so that + * the stop can be done. + * + * @param[in] handle TIM handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ); + +/** + * @brief Set TIM frequency in Hertz. + * + * This function is used to set the TIM frequency, it + * stops TIM module and sets duty_cycle on 0. + * Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param[in] handle TIM handle. + * @param[in] freq_hz TIM frequency in hz. + * + * @return This function returns the frequency value in hz, + * to which the PWM module is set. + * + * @note If the frequency value is less than allowed, + * the frequency will be set to the lowest possible value for the specified TIM. + */ +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ); + +/** + * @brief Set TIM duty cycle in percentages. + * + * The user should enter the duty_ratio in percentages. + * The dut_ratio value should be between 0 and 1 + * (where 0 represents 0% and 1 represents 100%). + * + * @param[in] handle TIM handle. + * @param[in] duty_ratio TIM duty ratio in percentages. + * + * @return hal_ll_err_t Module specific error. + * + * @note Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ); + +/** + * @brief Closes TIM master HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] handle TIM handle. + * + * @return void None. + */ +void hal_ll_tim_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h new file mode 100644 index 0000000000..564031e1be --- /dev/null +++ b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h @@ -0,0 +1,423 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Macro defining `weak` attribute */ +#define __weak __attribute__((weak)) +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief TIMER module base addresses. */ +#ifdef TIM_MODULE_0 +static const hal_ll_base_addr_t HAL_LL_TIM0_BASE_ADDR = 0x40030000; +#endif +#ifdef TIM_MODULE_1 +static const hal_ll_base_addr_t HAL_LL_TIM1_BASE_ADDR = 0x40031000; +#endif +#ifdef TIM_MODULE_2 +static const hal_ll_base_addr_t HAL_LL_TIM2_BASE_ADDR = 0x40032000; +#endif +#ifdef TIM_MODULE_3 +static const hal_ll_base_addr_t HAL_LL_TIM3_BASE_ADDR = 0x40033000; +#endif +#ifdef TIM_MODULE_4 +static const hal_ll_base_addr_t HAL_LL_TIM4_BASE_ADDR = 0x40034000; +#endif +#ifdef TIM_MODULE_5 +static const hal_ll_base_addr_t HAL_LL_TIM5_BASE_ADDR = 0x40035000; +#endif +#ifdef TIM_MODULE_6 +#ifdef TM4C129 +static const hal_ll_base_addr_t HAL_LL_TIM6_BASE_ADDR = 0x400E0000; +#else +static const hal_ll_base_addr_t HAL_LL_TIM6_BASE_ADDR = 0x4003E000; +#endif +#endif +#ifdef TIM_MODULE_7 +#ifdef TM4C129 +static const hal_ll_base_addr_t HAL_LL_TIM7_BASE_ADDR = 0x400E1000; +#else +static const hal_ll_base_addr_t HAL_LL_TIM7_BASE_ADDR = 0x4003E100; +#endif +#endif + +/*!< @brief TIM pin structure. */ +typedef struct { + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +/*!< TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef TIM0_CCP0_PB6_AF7 + {GPIO_PB6, HAL_LL_TIM0_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM0_CCP0_PF0_AF7 + {GPIO_PF0, HAL_LL_TIM0_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM0_CCP1_PB7_AF7 + {GPIO_PB7, HAL_LL_TIM0_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM0_CCP1_PF1_AF7 + {GPIO_PF1, HAL_LL_TIM0_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM1_CCP0_PB4_AF7 + {GPIO_PB4, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CCP0_PF2_AF7 + {GPIO_PF2, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CCP1_PB5_AF7 + {GPIO_PB5, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CCP1_PF3_AF7 + {GPIO_PF3, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CCP0_PB0_AF7 + {GPIO_PB0, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CCP0_PF4_AF7 + {GPIO_PF4, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CCP1_PB1_AF7 + {GPIO_PB1, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CCP0_PB2_AF7 + {GPIO_PB2, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CCP1_PB3_AF7 + {GPIO_PB3, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CCP0_PC0_AF7 + {GPIO_PC0, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CCP0_PG0_AF7 + {GPIO_PG0, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CCP1_PC1_AF7 + {GPIO_PC1, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CCP1_PG1_AF7 + {GPIO_PG1, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM5_CCP0_PC2_AF7 + {GPIO_PC2, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CCP0_PG2_AF7 + {GPIO_PG2, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CCP1_PC3_AF7 + {GPIO_PC3, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CCP1_PG3_AF7 + {GPIO_PG3, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM1_CCP0_PJ0_AF7 + {GPIO_PJ0, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CCP1_PJ1_AF7 + {GPIO_PJ1, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CCP0_PJ2_AF7 + {GPIO_PJ2, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CCP1_PF5_AF7 + {GPIO_PF5, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CCP0_PF6_AF7 + {GPIO_PF6, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CCP1_PF7_AF7 + {GPIO_PF7, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM0_CCP0_PL0_AF7 + {GPIO_PL0, HAL_LL_TIM0_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM0_CCP1_PL1_AF7 + {GPIO_PL1, HAL_LL_TIM0_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM1_CCP0_PL2_AF7 + {GPIO_PL2, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CCP1_PL3_AF7 + {GPIO_PL3, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CCP0_PL4_AF7 + {GPIO_PL4, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CCP1_PJ3_AF7 + {GPIO_PJ3, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CCP1_PL5_AF7 + {GPIO_PL5, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CCP0_PJ4_AF7 + {GPIO_PJ4, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CCP0_PL6_AF7 + {GPIO_PL6, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CCP1_PJ5_AF7 + {GPIO_PJ5, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CCP1_PL7_AF7 + {GPIO_PL7, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CCP0_PM0_AF7 + {GPIO_PM0, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CCP0_PP0_AF7 + {GPIO_PP0, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CCP1_PM1_AF7 + {GPIO_PM1, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CCP1_PP1_AF7 + {GPIO_PP1, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM5_CCP0_PM2_AF7 + {GPIO_PM2, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CCP0_PP2_AF7 + {GPIO_PP2, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CCP1_PM3_AF7 + {GPIO_PM3, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CCP1_PP3_AF7 + {GPIO_PP3, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM0_CCP0_PA0_AF3 + {GPIO_PA0, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM0_CCP0_PD0_AF3 + {GPIO_PD0, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM0_CCP0_PL4_AF3 + {GPIO_PL4, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM0_CCP1_PA1_AF3 + {GPIO_PA1, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM0_CCP1_PD1_AF3 + {GPIO_PD1, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM0_CCP1_PL5_AF3 + {GPIO_PL5, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM1_CCP0_PA2_AF3 + {GPIO_PA2, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CCP0_PD2_AF3 + {GPIO_PD2, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CCP0_PL6_AF3 + {GPIO_PL6, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CCP1_PA3_AF3 + {GPIO_PA3, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CCP1_PD3_AF3 + {GPIO_PD3, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CCP1_PL7_AF3 + {GPIO_PL7, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CCP0_PA4_AF3 + {GPIO_PA4, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CCP0_PM0_AF3 + {GPIO_PM0, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CCP1_PA5_AF3 + {GPIO_PA5, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CCP1_PM1_AF3 + {GPIO_PM1, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CCP0_PA6_AF3 + {GPIO_PA6, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CCP0_PD4_AF3 + {GPIO_PD4, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CCP0_PM2_AF3 + {GPIO_PM2, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CCP1_PA7_AF3 + {GPIO_PA7, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CCP1_PD5_AF3 + {GPIO_PD5, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CCP1_PM3_AF3 + {GPIO_PM3, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CCP0_PB0_AF3 + {GPIO_PB0, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CCP0_PD6_AF3 + {GPIO_PD6, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CCP0_PM4_AF3 + {GPIO_PM4, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CCP1_PB1_AF3 + {GPIO_PB1, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CCP1_PD7_AF3 + {GPIO_PD7, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CCP1_PM5_AF3 + {GPIO_PM5, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM5_CCP0_PB2_AF3 + {GPIO_PB2, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CCP0_PM6_AF3 + {GPIO_PM6, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CCP1_PB3_AF3 + {GPIO_PB3, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CCP1_PM7_AF3 + {GPIO_PM7, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM0_CCP0_PR4_AF3 + {GPIO_PR4, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM0_CCP1_PR5_AF3 + {GPIO_PR5, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM1_CCP0_PR6_AF3 + {GPIO_PR6, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CCP1_PR7_AF3 + {GPIO_PR7, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CCP0_PS0_AF3 + {GPIO_PS0, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CCP1_PS1_AF3 + {GPIO_PS1, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CCP0_PS2_AF3 + {GPIO_PS2, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CCP1_PS3_AF3 + {GPIO_PS3, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CCP0_PS4_AF3 + {GPIO_PS4, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CCP1_PS5_AF3 + {GPIO_PS5, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM5_CCP0_PS6_AF3 + {GPIO_PS6, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CCP1_PS7_AF3 + {GPIO_PS7, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM6_CCP0_PB6_AF3 + {GPIO_PB6, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_6)}, + #endif + #ifdef TIM6_CCP0_PP0_AF5 + {GPIO_PP0, HAL_LL_TIM6_BASE_ADDR, 5, hal_ll_tim_module_num(TIM_MODULE_6)}, + #endif + #ifdef TIM6_CCP0_PQ0_AF3 + {GPIO_PQ0, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_6)}, + #endif + #ifdef TIM6_CCP0_PT0_AF3 + {GPIO_PT0, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_6)}, + #endif + #ifdef TIM6_CCP1_PB7_AF3 + {GPIO_PB7, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_6)}, + #endif + #ifdef TIM6_CCP1_PP1_AF5 + {GPIO_PP1, HAL_LL_TIM6_BASE_ADDR, 5, hal_ll_tim_module_num(TIM_MODULE_6)}, + #endif + #ifdef TIM6_CCP1_PQ1_AF3 + {GPIO_PQ1, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_6)}, + #endif + #ifdef TIM6_CCP1_PT1_AF3 + {GPIO_PT1, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_6)}, + #endif + #ifdef TIM7_CCP0_PC4_AF3 + {GPIO_PC4, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_7)}, + #endif + #ifdef TIM7_CCP0_PQ2_AF3 + {GPIO_PQ2, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_7)}, + #endif + #ifdef TIM7_CCP0_PT2_AF3 + {GPIO_PT2, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_7)}, + #endif + #ifdef TIM7_CCP1_PC5_AF3 + {GPIO_PC5, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_7)}, + #endif + #ifdef TIM7_CCP1_PQ3_AF3 + {GPIO_PQ3, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_7)}, + #endif + #ifdef TIM7_CCP1_PT3_AF3 + {GPIO_PT3, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_7)}, + #endif + + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h new file mode 100644 index 0000000000..226d71a8eb --- /dev/null +++ b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h @@ -0,0 +1,325 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.h + * @brief API for UART HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_UART_H_ +#define _HAL_LL_UART_H_ + +#include "hal_ll_target.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief Interrupt request type enum. + */ +typedef enum +{ + HAL_LL_UART_IRQ_RX, /**< RX INT */ + HAL_LL_UART_IRQ_TX /**< TX INT */ +} hal_ll_uart_irq_t; + +/** + * @brief Pointer to interrupt handler function. + */ +typedef void ( *hal_ll_uart_isr_t )( handle_t handle, hal_ll_uart_irq_t event ); + +/** + * @brief Predefined enum values for parity selection. + */ +typedef enum +{ + HAL_LL_UART_PARITY_NONE = 0, + HAL_LL_UART_PARITY_EVEN, + HAL_LL_UART_PARITY_ODD, + + HAL_LL_UART_PARITY_DEFAULT = HAL_LL_UART_PARITY_NONE +} hal_ll_uart_parity_t; + +/** + * @brief Predefined enum values for stop bit selection. + */ +typedef enum +{ + HAL_LL_UART_STOP_BITS_HALF = 0, + HAL_LL_UART_STOP_BITS_ONE, + HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF, + HAL_LL_UART_STOP_BITS_TWO, + + HAL_LL_UART_STOP_BITS_DEFAULT = HAL_LL_UART_STOP_BITS_ONE +} hal_ll_uart_stop_bits_t; + +/** + * @brief Predefined enum values for data bit selection. + */ +typedef enum +{ + HAL_LL_UART_DATA_BITS_5 = -2, + HAL_LL_UART_DATA_BITS_6, + HAL_LL_UART_DATA_BITS_7, + HAL_LL_UART_DATA_BITS_8, + + HAL_LL_UART_DATA_BITS_DEFAULT = HAL_LL_UART_DATA_BITS_8 +} hal_ll_uart_data_bits_t; + +/** + * @brief UART low level pins config structure. + * + * The context structure for storing low level pin configuration + * for both TX and RX pins. + * + */ +typedef struct +{ + hal_ll_pin_af_t tx_pin; + hal_ll_pin_af_t rx_pin; +} hal_ll_uart_pins_t; + +/** + * @brief UART low level handle. + * + * The context for storing low level object handler. + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + handle_t *hal_ll_uart_handle; + handle_t *hal_drv_uart_handle; + bool init_ll_state; +} hal_ll_uart_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] tx_pin UART TX pin. + * @param[in] rx_pin UART RX pin. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ); + +/** + * @brief Registers interrupt handlers for future use. + * + * Registers low level interrupt handlers + * for use with appropriate functions. + * + * @param[in] handle HAL context object handle. + * @param[in] handler Predefined pointer function. + * @param[in] obj HAL context handle address. + + * @return None. + */ +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ); + +/** + * @brief Sets desired baud rate. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] handle HAL context object handle. + * @param[in] baud Desired baud rate value in Bits/s. + * + * @return Actual baud rate value the hw module was initialized to, + * or module specific error value if init failed. + */ +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ); + +/** + * @brief Sets desired parity. + * + * Initializes module with specified parity value. + * + * @param[in] handle HAL context object handle. + * @param[in] parity One of pre-defined values. + * + * @return Re-init module state. If neccessary. + */ +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module with specified stop bits value. + * + * @param[in] handle HAL context object handle. + * @param[in] stop_bit One of pre-defined values. + * + * @return Re-init module state. If neccessary. + */ +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ); + +/** + * @brief Sets desired data bits. + * + * Initializes module with specified data bits value. + * + * @param[in] handle HAL context object handle. + * @param[in] data_bit One of pre-defined values. + * + * @return Re-init module state. If neccessary. + */ +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ); + +/** + * @brief Enables module specific interrupt. + * + * Enables module specific interrupt and registers + * interrupt on hardware level and enables it. + * + * @param[in] handle HAL context object handle. + * @param[in] irq Chip interrupt IRQ value. + * + * @return void None. + */ +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ); + +/** + * @brief Disables module specific interrupt. + * + * Disables module specific interrupt. + * + * @param[in] handle HAL context object handle. + * @param[in] irq Chip interrupt IRQ value. + * + * @return void None. + */ +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ); + +/** + * @brief Performs read operation. + * + * Reads one byte on a hardware level. + * + * @param[in] handle HAL context object handle. + * + * @return uint8_t Data read from hw register. + */ +uint8_t hal_ll_uart_read( handle_t *handle ); + +/** + * @brief Performs read operation in polling mode. + * + * Reads one byte on a hardware level. + * + * @param[in] handle HAL context object handle. + * + * @return uint8_t Data read from hw register. + */ +uint8_t hal_ll_uart_read_polling( handle_t *handle ); + +/** + * @brief Performs write operation. + * + * Accesses hardware data registers and + * writes data directly to it. + * + * @param[in] handle HAL context object handle. + * @param[in] wr_data Data to be written. + * + * @return void None. + */ +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data); + +/** + * @brief Performs write operation in polling mode. + * + * Accesses hardware data registers and + * writes data directly to it. + * + * @param[in] handle HAL context object handle. + * @param[in] wr_data Data to be written. + * + * @return void None. + */ +void hal_ll_uart_write_polling( handle_t *handle, uint8_t wr_data); + +/** + * @brief Closes UART HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_uart_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h new file mode 100644 index 0000000000..e5e17d758c --- /dev/null +++ b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h @@ -0,0 +1,278 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Macro defining `weak` attribute */ +#define __weak __attribute__((weak)) +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) + +/*!< @brief UART module base addresses */ +#ifdef UART_MODULE_0 +static const hal_ll_base_addr_t HAL_LL_UART0_BASE_ADDRESS = 0x4000C000; +#endif +#ifdef UART_MODULE_1 +static const hal_ll_base_addr_t HAL_LL_UART1_BASE_ADDRESS = 0x4000D000; +#endif +#ifdef UART_MODULE_2 +static const hal_ll_base_addr_t HAL_LL_UART2_BASE_ADDRESS = 0x4000E000; +#endif +#ifdef UART_MODULE_3 +static const hal_ll_base_addr_t HAL_LL_UART3_BASE_ADDRESS = 0x4000F000; +#endif +#ifdef UART_MODULE_4 +static const hal_ll_base_addr_t HAL_LL_UART4_BASE_ADDRESS = 0x40010000; +#endif +#ifdef UART_MODULE_5 +static const hal_ll_base_addr_t HAL_LL_UART5_BASE_ADDRESS = 0x40011000; +#endif +#ifdef UART_MODULE_6 +static const hal_ll_base_addr_t HAL_LL_UART6_BASE_ADDRESS = 0x40012000; +#endif +#ifdef UART_MODULE_7 +static const hal_ll_base_addr_t HAL_LL_UART7_BASE_ADDRESS = 0x40013000; +#endif + + +/*!< @brief UART pin structure. */ +typedef struct { + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t af; +} hal_ll_uart_pin_map_t; + +/*!< UART TX Pins. */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { + #ifdef UART0_TX_PA1_AF1 + {hal_ll_uart_module_num(UART_MODULE_0), GPIO_PA1, HAL_LL_UART0_BASE_ADDRESS, 1}, + #endif + #ifdef UART1_TX_PB1_AF1 + {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PB1, HAL_LL_UART1_BASE_ADDRESS, 1}, + #endif + #ifdef UART1_TX_PC5_AF2 + {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC5, HAL_LL_UART1_BASE_ADDRESS, 2}, + #endif + #ifdef UART2_TX_PD7_AF1 + {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PD7, HAL_LL_UART2_BASE_ADDRESS, 1}, + #endif + #ifdef UART2_TX_PG5_AF1 + {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PG5, HAL_LL_UART2_BASE_ADDRESS, 1}, + #endif + #ifdef UART3_TX_PC7_AF1 + {hal_ll_uart_module_num(UART_MODULE_3), GPIO_PC7, HAL_LL_UART3_BASE_ADDRESS, 1}, + #endif + #ifdef UART4_TX_PC5_AF1 + {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PC5, HAL_LL_UART4_BASE_ADDRESS, 1}, + #endif + #ifdef UART5_TX_PE5_AF1 + {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PE5, HAL_LL_UART5_BASE_ADDRESS, 1}, + #endif + #ifdef UART6_TX_PD5_AF1 + {hal_ll_uart_module_num(UART_MODULE_6), GPIO_PD5, HAL_LL_UART6_BASE_ADDRESS, 1}, + #endif + #ifdef UART7_TX_PE1_AF1 + {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PE1, HAL_LL_UART7_BASE_ADDRESS, 1}, + #endif + #ifdef UART4_TX_PJ1_AF1 + {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PJ1, HAL_LL_UART4_BASE_ADDRESS, 1}, + #endif + #ifdef UART5_TX_PJ3_AF1 + {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PJ3, HAL_LL_UART5_BASE_ADDRESS, 1}, + #endif + #ifdef UART6_TX_PJ5_AF1 + {hal_ll_uart_module_num(UART_MODULE_6), GPIO_PJ5, HAL_LL_UART6_BASE_ADDRESS, 1}, + #endif + #ifdef UART7_TX_PK5_AF1 + {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PK5, HAL_LL_UART7_BASE_ADDRESS, 1}, + #endif + #ifdef UART1_TX_PQ5_AF1 + {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PQ5, HAL_LL_UART1_BASE_ADDRESS, 1}, + #endif + #ifdef UART2_TX_PA7_AF1 + {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PA7, HAL_LL_UART2_BASE_ADDRESS, 1}, + #endif + #ifdef UART2_TX_PD5_AF1 + {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PD5, HAL_LL_UART2_BASE_ADDRESS, 1}, + #endif + #ifdef UART3_TX_PA5_AF1 + {hal_ll_uart_module_num(UART_MODULE_3), GPIO_PA5, HAL_LL_UART3_BASE_ADDRESS, 1}, + #endif + #ifdef UART3_TX_PJ1_AF1 + {hal_ll_uart_module_num(UART_MODULE_3), GPIO_PJ1, HAL_LL_UART3_BASE_ADDRESS, 1}, + #endif + #ifdef UART4_TX_PA3_AF1 + {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PA3, HAL_LL_UART4_BASE_ADDRESS, 1}, + #endif + #ifdef UART4_TX_PK1_AF1 + {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PK1, HAL_LL_UART4_BASE_ADDRESS, 1}, + #endif + #ifdef UART5_TX_PC7_AF1 + {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PC7, HAL_LL_UART5_BASE_ADDRESS, 1}, + #endif + #ifdef UART6_TX_PP1_AF1 + {hal_ll_uart_module_num(UART_MODULE_6), GPIO_PP1, HAL_LL_UART6_BASE_ADDRESS, 1}, + #endif + #ifdef UART7_TX_PC5_AF1 + {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PC5, HAL_LL_UART7_BASE_ADDRESS, 1}, + #endif + #ifdef UART1_TX_PR6_AF1 + {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PR6, HAL_LL_UART1_BASE_ADDRESS, 1}, + #endif + #ifdef UART4_TX_PR0_AF1 + {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PR0, HAL_LL_UART4_BASE_ADDRESS, 1}, + #endif + #ifdef UART5_TX_PH7_AF1 + {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PH7, HAL_LL_UART5_BASE_ADDRESS, 1}, + #endif + #ifdef UART7_TX_PH7_AF2 + {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PH7, HAL_LL_UART7_BASE_ADDRESS, 2}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +/*!< UART RX Pins. */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = { + #ifdef UART0_RX_PA0_AF1 + {hal_ll_uart_module_num(UART_MODULE_0), GPIO_PA0, HAL_LL_UART0_BASE_ADDRESS, 1}, + #endif + #ifdef UART1_RX_PB0_AF1 + {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PB0, HAL_LL_UART1_BASE_ADDRESS, 1}, + #endif + #ifdef UART1_RX_PC4_AF2 + {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC4, HAL_LL_UART1_BASE_ADDRESS, 2}, + #endif + #ifdef UART2_RX_PD6_AF1 + {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PD6, HAL_LL_UART2_BASE_ADDRESS, 1}, + #endif + #ifdef UART2_RX_PG4_AF1 + {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PG4, HAL_LL_UART2_BASE_ADDRESS, 1}, + #endif + #ifdef UART3_RX_PC6_AF1 + {hal_ll_uart_module_num(UART_MODULE_3), GPIO_PC6, HAL_LL_UART3_BASE_ADDRESS, 1}, + #endif + #ifdef UART4_RX_PC4_AF1 + {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PC4, HAL_LL_UART4_BASE_ADDRESS, 1}, + #endif + #ifdef UART5_RX_PE4_AF1 + {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PE4, HAL_LL_UART5_BASE_ADDRESS, 1}, + #endif + #ifdef UART6_RX_PD4_AF1 + {hal_ll_uart_module_num(UART_MODULE_6), GPIO_PD4, HAL_LL_UART6_BASE_ADDRESS, 1}, + #endif + #ifdef UART7_RX_PE0_AF1 + {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PE0, HAL_LL_UART7_BASE_ADDRESS, 1}, + #endif + #ifdef UART4_RX_PJ0_AF1 + {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PJ0, HAL_LL_UART4_BASE_ADDRESS, 1}, + #endif + #ifdef UART5_RX_PJ2_AF1 + {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PJ2, HAL_LL_UART5_BASE_ADDRESS, 1}, + #endif + #ifdef UART6_RX_PJ4_AF1 + {hal_ll_uart_module_num(UART_MODULE_6), GPIO_PJ4, HAL_LL_UART6_BASE_ADDRESS, 1}, + #endif + #ifdef UART7_RX_PK4_AF1 + {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PK4, HAL_LL_UART7_BASE_ADDRESS, 1}, + #endif + #ifdef UART1_RX_PQ4_AF1 + {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PQ4, HAL_LL_UART1_BASE_ADDRESS, 1}, + #endif + #ifdef UART2_RX_PA6_AF1 + {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PA6, HAL_LL_UART2_BASE_ADDRESS, 1}, + #endif + #ifdef UART2_RX_PD4_AF1 + {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PD4, HAL_LL_UART2_BASE_ADDRESS, 1}, + #endif + #ifdef UART3_RX_PA4_AF1 + {hal_ll_uart_module_num(UART_MODULE_3), GPIO_PA4, HAL_LL_UART3_BASE_ADDRESS, 1}, + #endif + #ifdef UART3_RX_PJ0_AF1 + {hal_ll_uart_module_num(UART_MODULE_3), GPIO_PJ0, HAL_LL_UART3_BASE_ADDRESS, 1}, + #endif + #ifdef UART4_RX_PA2_AF1 + {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PA2, HAL_LL_UART4_BASE_ADDRESS, 1}, + #endif + #ifdef UART4_RX_PK0_AF1 + {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PK0, HAL_LL_UART4_BASE_ADDRESS, 1}, + #endif + #ifdef UART5_RX_PC6_AF1 + {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PC6, HAL_LL_UART5_BASE_ADDRESS, 1}, + #endif + #ifdef UART6_RX_PP0_AF1 + {hal_ll_uart_module_num(UART_MODULE_6), GPIO_PP0, HAL_LL_UART6_BASE_ADDRESS, 1}, + #endif + #ifdef UART7_RX_PC4_AF1 + {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PC4, HAL_LL_UART7_BASE_ADDRESS, 1}, + #endif + #ifdef UART1_RX_PR5_AF1 + {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PR5, HAL_LL_UART1_BASE_ADDRESS, 1}, + #endif + #ifdef UART4_RX_PR1_AF1 + {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PR1, HAL_LL_UART4_BASE_ADDRESS, 1}, + #endif + #ifdef UART5_RX_PH6_AF1 + {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PH6, HAL_LL_UART5_BASE_ADDRESS, 1}, + #endif + #ifdef UART7_RX_PH6_AF2 + {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PH6, HAL_LL_UART7_BASE_ADDRESS, 2}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt b/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt new file mode 100644 index 0000000000..f146c6a315 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt @@ -0,0 +1,62 @@ +## ./targets/arm/mikroe/tiva/src/adc/CMakeLists.txt +set(hal_ll_def_list "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +# BEGIN ADC +list(APPEND hal_ll_def_list "MACRO_USAGE_ADC") +list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +set(adc_subimplementation "implementation_1/hal_ll_adc.c") +set(adc_pin_map "hal_ll_adc_pin_map/implementation_1") +# END ADC + +mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC + ${adc_subimplementation} + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h +#BEGIN ADC + ../../include/adc/hal_ll_adc.h + ../../include/adc/${adc_pin_map}/hal_ll_adc_pin_map.h +#END ADC +) + +target_compile_definitions(lib_hal_ll_adc PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_adc PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_adc + PRIVATE + ../../include + ../../include/gpio + #BEGINADC + ../../include/adc + ../../include/adc/${adc_pin_map} + #ENDADC + INTERFACE + $ + $ + $ + $ + + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.ADC) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.ADC ../../include/adc/hal_ll_adc.h) diff --git a/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c new file mode 100644 index 0000000000..35c3b6b21e --- /dev/null +++ b/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c @@ -0,0 +1,224 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base + +/*!< @brief Helper macro for getting adequate module index number. */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +// TODO + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list. */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ ADC_MODULE_COUNT ] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/*!< @brief ADC register structure. */ +typedef struct { + volatile uint32_t TODO; +} hal_ll_adc_base_handle_t; + +/** + * Return values. + */ +typedef enum { + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +/*!< @brief ADC hw specific module values. */ +typedef struct { + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +// ---------------------------------------------------------- PRIVATE VARIABLES + +/** + * @brief Array of maps holding information for configuring hardware. + */ +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[ADC_MODULE_COUNT + 1] = { + #ifdef ADC_MODULE_0 + {ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_1 ), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_DEFAULT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Check if pins are adequate. + * @Details Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * @details Maps pin name, register address and channel from analog register list to module in hardware specific map. + * @param[in] module_index ADC HW module index -- 0,1,2... Index in hal_ll_adc_hw_specifics_map, + * destination of copying. + * @param[in] index Pointer with ADC pin map index value. Index in hal_ll_analog_in_register_list + * source of copying information + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Get local hardware specific map. + * @details Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array element. + * @param[in] handle - Object specific context handler. + * @return address of a member in hal_ll_adc_hw_specifics_map, either a correct member + * or an 'error' terminating member in map. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable ADC module gate clock. + * @param module_index - ADC HW module index -- 0,1,2... + * @param state - true/false + * @return None + */ +static void adc_clock_enable(uint8_t module_index , bool state ); + +/** + * @brief Initialize hardware ADC module. + * @details Hardware initialization of Tiva. + * @param *map - ADC module local map, pointer to a + * member in hal_ll_adc_hw_specifics_map global array. + * @return None + */ +static void hal_ll_adc_hw_init(hal_ll_adc_hw_specifics_map_t *map); + +/** + * @brief Initialize ADC module @p map. + * @details from @p map, uses pin information to set it as analog & sets + * @param[in] *map - ADC module local map, pointer to a + * member in hal_ll_adc_hw_specifics_map global array. + * @return None. + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, + hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id){ + return 0; + } + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ){ + return 0; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution){ + return 0; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) { + return 0; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value){ + return; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ){ + return 0; +} + +void hal_ll_adc_close( handle_t *handle ){ + return; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) { + return 0; +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) {} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + return 0; +} + +static void adc_clock_enable( uint8_t module_index , bool state ) {} + +static void hal_ll_adc_hw_init(hal_ll_adc_hw_specifics_map_t *map) {} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) {} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/can/CMakeLists.txt b/targets/arm/mikroe/renesas/src/can/CMakeLists.txt new file mode 100644 index 0000000000..0e6f9404ef --- /dev/null +++ b/targets/arm/mikroe/renesas/src/can/CMakeLists.txt @@ -0,0 +1,54 @@ +## ./targets/arm/mikroe/tiva/src/can/CMakeLists.txt +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +## BEGIN CAN +set(can_subimplementation "implementation_1/hal_ll_can.c") +set(can_pin_map "hal_ll_can_pin_map") +## END CAN + +mikrosdk_add_library(lib_hal_ll_can MikroSDK.HalLowLevel.CAN + ${can_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN CAN + ../../include/can/hal_ll_can.h + ../../include/can/${can_pin_map}/hal_ll_can_pin_map.h + # END CAN +) + +target_compile_definitions(lib_hal_ll_can PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_can PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_can + PRIVATE + ../../include + ../../include/gpio + # BEGIN CAN + ../../include/can + ../../include/can/${can_pin_map} + # END CAN + + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.CAN) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.CAN ../../include/can/hal_ll_can.h) diff --git a/targets/arm/mikroe/renesas/src/can/implementation_1/hal_ll_can.c b/targets/arm/mikroe/renesas/src/can/implementation_1/hal_ll_can.c new file mode 100644 index 0000000000..e1d1854fef --- /dev/null +++ b/targets/arm/mikroe/renesas/src/can/implementation_1/hal_ll_can.c @@ -0,0 +1,1017 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can.c + * @brief CAN HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_can.h" +#include "hal_ll_gpio.h" +#include "hal_ll_can_pin_map.h" +#include "hal_ll_bit_control.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_can_handle_register_t hal_ll_module_state[CAN_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_can_get_module_state_address ((hal_ll_can_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_can_get_handle (hal_ll_can_handle_register_t *)hal_ll_can_get_module_state_address->hal_ll_can_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_can_get_base_struct(_handle) ((hal_ll_can_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_can_get_base_from_hal_handle ((hal_ll_can_hw_specifics_map_t *)((hal_ll_can_handle_register_t *)\ + (((hal_ll_can_handle_register_t *)(handle))->hal_ll_can_handle))->hal_ll_can_handle)->base + +#define HAL_LL_CAN_AF_CONFIG (GPIO_CFG_ALT_FUNCTION | GPIO_CFG_DIGITAL_ENABLE | GPIO_CFG_DRIVE_8mA) + +#define HAL_LL_CAN1_CLOCK_ENABLE (0) +#define HAL_LL_CAN2_CLOCK_ENABLE (1) + +#define HAL_LL_CAN_CANCTL_INIT_BIT (0) +#define HAL_LL_CAN_CANCTL_DAR_BIT (5) +#define HAL_LL_CAN_CANCTL_TEST_BIT (7) +#define HAL_LL_CAN_CANTST_LBACK_BIT (4) +#define HAL_LL_CAN_CANCTL_CCE_BIT (6) + +#define HAL_LL_CAN_IF_CRQ_BUSY_BIT (15) + +#define HAL_LL_CAN_IF_CMSK_WRNRD_MASK (0x80UL) +#define HAL_LL_CAN_IF_CMSK_MASK_MASK (0x40UL) +#define HAL_LL_CAN_IF_CMSK_ARB_MASK (0x20UL) +#define HAL_LL_CAN_IF_CMSK_CONTROL_MASK (0x10UL) +#define HAL_LL_CAN_IF_CMSK_CLRINTPND_MASK (0x8UL) +#define HAL_LL_CAN_IF_CMSK_NEWDAT_MASK (0x4UL) +#define HAL_LL_CAN_IF_CMSK_TXRQST_MASK (HAL_LL_CAN_IF_CMSK_NEWDAT_MASK) +#define HAL_LL_CAN_IF_CMSK_DATAA_MASK (0x2UL) +#define HAL_LL_CAN_IF_CMSK_DATAB_MASK (0x1UL) +#define HAL_LL_CAN_IF_CMSK_TXRQST_BIT (2) +#define HAL_LL_CAN_IF_CMSK_NEWDAT_BIT (HAL_LL_CAN_IF_CMSK_TXRQST_BIT) + +#define HAL_LL_CAN_IF_MCTL_RMTEN_BIT (9) +#define HAL_LL_CAN_IF_MCTL_TXRQST_BIT (8) +#define HAL_LL_CAN_IF_MCTL_EOB_BIT (7) +#define HAL_LL_CAN_IF_MCTL_NEWDAT_BIT (15) +#define HAL_LL_CAN_IF_MCTL_DLC_MASK (0xFUL) +#define HAL_LL_CAN_IF_MCTL_TXRQST_MASK (0x100UL) +#define HAL_LL_CAN_IF_MCTL_UMASK_BIT (12) + +#define HAL_LL_CAN_IF_ARB2_MSGVAL_BIT (15) +#define HAL_LL_CAN_IF_ARB2_XTD_BIT (14) +#define HAL_LL_CAN_IF_ARB2_DIR_BIT (13) +#define HAL_LL_CAN_IF_ARB2_ID_MASK (0x1FFFUL) +#define HAL_LL_CAN_IF_ARB2_MSGVAL_MASK (0x8000UL) +#define HAL_LL_CAN_IF_ARB2_DIR_MASK (0x2000UL) +#define HAL_LL_CAN_IF_ARB2_ID_SHIFT (2) + +#define HAL_LL_CAN_IF_MSK2_ID_SHIFT (HAL_LL_CAN_IF_ARB2_ID_SHIFT) + +#define HAL_LL_CAN_CANBIT_SJW_SHIFT (6) +#define HAL_LL_CAN_CANBIT_TSEG1_SHIFT (8) +#define HAL_LL_CAN_CANBIT_TSEG2_SHIFT (12) +#define HAL_LL_CAN_CANBRPE_PRESCALER_SHIFT (6) +#define HAL_LL_CAN_PRESCALER_BITS_5_0 (0x3FUL) +#define HAL_LL_CAN_PRESCALER_BITS_10_6 (0x3CUL) + +#define HAL_LL_CAN_SJW_CONST_VALUE (1) +#define HAL_LL_CAN_TSEG1_MAX_VAL (16) +#define HAL_LL_CAN_TSEG2_MAX_VAL (8) +#define HAL_LL_CAN_PRESCALER_MAX_VAL (1024) +#define HAL_LL_CAN_BIT_RATE_SAMPLE_POINT (0.875) + +#define HAL_LL_CAN_TRANSMIT_MESSAGE_ID (1) + +#define HAL_LL_CAN_EID_BITS_28_11 (0x3FFFF800UL) +#define HAL_LL_CAN_SID_MASK (0x7FFUL) + +#define HAL_LL_CAN_MAX_MNUM (32) + +#define HAL_LL_CAN_REG_CLEAR (0x0000UL) + +#define HAL_LL_CAN_IF_DATA_SHIFT (8) + +#define HAL_LL_CAN_TIMEOUT_VALUE (10000UL) + +/*!< @brief CAN hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_can_pins_t pins; + hal_ll_can_mode_t mode; + uint32_t frequency; +} hal_ll_can_hw_specifics_map_t; + +/*!< @brief CAN hw specific module values */ +typedef struct +{ + hal_ll_pin_name_t pin_tx; + hal_ll_pin_name_t pin_rx; +} hal_ll_can_pin_id; + +/*!< @brief CAN IF structure */ +typedef struct +{ + hal_ll_base_addr_t crq; + hal_ll_base_addr_t cmsk; + hal_ll_base_addr_t msk1; + hal_ll_base_addr_t msk2; + hal_ll_base_addr_t arb1; + hal_ll_base_addr_t arb2; + hal_ll_base_addr_t mctl; + hal_ll_base_addr_t da1; + hal_ll_base_addr_t da2; + hal_ll_base_addr_t db1; + hal_ll_base_addr_t db2; +} hal_ll_can_if; + +/*!< @brief CAN HW register structure */ +typedef struct +{ + hal_ll_base_addr_t canctl; + hal_ll_base_addr_t cansts; + hal_ll_base_addr_t canerr; + hal_ll_base_addr_t canbit; + hal_ll_base_addr_t canint; + hal_ll_base_addr_t cantst; + hal_ll_base_addr_t canbrpe; + hal_ll_base_addr_t res0; + hal_ll_can_if can_if1; + hal_ll_base_addr_t res[13]; + hal_ll_can_if can_if2; + hal_ll_base_addr_t res1[21]; + hal_ll_base_addr_t cantxrq[2]; + hal_ll_base_addr_t res2[6]; + hal_ll_base_addr_t cannwda[2]; + hal_ll_base_addr_t res5[6]; + hal_ll_base_addr_t canmsgint[2]; + hal_ll_base_addr_t res4[6]; + hal_ll_base_addr_t canmsgval[2]; +} hal_ll_can_base_handle_t; + +/*!< @brief CAN hw specific error values */ +typedef enum +{ + HAL_LL_CAN_SUCCESS = 0, + HAL_LL_CAN_WRONG_PINS, + HAL_LL_CAN_MODULE_ERROR, + + HAL_LL_CAN_ERROR = (-1) +} hal_ll_can_err_t; +// ------------------------------------------------------------------ VARIABLES +/*!< @brief CAN hardware specific info */ +static hal_ll_can_hw_specifics_map_t hal_ll_can_hw_specifics_map[] = +{ + #ifdef CAN_MODULE_0 + { HAL_LL_CAN0_BASE_ADDRESS, hal_ll_can_module_num( CAN_MODULE_0 ), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, HAL_LL_CAN_MODE_NORMAL, 125000 }, + #endif + #ifdef CAN_MODULE_1 + { HAL_LL_CAN1_BASE_ADDRESS, hal_ll_can_module_num( CAN_MODULE_1 ), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, HAL_LL_CAN_MODE_NORMAL, 125000 }, + #endif + + { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, HAL_LL_CAN_MODE_NORMAL, 125000 } +}; + + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_can_handle_register_t *low_level_handle; +static volatile hal_ll_can_hw_specifics_map_t *hal_ll_can_hw_specifics_map_local; +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx - TX pre-defined pin name. + * @param[in] rx - RX pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_can_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, + hal_ll_can_pin_id *index_list, hal_ll_can_handle_register_t *handle_map ); + +/** + * @brief Sets CAN pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if CAN is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_can_alternate_functions_set_state( hal_ll_can_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * CAN TX and RX pins. + * + * @param[in] module_index CAN HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_can_map_pins( uint8_t module_index, hal_ll_can_pin_id *index_list ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_can_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_can_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_can_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Full CAN module initialization procedure. + * + * Initializes CAN module on hardware level, based on beforehand + * set configuration and module handler. Sets control and filter registers. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @param[in] config - CAN config structure. + * @param[in] filter_config - CAN filter config structure. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ); + +/** + * @brief Calculates parameters for desired CAN frequency. + * + * Calculates adequate values to be written in CAN_BTR register + * in order to set appropriate baud rate. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_can_bit_timing( hal_ll_can_hw_specifics_map_t *map ); + +/** + * @brief Initialize CAN module on hardware level. + * + * Initializes CAN module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] config - CAN config structure. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_can_module_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config ); + +/** + * @brief Configure CAN filter. + * + * Initializes CAN filter on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] filter_config - CAN filter config structure. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_can_filter_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_filter_config_t *filter_config ); + +/** + * @brief Enable clock for CAN module on hardware level. + * + * Initializes CAN module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] clock_enable - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_can_clock_enable( uint8_t module_index, bool clock_enable ); + +/** + * @brief Configure CAN message object. + * + * Initializes CAN message object on hardware level, based on its number and identifier. + * + * @param[in] base - CAN module base address. + * @param[in] message_object_num - Message object number. + * @return identifier Message/filter ID. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t message_config( hal_ll_base_addr_t *base, uint8_t message_object_num, uint32_t identifier ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_can_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_can_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_can_pin_id index_list[CAN_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( HAL_LL_PIN_NC == ( pin_check_result = hal_ll_can_check_pins( tx_pin, rx_pin, &index_list, handle_map ))) { + return HAL_LL_CAN_WRONG_PINS; + }; + + if ( (hal_ll_can_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_can_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_can_alternate_functions_set_state( &hal_ll_can_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_can_map_pins( pin_check_result, &index_list ); + + hal_ll_can_alternate_functions_set_state( &hal_ll_can_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_can_handle = (handle_t *)&hal_ll_can_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_can_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_can_handle; + + return HAL_LL_CAN_SUCCESS; +} + +hal_ll_err_t hal_ll_can_init( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_can_get_module_state_address); + hal_ll_can_handle_register_t *hal_handle = (hal_ll_can_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_can_hw_specifics_map_local->module_index; + + hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_local, config, filter_config ); + + hal_ll_module_state[pin_check_result].hal_ll_can_handle = (handle_t *)&hal_ll_can_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_CAN_SUCCESS; +} + +hal_ll_err_t hal_ll_can_set_filter( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ) { + low_level_handle = hal_ll_can_get_handle; + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + + low_level_handle->init_ll_state = false; + hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_local, config, filter_config ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_CAN_SUCCESS; +} + +hal_ll_err_t hal_ll_can_set_frequency( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ) { + low_level_handle = hal_ll_can_get_handle; + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + uint32_t original_frequency; + hal_ll_err_t result; + + low_level_handle->init_ll_state = false; + + original_frequency = hal_ll_can_hw_specifics_map_local->frequency; + + hal_ll_can_hw_specifics_map_local->frequency = config->frequency; + result = hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_local, config, filter_config ); + + // In case the desired frequency setting hasn't been achieved, there's no need to update the map. + if( HAL_LL_CAN_SUCCESS != result ) + hal_ll_can_hw_specifics_map_local->frequency = original_frequency; + + low_level_handle->init_ll_state = true; + + return result; +} + +hal_ll_err_t hal_ll_can_get_frequency( handle_t *handle ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + + return hal_ll_can_hw_specifics_map_local->frequency; +} + +hal_ll_err_t hal_ll_can_set_mode( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ) { + low_level_handle = hal_ll_can_get_handle; + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + hal_ll_err_t result; + + low_level_handle->init_ll_state = false; + + // NOTE: Changing mode won't result in an error, so saving the previous value is not needed. + hal_ll_can_hw_specifics_map_local->mode = config->mode; + result = hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_local, config, filter_config ); + + low_level_handle->init_ll_state = true; + + return result; +} + +hal_ll_err_t hal_ll_can_get_mode( handle_t *handle ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + + return hal_ll_can_hw_specifics_map_local->mode; +} + +hal_ll_err_t hal_ll_can_transmit( handle_t *handle, hal_ll_can_transmit_message_struct *transmit_message ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_can_get_module_state_address); + hal_ll_can_base_handle_t *hal_ll_hw_reg = ( hal_ll_can_base_handle_t *)hal_ll_can_hw_specifics_map_local->base; + uint32_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + // Configure transmit message object + message_config( (hal_ll_base_addr_t *)hal_ll_can_hw_specifics_map_local->base, + HAL_LL_CAN_TRANSMIT_MESSAGE_ID, transmit_message->message.std_id ); + + // Wait for BUSY bit to clear. + while( check_reg_bit( &hal_ll_hw_reg->can_if1.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) + if( !timeout-- ) + return HAL_LL_CAN_ERROR; + + hal_ll_hw_reg->can_if2.cmsk = HAL_LL_CAN_IF_CMSK_CONTROL_MASK | HAL_LL_CAN_IF_CMSK_MASK_MASK | HAL_LL_CAN_IF_CMSK_ARB_MASK | + HAL_LL_CAN_IF_CMSK_DATAA_MASK | HAL_LL_CAN_IF_CMSK_DATAB_MASK; + + hal_ll_hw_reg->can_if2.crq = HAL_LL_CAN_TRANSMIT_MESSAGE_ID; + + timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + // Wait for BUSY bit to clear. + while( check_reg_bit( &hal_ll_hw_reg->can_if2.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) + if( !timeout-- ) + return HAL_LL_CAN_ERROR; + + hal_ll_hw_reg->can_if1.da1 = (uint32_t)transmit_message->message.message_data[0]; + hal_ll_hw_reg->can_if1.da1 |= (uint32_t)transmit_message->message.message_data[1] << HAL_LL_CAN_IF_DATA_SHIFT; + hal_ll_hw_reg->can_if1.da2 = (uint32_t)transmit_message->message.message_data[2]; + hal_ll_hw_reg->can_if1.da2 |= (uint32_t)transmit_message->message.message_data[3] << HAL_LL_CAN_IF_DATA_SHIFT; + hal_ll_hw_reg->can_if1.db1 = (uint32_t)transmit_message->message.message_data[4]; + hal_ll_hw_reg->can_if1.db1 |= (uint32_t)transmit_message->message.message_data[5] << HAL_LL_CAN_IF_DATA_SHIFT; + hal_ll_hw_reg->can_if1.db2 = (uint32_t)transmit_message->message.message_data[6]; + hal_ll_hw_reg->can_if1.db2 |= (uint32_t)transmit_message->message.message_data[7] << HAL_LL_CAN_IF_DATA_SHIFT; + + hal_ll_hw_reg->can_if1.cmsk = HAL_LL_CAN_IF_CMSK_WRNRD_MASK | HAL_LL_CAN_IF_CMSK_DATAA_MASK | HAL_LL_CAN_IF_CMSK_DATAB_MASK | + HAL_LL_CAN_IF_CMSK_CONTROL_MASK | HAL_LL_CAN_IF_CMSK_ARB_MASK; + + hal_ll_hw_reg->can_if1.arb2 |= (( transmit_message->message.std_id << HAL_LL_CAN_IF_ARB2_ID_SHIFT ) & HAL_LL_CAN_IF_ARB2_ID_MASK ) | + HAL_LL_CAN_IF_ARB2_MSGVAL_MASK | HAL_LL_CAN_IF_ARB2_DIR_MASK; + hal_ll_hw_reg->can_if1.mctl |= ( transmit_message->message.data_len & HAL_LL_CAN_IF_MCTL_DLC_MASK ) | + HAL_LL_CAN_IF_MCTL_TXRQST_MASK; + + hal_ll_hw_reg->can_if1.crq = HAL_LL_CAN_TRANSMIT_MESSAGE_ID; + set_reg_bit( &hal_ll_hw_reg->can_if2.cmsk, HAL_LL_CAN_IF_CMSK_TXRQST_BIT ); + + return HAL_LL_CAN_SUCCESS; +} + +void hal_ll_can_transmission_stop( handle_t *handle ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_can_get_module_state_address); + hal_ll_can_base_handle_t *hal_ll_hw_reg = ( hal_ll_can_base_handle_t *)hal_ll_can_hw_specifics_map_local->base; + + // Putting CAN module in initialization mode stops all bus activities. + set_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_INIT_BIT ); +} + +hal_ll_err_t hal_ll_can_receive( handle_t *handle, hal_ll_can_receive_message_struct *receive_message ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_can_get_module_state_address); + hal_ll_can_base_handle_t *hal_ll_hw_reg = ( hal_ll_can_base_handle_t *)hal_ll_can_hw_specifics_map_local->base; + uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + hal_ll_hw_reg->can_if2.cmsk = HAL_LL_CAN_IF_CMSK_DATAA_MASK | HAL_LL_CAN_IF_CMSK_DATAB_MASK | HAL_LL_CAN_IF_CMSK_CONTROL_MASK | + HAL_LL_CAN_IF_CMSK_MASK_MASK | HAL_LL_CAN_IF_CMSK_ARB_MASK; + + // Configure ARB2 register. + clear_reg_bit( &hal_ll_hw_reg->can_if2.arb2, HAL_LL_CAN_IF_ARB2_XTD_BIT ); + clear_reg_bit( &hal_ll_hw_reg->can_if2.arb2, HAL_LL_CAN_IF_ARB2_DIR_BIT ); + set_reg_bit( &hal_ll_hw_reg->can_if2.arb2, HAL_LL_CAN_IF_ARB2_MSGVAL_BIT ); + + // Configure MCTL register. + set_reg_bit( &hal_ll_hw_reg->can_if2.mctl, HAL_LL_CAN_IF_MCTL_UMASK_BIT ); + clear_reg_bit( &hal_ll_hw_reg->can_if2.mctl, HAL_LL_CAN_IF_MCTL_RMTEN_BIT ); + set_reg_bit( &hal_ll_hw_reg->can_if2.mctl, HAL_LL_CAN_IF_MCTL_EOB_BIT ); + + hal_ll_hw_reg->can_if2.crq = receive_message->rx_fifo_number; + + // Wait for BUSY bit to clear. + while( check_reg_bit( &hal_ll_hw_reg->can_if2.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) + if( !timeout-- ) + return HAL_LL_CAN_ERROR; + + receive_message->message.std_id = ( hal_ll_hw_reg->can_if1.arb2 & HAL_LL_CAN_IF_ARB2_ID_MASK ) >> HAL_LL_CAN_IF_ARB2_ID_SHIFT; + + // Check for new data. + if( check_reg_bit( &hal_ll_hw_reg->can_if2.mctl, HAL_LL_CAN_IF_MCTL_NEWDAT_BIT )) { + receive_message->message.data_len = hal_ll_hw_reg->can_if2.mctl & HAL_LL_CAN_IF_MCTL_DLC_MASK; + receive_message->message.message_data[0] = hal_ll_hw_reg->can_if2.da1; + receive_message->message.message_data[1] = hal_ll_hw_reg->can_if2.da1 >> HAL_LL_CAN_IF_DATA_SHIFT; + receive_message->message.message_data[2] = hal_ll_hw_reg->can_if2.da2; + receive_message->message.message_data[3] = hal_ll_hw_reg->can_if2.da2 >> HAL_LL_CAN_IF_DATA_SHIFT; + receive_message->message.message_data[4] = hal_ll_hw_reg->can_if2.db1; + receive_message->message.message_data[5] = hal_ll_hw_reg->can_if2.db1 >> HAL_LL_CAN_IF_DATA_SHIFT; + receive_message->message.message_data[6] = hal_ll_hw_reg->can_if2.db2; + receive_message->message.message_data[7] = hal_ll_hw_reg->can_if2.db2 >> HAL_LL_CAN_IF_DATA_SHIFT; + } + + // Clear NEWDAT. + clear_reg_bit( &hal_ll_hw_reg->can_if2.mctl, HAL_LL_CAN_IF_MCTL_NEWDAT_BIT ); + set_reg_bit( &hal_ll_hw_reg->can_if2.cmsk, HAL_LL_CAN_IF_CMSK_NEWDAT_BIT ); + + hal_ll_hw_reg->can_if2.crq = receive_message->rx_fifo_number; + + timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + // Wait for BUSY bit to clear. + while( check_reg_bit( &hal_ll_hw_reg->can_if2.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) + if( !timeout-- ) + return HAL_LL_CAN_ERROR; + + return HAL_LL_CAN_SUCCESS; +} + +hal_ll_err_t hal_ll_can_close( handle_t *handle ) { + low_level_handle = hal_ll_can_get_handle; + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_can_get_module_state_address); + + if( low_level_handle->hal_ll_can_handle != NULL ) { + hal_ll_can_clock_enable(hal_ll_can_hw_specifics_map_local->module_index, true); + hal_ll_can_alternate_functions_set_state( hal_ll_can_hw_specifics_map_local, false ); + + hal_ll_can_clock_enable(hal_ll_can_hw_specifics_map_local->module_index, false); + + hal_ll_can_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_can_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_can_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_can_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_can_hw_specifics_map_local->frequency = 500000UL; + + low_level_handle->hal_ll_can_handle = NULL; + low_level_handle->hal_drv_can_handle = NULL; + + low_level_handle->init_ll_state = false; + + return HAL_LL_CAN_SUCCESS; + } else + return HAL_LL_CAN_ERROR; +} + +// ---------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_pin_name_t hal_ll_can_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, + hal_ll_can_pin_id *index_list, hal_ll_can_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_can_tx_map ) / sizeof( hal_ll_can_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_can_rx_map ) / sizeof( hal_ll_can_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_can_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_can_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_can_tx_map[ tx_index ].base == hal_ll_can_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_can_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_can_handle ) { + return hal_ll_module_id; + } else if ( CAN_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_can_alternate_functions_set_state( hal_ll_can_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = GPIO_CFG_ALT_FUNCTION | GPIO_CFG_DIGITAL_OUTPUT; + module.configs[1] = GPIO_CFG_ALT_FUNCTION | GPIO_CFG_DIGITAL_INPUT; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_can_map_pins( uint8_t module_index, hal_ll_can_pin_id *index_list ) { + // Map new pins + hal_ll_can_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_can_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_can_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_can_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_can_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_can_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_can_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_can_rx_map[ index_list[module_index].pin_rx ].af; +} + +static hal_ll_can_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_can_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_can_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_can_get_base_from_hal_handle == hal_ll_can_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_can_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_can_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_can_clock_enable( uint8_t module_index, bool clock_enable ) { + + switch( module_index ) { + #ifdef CAN_MODULE_0 + case ( hal_ll_can_module_num( CAN_MODULE_0 ) ): + if( true == clock_enable ) + set_reg_bit( _SYSCTL_RCGCCAN, HAL_LL_CAN1_CLOCK_ENABLE ); + else + clear_reg_bit( _SYSCTL_RCGCCAN, HAL_LL_CAN1_CLOCK_ENABLE ); + break; + #endif + #ifdef CAN_MODULE_1 + case ( hal_ll_can_module_num( CAN_MODULE_1 ) ): + if( true == clock_enable ) + set_reg_bit( _SYSCTL_RCGCCAN, HAL_LL_CAN2_CLOCK_ENABLE ); + else + clear_reg_bit( _SYSCTL_RCGCCAN, HAL_LL_CAN2_CLOCK_ENABLE ); + break; + #endif + + default: + break; + } +} + +static hal_ll_err_t hal_ll_can_bit_timing( hal_ll_can_hw_specifics_map_t *map ) { + hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct(map->base); + uint16_t prescaler = 0, tseg1 = 0, tseg2 = 0, temp = 0; + float time_quanta = 0.0, bit_time = 0.0, num_of_tq = 0.0; + uint32_t baud_rate = 0, can_clock = 0; + uint8_t sjw = 0; + + baud_rate = map->frequency; + + can_clock = Get_Fosc_kHz() * 1000; // CAN clock in Hz + + /* + * Description: This code snippet calculates the optimal settings for configuring + * the CAN bus baud rate on Tiva microcontrollers, based on the provided parameters. + * + * Initial parameters: + * - can_clock: CAN source clock frequency in Hz. + * - baud_rate: Desired CAN bus baud rate. + * + * Calculated parameters: + * - prescaler: The prescaler value to achieve the desired baud rate. + * - tseg1, tseg2: Time segment values for configuring the CAN bus. + * + * Formulas used: + * - time_quanta = 1 / can_clock + * - bit_time = 1 / baud_rate + * - num_of_tq = bit_time / time_quanta (number of time quanta) + * - (sjw + tseg1) / (sjw + tseg1 + tseg2) = 87.5% (optimal sampling for CAN) + * - baud_rate = can_clock / (prescaler * (tseg1 + tseg2 + 1)) (from Tiva Reference manuals) + * + * Note: sjw (synchronization jump width) is fixed to 1, the preferred value, but can range from 1 to 4. + */ + + sjw = HAL_LL_CAN_SJW_CONST_VALUE; + + bit_time = (float) 1 / baud_rate; + + set_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_CCE_BIT ); + for( prescaler = 1; prescaler <= HAL_LL_CAN_PRESCALER_MAX_VAL; prescaler++ ) { + time_quanta = (float) prescaler / can_clock; + num_of_tq = (float)bit_time / (float)time_quanta; + tseg1 = HAL_LL_CAN_BIT_RATE_SAMPLE_POINT * num_of_tq - sjw; + tseg2 = num_of_tq - tseg1 - sjw; + + // Time segment 1 can be anywhere between 1 and 16, while the value of time segment 2 goes from 1 to 8. + if( ( HAL_LL_CAN_TSEG1_MAX_VAL < tseg1 ) || ( HAL_LL_CAN_TSEG2_MAX_VAL < tseg2 ) || !tseg1 || !tseg2 ) continue; + + temp = prescaler * ( tseg1 + tseg2 + 1 ); + uint32_t actual_baud_rate = can_clock / temp; + + if( actual_baud_rate == baud_rate ) { + // Exact match found + uint32_t sjw_val = ((uint32_t)(sjw - 1)) << HAL_LL_CAN_CANBIT_SJW_SHIFT; + uint32_t tseg1_val = ((uint32_t)(tseg1 - 1)) << HAL_LL_CAN_CANBIT_TSEG1_SHIFT; + uint32_t tseg2_val = ((uint32_t)(tseg2 - 1)) << HAL_LL_CAN_CANBIT_TSEG2_SHIFT; + uint32_t prescaler_val_low = HAL_LL_CAN_PRESCALER_BITS_5_0 & (prescaler - 1); + uint32_t prescaler_val_high = (HAL_LL_CAN_PRESCALER_BITS_10_6 & (prescaler - 1)) >> HAL_LL_CAN_CANBRPE_PRESCALER_SHIFT; + hal_ll_hw_reg->canbit = sjw_val | tseg1_val | tseg2_val | prescaler_val_low; + hal_ll_hw_reg->canbrpe = prescaler_val_high; + clear_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_CCE_BIT ); + + return HAL_LL_CAN_SUCCESS; + } + + /* + * Note: Setting parameters that result in a baud rate that differs from the desired value is not acceptable. + * If two devices communicate over CAN, their baud rates need to be exactly the same. + */ + } + + // If this point was reached, baud rate wasn't set to the desired value and error is returned. + clear_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_CCE_BIT ); + + return HAL_LL_CAN_ERROR; +} + +static hal_ll_err_t hal_ll_can_module_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config ) { + hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct(map->base); + uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + // Start SW initialization. + set_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_INIT_BIT ); + + // Wait for BUSY bit to clear. + while( check_reg_bit( &hal_ll_hw_reg->can_if1.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) + if( !timeout-- ) + return HAL_LL_CAN_ERROR; + + hal_ll_hw_reg->can_if1.cmsk = HAL_LL_CAN_IF_CMSK_WRNRD_MASK | HAL_LL_CAN_IF_CMSK_ARB_MASK | HAL_LL_CAN_IF_CMSK_CONTROL_MASK; + + hal_ll_hw_reg->can_if1.arb1 = HAL_LL_CAN_REG_CLEAR; + hal_ll_hw_reg->can_if1.arb2 = HAL_LL_CAN_REG_CLEAR; + hal_ll_hw_reg->can_if1.mctl = HAL_LL_CAN_REG_CLEAR; + + timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + // Loop through to program all 32 message objects. + for( uint8_t i = 1; i <= HAL_LL_CAN_MAX_MNUM; i++ ) { + hal_ll_hw_reg->can_if1.crq = i; + // Wait for BUSY bit to clear. + while( check_reg_bit( &hal_ll_hw_reg->can_if1.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) + if( !timeout-- ) + return HAL_LL_CAN_ERROR; + } + + hal_ll_hw_reg->can_if1.cmsk = HAL_LL_CAN_IF_CMSK_CLRINTPND_MASK | HAL_LL_CAN_IF_CMSK_NEWDAT_MASK; + + timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + // Loop through to program all 32 message objects. + for( uint8_t i = 1; i < HAL_LL_CAN_MAX_MNUM; i++ ) { + hal_ll_hw_reg->can_if1.crq = i; + // Wait for BUSY bit to clear. + while( check_reg_bit( &hal_ll_hw_reg->can_if1.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) + if( !timeout-- ) + return HAL_LL_CAN_ERROR; + } + + // Read CANSTS register to clear message interrupts. + (void)hal_ll_hw_reg->cansts; + + if( HAL_LL_CAN_ERROR == hal_ll_can_bit_timing( map )) + return HAL_LL_CAN_ERROR; + + // Disable auto retransmission. + set_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_DAR_BIT ); + + // Start SW initialization. + set_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_INIT_BIT ); + + return HAL_LL_CAN_SUCCESS; +} + +static hal_ll_err_t hal_ll_can_filter_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_filter_config_t *filter_config ) { + hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct(map->base); + uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + // Mask configuration. + hal_ll_hw_reg->can_if2.cmsk |= HAL_LL_CAN_IF_CMSK_ARB_MASK | HAL_LL_CAN_IF_CMSK_CONTROL_MASK | + HAL_LL_CAN_IF_CMSK_MASK_MASK | HAL_LL_CAN_IF_CMSK_DATAA_MASK | HAL_LL_CAN_IF_CMSK_DATAB_MASK; + + hal_ll_hw_reg->can_if2.crq = filter_config->can_filter_fifo; + + // Wait for BUSY bit to clear. + while( check_reg_bit( &hal_ll_hw_reg->can_if2.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) + if( !timeout-- ) + return HAL_LL_CAN_ERROR; + + hal_ll_hw_reg->can_if1.cmsk |= HAL_LL_CAN_IF_CMSK_WRNRD_MASK | HAL_LL_CAN_IF_CMSK_CONTROL_MASK | HAL_LL_CAN_IF_CMSK_MASK_MASK; + + hal_ll_hw_reg->can_if1.msk1 = HAL_LL_CAN_REG_CLEAR; + + if ( filter_config->can_filter_id & HAL_LL_CAN_EID_BITS_28_11 ) { + // Extended filter mask ID + hal_ll_hw_reg->can_if1.msk1 = filter_config->can_filter_mask_id_low; + hal_ll_hw_reg->can_if1.msk2 = filter_config->can_filter_mask_id_high; + } else { + // Standard filter mask ID + hal_ll_hw_reg->can_if1.msk2 = ( filter_config->can_filter_mask_id_low & HAL_LL_CAN_SID_MASK ) << HAL_LL_CAN_IF_MSK2_ID_SHIFT; + } + + // Use acceptance mask + set_reg_bit( &hal_ll_hw_reg->can_if1.mctl, HAL_LL_CAN_IF_MCTL_UMASK_BIT ); + // End of mask configuration. + + // Filter configuration. + hal_ll_hw_reg->can_if2.cmsk |= HAL_LL_CAN_IF_CMSK_MASK_MASK | HAL_LL_CAN_IF_CMSK_CONTROL_MASK | + HAL_LL_CAN_IF_CMSK_ARB_MASK | HAL_LL_CAN_IF_CMSK_DATAA_MASK | + HAL_LL_CAN_IF_CMSK_DATAB_MASK; + + hal_ll_hw_reg->can_if2.crq = filter_config->can_filter_fifo; + + timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + // Wait for BUSY bit to clear. + while( check_reg_bit( &hal_ll_hw_reg->can_if2.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) + if( !timeout-- ) + return HAL_LL_CAN_ERROR; + + hal_ll_hw_reg->can_if1.cmsk = HAL_LL_CAN_IF_CMSK_WRNRD_MASK | HAL_LL_CAN_IF_CMSK_ARB_MASK; + + if ( filter_config->can_filter_id & HAL_LL_CAN_EID_BITS_28_11 ) { + // Extended filter ID + hal_ll_hw_reg->can_if1.arb1 |= filter_config->can_filter_id_low; + hal_ll_hw_reg->can_if1.arb2 |= filter_config->can_filter_id_high; + } else { + // Standard filter ID + hal_ll_hw_reg->can_if1.arb2 |= ( filter_config->can_filter_id_low & HAL_LL_CAN_SID_MASK ) << HAL_LL_CAN_IF_ARB2_ID_SHIFT; + } + + set_reg_bit( &hal_ll_hw_reg->can_if1.arb2, HAL_LL_CAN_IF_ARB2_MSGVAL_BIT ); + + hal_ll_hw_reg->can_if1.crq = filter_config->can_filter_fifo; + // End of filter configuration. + + return HAL_LL_CAN_SUCCESS; +} + +static hal_ll_err_t message_config( hal_ll_base_addr_t *base, uint8_t message_object_num, uint32_t identifier ) { + hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct(base); + volatile hal_ll_can_if *can_interface; + uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + // One interface is used to transmit and the other to receive data. + if ( HAL_LL_CAN_TRANSMIT_MESSAGE_ID == message_object_num ) { + can_interface = &hal_ll_hw_reg->can_if1; + } else { + can_interface = &hal_ll_hw_reg->can_if2; + } + + // Wait for BUSY bit to clear. + while( check_reg_bit( &can_interface->crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) + if( !timeout-- ) + return HAL_LL_CAN_ERROR; + + can_interface->cmsk |= HAL_LL_CAN_IF_CMSK_WRNRD_MASK | HAL_LL_CAN_IF_CMSK_CONTROL_MASK | HAL_LL_CAN_IF_CMSK_ARB_MASK; + + can_interface->crq = message_object_num; + + timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + // Wait for BUSY bit to clear. + while( check_reg_bit( &can_interface->crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) + if( !timeout-- ) + return HAL_LL_CAN_ERROR; + + if( HAL_LL_CAN_EID_BITS_28_11 & identifier ) + // Extended ID + set_reg_bit( &can_interface->arb2, HAL_LL_CAN_IF_ARB2_XTD_BIT ); + else + // Standard ID + clear_reg_bit( &can_interface->arb2, HAL_LL_CAN_IF_ARB2_XTD_BIT ); + + set_reg_bit( &can_interface->arb2, HAL_LL_CAN_IF_ARB2_MSGVAL_BIT ); + + if( HAL_LL_CAN_TRANSMIT_MESSAGE_ID == message_object_num ) { + // Transmit message object + set_reg_bit( &can_interface->arb2, HAL_LL_CAN_IF_ARB2_DIR_BIT ); // Set direction to Transmit + } else { + // Receive message object + clear_reg_bit( &can_interface->arb2, HAL_LL_CAN_IF_ARB2_DIR_BIT ); // Set direction to Receive + } + + can_interface->crq = message_object_num; + + return HAL_LL_CAN_SUCCESS; +} + +static hal_ll_err_t hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ) { + hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct(map->base); + hal_ll_err_t result = HAL_LL_CAN_SUCCESS; + + // Enable clock for CAN. + hal_ll_can_clock_enable( map->module_index, true ); + /* + * According to the Datasheet: + * "There must be a delay of 3 system clocks after the CAN module clock is enabled before + * any CAN module registers are accessed." + */ + assembly( nop ); + assembly( nop ); + assembly( nop ); + + if( HAL_LL_CAN_ERROR == hal_ll_can_module_init( map, config )) + return HAL_LL_CAN_ERROR; + + // Configure receive message object + if( HAL_LL_CAN_ERROR == message_config( (hal_ll_base_addr_t *)map->base, filter_config->can_filter_fifo, filter_config->can_filter_id )) + return HAL_LL_CAN_ERROR; + + if( HAL_LL_CAN_ERROR == hal_ll_can_filter_init( map, filter_config )) + return HAL_LL_CAN_ERROR; + + if( HAL_LL_CAN_MODE_LOOPBACK == config->mode ) { + set_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_TEST_BIT ); + set_reg_bit( &hal_ll_hw_reg->cantst, HAL_LL_CAN_CANTST_LBACK_BIT ); + } + + // Leave SW initialization. + clear_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_INIT_BIT ); + + return result; +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/dma/CMakeLists.txt b/targets/arm/mikroe/renesas/src/dma/CMakeLists.txt new file mode 100644 index 0000000000..204996e47f --- /dev/null +++ b/targets/arm/mikroe/renesas/src/dma/CMakeLists.txt @@ -0,0 +1,56 @@ +## ./targets/arm/mikroe/tiva/src/dma/CMakeLists.txt +set(hal_ll_def_list "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +## BEGIN DMA +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() +## END DMA +list(APPEND hal_ll_def_list "MACRO_USAGE_DMA") + +mikrosdk_add_library(lib_hal_ll_dma MikroSDK.HalLowLevel.DMA + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN DMA + ../../include/dma/hal_ll_dma.h + implementation_1/hal_ll_dma.c + # END DMA +) + +target_compile_definitions(lib_hal_ll_dma PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_dma PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) + +target_include_directories(lib_hal_ll_dma + PRIVATE + ../../include + # BEGIN DMA + ../../include/dma + # END DMA + + INTERFACE + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.DMA) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.DMA ../../include/dma/hal_ll_dma.h) diff --git a/targets/arm/mikroe/renesas/src/dma/implementation_1/hal_ll_dma.c b/targets/arm/mikroe/renesas/src/dma/implementation_1/hal_ll_dma.c new file mode 100644 index 0000000000..e839651832 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/dma/implementation_1/hal_ll_dma.c @@ -0,0 +1,759 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief To ensure that the whole DMA channel control structure can fit into buffer after 1024 byte aligned address, the buffer must to be expanded by 1023 bytes. */ +#define HAL_LL_DMA_BASE_ADDR (0x400FF000UL) +#define HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK (0x3FFUL) + +// RCGCDMA register definitions. +#define HAL_LL_DMA_SYSCTL_RCGCDMA (*((volatile uint32_t *)0x400FE60C)) +#define HAL_LL_DMA_SYSCTL_RCGCDMA_CLOCK_DMA (0x1UL) + +// PRDMA register definitions. +#define HAL_LL_DMA_SYSCTL_PRDMA (*((volatile uint32_t *)0x400FEA0C)) +#define HAL_LL_DMA_SYSCTL_PRDMA_DMA_READY (0x1UL) + +// FLASHDMAPP register definitions. +#define HAL_LL_DMA_FLASHPP (*((volatile uint32_t *)0x400FDFC0)) +#define HAL_LL_DMA_FLASHPP_SIZE_POSITION ((uint8_t)0) +#define HAL_LL_DMA_FLASHPP_SIZE_MASK (0xFFFFUL << HAL_LL_DMA_FLASHPP_SIZE_POSITION) +#define HAL_LL_DMA_FLASHPP_DFA_POSITION ((uint8_t)28) +#define HAL_LL_DMA_FLASHPP_DFA_MASK (0x1UL << HAL_LL_DMA_FLASHPP_DFA_POSITION) +#define HAL_LL_DMA_FLASHPP_DFA HAL_LL_DMA_FLASHPP_DFA_MASK + +// FLASHDMASZ register definitions. +#define HAL_LL_DMA_FLASHDMASZ (*((volatile uint32_t *)0x400FDFD0)) +#define HAL_LL_DMA_FLASHDMASZ_SIZE_POSITION ((uint8_t)0) +#define HAL_LL_DMA_FLASHDMASZ_SIZE_MASK (0x3FFFFUL << HAL_LL_DMA_FLASHDMASZ_SIZE_POSITION) + +// FLASHDMAST register definitions. +#define HAL_LL_DMA_FLASHDMAST (*((volatile uint32_t *)0x400FDFD4)) +#define HAL_LL_DMA_FLASHDMAST_ADDR_POSITION ((uint8_t)11) +#define HAL_LL_DMA_FLASHDMAST_ADDR_MASK (0x3FFFFUL << HAL_LL_DMA_FLASHDMAST_ADDR_POSITION) + +// DMASTAT register definitions. +#define HAL_LL_DMA_DMASTAT_MASTEN (0x1UL) +// DMACFG register definitions. +#define HAL_LL_DMA_DMACFG_MASTEN (0x1UL) +// DMASWREQ register definitions. +#define HAL_LL_DMA_SWREQ (0x1UL) +// DMAUSEBURSTCLR register definitions. +#define HAL_LL_DMA_USEBURSTCLR (0x1UL) +// DMAREQMASKCLR register definitions. +#define HAL_LL_DMA_REQMASKCLR (0x1UL) +// DMAENSET register definitions. +#define HAL_LL_DMA_ENASET (0x1UL) +// DMAENCLR register definitions. +#define HAL_LL_DMA_ENACLR (0x1UL) +// Mask used to check if the DMA stream is in use. +#define HAL_LL_DMA_STREAM_ENABLED_MASK (0xFFFFFFFFUL) +// DMAALTCLR register definitions. +#define HAL_LL_DMA_ALTCLR (0x1UL) +// DMAPRIOSET register definitions. +#define HAL_LL_DMA_PRIOSET (0x1UL) +// DMAPRIOCLR register definitions. +#define HAL_LL_DMA_PRIOCLR (0x1UL) + +// DMA Channel Control Word (DMACHTL) definitions. +#define HAL_LL_DMA_DMACHCTL_XFERMODE_MASK (0x7UL) +#define HAL_LL_DMA_DMACHCTL_XFERMODE_STOP (0x0UL) +#define HAL_LL_DMA_DMACHCTL_XFERMODE_BASIC (0x1UL) +#define HAL_LL_DMA_DMACHCTL_XFERMODE_AUTO_REQUEST (0x2UL) +#define HAL_LL_DMA_DMACHCTL_XFERMODE_PING_PONG (0x3UL) +#define HAL_LL_DMA_DMACHCTL_XFERMODE_MEM_SCATTER_GATHER (0x4UL) +#define HAL_LL_DMA_DMACHCTL_XFERMODE_ALT_MEM_SCATTER_GATHER (0x5UL) +#define HAL_LL_DMA_DMACHCTL_XFERMODE_PERIPH_SCATTER_GATHER (0x6UL) +#define HAL_LL_DMA_DMACHCTL_XFERMODE_ALT_PERIPH_SCATTER_GATHER (0x7UL) +#define HAL_LL_DMA_DMACHTL_NXTUSEBURST_POSITION ((uint8_t)3) +#define HAL_LL_DMA_DMACHTL_NXTUSEBURST_MASK (0x1UL << HAL_LL_DMA_DMACHTL_NXTUSEBURST_POSITION) +#define HAL_LL_DMA_DMACHTL_NXTUSEBURST HAL_LL_DMA_DMACHTL_NXTUSEBURST_MASK +#define HAL_LL_DMA_DMACHTL_XFERSIZE_POSITION ((uint8_t)4) +#define HAL_LL_DMA_DMACHTL_XFERSIZE_MASK (0x3FFUL << HAL_LL_DMA_DMACHTL_XFERSIZE_POSITION) +#define HAL_LL_DMA_DMACHTL_ARBSIZE_POSITION ((uint8_t)14) +#define HAL_LL_DMA_DMACHTL_ARBSIZE_MASK (0xFUL << HAL_LL_DMA_DMACHTL_ARBSIZE_POSITION) +#define HAL_LL_DMA_DMACHTL_SRCSIZE_POSITION ((uint8_t)24) +#define HAL_LL_DMA_DMACHTL_SRCSIZE_MASK (0x3UL << HAL_LL_DMA_DMACHTL_SRCSIZE_POSITION) +#define HAL_LL_DMA_DMACHTL_SRCSIZE_BYTE (0x0UL) +#define HAL_LL_DMA_DMACHTL_SRCSIZE_HALF_WORD (0x1UL << HAL_LL_DMA_DMACHTL_SRCSIZE_POSITION) +#define HAL_LL_DMA_DMACHTL_SRCSIZE_WORD (0x2UL << HAL_LL_DMA_DMACHTL_SRCSIZE_POSITION) +#define HAL_LL_DMA_DMACHTL_SRCINC_POSITION ((uint8_t)26) +#define HAL_LL_DMA_DMACHTL_SRCINC_MASK (0x3UL << HAL_LL_DMA_DMACHTL_SRCINC_POSITION) +#define HAL_LL_DMA_DMACHTL_SRCINC_BYTE (0x0UL) +#define HAL_LL_DMA_DMACHTL_SRCINC_HALF_WORD (0x1UL << HAL_LL_DMA_DMACHTL_SRCINC_POSITION) +#define HAL_LL_DMA_DMACHTL_SRCINC_WORD (0x2UL << HAL_LL_DMA_DMACHTL_SRCINC_POSITION) +#define HAL_LL_DMA_DMACHTL_SRCINC_NO_INCREMENT (0x3UL << HAL_LL_DMA_DMACHTL_SRCINC_POSITION) +#define HAL_LL_DMA_DMACHTL_DSTSIZE_POSITION ((uint8_t)28) +#define HAL_LL_DMA_DMACHTL_DSTSIZE_MASK (0x3UL << HAL_LL_DMA_DMACHTL_DSTSIZE_POSITION) +#define HAL_LL_DMA_DMACHTL_DSTSIZE_BYTE (0x0UL) +#define HAL_LL_DMA_DMACHTL_DSTSIZE_HALF_WORD (0x1UL << HAL_LL_DMA_DMACHTL_DSTSIZE_POSITION) +#define HAL_LL_DMA_DMACHTL_DSTSIZE_WORD (0x2UL << HAL_LL_DMA_DMACHTL_DSTSIZE_POSITION) +#define HAL_LL_DMA_DMACHTL_DSTINC_POSITION ((uint8_t)30) +#define HAL_LL_DMA_DMACHTL_DSTINC_MASK (0x3UL << HAL_LL_DMA_DMACHTL_DSTINC_POSITION) +#define HAL_LL_DMA_DMACHTL_DSTINC_BYTE (0x0UL) +#define HAL_LL_DMA_DMACHTL_DSTINC_HALF_WORD (0x1UL << HAL_LL_DMA_DMACHTL_DSTINC_POSITION) +#define HAL_LL_DMA_DMACHTL_DSTINC_WORD (0x2UL << HAL_LL_DMA_DMACHTL_DSTINC_POSITION) +#define HAL_LL_DMA_DMACHTL_DSTINC_NO_INCREMENT (0x3UL << HAL_LL_DMA_DMACHTL_DSTINC_POSITION) + +/*!< Read Only access. */ +#ifdef __GNUC__ + #define _HAL_LL_DMA_RO volatile const +#else + #define _HAL_LL_DMA_RO volatile +#endif +/*!< Read and Write access. */ +#define _HAL_LL_DMA_RW volatile +/*!< Write Only access. */ +#define _HAL_LL_DMA_WO volatile + +/*!< @brief Macro use to determine if the DMA has access to flash memory */ +#define HAL_LL_DMA_HAS_FLASH_ACCESS (HAL_LL_DMA_FLASHPP & HAL_LL_DMA_FLASHPP_DFA) +/*!< @brief Macro use to determine the size of the flash memory */ +#define HAL_LL_DMA_FLASH_SIZE ((HAL_LL_DMA_FLASHPP & HAL_LL_DMA_FLASHPP_SIZE_MASK) >> HAL_LL_DMA_FLASHPP_SIZE_POSITION) +/*!< @brief Macro use to validate appropriate DMA access to transfer buffers located in flash memory */ +#define HAL_LL_DMA_FLASH_ACCESS_OK HAL_LL_DMA_SUCCESS + +/*!< @brief Clock enable macro. */ +#define _HAL_LL_ENABLE_CLOCK_SYS_ (HAL_LL_DMA_SYSCTL_RCGCDMA |= HAL_LL_DMA_SYSCTL_RCGCDMA_CLOCK_DMA) +/*!< @brief Clock disable macro. */ +#define _HAL_LL_DISABLE_CLOCK_SYS_ (HAL_LL_DMA_SYSCTL_RCGCDMA &= !HAL_LL_DMA_SYSCTL_RCGCDMA_CLOCK_DMA) + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE (dma->cfg |= HAL_LL_DMA_DMACFG_MASTEN) +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE (dma->cfg &= ~HAL_LL_DMA_DMACFG_MASTEN) +/*!< @brief DMA module usage status macro. */ +#define HAL_LL_DMA_MODULE_UNUSED (0x0UL) + +/*!< @brief DMA stream enable macro. */ +#define HAL_LL_DMA_STREAM_ENABLE(_stream) (dma->ena_set |= HAL_LL_DMA_ENASET << _stream) +/*!< @brief DMA stream disable macro. */ +#define HAL_LL_DMA_STREAM_DISABLE(_stream) (dma->ena_clr |= HAL_LL_DMA_ENASET << _stream) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW channel control structure. */ +typedef struct dma_ch_ctl_struct +{ + _HAL_LL_DMA_RW uint32_t src_endp; /*!< DMA channel source address end pointer. */ + _HAL_LL_DMA_RW uint32_t dst_endp; /*!< DMA channel destination address end pointer. */ + _HAL_LL_DMA_RW uint32_t ch_ctl; /*!< DMA channel control word. */ + uint32_t __unused1; +} dma_ch_ctl_struct_t; + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + _HAL_LL_DMA_RO uint32_t stat; /*!< DMA status register. */ + _HAL_LL_DMA_WO uint32_t cfg; /*!< DMA configuration register. */ + _HAL_LL_DMA_RW uint32_t ctl_base; /*!< DMA channel control base pointer. */ + _HAL_LL_DMA_RO uint32_t alt_base; /*!< DMA alternate channel control base pointer. */ + _HAL_LL_DMA_RO uint32_t wait_stat; /*!< DMA channel wait-on request status register. */ + _HAL_LL_DMA_WO uint32_t sw_req; /*!< DMA channel software request register. */ + _HAL_LL_DMA_RW uint32_t use_burst_set; /*!< DMA channel useburst set register. */ + _HAL_LL_DMA_WO uint32_t use_burst_clr; /*!< DMA channel useburst clear register. */ + _HAL_LL_DMA_RW uint32_t req_mask_set; /*!< DMA channel request mask set register. */ + _HAL_LL_DMA_WO uint32_t req_mask_clr; /*!< DMA channel request mask clear register. */ + _HAL_LL_DMA_RW uint32_t ena_set; /*!< DMA channel enable set register. */ + _HAL_LL_DMA_WO uint32_t ena_clr; /*!< DMA channel enable clear register. */ + _HAL_LL_DMA_RW uint32_t alt_set; /*!< DMA channel primary alternate set register. */ + _HAL_LL_DMA_WO uint32_t alt_clr; /*!< DMA channel primary alternate clear register */ + _HAL_LL_DMA_RW uint32_t prio_set; /*!< DMA channel priority set register */ + _HAL_LL_DMA_WO uint32_t prio_clr; /*!< DMA channel priority clear register */ + uint32_t unused1[3]; + _HAL_LL_DMA_RW uint32_t err_clr; /*!< DMA bus error clear register */ + uint32_t unused2[300]; + _HAL_LL_DMA_RW uint32_t ch_asgn; /*!< DMA channel assignment register */ + uint32_t unused3[3]; + _HAL_LL_DMA_RW uint32_t ch_map[4]; /*!< DMA channel map select registers */ +} dma_handle_t; + +// ------------------------------------------------------------------ VARIABLES + +/* Note: The channel control structure buffer is created with overhead of 1023 bytes to ensure that + * there is one address aligned/divisible with 1024 inside the buffer, and there are enough + * enough bytes needed for channel control structure (sizeof(dma_ch_ctl_struct_t) * DMA_NUM_OF_STREAMS), + * after this address. + */ + /*!< @brief DMA HW channel control structure extended buffer */ +static dma_ch_ctl_struct_t dma_ch_ctl_buffer[ ( ( ( sizeof( dma_ch_ctl_struct_t ) * DMA_NUM_OF_STREAMS ) << 1 ) + + HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ) + / sizeof( dma_ch_ctl_struct_t ) ]; +/*!< @brief Pointer to 1024 byte aligned address inside dma_ch_ctl_buffer where actual channel control data will be stored */ +static dma_ch_ctl_struct_t * dma_ch_ctl; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream and channel to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Sets DMA channel. + * @details Sets appropriate value HW register for the desired @ref channel. + * @param[in] dma DMA HW handle. + * @param[in] stream DMA Stream number. + * @param[in] channel DMA Channel number. + * @return Nothing. + */ +static inline void hal_ll_dma_set_channel( dma_handle_t *dma, uint8_t stream, uint8_t channel ); + +/** + * @brief Configures DMA access to FLASH memory. + * @details If DMA has access to the flash memory, the function + * will configure the region in flash memory, + * where DMA read access is allowed, by setting the starting address and size + * starting from that address where reading is allowed. + * @return Nothing. + */ +static void hal_ll_dma_configure_flash_access(); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint8_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA stream peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint32_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc, hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA stream memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint32_t hal_ll_dma_get_reg_value_src_inc( bool set_inc, hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA stream memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint32_t hal_ll_dma_get_reg_value_src_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA stream peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint32_t hal_ll_dma_get_reg_value_dst_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Sets DMA stream priority value. + * @details Sets the appropriate value in HW register + * for desired @ref priority. + * @param[in] dma DMA HW handle. + * @param[in] stream DMA Stream number. + * @param[in] priority DMA priority for object stream. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return Nothing. + */ +static inline void hal_ll_dma_set_stream_priority( dma_handle_t *dma, uint8_t stream, hal_ll_dma_priority_t priority ); + +/** + * @brief Gets DMA burst size value. + * @details Returns appropriate value to be set in HW register + * for desired @ref burst_size. + * @param[in] burst_size DMA burst size for channel. + * Refer to @ref hal_ll_dma_burst_size_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref burst_size. + */ +static inline uint32_t hal_ll_dma_get_reg_value_burst_size( hal_ll_dma_burst_size_t burst_size ); + +/** + * @brief Validates DMA flash memory access. + * @details For transfer buffers stored in flash memory, + * validates that the DMA has access to flash memory. + * @param[in] addr_src DMA source buffer address. + * @param[in] addr_dst DMA destination buffer address. + * @return hal_ll_err_t Returns DMA flash memory access status + * for transfer buffers stored in flash memory. + */ +static hal_ll_dma_err_t hal_ll_dma_check_flash_access( uint32_t addr_src, uint32_t addr_dst ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable SYSCLK. + _HAL_LL_ENABLE_CLOCK_SYS_; + + // Wait until the DMA module is ready for access. + while ( !( HAL_LL_DMA_SYSCTL_PRDMA & HAL_LL_DMA_SYSCTL_PRDMA_DMA_READY) ); + + obj->handle = HAL_LL_DMA_BASE_ADDR; + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + dma_handle_t * dma = (dma_handle_t *)obj->handle; + // Disable module and module clock, only if all streams are disabled and inactive. + if ( HAL_LL_DMA_MODULE_UNUSED == ( dma->ena_set & HAL_LL_DMA_STREAM_ENABLED_MASK ) ) { + HAL_LL_DMA_MODULE_DISABLE; + _HAL_LL_DISABLE_CLOCK_SYS_; + } + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = ( dma_handle_t * )obj->handle; + // Set pointer to 1024 byte aligned address inside dma_ch_ctl_buffer, where actual channel control structure data will be located. + dma_ch_ctl = (dma_ch_ctl_struct_t *)( ( (uint32_t)dma_ch_ctl_buffer + HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ) & ~HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ); + uint8_t transfer_size_shift_divisor = 2; // default value for HAL_LL_DMA_DATA_ALIGN_BYTES_4 + uint8_t stream = obj->config.stream; + uint16_t endpoint_offset; + + // Memory type parameter is unused. + (void)src_mem_type; + + // Configure DMA Stream data length. + if ( HAL_LL_DMA_DATA_ALIGN_BYTES_4 != obj->config.data_align_destination ) { + transfer_size_shift_divisor = obj->config.data_align_destination; + } + + // If DMA transfer buffers are stored in flash memory, validate DMA access to the. + if (HAL_LL_DMA_FLASH_ACCESS_OK != hal_ll_dma_check_flash_access( addr_src, addr_dst ) ) { + // DMA does not have appropriate access to flash memory. + return HAL_LL_DMA_ERROR; + } else { // Proceed with the DMA channel configuration. + // Calculate the address offset of the last buffer item. + endpoint_offset = transfer_size - ( 1 << transfer_size_shift_divisor ); + // Calculate the source data buffer inclusive endpoint. + addr_src += obj->config.src_inc ? endpoint_offset : 0; + // Calculate the destination data buffer inclusive endpoint. + addr_dst += obj->config.dst_inc ? endpoint_offset : 0; + // Recalculate the transfer size. + transfer_size >>= transfer_size_shift_divisor; + --transfer_size; + + // Write calculated endpoint addresses and transfer size into channel control structure. + dma_ch_ctl[ stream ].ch_ctl |= (uint32_t)transfer_size << HAL_LL_DMA_DMACHTL_XFERSIZE_POSITION; + dma_ch_ctl[ stream ].dst_endp |= addr_dst; + dma_ch_ctl[ stream ].src_endp |= addr_src; + } + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + // Set pointer to 1024 byte aligned address inside dma_ch_ctl_buffer, where actual channel control structure data will be located. + dma_ch_ctl = (dma_ch_ctl_struct_t *)( ( (uint32_t)dma_ch_ctl_buffer + HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ) & ~HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ); + uint8_t stream = obj->config.stream; + + // Enable the DMA stream. + HAL_LL_DMA_STREAM_ENABLE( stream ); + // Transfer will start immediately after the channel periphery sends the request. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY == obj->config.direction ) { + // in case of the M2M direction start transfer using software request. + dma->sw_req = HAL_LL_DMA_SWREQ << stream; + } + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + // Set pointer to 1024 byte aligned address inside dma_ch_ctl_buffer, where actual channel control structure data will be located. + dma_ch_ctl = (dma_ch_ctl_struct_t *)( ( (uint32_t)dma_ch_ctl_buffer + HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ) & ~HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ); + + // Wait until transfer completes. + while ( dma_ch_ctl->ch_ctl & HAL_LL_DMA_DMACHCTL_XFERMODE_STOP ) { + if (0 == timeout--) { + // TODO consider forcing the stream to disable here. + return HAL_LL_DMA_ERROR; + } + } + // When transfer completes the DMA stream disables itself. + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + // Set pointer to 1024 byte aligned address inside dma_ch_ctl_buffer, where actual channel control structure data will be located. + dma_ch_ctl = (dma_ch_ctl_struct_t *)( ( (uint32_t)dma_ch_ctl_buffer + HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ) & ~HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ); + + // Disable the stream. + // Disabling the stream, just pauses it. + HAL_LL_DMA_STREAM_DISABLE( obj->config.stream ); + // Stop transfer. + dma_ch_ctl->ch_ctl &= HAL_LL_DMA_DMACHCTL_XFERMODE_STOP; + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + // Set pointer to 1024 byte aligned address inside dma_ch_ctl_buffer, where actual channel control structure data will be located. + dma_ch_ctl = (dma_ch_ctl_struct_t *)( ( (uint32_t)dma_ch_ctl_buffer + HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ) & ~HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ); + uint8_t stream = config.stream; + + // Allow the DMA read access to the whole flash memory. + hal_ll_dma_configure_flash_access(); + + // Enable the DMA module. + HAL_LL_DMA_MODULE_ENABLE; + + // Disable the DMA stream first. + HAL_LL_DMA_STREAM_DISABLE( stream ); + + // Set channel control structure address. + dma->ctl_base = (uint32_t)dma_ch_ctl; + // Configure DMA to use the primary channel control structure. + dma->alt_clr = HAL_LL_DMA_ALTCLR << stream; + // Allow both single and burst requests. + dma->use_burst_clr = HAL_LL_DMA_USEBURSTCLR << stream; + // Allow channel to send requests. + dma->req_mask_clr = HAL_LL_DMA_REQMASKCLR << stream; + // Set the desired channel. + hal_ll_dma_set_channel( dma, stream, config.channel ); + // Set the desired priority. + hal_ll_dma_set_stream_priority( dma, stream, config.priority ); + + // Stream configuration. + // Clear source endpoint address. + dma_ch_ctl[ stream ].src_endp = 0; + // Clear destination endpoint address. + dma_ch_ctl[ stream ].dst_endp = 0; + // Clear the stream control word. + dma_ch_ctl[ stream ].ch_ctl = 0; + + // Set desired direction value. + dma_ch_ctl[ stream ].ch_ctl |= hal_ll_dma_get_reg_value_direction( config.direction ); + // Set desired memory increment settings. + dma_ch_ctl[ stream ].ch_ctl |= hal_ll_dma_get_reg_value_src_inc( config.src_inc, config.data_align_source ); + dma_ch_ctl[ stream ].ch_ctl |= hal_ll_dma_get_reg_value_dst_inc( config.dst_inc, config.data_align_source ); + + // Set desired data size settings. + if ( config.data_align_source != config.data_align_destination ) { + // Source and Destination Data sizes must be equal. + return HAL_LL_DMA_ERROR; + } + if ( ( HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source ) || ( HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) ) { + // Source and Destination Data sizes cannot be 3 bytes. + return HAL_LL_DMA_ERROR; + } + dma_ch_ctl[ stream ].ch_ctl |= hal_ll_dma_get_reg_value_src_size( config.data_align_source ); + dma_ch_ctl[ stream ].ch_ctl |= hal_ll_dma_get_reg_value_dst_size( config.data_align_source ); + + // Set desired burst transfer settings. + if ( config.burst_size_source != config.burst_size_destination ) { + // No multiple burst on TIVA. + return HAL_LL_DMA_ERROR; + } + // TODO On TIVA burst size can go up to 1024. Consider adding more enums to cover all of them. + dma_ch_ctl[ stream ].ch_ctl |= hal_ll_dma_get_reg_value_burst_size( config.burst_size_source ); + + // Set desired mode. + if ( HAL_LL_DMA_MODE_CIRCULAR == config.mode ) { + // TODO Implement circular mode later, during DMA peripheral synthesis. + /* NOTE: Channel control structure register do not posses the auto-reloading functionality, + * therefore they must be reloaded by software in interrupt routine. + * The DMA ISR is not used for this, instead the ISR form the peripheral that is using the DMA is used. + */ + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline void hal_ll_dma_set_channel( dma_handle_t *dma, uint8_t stream, uint8_t channel ) { + dma->ch_map[ (uint8_t)( stream >> 3 ) ] |= (uint32_t)( channel << (uint8_t)( ( stream & 0x7 ) << 2 ) ) ; +} + +static void hal_ll_dma_configure_flash_access() { + // If DMA has access to flash memory. + if ( HAL_LL_DMA_HAS_FLASH_ACCESS ) { + // Clear the DMA flash access address, and at the same time indirectly set DMA starting access address to 0x00000000UL. + HAL_LL_DMA_FLASHDMAST &= ~HAL_LL_DMA_FLASHDMAST_ADDR_MASK; + // Clear DMA flash access size. + HAL_LL_DMA_FLASHDMASZ &= ~HAL_LL_DMA_FLASHDMASZ_SIZE_MASK; + // Set DMA access to whole flash memory. + HAL_LL_DMA_FLASHDMASZ |= ( HAL_LL_DMA_FLASH_SIZE ) << HAL_LL_DMA_FLASHDMASZ_SIZE_POSITION; + } +} + +static inline uint8_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint32_t direction_set = HAL_LL_DMA_DMACHCTL_XFERMODE_BASIC; + + // For M2M direction AUTO mode is used, and for all other directions, BASIC mode is used. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY == direction ) { + direction_set = HAL_LL_DMA_DMACHCTL_XFERMODE_AUTO_REQUEST; + } + + return direction_set; +} + +static inline uint32_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc, hal_ll_dma_data_align_t align ) { + volatile uint32_t dst_inc = HAL_LL_DMA_DMACHTL_DSTINC_NO_INCREMENT; + + if ( set_inc ) { + switch ( align ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + // Source address increment. Data is 1 byte. + dst_inc = HAL_LL_DMA_DMACHTL_DSTINC_BYTE; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + // Source address increment. Data is halfword. + dst_inc = HAL_LL_DMA_DMACHTL_DSTINC_HALF_WORD; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + // Source address increment. Data is word. + dst_inc = HAL_LL_DMA_DMACHTL_DSTINC_WORD; + break; + + default: + break; + } + } + + return dst_inc; +} + +static inline uint32_t hal_ll_dma_get_reg_value_src_inc( bool set_inc, hal_ll_dma_data_align_t align ) { + volatile uint32_t src_inc = HAL_LL_DMA_DMACHTL_SRCINC_NO_INCREMENT; + + if ( set_inc ) { + switch ( align ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + // Source address increment. Data is 1 byte. + src_inc = HAL_LL_DMA_DMACHTL_SRCINC_BYTE; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + // Source address increment. Data is halfword. + src_inc = HAL_LL_DMA_DMACHTL_SRCINC_HALF_WORD; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + // Source address increment. Data is word. + src_inc = HAL_LL_DMA_DMACHTL_SRCINC_WORD; + break; + + default: + break; + } + } + + return src_inc; +} + +static inline uint32_t hal_ll_dma_get_reg_value_src_size( hal_ll_dma_data_align_t align ) { + volatile uint32_t align_set; + + switch ( align ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + // Data is 1 byte. + align_set = HAL_LL_DMA_DMACHTL_SRCSIZE_BYTE; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + // Data is halfword. + align_set = HAL_LL_DMA_DMACHTL_SRCSIZE_HALF_WORD; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + // Data is word. + align_set = HAL_LL_DMA_DMACHTL_SRCSIZE_WORD; + break; + + default: + break; + } + + return align_set; +} + +static inline uint32_t hal_ll_dma_get_reg_value_dst_size( hal_ll_dma_data_align_t align ) { + volatile uint32_t align_set; + + switch ( align ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + // Data is 1 byte. + align_set = HAL_LL_DMA_DMACHTL_DSTSIZE_BYTE; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + // Data is halfword. + align_set = HAL_LL_DMA_DMACHTL_DSTSIZE_HALF_WORD; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + // Data is word. + align_set = HAL_LL_DMA_DMACHTL_DSTSIZE_WORD; + break; + + default: + break; + } + + return align_set; +} + +static inline void hal_ll_dma_set_stream_priority( dma_handle_t *dma, uint8_t stream, hal_ll_dma_priority_t priority ) { + switch ( priority ) { + case HAL_LL_DMA_PRIORITY_LOW: + case HAL_LL_DMA_PRIORITY_MEDIUM: + dma->prio_clr = HAL_LL_DMA_PRIOCLR << stream; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + dma->prio_set = HAL_LL_DMA_PRIOSET << stream; + break; + + default: + break; + } +} + +static inline uint32_t hal_ll_dma_get_reg_value_burst_size( hal_ll_dma_burst_size_t burst_size ) { + return ((uint32_t)burst_size << HAL_LL_DMA_DMACHTL_ARBSIZE_POSITION); +} + +static hal_ll_dma_err_t hal_ll_dma_check_flash_access( uint32_t addr_src, uint32_t addr_dst ) { + uint32_t flash_memory_end = ( ( HAL_LL_DMA_FLASH_SIZE + 1 ) << 11 ) - 1; + + // Check whether destination address is in FLASH memory. + if ( addr_dst <= flash_memory_end ) { + // DMA does not have write access to FLASH memory. + return HAL_LL_DMA_ERROR; + } + + // Check whether source address is in FLASH memory. + if ( addr_src <= flash_memory_end ) { + if ( !HAL_LL_DMA_HAS_FLASH_ACCESS ) { + // DMA does not have access to FLASH memory. + return HAL_LL_DMA_ERROR; + } + } + + return HAL_LL_DMA_SUCCESS; +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt b/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt new file mode 100644 index 0000000000..101edda177 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt @@ -0,0 +1,63 @@ +## ./targets/arm/mikroe/tiva/src/gpio/CMakeLists.txt +set(hal_ll_def_list "") +set(MCU_NAME_FIRST_7 "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) +string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) +list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +# BEGIN GPIO +list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") +set(gpio_subimplementation "implementation_1/hal_ll_gpio_port.c") +# END GPIO + +mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO + # BEGIN GPIO + hal_ll_gpio.c + ${gpio_subimplementation} + # END GPIO + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN GPIO + ../../include/gpio/hal_ll_gpio.h + ../../include/gpio/hal_ll_gpio_port.h + ../../include/gpio/hal_ll_gpio_constants.h + # END GPIO +) + +target_compile_definitions(lib_hal_ll_gpio PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_gpio PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_gpio + PRIVATE + ../../include + # BEGIN GPIO + ../../include/gpio + # END GPIO + + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.GPIO) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) diff --git a/targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c b/targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c new file mode 100644 index 0000000000..f362122900 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c @@ -0,0 +1,166 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio.c + * @brief GPIO HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio_port.h" + +/******************************************************************************* + * + */ +void hal_ll_gpio_configure_pin(hal_ll_gpio_pin_t *pin, hal_ll_pin_name_t name, hal_ll_gpio_direction_t direction) { + pin->base = (hal_ll_gpio_base_t)hal_ll_gpio_port_base(hal_ll_gpio_port_index(name)); + pin->mask = hal_ll_gpio_pin_mask(name); + + if ( direction == HAL_LL_GPIO_DIGITAL_INPUT) + hal_ll_gpio_digital_input(&pin->base, pin->mask); + else + hal_ll_gpio_digital_output(&pin->base, pin->mask); +} + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +uint8_t hal_ll_gpio_read_pin_input(hal_ll_gpio_pin_t *pin) { + uint8_t gpio_data_value; + + gpio_data_value = ((hal_ll_gpio_base_handle_t *)(pin->base))->gpiodata; + return (gpio_data_value & pin->mask) ? 0x01 : 0x00; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +uint8_t hal_ll_gpio_read_pin_output(hal_ll_gpio_pin_t *pin) { + uint8_t gpio_data_value; + + gpio_data_value = ((hal_ll_gpio_base_handle_t *)(pin->base))->gpiodata; + return (gpio_data_value & pin->mask) ? 0x01 : 0x00; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_write_pin_output(hal_ll_gpio_pin_t *pin, uint8_t value) { + if (value) + ((hal_ll_gpio_base_handle_t *)(pin->base))->gpiodata |= pin->mask; + else + ((hal_ll_gpio_base_handle_t *)(pin->base))->gpiodata &= ~pin->mask; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_toggle_pin_output(hal_ll_gpio_pin_t *pin) { + uint8_t gpio_data_value = hal_ll_gpio_read_pin_output(pin); + hal_ll_gpio_write_pin_output(pin, !gpio_data_value); +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_set_pin_output(hal_ll_gpio_pin_t *pin) { + ((hal_ll_gpio_base_handle_t *)(pin->base))->gpiodata |= pin->mask; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_clear_pin_output(hal_ll_gpio_pin_t *pin) { + ((hal_ll_gpio_base_handle_t *)(pin->base))->gpiodata &= ~pin->mask; +} +#endif + +/******************************************************************************* + * + */ +void hal_ll_gpio_configure_port(hal_ll_gpio_port_t *port, hal_ll_port_name_t name, hal_ll_gpio_mask_t mask, hal_ll_gpio_direction_t direction) { + port->base = hal_ll_gpio_port_base(name); + port->mask = mask; + + if (direction == HAL_LL_GPIO_DIGITAL_INPUT) + hal_ll_gpio_digital_input(&port->base, port->mask); + else + hal_ll_gpio_digital_output(&port->base, port->mask); +} + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +hal_ll_port_size_t hal_ll_gpio_read_port_input(hal_ll_gpio_port_t *port) { + uint8_t gpio_data_value; + return ((hal_ll_gpio_base_handle_t *)(port->base))->gpiodata & port->mask; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +hal_ll_port_size_t hal_ll_gpio_read_port_output(hal_ll_gpio_port_t *port) { + uint8_t gpio_data_value; + return ((hal_ll_gpio_base_handle_t *)(port->base))->gpiodata & port->mask; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_write_port_output(hal_ll_gpio_port_t *port, hal_ll_port_size_t value) { + hal_ll_gpio_base_handle_t *base_reg = (hal_ll_gpio_base_handle_t *)port->base; + base_reg->gpiodata = (uint32_t)(port->mask & value); +} +#endif + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c new file mode 100644 index 0000000000..792e16a91b --- /dev/null +++ b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c @@ -0,0 +1,614 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/*!< @brief Helper macro for extracting appropriate pin mask. */ +#define HAL_LL_GPIO_PIN_MASK 0xFUL + +/*!< @brief Helper macro for extracting appropriate port mask. */ +#define HAL_LL_GPIO_PORT_MASK 0xFFUL + +/*!< @brief Helper macro for extracting appropriate alternate function. */ +#define HAL_LL_GPIO_AF_MASK 0xF00UL + +/*!< @brief Helper macro for getting appropriate alternate function mask. */ +#define HAL_LL_GPIO_AFSEL_MULTIPLIER 4 + +/*!< @brief Helper macro. */ +#define HAL_LL_GPIO_GPIOCR_MASK 0xFFFFFF00 + +/*!< @brief Helper macro for hexadecimal number for unlocking the GPIOCR register. */ +#define HAL_LL_GPIO_GPIOCR_UNLOCK_VALUE 0x4C4F434B + +/*!< @brief Helper macro for checking against pins GPIO_PE7 and GPIO_PD7. */ +#define HAL_LL_GPIO_PINMASK_PIN7 0x80UL + +/*!< @brief Helper macro for checking against pins on PORTC[0:3]. */ +#define HAL_LL_GPIO_PINMASK_PIN0_3 0xFUL + +/*!< @brief Helper macro for checking against pins GPIO_PF0. */ +#define HAL_LL_GPIO_PINMASK_PIN0 0x01UL + +/** + * Defines used in source + */ +#ifdef TM4C123 + #define GPIOA_BASE_ADDR 0x400043FCUL + #define GPIOB_BASE_ADDR 0x400053FCUL + #define GPIOC_BASE_ADDR 0x400063FCUL + #define GPIOD_BASE_ADDR 0x400073FCUL + #define GPIOE_BASE_ADDR 0x400243FCUL + #define GPIOF_BASE_ADDR 0x400253FCUL + #define GPIOG_BASE_ADDR 0x400263FCUL + #define GPIOH_BASE_ADDR 0x400273FCUL + #define GPIOJ_BASE_ADDR 0x4003D3FCUL + #define GPIOK_BASE_ADDR 0x400613FCUL +#else + #define GPIOA_BASE_ADDR 0x400583FCUL + #define GPIOB_BASE_ADDR 0x400593FCUL + #define GPIOC_BASE_ADDR 0x4005A3FCUL + #define GPIOD_BASE_ADDR 0x4005B3FCUL + #define GPIOE_BASE_ADDR 0x4005C3FCUL + #define GPIOF_BASE_ADDR 0x4005D3FCUL + #define GPIOG_BASE_ADDR 0x4005E3FCUL + #define GPIOH_BASE_ADDR 0x4005F3FCUL + #define GPIOJ_BASE_ADDR 0x400603FCUL + #define GPIOK_BASE_ADDR 0x400613FCUL + #define GPIOL_BASE_ADDR 0x400623FCUL + #define GPIOM_BASE_ADDR 0x400633FCUL + #define GPION_BASE_ADDR 0x400643FCUL + #define GPIOP_BASE_ADDR 0x400653FCUL + #define GPIOQ_BASE_ADDR 0x400663FCUL + #define GPIOR_BASE_ADDR 0x400673FCUL + #define GPIOS_BASE_ADDR 0x400683FCUL + #define GPIOT_BASE_ADDR 0x400693FCUL +#endif + +#define RCC_GPIOCLOCK _SYSCTL_RCGCGPIO + +#define hal_ll_gpio_port_get_pin_index(__index) ( __index & 0xF0 )?( ( uint8_t )__index % PORT_SIZE ): \ + ( ( uint8_t )__index % PORT_SIZE ) + +#define hal_ll_gpio_port_get_port_index(__index) ( __index & 0xF0 )?( ( uint8_t )__index / PORT_SIZE ): \ + ( ( uint8_t )__index / PORT_SIZE ) + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 1 +#endif +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 2 +#endif +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 3 +#endif +#ifndef GPIOE_BASE_ADDR + #define GPIOE_BASE_ADDR 4 +#endif +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 5 +#endif +#ifndef GPIOG_BASE_ADDR + #define GPIOG_BASE_ADDR 6 +#endif +#ifndef GPIOH_BASE_ADDR + #define GPIOH_BASE_ADDR 7 +#endif +#ifndef GPIOJ_BASE_ADDR + #define GPIOJ_BASE_ADDR 8 +#endif +#ifndef GPIOK_BASE_ADDR + #define GPIOK_BASE_ADDR 9 +#endif +#ifndef GPIOL_BASE_ADDR + #define GPIOL_BASE_ADDR 10 +#endif +#ifndef GPIOM_BASE_ADDR + #define GPIOM_BASE_ADDR 11 +#endif +#ifndef GPION_BASE_ADDR + #define GPION_BASE_ADDR 12 +#endif +#ifndef GPIOP_BASE_ADDR + #define GPIOP_BASE_ADDR 13 +#endif +#ifndef GPIOQ_BASE_ADDR + #define GPIOQ_BASE_ADDR 14 +#endif +#ifndef GPIOR_BASE_ADDR + #define GPIOR_BASE_ADDR 15 +#endif +#ifndef GPIOS_BASE_ADDR + #define GPIOS_BASE_ADDR 16 +#endif +#ifndef GPIOT_BASE_ADDR + #define GPIOT_BASE_ADDR 17 +#endif + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base[] = +{ + #ifdef TM4C123 + GPIOA_BASE_ADDR, + GPIOB_BASE_ADDR, + GPIOC_BASE_ADDR, + GPIOD_BASE_ADDR, + GPIOE_BASE_ADDR, + GPIOF_BASE_ADDR, + GPIOG_BASE_ADDR, + GPIOH_BASE_ADDR, + GPIOJ_BASE_ADDR, + GPIOK_BASE_ADDR + #else + GPIOA_BASE_ADDR, + GPIOB_BASE_ADDR, + GPIOC_BASE_ADDR, + GPIOD_BASE_ADDR, + GPIOE_BASE_ADDR, + GPIOF_BASE_ADDR, + GPIOG_BASE_ADDR, + GPIOH_BASE_ADDR, + GPIOJ_BASE_ADDR, + GPIOK_BASE_ADDR, + GPIOL_BASE_ADDR, + GPIOM_BASE_ADDR, + GPION_BASE_ADDR, + GPIOP_BASE_ADDR, + GPIOQ_BASE_ADDR, + GPIOR_BASE_ADDR, + GPIOS_BASE_ADDR, + GPIOT_BASE_ADDR + #endif +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint8_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +/** + * @brief Enables write access to pins + * that were originally locked. + * @param[in] *gpio_ptr - Register list for one GPIO module. + * @param[in] port - Port base address. + * @param[in] pin - Pin mask. + * + * @return none + */ +static void hal_ll_gpio_unlock_pin( hal_ll_gpio_base_handle_t *gpio_ptr, uint32_t port, uint8_t pin_mask ); + +/** + * @brief Unlock access to generic GPIO registers + * (GPIOAFSEL, GPIOPUR, GPIOPDR and GPIODEN) + * for pin which is locked on POR -> power-on reset. + * @param[in] *gpio_ptr - Register list for one GPIO module. + * @param[in] pin_mask - GPIO pin mask. + * + * @return none + */ +static void hal_ll_gpio_commit_pin( hal_ll_gpio_base_handle_t *gpio_ptr, uint8_t pin_mask ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) { + return hal_ll_gpio_port_get_pin_index( name ); +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) { + return hal_ll_gpio_port_get_port_index( name ); +} + +uint8_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) { + return ( 1UL << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) { + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint8_t pin_mask ) { + _hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint8_t pin_mask ) { + _hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint8_t pin_mask ) { + _hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) { + uint8_t index = 0; + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t port ) { + uint8_t shift_value; + + switch ( port ) { + case GPIOA_BASE_ADDR: + shift_value = 0; + break; + case GPIOB_BASE_ADDR: + shift_value = 1; + break; + case GPIOC_BASE_ADDR: + shift_value = 2; + break; + case GPIOD_BASE_ADDR: + shift_value = 3; + break; + case GPIOE_BASE_ADDR: + shift_value = 4; + break; + case GPIOF_BASE_ADDR: + shift_value = 5; + break; + case GPIOG_BASE_ADDR: + shift_value = 6; + break; + case GPIOH_BASE_ADDR: + shift_value = 7; + break; + case GPIOJ_BASE_ADDR: + shift_value = 8; + break; + case GPIOK_BASE_ADDR: + shift_value = 9; + break; + case GPIOL_BASE_ADDR: + shift_value = 10; + break; + case GPIOM_BASE_ADDR: + shift_value = 11; + break; + case GPION_BASE_ADDR: + shift_value = 12; + break; + case GPIOP_BASE_ADDR: + shift_value = 13; + break; + case GPIOQ_BASE_ADDR: + shift_value = 14; + break; + case GPIOR_BASE_ADDR: + shift_value = 15; + break; + case GPIOS_BASE_ADDR: + shift_value = 16; + break; + case GPIOT_BASE_ADDR: + shift_value = 17; + break; + + default: + return; + } + + *RCC_GPIOCLOCK |= 1UL << shift_value; +} + +static void hal_ll_gpio_commit_pin( hal_ll_gpio_base_handle_t *gpio_ptr, uint8_t pin_mask ) { + // Unlock GPIOCR register. + gpio_ptr->gpiolock = HAL_LL_GPIO_GPIOCR_UNLOCK_VALUE; + + // Unlock access to generic GPIO registers (GPIOAFSEL, GPIOPUR, GPIOPDR and GPIODEN) + // for pin which is locked on POR -> power-on reset. + gpio_ptr->gpiocr = pin_mask; +} + +static void hal_ll_gpio_unlock_pin( hal_ll_gpio_base_handle_t *gpio_ptr, uint32_t port, uint8_t pin_mask ) { + switch ( port ) { + // JTAG/SWD pins are based on PORTC. + case GPIOC_BASE_ADDR: + if ( pin_mask == ( pin_mask & HAL_LL_GPIO_PINMASK_PIN0_3 ) ) { + hal_ll_gpio_commit_pin( gpio_ptr, pin_mask ); + } + break; + // Non-maskable interrupt pin is based on both PORTD and PORTE. + case GPIOD_BASE_ADDR: + case GPIOE_BASE_ADDR: + if ( pin_mask == HAL_LL_GPIO_PINMASK_PIN7 ) { + hal_ll_gpio_commit_pin( gpio_ptr, pin_mask ); + } + break; + case GPIOF_BASE_ADDR: + if ( pin_mask == HAL_LL_GPIO_PINMASK_PIN0 ) { + hal_ll_gpio_commit_pin( gpio_ptr, pin_mask ); + } + break; + + default: + return; + } +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint8_t pin_mask, uint32_t config ) { + uint8_t i; + uint32_t tmp_code; + + hal_ll_gpio_base_handle_t *gpio_ptr = ( hal_ll_gpio_base_handle_t * )( *port ); + + hal_ll_gpio_clock_enable( *port ); + + hal_ll_gpio_unlock_pin( gpio_ptr, *port, pin_mask ); + + if ( config & GPIO_CFG_MODE_OUTPUT ) { + gpio_ptr->gpiodir |= pin_mask; + } else { + // Else, digital input. + gpio_ptr->gpiodir &= ~pin_mask; + } + + if ( config & GPIO_CFG_PULL_UP ) { + gpio_ptr->gpiopur |= pin_mask; + } else { + gpio_ptr->gpiopur &= ~pin_mask; + } + + if( config & GPIO_CFG_PULL_DOWN ) { + gpio_ptr->gpiopdr |= pin_mask; + } else { + gpio_ptr->gpiopdr &= ~pin_mask; + } + + if ( config & GPIO_CFG_OPEN_DRAIN ) { + gpio_ptr->gpioodr |= pin_mask; + } else { + gpio_ptr->gpioodr &= ~pin_mask; + } + + if ( config & GPIO_CFG_DRIVE_2mA) { + gpio_ptr->gpiodr2r |= pin_mask; + } else { + gpio_ptr->gpiodr2r &= ~pin_mask; + } + + if ( config & GPIO_CFG_DRIVE_4mA ) { + gpio_ptr->gpiodr4r |= pin_mask; + } else { + gpio_ptr->gpiodr4r &= ~pin_mask; + } + + if ( config & GPIO_CFG_DRIVE_8mA) { + gpio_ptr->gpiodr8r |= pin_mask; + } else { + gpio_ptr->gpiodr8r &= ~pin_mask; + } + + if( ( 1 == ( config & GPIO_CFG_DRIVE_6mA ) ) || + ( 1 == ( config & GPIO_CFG_DRIVE_10mA ) ) || + ( 1 == ( config & GPIO_CFG_DRIVE_12mA ) ) ) + { + tmp_code = 0; + for ( i = 0; i < 8; i++ ) { + if( ( pin_mask >> i ) & 1 ) { + tmp_code |= 0x3UL << ( i * 2 ); + } + } + + gpio_ptr->gpiopc &= ~tmp_code; + gpio_ptr->gpiodr8r &= ~pin_mask; + gpio_ptr->gpiodr4r &= ~pin_mask; + gpio_ptr->gpiodr12r &= ~pin_mask; + } + + tmp_code = 0; + + if ( config & GPIO_CFG_DRIVE_6mA ) { + for( i = 0; i < 8; i++ ) { + if( ( pin_mask >> i ) & 1 ) { + tmp_code |= 0x1UL << ( i * 2 ); + } + } + + gpio_ptr->gpiopc |= tmp_code; + gpio_ptr->gpiodr8r |= pin_mask; + } + + tmp_code = 0; + + if( config & GPIO_CFG_DRIVE_10mA ) { + for( i = 0; i < 8; i++ ) { + if( ( pin_mask >> i ) & 1 ) { + tmp_code |= 0x3UL << ( i * 2 ); + } + } + + gpio_ptr->gpiopc |= tmp_code; + gpio_ptr->gpiodr8r |= pin_mask; + gpio_ptr->gpiodr12r |= pin_mask; + } + + tmp_code = 0; + + if( config & GPIO_CFG_DRIVE_12mA ) { + for( i = 0; i < 8; i++ ) { + if( ( pin_mask >> i ) & 1 ) { + tmp_code |= 0x3UL << ( i * 2 ); + } + } + + gpio_ptr->gpiopc |= tmp_code; + gpio_ptr->gpiodr8r |= pin_mask; + gpio_ptr->gpiodr4r |= pin_mask; + gpio_ptr->gpiodr12r |= pin_mask; + } + + if ( config & GPIO_CFG_SLEW_RATE ) { + if ( config & GPIO_CFG_DRIVE_8mA ) { + gpio_ptr->gpioslr |= pin_mask; + } else { + return; + } + } else { + gpio_ptr->gpioslr &= ~pin_mask; + } + + if ( config & GPIO_CFG_DIGITAL_ENABLE ) { + gpio_ptr->gpioden |= pin_mask; + } else { + gpio_ptr->gpioden &= ~pin_mask; + } + + if ( config & GPIO_CFG_ISOLATION_DISABLE ) { + if( ( GPIOE_BASE_ADDR != *port ) & ( GPIOD_BASE_ADDR != *port ) & ( GPIOB_BASE_ADDR != *port ) & + ( GPIOK_BASE_ADDR != *port ) & ( GPIOP_BASE_ADDR != *port ) ) + { + return; + } else { + gpio_ptr->gpioamsel |= pin_mask; + } + } else { + if( ( GPIOE_BASE_ADDR == *port ) | ( GPIOD_BASE_ADDR == *port ) | ( GPIOB_BASE_ADDR == *port ) | + ( GPIOK_BASE_ADDR == *port ) | ( GPIOP_BASE_ADDR == *port ) ) + { + gpio_ptr->gpioamsel &= ~pin_mask; + } + } + + if ( config & GPIO_CFG_ADC_SRC_TRIGGER ) { + gpio_ptr->gpioadcctl |= pin_mask; + } else { + gpio_ptr->gpioadcctl &= ~pin_mask; + } + + if ( config & GPIO_CFG_ALT_FUNCTION ) + gpio_ptr->gpioafsel |= pin_mask; + else + gpio_ptr->gpioafsel &= ~pin_mask; +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) { + // Pin, port & alternate function mask declaration & initialization. + uint8_t pin_mask_raw = 0; + uint8_t pin_mask = 0; + uint8_t port_mask = 0; + uint32_t af_mask = 0; + uint32_t *port = 0; + + // Extract appropriate info from "module_pin" variable. + pin_mask_raw = ( ( module_pin & HAL_LL_GPIO_PIN_MASK ) % PORT_SIZE ); + pin_mask = ( 0x1UL << pin_mask_raw ); + port_mask = ( module_pin & HAL_LL_GPIO_PORT_MASK ) / PORT_SIZE; + af_mask = ( ( ( module_pin & HAL_LL_GPIO_AF_MASK ) >> 8 ) << ( pin_mask_raw * HAL_LL_GPIO_AFSEL_MULTIPLIER ) ); + + // Get appropriate GPIO module. + port = (uint32_t *)_hal_ll_gpio_port_base[port_mask]; + + // Configure basic GPIO settings. + _hal_ll_gpio_config( &port, pin_mask, module_config ); + + // Get appropriate register list. + hal_ll_gpio_base_handle_t *gpio_ptr = ( hal_ll_gpio_base_handle_t * )( port ); + + /* + * NOTE: On TM4C123 microcontrollers, the GPIO_PCTL register + * retains a non-zero value after reset. Therefore, clearing specific bits + * corresponding to the currently selected pin in the register before + * assigning new values is necessary for proper initialization. + */ + gpio_ptr->gpiopctl &= ~( HAL_LL_GPIO_PIN_MASK << ( module_pin * HAL_LL_GPIO_AFSEL_MULTIPLIER )); + + if ( state ) { + // Set appropriate bit in AFSEL register. + gpio_ptr->gpioafsel |= ( 0x1UL << pin_mask ); + + // Set appropriate bit in GPIOPCTL register. + gpio_ptr->gpiopctl |= af_mask; + } else { + // Clear appropriate bit in AFSEL register. + gpio_ptr->gpioafsel &= ~( 0x1UL << pin_mask ); + + // Clear appropriate bit in GPIOPCTL register. + gpio_ptr->gpiopctl &= ~( af_mask ); + } +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt b/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt new file mode 100644 index 0000000000..219b13c6a2 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt @@ -0,0 +1,15 @@ +## ./targets/arm/mikroe/tiva/src/hal_ll/CMakeLists.txt +add_library(lib_hal_ll INTERFACE) + +add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) + +set(module_list "") +set(module_list_supported "") +set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") + +target_link_libraries(lib_hal_ll INTERFACE + ${module_list} +) + +mikrosdk_install(MikroSDK.HalLowLevel) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_rcc.h ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) diff --git a/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt b/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt new file mode 100644 index 0000000000..28ab72984c --- /dev/null +++ b/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt @@ -0,0 +1,72 @@ +## ./targets/arm/mikroe/tiva/src/i2c/CMakeLists.txt +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +## BEGIN I2C +list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") +set(i2c_subimplementation "implementation_1/hal_ll_i2c_master.c") +set(i2c_pin_map "hal_ll_i2c_pin_map/implementation_1") +## END I2C + +# TSC2003 Special case +if (NOT DEFINED _MSDK_TFT_TP_) + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") +else() + if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") + list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") + else() + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") + endif() +endif() + +mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master + ${i2c_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h +# BEGIN I2C + ../../include/i2c/hal_ll_i2c_master.h + ../../include/i2c/${i2c_pin_map}/hal_ll_i2c_pin_map.h +# END I2C +) + +target_compile_definitions(lib_hal_ll_i2c_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_i2c_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_i2c_master + PRIVATE + ../../include + ../../include/gpio + # BEGIN I2C + ../../include/i2c + ../../include/i2c/${i2c_pin_map} + # END I2C + + INTERFACE + $ + $ + $ + $ + $ + $ + ) + +mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h) diff --git a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c new file mode 100644 index 0000000000..c0c73ecc03 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c @@ -0,0 +1,453 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" +#include "hal_ll_rcc.h" +#include "delays.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K (100000UL) +#define HAL_LL_I2C_MASTER_SPEED_400K (400000UL) +#define HAL_LL_I2C_MASTER_SPEED_1M (1000000UL) +#define HAL_LL_I2C_MASTER_SPEED_3M2 (3200000UL) + +#define HAL_LL_I2C_DEFAULT_PASS_COUNT (10000) + +/*!< @brief I2C register structure */ +typedef struct { + hal_ll_base_addr_t TODO; +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct { + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct { + uint32_t pin_scl; + uint32_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C end mode selection values */ +typedef enum { + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C hw specific error values */ +typedef enum { + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C timeout error values */ +typedef enum { + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT, + HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE +} hal_ll_i2c_master_timeout_t; + +/*!< @brief Enum containing predefined module standard speed values */ +typedef enum { + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[ I2C_MODULE_COUNT + 1 ] = { + #ifdef I2C_MODULE_0 + {HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_2 + {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_2 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_3 + {HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_3 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_4 + {HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_4 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_5 + {HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_5 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_6 + {HAL_LL_I2C6_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_6 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_7 + {HAL_LL_I2C7_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_7 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_8 + {HAL_LL_I2C8_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_8 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_9 + {HAL_LL_I2C9_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_9 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, + bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @return None + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return None + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, + bool hal_ll_state ); + +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, + hal_ll_pin_name_t sda, + hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Get I2C busy bit value. + * + * Checks I2C busy bit value and returns true if device is in operation. + * Else returns false. + * + * @param[in] *hal_ll_hw_reg - Object specific context handler. + * @return bool State of register busy bit. + */ +static bool hal_ll_i2c_master_is_idle( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Waits until device is free to operate. + * + * Polls I2C busy bit value and waits until device has finished any + * on-going operation. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + */ +static hal_ll_err_t hal_ll_i2c_master_wait_for_idle( hal_ll_i2c_hw_specifics_map_t *map ) ; + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( uint32_t bit_rate ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, + uint8_t *read_data_buf, + size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, + uint8_t *write_data_buf, + size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + return 0; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + return 0; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + return 0; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + return; +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + return; +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + return 0; +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + return 0; +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + return 0; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + return; +} +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ){ + return 0; +} + +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ){ + return 0; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + return; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + return; +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + return; +} + +static uint32_t hal_ll_i2c_get_speed( uint32_t bit_rate ) { + return 0; +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + return 0; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list ) { + return 0; +} + +static bool hal_ll_i2c_master_is_idle( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + return 0; +} + +static hal_ll_err_t hal_ll_i2c_master_wait_for_idle( hal_ll_i2c_hw_specifics_map_t *map ) { + return 0; +} + +static void hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + return; +} + +static void hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + return; +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/one_wire/CMakeLists.txt b/targets/arm/mikroe/renesas/src/one_wire/CMakeLists.txt new file mode 100644 index 0000000000..8e2be839d5 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/one_wire/CMakeLists.txt @@ -0,0 +1,31 @@ +## ./targets/arm/mikroe/tiva/src/one_wire/CMakeLists.txt +set(hal_ll_def_list "") +list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") + +mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire + hal_ll_one_wire.c + + ../../include/one_wire/hal_ll_one_wire.h) + +target_compile_definitions(lib_hal_ll_one_wire PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_one_wire PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.GPIO + MikroSDK.HalLowLevelCommon +) + +target_include_directories(lib_hal_ll_one_wire + PRIVATE + ../../include/one_wire + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.OneWire) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) diff --git a/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c b/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c new file mode 100644 index 0000000000..f6f5008af2 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c @@ -0,0 +1,557 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_one_wire.c + * @brief One Wire HAL LOW LEVEL layer implementation. + */ +#include "hal_ll_one_wire.h" +#include "delays.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro getting minimum bits per transfer. */ +#define HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER (8) + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief Static array for selecting One Wire data bits. */ +static const uint8_t hal_ll_one_wire_selected_bit[ HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ] = { + 1, 2, 4, 8, 16, 32, 64, 128 +}; + +/*!< @brief Helper macro for starting to enumerate device ID(s). */ +static uint8_t hal_ll_one_wire_search_rom_command = ONE_WIRE_CMD_ROM_SEARCH; + +/*!< @brief Helper macro for reading a device ID. */ +static uint8_t hal_ll_one_wire_read_rom_command_legacy = ONE_WIRE_CMD_ROM_READ_LEGACY; +static uint8_t hal_ll_one_wire_read_rom_command = ONE_WIRE_CMD_ROM_READ; + +/*!< @brief Helper macro for ignoring a device ID. */ +static uint8_t hal_ll_one_wire_skip_rom_command = ONE_WIRE_CMD_ROM_SKIP; + +/*!< @brief Helper macro for selecting a device with specific ID. */ +static uint8_t hal_ll_one_wire_match_rom_command = ONE_WIRE_CMD_ROM_MATCH; + +/*!< @brief Helper flag if One Wire device is the last one left on the bus. */ +static uint8_t last_device_flag = 0; + +/*!< @brief Helper flag for last discrepancy. */ +static uint8_t last_discrepancy = 0; + +/*!< @brief Helper flag for last family discrepancy. */ +static uint8_t last_family_discrepancy = 0; + +/*!< @brief Helper instance consisting of hardware specifics. */ +static hal_ll_one_wire_local_t one_wire_handle; + +__weak void one_wire_timing_value_a( void ) { + Delay_6us(); +} + +__weak void one_wire_timing_value_b( void ) { + Delay_64us(); +} + +__weak void one_wire_timing_value_c( void ) { + Delay_60us(); +} + +__weak void one_wire_timing_value_d( void ) { + Delay_10us(); +} + +__weak void one_wire_timing_value_e( void ) { + Delay_9us(); +} + +__weak void one_wire_timing_value_f( void ) { + Delay_55us(); +} + +__weak void one_wire_timing_value_h( void ) { + Delay_480us(); +} + +__weak void one_wire_timing_value_i( void ) { + Delay_70us(); +} + +__weak void one_wire_timing_value_j( void ) { + Delay_410us(); +} +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Writes bit to One Wire bus. + * @details Writes bit to One Wire bus. + * @param[in] write_data_buffer Data transmit buffer. + */ +static void hal_ll_one_wire_write_bit( uint8_t write_data_buffer ); + +/** + * @brief Reads bit from One Wire bus. + * @details Reads bit from One Wire bus. + * @param[in] write_data_buffer Data receive buffer. + */ +static void hal_ll_one_wire_read_bit( uint8_t *read_data_buffer ); + +/** + * @brief Search One Wire capable device on bus. + * @details Search One Wire capable device on bus. + * + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @param[out] *one_wire_device_list Buffer for One Wire device ROM information. + */ +static hal_ll_err_t hal_ll_one_wire_search( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +void hal_ll_one_wire_open( hal_ll_one_wire_t *obj ) { + // Local instance of One Wire pin. + hal_ll_gpio_pin_t one_wire_pin; + + // Enable appropriate PORT clock, set pin to be digital output. + hal_ll_gpio_configure_pin( &one_wire_pin, obj->data_pin, HAL_LL_GPIO_DIGITAL_OUTPUT ); + + /* Enables appropriate PORT clock, configures pin to have digital output functionality, + * makes sure that HIGH voltage state is applied on pin before any One Wire actions. */ + hal_ll_one_wire_reconfigure( obj ); +} + +hal_ll_err_t hal_ll_one_wire_reset( hal_ll_one_wire_t *obj ) { + /* Variable for checking whether there are device(s) on + * One Wire data pin (0) or there aren't any devices at all (1). */ + uint8_t device_response = 1; + + uint32_t bit_location = 1 << one_wire_handle.data_pin; + + if ( !obj->state ) + return HAL_LL_ONE_WIRE_ERROR; + + *(uint32_t *)one_wire_handle.direction |= bit_location; + + // Set pin to LOW voltage level. + *(uint32_t *)one_wire_handle.input_output &= ~bit_location; + + // Timing value for reset of One Wire bus - LOW voltage level. + one_wire_timing_value_h(); + + // Release pin ( pull-up resistor will do the rest (pull the data line up) ). + *(uint32_t *)one_wire_handle.direction &= ~(bit_location); + + // Timing value for reset of One Wire bus - Master sample pulse. + one_wire_timing_value_i(); + + // Check whether there are devices on One Wire data pin. + device_response = *(uint32_t *)one_wire_handle.input_output & bit_location; + + // Provide enough time for power injection into internal power logic of devices that are present. + one_wire_timing_value_j(); + + // Return final result of device response. + return device_response; +} + +hal_ll_err_t hal_ll_one_wire_read_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ) { + // Initiate Reset sequence. + if ( hal_ll_one_wire_reset( obj ) != 0 ) { + return HAL_LL_ONE_WIRE_ERROR; + } + + // Initiate "Read ROM" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_read_rom_command, 1 ); + + // Read ROM address. + hal_ll_one_wire_read_byte( &device_rom_address->address[0], 8 ); + + return HAL_LL_ONE_WIRE_SUCCESS; +} + +hal_ll_err_t hal_ll_one_wire_skip_rom( hal_ll_one_wire_t *obj ) { + // Initiate Reset sequence. + if ( hal_ll_one_wire_reset( obj ) != 0 ) { + return HAL_LL_ONE_WIRE_ERROR; + } + + // Initiate "Skip ROM" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_skip_rom_command, 1 ); + + return HAL_LL_ONE_WIRE_SUCCESS; +} + +hal_ll_err_t hal_ll_one_wire_match_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ) { + // Initiate Reset sequence. + if ( hal_ll_one_wire_reset( obj ) != 0 ) { + return HAL_LL_ONE_WIRE_ERROR; + } + + // Initiate "Match" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_match_rom_command, 1 ); + + // Send ROM address. + hal_ll_one_wire_write_byte( (uint32_t)device_rom_address, 8 ); + + return HAL_LL_ONE_WIRE_SUCCESS; +} + +static hal_ll_err_t hal_ll_one_wire_search( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) { + // Final search result variable. + uint8_t search_result = 0; + + // Initialize variables for search method. + uint8_t rom_byte_number = 0; + uint8_t rom_byte_mask = 1; + uint8_t id_bit_number = 1; + uint8_t last_zero = 0; + + // The first bit read in a bit search sequence. + // ( logical AND of all of the id_bit_number bits of the devices that are still participating in the search ). + uint8_t id_bit = 0; + + // The complement of id_bit. + // ( logical AND of the complement of all id_bit_number bits of the devices that are still participating in the search ). + uint8_t cmp_id_bit = 0; + + // Search direction ( bit-per-bit search ). + uint8_t search_direction = 0; + + // If the last call was not the last one... + if ( !last_device_flag ) { + + // If there were no any device while executing One Wire reset sequence... + if ( hal_ll_one_wire_reset( obj ) ) { + + // Reset all the important variables. + last_device_flag = 0; + last_discrepancy = 0; + last_family_discrepancy = 0; + + // Stop searching because there are no any One Wire capable devices. + return HAL_LL_ONE_WIRE_ERROR; + } + + // If device(s) has(have) been found, initiate "Search" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_search_rom_command, 1 ); + + // Iterate until all 64 bits (8 bytes) of unique ROM 'registration' numbers have not been found. + do { + // Read a bit. + hal_ll_one_wire_read_bit( &id_bit ); + + // Then, read its complement. + hal_ll_one_wire_read_bit( &cmp_id_bit ); + + // Check whether no devices participating in current search. + if ( ( id_bit == 1 ) && ( cmp_id_bit == 1 ) ) { + break; + // Proceed, because we have found some device(s). + } else { + // We are going to check once again whether read bit and + // its complement of all the devices on the One Wire grid are not the same. + // If they are not the same, we are going to start our search with non-complement bit. + if ( id_bit != cmp_id_bit ) { + search_direction = id_bit; // Bit write value for search. + + // Otherwise, there are both binary zeros and ones in the current + // bit position of the participating ROM numbers. This is a discrepancy. + } else { + if ( id_bit_number < last_discrepancy ) { + search_direction = ( ( one_wire_device_list->address[ rom_byte_number ] & rom_byte_mask ) > 0 ); + } else { + search_direction = ( id_bit_number == last_discrepancy ); + } + + // If 0 is picked, save its position. + if ( search_direction == 0) { + last_zero = id_bit_number; + + // Check for last discrepancy in family. + if ( last_zero < 9 ) { + last_family_discrepancy = last_zero; + } + } + } + + // Set or clear bit in the ROM byte rom_byte_number with mask rom_byte_mask. + if ( search_direction == 1 ) { + one_wire_device_list->address[ rom_byte_number ] |= rom_byte_mask; + } else { + one_wire_device_list->address[ rom_byte_number ] &= ~rom_byte_mask; + } + + // Search number search direction write bit. + hal_ll_one_wire_write_bit( search_direction ); + + // Increment the byte counter "id_bit_number", and shift the mask "rom_byte_mask". + id_bit_number++; + rom_byte_mask <<= 1; + + // If the mask is zero, then go to new "serial_num" byte, "rom_byte_number" and "reset_mask". + if ( rom_byte_mask == 0 ) { + rom_byte_number++; + rom_byte_mask = 1; + } + } + } while ( rom_byte_number < HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ); + + // If the search was successful then... + if ( !( id_bit_number < 65 ) ) { + + last_discrepancy = last_zero; + + // Check for last device. + if ( last_discrepancy == 0 ) { + last_device_flag = 1; + } + search_result = 1; + } + } + // If no device found then reset counters so next "search" will be like a first. + if ( !search_result || !one_wire_device_list->address[0] ) { + last_discrepancy = 0; + last_family_discrepancy = 0; + last_device_flag = 0; + search_result = 0; + } + + // Return info whether we have found some device ID or not. + return search_result; +} + +hal_ll_err_t hal_ll_one_wire_search_first_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) { + // Reset the search state. + last_discrepancy = 0; + last_device_flag = 0; + last_family_discrepancy = 0; + + // Initiate search algorithm, in order to get first device on One Wire grid. + hal_ll_one_wire_search( obj, one_wire_device_list ); + + return HAL_LL_ONE_WIRE_SUCCESS; +} + +hal_ll_err_t hal_ll_one_wire_search_next_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) { + // Initiate search algorithm, in order to get first device on One Wire grid. + hal_ll_one_wire_search( obj, one_wire_device_list ); + + return HAL_LL_ONE_WIRE_SUCCESS; +} + +void hal_ll_one_wire_write_byte( uint8_t *write_data_buffer, size_t write_data_length ) { + uint8_t bit_location = 1 << one_wire_handle.data_pin; + size_t local_byte_checker = 0; + uint8_t local_bit_checker = 0; + + // For every byte to be sent... + while ( local_byte_checker != write_data_length ) { + + // ...restart bit checker... + local_bit_checker = 0; + + // For every bit in byte to be sent... + while ( local_bit_checker != HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ) { + // Set pin to be digital output. + *(uint32_t *)one_wire_handle.direction |= bit_location; + + // Set pin to LOW voltage level. + *(uint32_t *)one_wire_handle.input_output &= ~bit_location; + + // Check whether a bit is binary one. + if ( write_data_buffer[ local_byte_checker ] & hal_ll_one_wire_selected_bit[ local_bit_checker ] ) { + // Timing value "a" for writing logical '1' - LOW voltage level. + one_wire_timing_value_a(); + // Else, bit is binary zero. + } else { + // Timing value "c" for writing logical '0' - LOW voltage level. + one_wire_timing_value_c(); + } + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint32_t *)one_wire_handle.direction &= ~bit_location; + + // Recommended timing after writing 1's or 0's. + if ( write_data_buffer[ local_byte_checker ] & hal_ll_one_wire_selected_bit[ local_bit_checker ] ) { + // Timing value "b" for writing logical '1' - LOW voltage level. + one_wire_timing_value_b(); + } else { + // Timing value "d" for writing logical '0' - HIGH voltage level. + one_wire_timing_value_d(); + } + // Increment so we could send another bit. + ++local_bit_checker; + } + // Increment so we could send another byte. + ++local_byte_checker; + } +} + +void hal_ll_one_wire_read_byte( uint8_t *read_data_buffer, size_t read_data_length ) { + size_t local_byte_checker = 0; + uint8_t local_bit_checker = 0; + uint8_t bit_location = 1 << one_wire_handle.data_pin; + uint8_t local_buffer = 0; + + // For every byte to be read... + while ( local_byte_checker != read_data_length ) { + + // ...restart bit checker and buffer... + local_bit_checker = 0; + local_buffer = 0; + + // For every bit in byte to be read... + while ( local_bit_checker != HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ) { + // Set pin to be digital output. + *(uint32_t*)one_wire_handle.direction |= bit_location; + + // Set pin to LOW voltage level. + *(uint32_t*)one_wire_handle.input_output &= ~bit_location; + + // Timing value "a" for bit reading - LOW voltage level. + one_wire_timing_value_a(); + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint32_t*)one_wire_handle.direction &= ~bit_location; + + // Timing value "e" for sampling read information. + one_wire_timing_value_e(); + + // Read bit. + local_buffer += ( (*(uint32_t*)one_wire_handle.input_output & bit_location)?(1):(0) ) << local_bit_checker; + + // Timing value "f" for the rest of the read operation. + one_wire_timing_value_f(); + + // Increment so we could send another bit. + ++local_bit_checker; + } + // Send back one logical level up a byte of data that has been just read. + read_data_buffer[local_byte_checker++] = local_buffer; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static void hal_ll_one_wire_write_bit( uint8_t write_data_buffer ) { + size_t local_byte_checker = 0; + uint8_t local_bit_checker = 0; + uint8_t bit_location = 1 << one_wire_handle.data_pin; + + // Set pin to be digital output. + *(uint32_t *)one_wire_handle.direction |= bit_location; + + // Set pin to LOW voltage level. + *(uint32_t *)one_wire_handle.input_output &= ~bit_location; + + // Check whether a bit is binary one. + if ( write_data_buffer & hal_ll_one_wire_selected_bit[ local_bit_checker ] ) { + // Timing value "a" for writing logical '1' - LOW voltage level. + one_wire_timing_value_a(); + // Else, bit is binary zero. + } else { + // Timing value "c" for writing logical '0' - LOW voltage level. + one_wire_timing_value_c(); + } + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint32_t *)one_wire_handle.direction &= ~bit_location; + + // Recommended timing after writing 1's or 0's. + if ( write_data_buffer & hal_ll_one_wire_selected_bit[ local_bit_checker ] ) { + // Timing value "b" for writing logical '1' - LOW voltage level. + one_wire_timing_value_b(); + } else { + // Timing value "d" for writing logical '0' - HIGH voltage level. + one_wire_timing_value_d(); + } +} + +static void hal_ll_one_wire_read_bit( uint8_t *read_data_buffer ) { + uint8_t bit_location = 1 << one_wire_handle.data_pin; + + // Set pin to be digital output. + *(uint32_t *)one_wire_handle.direction |= bit_location; + + // Set pin to LOW voltage level. + *(uint32_t *)one_wire_handle.input_output &= ~bit_location; + + // Timing value "a" for bit reading - LOW voltage level. + one_wire_timing_value_a(); + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint32_t *)one_wire_handle.direction &= ~bit_location; + + // Timing value "e" for sampling read information. + one_wire_timing_value_e(); + + // Read bit. + read_data_buffer[ 0 ] = ( *(uint32_t *)one_wire_handle.input_output & bit_location ) ? 0x01 : 0x00; + + // Timing value "f" for the rest of the read operation. + one_wire_timing_value_f(); +} + +void hal_ll_one_wire_reconfigure( hal_ll_one_wire_t *obj ) { + // Local instance of One Wire pin. + hal_ll_gpio_pin_t one_wire_pin; + + // Get pin base address and mask. + one_wire_pin.base = (hal_ll_gpio_base_t)hal_ll_gpio_port_base(hal_ll_gpio_port_index(obj->data_pin)); + one_wire_pin.mask = hal_ll_gpio_pin_mask(obj->data_pin); + + // The idle state for the One Wire bus is HIGH. + do { + // Make sure that we have HIGH voltage state before any actions. + hal_ll_gpio_write_pin_output( &one_wire_pin, 1 ); + + // Make sure that pin is at HIGH voltage state. + } while ( !hal_ll_gpio_read_pin_output( &one_wire_pin ) ); + + // Memorize info about pin number (for future use). + one_wire_handle.data_pin = obj->data_pin % PORT_SIZE; + + // Get all the necessary registers for appropriate PORT which holds One Wire pin. + hal_ll_gpio_base_handle_t *gpio_ptr = (hal_ll_gpio_base_handle_t *)one_wire_pin.base; + + // MODER register 32-bit address. + one_wire_handle.direction = (uint32_t)&gpio_ptr->gpiodir; + + // Memorize info about register whose main task is to alter GPIO pin direction. + one_wire_handle.input_output = (uint32_t)&gpio_ptr->gpiodata; + + // Set object state to true. + obj->state = true; +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/rtc/CMakeLists.txt b/targets/arm/mikroe/renesas/src/rtc/CMakeLists.txt new file mode 100644 index 0000000000..06a7e7ca95 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/rtc/CMakeLists.txt @@ -0,0 +1,39 @@ +## ./targets/arm/mikroe/tiva/src/rtc/CMakeLists.txt +set(hal_ll_def_list "") + +## BEGIN RTC +list(APPEND hal_ll_def_list "MACRO_USAGE_RTC") + +if(${MCU_NAME} MATCHES "TM4C129.+") + set(rtc_subimplementation "implementation_1/hal_ll_rtc.c") +elseif(${MCU_NAME} MATCHES "TM4C123[137BG].+") + set(rtc_subimplementation "implementation_2/hal_ll_rtc.c") +endif() +## END RTC + +mikrosdk_add_library(lib_hal_ll_rtc MikroSDK.HalLowLevel.RTC + ${rtc_subimplementation} + + ../../include/rtc/hal_ll_rtc.h) + +target_compile_definitions(lib_hal_ll_rtc PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_rtc PUBLIC + MikroC.Core + MikroSDK.HalInterface + MikroSDK.HalLowLevelCommon +) + +target_include_directories(lib_hal_ll_rtc + PRIVATE + ../../include/rtc + INTERFACE + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.RTC) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.RTC ../../include/rtc/hal_ll_rtc.h) diff --git a/targets/arm/mikroe/renesas/src/rtc/implementation_1/hal_ll_rtc.c b/targets/arm/mikroe/renesas/src/rtc/implementation_1/hal_ll_rtc.c new file mode 100644 index 0000000000..f0f9279d59 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/rtc/implementation_1/hal_ll_rtc.c @@ -0,0 +1,276 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rtc.c + * @brief Rtc HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rtc.h" + +/** + * Return values + */ +typedef enum +{ + HAL_LL_RTC_SUCCESS = 0, + HAL_LL_RTC_ERROR = (-1) +} hal_ll_rtc_err_t; + +#define SYSCTL_RCGCHIB_R0_BIT 0 +#define HIB_IM_WC_BIT 4 +#define HIB_CTL_RTCEN_BIT 0 +#define HIB_CTL_CLK32EN_BIT 6 +#define HIB_CTL_WRC_BIT 31 +#define HIB_MIS_WC_BIT 4 +#define HIB_CALCTL_CALEN_BIT 0 +#define HIB_CALCTL_CAL24_BIT 2 + +#define WRC !check_reg_bit( registers.hib_ctl, HIB_CTL_WRC_BIT ) +#define WC !check_reg_bit( registers.hib_mis, HIB_MIS_WC_BIT ) + +#define MASK_SECOND 0x0000003F +#define MASK_MINUTE 0x00003F00 +#define MASK_HOUR 0x001f0000 +#define MASK_DAY_MONTH 0x0000001F +#define MASK_MONTH 0x00000F00 +#define MASK_YEAR 0x007f0000 + +#define GET_SECOND time_second % 60 +#define GET_HOUR time_second / 3600 +#define GET_MINUTE time_second / 60 - GET_HOUR * 60 + +#define SET_TIME (uint32_t)time->hour * 3600 + (uint32_t)time->minute * 60 + (uint32_t)time->second + +#define SECOND_IN_ONE_DAY 86400 + +#define RESET 0x00000000 +#define LOCK_KEY 0xA3359554 +#define SOFTWARE_RESET_KEY 0x05FA0004 + +/** + * @brief Writes specified value to + * specified register. + * + * @param[in] reg - register address. + * @param[in] _val - Value to be written. + */ +#define write_reg(reg,_val) (selected_reg(reg) = (_val)) + +/** + * @brief Returns value stored + * in a register. + * + * @param[in] reg - register address. + * + * @return Register(reg) value. + */ +#define read_reg(reg) (selected_reg(reg)) + +typedef struct +{ + hal_ll_base_addr_t* sysctl_rcgchib; + hal_ll_base_addr_t* hib_mis; + hal_ll_base_addr_t* hib_ctl; + hal_ll_base_addr_t* hib_im; + hal_ll_base_addr_t* hib_rtcld; + hal_ll_base_addr_t* nvic_apint; + hal_ll_base_addr_t* hib_rtcc; + hal_ll_base_addr_t* hib_lock; +} reg_t; + +reg_t registers = { SYSCTL_RCGCHIB_REG_ADDRESS, HIB_MIS_REG_ADDRESS, HIB_CTL_REG_ADDRESS, HIB_IM_REG_ADDRESS, HIB_RTCLD_REG_ADDRESS, NVIC_AP_REG_ADDRESS, HIB_RTCC_REG_ADDRESS, HIB_LOCK_REG_ADDRESS }; + +#ifdef __GNUC__ + +/** + * @brief Initialize the RTC module. + * @details Initialize the RTC module. + * @param None. + */ +void __attribute__ ((weak)) hal_ll_rtc_init(); + +/** + * @brief Start the RTC module. + * @details Continue the RTC module count from the stored value in the counter register. + * @param None. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + */ +err_t __attribute__ ((weak)) hal_ll_rtc_start(); + +/** + * @brief Stop the RTC module. + * @details Stop the RTC module count. + * @param None. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + */ +err_t __attribute__ ((weak)) hal_ll_rtc_stop(); + +/** + * @brief Reset the RTC module. + * @details Reset the RTC counter to the default values of 0h:0m:0s. + * @param None. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + */ +err_t __attribute__ ((weak)) hal_ll_rtc_reset(); + +/** + * @brief Configure time of RTC module. + * @details Configure time registers with the values from hal_ll_rtc_time_t structure. + * @param time hal_ll_rtc_time_t structure. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + */ +err_t __attribute__ ((weak)) hal_ll_rtc_set_time( hal_ll_rtc_time_t *time ); + +/** + * @brief Get time and date. + * @details Configure hal_ll_rtc_time_t structure with the values from time registers. + * @param time hal_ll_rtc_time_t structure. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + */ +err_t __attribute__((weak)) hal_ll_rtc_get_time( hal_ll_rtc_time_t *rtc ); + +/** + * @brief Preforms system reset. + * @details Resets the core and all on-chip peripherals except the Debug + * interface. + * @param None. + * @warning System reset affects core and periferals, + * depending on the architecture you will need to reconfigure opened modules. + */ +void __attribute__ ((weak)) hal_ll_rtc_system_reset(); + +#endif + +void hal_ll_rtc_init() { + set_reg_bit( registers.sysctl_rcgchib, SYSCTL_RCGCHIB_R0_BIT ); + if ( !check_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN ) ) { + set_reg_bit( registers.hib_im, HIB_IM_WC_BIT ); + while ( WRC ); + set_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN_BIT ); + while ( WC ); + } +} + +err_t hal_ll_rtc_start() { + while ( WRC ); + set_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ); + while ( WRC ); + if ( check_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ) ) { + return HAL_LL_RTC_SUCCESS; + } + return HAL_LL_RTC_ERROR; +} + +err_t hal_ll_rtc_stop() { + while ( WRC ); + clear_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ); + while ( WRC ); + if ( check_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ) ) { + return HAL_LL_RTC_ERROR; + } + return HAL_LL_RTC_SUCCESS; +} + +err_t hal_ll_rtc_reset() { + if ( !check_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN_BIT ) ) { + return HAL_LL_RTC_ERROR; + } + if ( HAL_LL_RTC_ERROR == hal_ll_rtc_stop() ) { + return HAL_LL_RTC_ERROR; + } + if ( registers.hib_lock ) { + write_reg( registers.hib_lock, LOCK_KEY ); + } + while ( WRC ); + write_reg( registers.hib_rtcld, RESET ); + if ( HAL_LL_RTC_ERROR == hal_ll_rtc_start() ) { + return HAL_LL_RTC_ERROR; + } + return HAL_LL_RTC_SUCCESS; +} + +err_t hal_ll_rtc_set_time( hal_ll_rtc_time_t *time ) { + uint32_t value; + if ( !check_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN_BIT ) ) { + return HAL_LL_RTC_ERROR; + } + if ( HAL_LL_RTC_ERROR == hal_ll_rtc_stop() ) { + return HAL_LL_RTC_ERROR; + } + if ( registers.hib_lock ) { + write_reg( registers.hib_lock, LOCK_KEY ); + } + value = SET_TIME; + while ( WRC ); + write_reg( registers.hib_rtcld, value ); + while ( WRC ); + if ( read_reg( registers.hib_rtcc ) != value ) { + return HAL_LL_RTC_ERROR; + } + if ( HAL_LL_RTC_ERROR == hal_ll_rtc_start() ) { + return HAL_LL_RTC_ERROR; + } + return HAL_LL_RTC_SUCCESS; +} + +err_t hal_ll_rtc_get_time( hal_ll_rtc_time_t *time ) { + uint32_t time_second = read_reg( registers.hib_rtcc ); + if ( registers.hib_lock ) { + write_reg( registers.hib_lock, LOCK_KEY ); + } + while ( time_second >= SECOND_IN_ONE_DAY ) { + while ( WRC ); + write_reg( registers.hib_rtcld, time_second - SECOND_IN_ONE_DAY ); + while ( WRC ); + time_second = read_reg( registers.hib_rtcc ); + } + time->second = GET_SECOND; + time->minute = GET_MINUTE; + time->hour = GET_HOUR; + return HAL_LL_RTC_SUCCESS; +} + +void hal_ll_rtc_system_reset() { + write_reg( registers.nvic_apint, SOFTWARE_RESET_KEY ); +} diff --git a/targets/arm/mikroe/renesas/src/rtc/implementation_2/hal_ll_rtc.c b/targets/arm/mikroe/renesas/src/rtc/implementation_2/hal_ll_rtc.c new file mode 100644 index 0000000000..54b8c57b39 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/rtc/implementation_2/hal_ll_rtc.c @@ -0,0 +1,265 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rtc.c + * @brief Rtc HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rtc.h" + +/** + * Return values + */ +typedef enum +{ + HAL_LL_RTC_SUCCESS = 0, + HAL_LL_RTC_ERROR = (-1) +} hal_ll_rtc_err_t; + +#define SYSCTL_RCGCHIB_R0_BIT 0 +#define HIB_IM_WC_BIT 4 +#define HIB_CTL_RTCEN_BIT 0 +#define HIB_CTL_CLK32EN_BIT 6 +#define HIB_CTL_WRC_BIT 31 +#define HIB_MIS_WC_BIT 4 +#define HIB_CALCTL_CALEN_BIT 0 +#define HIB_CALCTL_CAL24_BIT 2 + +#define WRC !check_reg_bit( registers.hib_ctl, HIB_CTL_WRC_BIT ) +#define WC !check_reg_bit( registers.hib_mis, HIB_MIS_WC_BIT ) + +#define MASK_SECOND 0x0000003F +#define MASK_MINUTE 0x00003F00 +#define MASK_HOUR 0x001f0000 +#define MASK_DAY_MONTH 0x0000001F +#define MASK_MONTH 0x00000F00 +#define MASK_YEAR 0x007f0000 + +#define GET_SECOND time_second % 60 +#define GET_MINUTE time_second / 60 - GET_HOUR * 60 +#define GET_HOUR time_second / 3600 + +#define SET_TIME (uint32_t)time->hour * 3600 + (uint32_t)time->minute * 60 + (uint32_t)time->second + +#define SECOND_IN_ONE_DAY 86400 + +#define RESET 0x00000000 +#define SOFTWARE_RESET_KEY 0x05FA0004 + +/** + * @brief Writes specified value to + * specified register. + * + * @param[in] reg - register address. + * @param[in] _val - Value to be written. + */ +#define write_reg(reg,_val) (selected_reg(reg) = (_val)) + +/** + * @brief Returns value stored + * in a register. + * + * @param[in] reg - register address. + * + * @return Register(reg) value. + */ +#define read_reg(reg) (selected_reg(reg)) + +typedef struct +{ + hal_ll_base_addr_t* sysctl_rcgchib; + hal_ll_base_addr_t* hib_mis; + hal_ll_base_addr_t* hib_ctl; + hal_ll_base_addr_t* hib_im; + hal_ll_base_addr_t* hib_rtcld; + hal_ll_base_addr_t* nvic_apint; + hal_ll_base_addr_t* hib_rtcc; +} reg_t; + +reg_t registers = { SYSCTL_RCGCHIB_REG_ADDRESS, HIB_MIS_REG_ADDRESS, HIB_CTL_REG_ADDRESS, HIB_IM_REG_ADDRESS, HIB_RTCLD_REG_ADDRESS, NVIC_AP_REG_ADDRESS, HIB_RTCC_REG_ADDRESS }; + +#ifdef __GNUC__ + +/** + * @brief Initialize the RTC module. + * @details Initialize the RTC module. + * @param None. + */ +void __attribute__ ((weak)) hal_ll_rtc_init(); + +/** + * @brief Start the RTC module. + * @details Continue the RTC module count from the stored value in the counter register. + * @param None. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + */ +err_t __attribute__ ((weak)) hal_ll_rtc_start(); + +/** + * @brief Stop the RTC module. + * @details Stop the RTC module count. + * @param None. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + */ +err_t __attribute__ ((weak)) hal_ll_rtc_stop(); + +/** + * @brief Reset the RTC module. + * @details Reset the RTC counter to the default values of 0h:0m:0s. + * @param None. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + */ +err_t __attribute__ ((weak)) hal_ll_rtc_reset(); + +/** + * @brief Configure time of RTC module. + * @details Configure time registers with the values from hal_ll_rtc_time_t structure. + * @param time hal_ll_rtc_time_t structure. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + */ +err_t __attribute__ ((weak)) hal_ll_rtc_set_time( hal_ll_rtc_time_t *time ); + +/** + * @brief Get time and date. + * @details Configure hal_ll_rtc_time_t structure with the values from time registers. + * @param time hal_ll_rtc_time_t structure. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + */ +err_t __attribute__((weak)) hal_ll_rtc_get_time( hal_ll_rtc_time_t *rtc ); + +/** + * @brief Preforms system reset. + * @details Resets the core and all on-chip peripherals except the Debug + * interface. + * @param None. + * @warning System reset affects core and periferals, + * depending on the architecture you will need to reconfigure opened modules. + */ +void __attribute__ ((weak)) hal_ll_rtc_system_reset(); + +#endif + +void hal_ll_rtc_init() { + set_reg_bit( registers.sysctl_rcgchib, SYSCTL_RCGCHIB_R0_BIT ); + if ( !check_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN ) ) { + set_reg_bit( registers.hib_im, HIB_IM_WC_BIT ); + while ( WRC ); + set_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN_BIT ); + while ( WC ); + } +} + +err_t hal_ll_rtc_start() { + while ( WRC ); + set_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ); + while ( WRC ); + if ( check_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ) ) { + return HAL_LL_RTC_SUCCESS; + } + return HAL_LL_RTC_ERROR; +} + +err_t hal_ll_rtc_stop() { + while ( WRC ); + clear_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ); + while ( WRC ); + if ( check_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ) ) { + return HAL_LL_RTC_ERROR; + } + return HAL_LL_RTC_SUCCESS; +} + +err_t hal_ll_rtc_reset() { + if ( !check_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN_BIT ) ) { + return HAL_LL_RTC_ERROR; + } + if ( HAL_LL_RTC_ERROR == hal_ll_rtc_stop() ) { + return HAL_LL_RTC_ERROR; + } + while ( WRC ); + write_reg( registers.hib_rtcld, RESET ); + if ( HAL_LL_RTC_ERROR == hal_ll_rtc_start() ) { + return HAL_LL_RTC_ERROR; + } + return HAL_LL_RTC_SUCCESS; +} + +err_t hal_ll_rtc_set_time( hal_ll_rtc_time_t *time ) { + uint32_t value; + if ( !check_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN_BIT ) ) { + return HAL_LL_RTC_ERROR; + } + if ( HAL_LL_RTC_ERROR == hal_ll_rtc_stop() ) { + return HAL_LL_RTC_ERROR; + } + value = SET_TIME; + while ( WRC ); + write_reg( registers.hib_rtcld, value ); + while ( WRC ); + if ( read_reg( registers.hib_rtcc ) != value ) { + return HAL_LL_RTC_ERROR; + } + if ( HAL_LL_RTC_ERROR == hal_ll_rtc_start() ) { + return HAL_LL_RTC_ERROR; + } + return HAL_LL_RTC_SUCCESS; +} + +err_t hal_ll_rtc_get_time( hal_ll_rtc_time_t *time ) { + uint32_t time_second = read_reg( registers.hib_rtcc ); + while ( time_second >= SECOND_IN_ONE_DAY ) { + while ( WRC ); + write_reg( registers.hib_rtcld, time_second - SECOND_IN_ONE_DAY ); + while ( WRC ); + time_second = read_reg( registers.hib_rtcc ); + } + time->second = GET_SECOND; + time->minute = GET_MINUTE; + time->hour = GET_HOUR; + return HAL_LL_RTC_SUCCESS; +} + +void hal_ll_rtc_system_reset() { + write_reg( registers.nvic_apint, SOFTWARE_RESET_KEY ); +} diff --git a/targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt b/targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt new file mode 100644 index 0000000000..07cbb37ff6 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt @@ -0,0 +1,65 @@ +## ./targets/arm/mikroe/tiva/src/spi_master/CMakeLists.txt +set(hal_ll_def_list "") +set(MCU_NAME_FIRST_7 "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) +string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) +list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +# BEGIN SPI +list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") + +set( spi_subimplementation "implementation_1/hal_ll_spi_master.c" ) +set( spi_pin_map "hal_ll_spi_master_pin_map/implementation_1" ) +# END SPI + +mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master + ${spi_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN SPI + ../../include/spi_master/hal_ll_spi_master.h + ../../include/spi_master/${spi_pin_map}/hal_ll_spi_master_pin_map.h + # END SPI +) + +target_compile_definitions(lib_hal_ll_spi_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_spi_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_spi_master + PRIVATE + ../../include + ../../include/gpio + # BEGIN SPI + ../../include/spi_master + ../../include/spi_master/${spi_pin_map} + # END SPI + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h) diff --git a/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c b/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c new file mode 100644 index 0000000000..76bdca45fd --- /dev/null +++ b/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c @@ -0,0 +1,784 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[ SPI_MODULE_COUNT ] = { ( handle_t * )NULL, ( handle_t * )NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ( ( hal_ll_spi_master_handle_register_t * )*handle ) +/*!< @brief Helper macro for getting module specific control register structure base address */ +#define hal_ll_spi_master_get_handle ( hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct( _handle ) ( ( hal_ll_spi_master_base_handle_t * )_handle ) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ( ( hal_ll_spi_master_hw_specifics_map_t * )( ( hal_ll_spi_master_handle_register_t * )\ + ( ( ( hal_ll_spi_master_handle_register_t * )( handle ) )->hal_ll_spi_master_handle ) )->hal_ll_spi_master_handle )->base + +/*!< @brief SSI mode constants. */ +#define HAL_LL_SPI_MASTER_CLK_POLARITY (6) +#define HAL_LL_SPI_MASTER_CLK_PHASE (7) + +/*!< @brief SSI enable constants. */ +#define HAL_LL_SPI_SSI_ENABLE (1) +#define HAL_LL_SPI0_ENABLE (0) +#define HAL_LL_SPI1_ENABLE (1) +#define HAL_LL_SPI2_ENABLE (2) +#define HAL_LL_SPI3_ENABLE (3) + +/*!< @brief Status register bit check. */ +#define HAL_LL_SPI1_FIFO_NOT_EMPTY (2) + +/*!< @brief General constants. */ +#define HAL_LL_SPI_CLK_POLARITY (1) +#define HAL_LL_SPI_CLK_PHASE (0) + +/*!< @brief Default SPI Master bit-rate if no speed is set. */ +#define HAL_LL_SPI_MASTER_SPEED_100K (100000) + +/*!< @brief Data transfer mode. */ +#define HAL_LL_SPI_8_BIT (0x7) + +/*!< @brief Alternate function config macros. */ +#define HAL_LL_SPI_AF_CONFIG_SCK (GPIO_CFG_DIGITAL_OUTPUT | GPIO_CFG_ALT_FUNCTION) +#define HAL_LL_SPI_AF_CONFIG_MOSI (GPIO_CFG_DIGITAL_OUTPUT | GPIO_CFG_ALT_FUNCTION) +#define HAL_LL_SPI_AF_CONFIG_MISO (GPIO_CFG_DIGITAL_INPUT | GPIO_CFG_ALT_FUNCTION) + +/*!< @brief Helper macro for retrieving end-user's selected frequency. */ +#define _fosc (Get_Fosc_kHz()*1000ul) + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI Master hw specific error values. */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr0; // QSSI module Control 0 Register. + uint32_t cr1; // QSSI module Control 1 Register. + uint32_t dr; // QSSI module Data read Register. + uint32_t ssisr; // QSSI module Status Register. + uint32_t cpsdvsr; // QSSI module Clock prescale divisor Register. + uint32_t ssiim; // QSSI module Interrupt Mask Register. + uint32_t ssiris; // QSSI module Raw Interrupt Status Register. + uint32_t ssimis; // QSSI module Masked Interrupt Status Register. + uint32_t ssiicr; // QSSI module Interrupt Clear Register. + uint32_t ssidmactl; // QSSI module DMA control Register. + /* Commented out for memory optimization; + * Uncomment if needed. + */ + // uint32_t __unused1[998];// Reserved memory space. + // uint32_t ssipp; // QSSI module Peripheral properties Register. + // uint32_t __unused2; // Reserved memory space. + // uint32_t ssicc; // QSSI module Clock configuration Register. + // uint32_t __unused3[6]; // Reserved memory space. + // uint32_t ssipid4; // QSSI module Peripheral ID 4. + // uint32_t ssipid5; // QSSI module Peripheral ID 5. + // uint32_t ssipid6; // QSSI module peripheral ID 6. + // uint32_t ssipid7; // QSSI module peripheral ID 7. + // uint32_t ssipid0; // QSSI module peripheral ID 0. + // uint32_t ssipid1; // QSSI module peripheral ID 1. + // uint32_t ssipid2; // QSSI module peripheral ID 2. + // uint32_t ssipid3; // QSSI module peripheral ID 3. + // uint32_t ssipcd0; // QSSI module prime cell ID 0. + // uint32_t ssipcd1; // QSSI prime cell ID 1. + // uint32_t ssipcd2; // QSSI prime cell ID 2. + // uint32_t ssipcd3; // QSSI prime cell ID 3. +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific module values. */ +typedef struct { + uint8_t pin_miso; + uint8_t pin_mosi; + uint8_t pin_sck; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hardware specific structure. */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions. */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +/*!< @brief SPI Master hardware specific info. */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[ SPI_MODULE_COUNT + 1 ] = { + #ifdef SPI_MODULE_0 + { HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT }, + #endif + #ifdef SPI_MODULE_1 + { HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT }, + #endif + #ifdef SPI_MODULE_2 + { HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT }, + #endif + #ifdef SPI_MODULE_3 + { HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT }, + #endif + + { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, 0, 0, 0 } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address. + * @param[out] *handle_map - Pointer to local handle list. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t _hal_ll_spi_master_check_pins( hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Enable clock for SPI module on hardware level. + * + * Initializes SPI module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @return None + */ +static void _hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *_hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void _hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ); + +/** + * @brief Initialize hardware SPI module. + * + * @param[in] *map - Object specific context handler. + * @return None + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void _hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map ); + +/** + * @brief Transfer function used in read and write bare metal. + * + * Performs a dummy read/write, and then the real transfer for + * read and write. + * + * @param[in] *hal_ll_hw_register - Registers defined + * in the program. + * @param[in] data_buffer - Data which is going to be tranfered. + * @return - None + */ +uint8_t _hal_ll_spi_master_transfer( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer ); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void _hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data, size_t write_data_size ); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + */ +static void _hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data ); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void _hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Enables or disables SPI module 0 clock. + * @param hal_ll_state - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_spi_master0_set_clock ( bool hal_ll_state ); + +/** + * @brief Enables or disables SPI module 1 clock. + * @param hal_ll_state - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_spi_master1_set_clock ( bool hal_ll_state ); + +/** + * @brief Enables or disables SPI module 2 clock. + * @param hal_ll_state - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_spi_master2_set_clock ( bool hal_ll_state ); + +/** + * @brief Enables or disables SPI module 3 clock. + * @param hal_ll_state - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_spi_master3_set_clock ( bool hal_ll_state ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * + * @return None + */ +static void _hal_ll_spi_master_map_pins( uint8_t module_index, hal_ll_spi_pin_id *index_list ); + +/** + * @brief Configures SPI mode. + * + * Sets adequate Clock Polarity and Clock Phase settings + * based on @mode parameter. + * + * @param[in] *hal_ll_hw_register - Registers defined + * in the program. + * @param[in] mode - User-defined SPI mode property. + * + * @return None + */ +static void _hal_ll_spi_master_mode_selection( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, hal_ll_spi_master_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_spi_master_register_handle( hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + hal_ll_spi_pin_id index_list[ SPI_MODULE_COUNT ] = { HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC }; + uint16_t pin_check_result; + + // Check user-defined pins. + if ( ( pin_check_result = _hal_ll_spi_master_check_pins( sck, miso, mosi, &index_list, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ( ( hal_ll_spi_master_hw_specifics_map[ pin_check_result ].pins.sck.pin_name != sck ) || + ( hal_ll_spi_master_hw_specifics_map[ pin_check_result ].pins.miso.pin_name != miso ) || + ( hal_ll_spi_master_hw_specifics_map[ pin_check_result ].pins.mosi.pin_name != mosi ) ) { + + _hal_ll_spi_master_alternate_functions_set_state( &hal_ll_spi_master_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_spi_master_map_pins( pin_check_result, &index_list ); + + _hal_ll_spi_master_alternate_functions_set_state( &hal_ll_spi_master_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle = ( handle_t * )&hal_ll_spi_master_hw_specifics_map[ pin_check_result ].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[ pin_check_result ].hal_ll_spi_master_handle = ( handle_t* )&hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi( handle_t *handle ) { + hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + _hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle = ( handle_t * )&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data( handle_t *handle, uint8_t dummy_data ) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + if( hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write( handle_t *handle, uint8_t *write_data_buffer, size_t length_data ) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + _hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data ); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read( handle_t *handle, uint8_t *read_data_buffer, size_t length_data ) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + _hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data ); + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data ) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + _hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data ); + + _hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data ); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed( handle_t *handle, uint32_t speed ) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + _hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode( handle_t *handle, hal_ll_spi_master_mode_t mode ) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + _hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close( handle_t* handle ) { + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + if( low_level_handle->hal_ll_spi_master_handle != NULL ) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + _hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_local, true ); + _hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_local, false ); + _hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_local, false ); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_pin_name_t _hal_ll_spi_master_check_pins( hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ) { + static uint16_t sck_map_size = ( sizeof( _spi_sck_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) ); + static uint16_t miso_map_size = ( sizeof( _spi_miso_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) ); + static uint16_t mosi_map_size = ( sizeof( _spi_mosi_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) ); + + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for( sck_index = 0; sck_index < sck_map_size; sck_index++ ) { + if( _spi_sck_map[ sck_index ].pin == sck_pin ) { + for( miso_index = 0; miso_index < miso_map_size; miso_index++ ) { + if( _spi_miso_map[ miso_index ].pin == miso_pin ) { + if( _spi_sck_map[ sck_index ].module_index == _spi_miso_map[ miso_index ].module_index ) { + for( mosi_index = 0; mosi_index < mosi_map_size; mosi_index++ ) { + if( _spi_mosi_map[ mosi_index ].pin == mosi_pin ) { + if( _spi_sck_map[ sck_index ].module_index == _spi_mosi_map[ mosi_index ].module_index ) { + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + index_list[ hal_ll_module_id ].pin_sck = sck_index; + index_list[ hal_ll_module_id ].pin_miso = miso_index; + index_list[ hal_ll_module_id ].pin_mosi = mosi_index; + + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +static hal_ll_spi_master_hw_specifics_map_t *_hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_spi_master_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_spi_master_handle_register_t ) ); + + while ( hal_ll_module_count-- ) { + if ( hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[ hal_ll_module_count ].base ) { + return &hal_ll_spi_master_hw_specifics_map[ hal_ll_module_count ]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_spi_master_map_pins( uint8_t module_index, hal_ll_spi_pin_id *index_list ) { + // If every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.sck.pin_name = _spi_sck_map[ index_list[ module_index ].pin_sck ].pin; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.miso.pin_name = _spi_miso_map[ index_list[ module_index ].pin_miso ].pin; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.mosi.pin_name = _spi_mosi_map[ index_list[ module_index ].pin_mosi ].pin; + + //SCK, MISO and MOSI pin could have different alternate function settings, hence save all of the AF-s. + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.sck.pin_af = _spi_sck_map[ index_list[ module_index ].pin_sck ].af; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.miso.pin_af = _spi_miso_map[ index_list[ module_index ].pin_miso ].af; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.mosi.pin_af = _spi_mosi_map[ index_list[ module_index ].pin_mosi ].af; +} + +static void _hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( ( map->pins.sck.pin_name != HAL_LL_PIN_NC ) && ( map->pins.miso.pin_name != HAL_LL_PIN_NC ) && ( map->pins.mosi.pin_name != HAL_LL_PIN_NC ) ) { + module.pins[ 0 ] = VALUE( map->pins.sck.pin_name, map->pins.sck.pin_af ); + module.pins[ 1 ] = VALUE( map->pins.mosi.pin_name, map->pins.mosi.pin_af ); + module.pins[ 2 ] = VALUE( map->pins.miso.pin_name, map->pins.miso.pin_af ); + module.pins[ 3 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = HAL_LL_SPI_AF_CONFIG_SCK; + module.configs[ 1 ] = HAL_LL_SPI_AF_CONFIG_MOSI; + module.configs[ 2 ] = HAL_LL_SPI_AF_CONFIG_MISO; + module.configs[ 3 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ) { + switch( map->module_index ) { + #if defined ( SPI_MODULE_0 ) + case ( hal_ll_spi_master_module_num( SPI_MODULE_0 ) ): + _hal_ll_spi_master0_set_clock( hal_ll_state ); + break; + #endif + #if defined ( SPI_MODULE_1 ) + case ( hal_ll_spi_master_module_num( SPI_MODULE_1 ) ): + _hal_ll_spi_master1_set_clock( hal_ll_state ); + break; + #endif + #if defined ( SPI_MODULE_2 ) + case ( hal_ll_spi_master_module_num( SPI_MODULE_2 ) ): + _hal_ll_spi_master2_set_clock( hal_ll_state ); + break; + #endif + #if defined ( SPI_MODULE_3 ) + case ( hal_ll_spi_master_module_num( SPI_MODULE_3 ) ): + _hal_ll_spi_master3_set_clock( hal_ll_state ); + break; + #endif + + default: + break; + } +} + +static inline void _hal_ll_spi_master0_set_clock ( bool hal_ll_state ) { + // Check hal_ll_state, and set the bit for the clock + hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI0_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI0_ENABLE ); +} + +static inline void _hal_ll_spi_master1_set_clock( bool hal_ll_state ) { + // Check hal_ll_state, and set the bit for the clock + hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI1_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI1_ENABLE ); +} + +static inline void _hal_ll_spi_master2_set_clock( bool hal_ll_state ) { + // Check hal_ll_state, and set the bit for the clock + hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI2_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI2_ENABLE ); +} + +static inline void _hal_ll_spi_master3_set_clock( bool hal_ll_state ) { + // Check hal_ll_state, and set the bit for the clock + hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI3_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI3_ENABLE ); +} + +uint8_t _hal_ll_spi_master_transfer( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer ) { + // Perform a dummy transfer. + volatile uint8_t temp = hal_ll_hw_reg->dr; + + hal_ll_hw_reg->dr = data_buffer; + + // Wait for the transfer to finish. + while( !( check_reg_bit ( &( hal_ll_hw_reg->ssisr ), HAL_LL_SPI1_FIFO_NOT_EMPTY ) ) ); + + return hal_ll_hw_reg->dr; +} + +static void _hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + size_t transfer_counter = 0; + + for ( transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++ ) { + _hal_ll_spi_master_transfer( hal_ll_hw_reg, write_data_buffer[ transfer_counter ] ); + } +} + +static void _hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data ) { + size_t transfer_counter = 0; + + for( transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++ ) { + read_data_buffer[ transfer_counter ] = _hal_ll_spi_master_transfer( hal_ll_hw_reg, dummy_data ); + } +} + +static void _hal_ll_spi_master_mode_selection( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, hal_ll_spi_master_mode_t mode ) { + // Clock Polarity configuration. + if ( mode <= HAL_LL_SPI_MASTER_MODE_1 ) { + // Idle state for the SPI clock is low level (0). + clear_reg_bit( &(hal_ll_hw_reg->cr0), HAL_LL_SPI_MASTER_CLK_POLARITY ); + } else { + // Idle state for the SPI clock is high level (1). + set_reg_bit( &(hal_ll_hw_reg->cr0), HAL_LL_SPI_MASTER_CLK_POLARITY ); + } + + // Clock Phase configuration. + if ( mode == HAL_LL_SPI_MASTER_MODE_0 || mode == HAL_LL_SPI_MASTER_MODE_2 ) { + // Data is captured on the 1st clock edge transition. + clear_reg_bit( &(hal_ll_hw_reg->cr0), HAL_LL_SPI_MASTER_CLK_PHASE ); + } else { + // Data is captured on the 2nd clock edge transition. + set_reg_bit( &(hal_ll_hw_reg->cr0), HAL_LL_SPI_MASTER_CLK_PHASE ); + } +} + +static void _hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map ) { + uint32_t bitrate; + uint32_t scaler = 0; + uint32_t prescaler = 0; + uint32_t min_diff = 0xFFFFFFFF; + uint16_t scaler_counter, prescaler_value; + bool appropriate_baud_rate_found = false; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = ( hal_ll_spi_master_base_handle_t* ) map->base; + + // Set 8bit transfer mode. + hal_ll_hw_reg->cr0 = HAL_LL_SPI_8_BIT; + + // SPI Mode selection process. + _hal_ll_spi_master_mode_selection( map->base, map->mode ); + + for ( scaler_counter = 2; scaler_counter < 255; scaler_counter += 2 ) { + for ( prescaler_value = 0; prescaler_value < 256; prescaler_value++ ) { + bitrate = _fosc / ( scaler_counter * ( 1 + prescaler_value ) ); + if ( map->speed >= bitrate ) { + uint32_t diff = map->speed - bitrate; + if ( min_diff > diff ) { + min_diff = diff; + prescaler = prescaler_value; + scaler = scaler_counter; + appropriate_baud_rate_found = true; + break; + } + } + } + + if( appropriate_baud_rate_found ) { + break; + } + } + // Saving scale and prescale values. + hal_ll_hw_reg->cr0 |= ( prescaler << 8 ); + hal_ll_hw_reg->cpsdvsr = scaler; + + // Enable the SSI module. + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_SPI_SSI_ENABLE ); + + // Memorize final hardware SPI speed. + hal_ll_spi_master_hw_specifics_map->hw_actual_speed = bitrate; +} + +static void _hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ) { + //Enable specific clock module. + _hal_ll_spi_master_set_clock( map, true ); + + //Enable specific alternate functions. + _hal_ll_spi_master_alternate_functions_set_state( map, true ); + + //Finally, write user-defined settings into hardware registers. + _hal_ll_spi_master_hw_init( map ); +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/tim/CMakeLists.txt b/targets/arm/mikroe/renesas/src/tim/CMakeLists.txt new file mode 100644 index 0000000000..3cfad235a8 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/tim/CMakeLists.txt @@ -0,0 +1,64 @@ +## ./targets/arm/mikroe/tiva/src/tim/CMakeLists.txt +set(hal_ll_def_list "") +set(MCU_NAME_FIRST_7 "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) +string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) +list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +# BEGIN TIM +list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") +set( tim_subimplementation "implementation_1/hal_ll_tim.c" ) +set( tim_pin_map "hal_ll_tim_pin_map/implementation_1" ) +# END TIM + +mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM + ${tim_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN TIM + ../../include/tim/hal_ll_tim.h + ../../include/tim/${tim_pin_map}/hal_ll_tim_pin_map.h + # END TIM +) + +target_compile_definitions(lib_hal_ll_tim PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_tim PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_tim + PRIVATE + ../../include + ../../include/gpio + # BEGIN TIM + ../../include/tim + ../../include/tim/${tim_pin_map} + # END TIM + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.TIM) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h) diff --git a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c new file mode 100644 index 0000000000..7f463cc74f --- /dev/null +++ b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c @@ -0,0 +1,1056 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_gpio.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +/*!< @brief Helper macros for choosing CCP based on pin parity. */ +#define HAL_LL_TIM_CCP_0 (0) +#define HAL_LL_TIM_CCP_1 (1) + +/*!< @brief Helper macros for getting TIMER clocks operational. */ +#define HAL_LL_TIM_RCGCTIMER_T0 (0) +#define HAL_LL_TIM_RCGCTIMER_T1 (1) +#define HAL_LL_TIM_RCGCTIMER_T2 (2) +#define HAL_LL_TIM_RCGCTIMER_T3 (3) +#define HAL_LL_TIM_RCGCTIMER_T4 (4) +#define HAL_LL_TIM_RCGCTIMER_T5 (5) +#define HAL_LL_TIM_RCGCTIMER_T6 (6) +#define HAL_LL_TIM_RCGCTIMER_T7 (7) + +/*!< @brief Helper macro for getting TIMER clock in on/off state - TIMER A. */ +#define HAL_LL_TIM_CTL_TAEN (0) + +/*!< @brief Helper macro for PWM Output Level (output non-inverted/inverted) - TIMER A. */ +#define HAL_LL_TIM_CTL_TAPWML (6) + +/*!< @brief Helper macro for applying PWM mode in TIMER A module. */ +#define HAL_LL_TIM_TAMR_TAAMS (3) + +/*!< @brief Helper macro for getting TIMER clock in on/off state - TIMER B. */ +#define HAL_LL_TIM_CTL_TBEN (8) + +/*!< @brief Helper macro for PWM Output Level (output non-inverted/inverted) - TIMER A. */ +#define HAL_LL_TIM_CTL_TBPWML (14) + +/*!< @brief Helper macro for applying PWM mode in TIMER B module. */ +#define HAL_LL_TIM_TBMR_TBAMS (3) + +/*!< @brief Helper macro for configuring TIMER module as a 16-bit timer. */ +#define HAL_LL_TIM_CFG_SET_16BIT_TIMER (4) + +/*!< @brief Helper macro for configuring basic TIMER module settings for PWM capability. */ +#define HAL_LL_TIM_PWM_MODE (10) + +/*!< @brief Helper macro for cleaning global operation of General Purpose Timer Module Register. */ +#define HAL_LL_TIM_CLEAN_GLOBAL_TIM_CONFIG (7) + +/*!< @brief Helper macro for cleaning General Purpose Timer Module Mode Register. */ +#define HAL_LL_TIM_CLEAN_MODE_TIM_CONFIG (15) + +/*!< @brief Helper macro for regulating configuration of duty cycle. */ +#define HAL_LL_TIM_REG_CLEAN_MASK1 (0xFF) +#define HAL_LL_TIM_REG_CLEAN_MASK2 (0xFFFF) + +/*!< @brief Helper macro for retrieving user-defined MCU (Necto Setups Wizard) frequency. */ +#define _fosc ( Get_Fosc_kHz() * 1000 ) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM hw specific error values. */ +typedef enum { + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +/*!< @brief TIM hw specific config structure. */ +typedef struct { + hal_ll_pin_name_t pin; + uint8_t pin_parity; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific pin parity pointers to functions. */ +typedef struct { + void ( *mapped_function_duty )( struct hal_ll_tim_base_handle_t *, uint32_t, uint32_t ); + void ( *mapped_function_signal_start )( struct hal_ll_tim_base_handle_t * ); + void ( *mapped_function_signal_stop )( struct hal_ll_tim_base_handle_t * ); + void ( *mapped_function_period )( struct hal_ll_tim_base_handle_t *, uint32_t ); + void ( *mapped_function_hw_init_control )( struct hal_ll_tim_base_handle_t * ); + void ( *mapped_function_hw_init_pwm_mode )( struct hal_ll_tim_base_handle_t * ); +} hal_ll_tim_functions; + +/*!< @brief TIM hw specific structure. */ +typedef struct { + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint32_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; + /* NOTE Added pointer function structure. + * Chips have two CCP's. + */ + hal_ll_tim_functions mapped_functions; +} hal_ll_tim_hw_specifics_map_t; + +typedef struct { + hal_ll_base_addr_t cfg; // General-Purpose Timer Module Config Register. + hal_ll_base_addr_t tamr; // General-Purpose Timer Module timer A Register. + hal_ll_base_addr_t tbmr; // General-Purpose Timer Module timer B Register. + hal_ll_base_addr_t ctl; // General-Purpose Timer Module Control Register. + hal_ll_base_addr_t sync; // General-Purpose Timer Module Sync Register. + hal_ll_base_addr_t __unused1; // Reserved memory space. + hal_ll_base_addr_t imr; // General-Purpose Timer Module Interrupt Mask Register. + hal_ll_base_addr_t ris; // General-Purpose Timer Module Raw Interrupt Status Register. + hal_ll_base_addr_t mis; // General-Purpose Timer Module Masked Interrupt Status Register. + hal_ll_base_addr_t icr; // General-Purpose Timer Module Interrupt Clear Register. + hal_ll_base_addr_t tailr; // General-Purpose Timer Module timer A Interval Load Register. + hal_ll_base_addr_t tbilr; // General-Purpose Timer Module timer B Interval Load Register. + hal_ll_base_addr_t tamatchr; // General-Purpose Timer Module timer A Match Register. + hal_ll_base_addr_t tbmatchr; // General-Purpose Timer Module timer B Match Register. + hal_ll_base_addr_t tapr; // General-Purpose Timer Module timer A Prescale Register. + hal_ll_base_addr_t tbpr; // General-Purpose Timer Module timer B Prescale Register. + hal_ll_base_addr_t tapmr; // General-Purpose Timer Module timer A Prescale Match Register. + hal_ll_base_addr_t tbpmr; // General-Purpose Timer Module timer B Prescale Match Register. + hal_ll_base_addr_t tar; // General-Purpose Timer Module timer A Register. + hal_ll_base_addr_t tbr; // General-Purpose Timer Module timer B Register. + hal_ll_base_addr_t tav; // General-Purpose Timer Module timer A Value Register. + hal_ll_base_addr_t tbv; // General-Purpose Timer Module timer B Value Register. + hal_ll_base_addr_t rtcpd; // General-Purpose Timer Module RTC Predivide Register. + hal_ll_base_addr_t taps; // General-Purpose Timer Module timer A Prescale Snapshot Register. + hal_ll_base_addr_t tbps; // General-Purpose Timer Module timer B Prescale Snapshot Register. + /* Commented out for memory optimization; + * Uncomment if needed. + */ + // hal_ll_base_addr_t __unused2[2]; // Reserved memory space. + // hal_ll_base_addr_t dmaev; // General-Purpose Timer Module DMA Event Register. + // hal_ll_base_addr_t adcev; // General-Purpose Timer Module ADC Event Register. + // hal_ll_base_addr_t __unused4[979]; // Reserved memory space. + // hal_ll_base_addr_t mpp; // General-Purpose Timer Module Peripheral Properties. + // hal_ll_base_addr_t __unused5; // Reserved memory space. + // hal_ll_base_addr_t mcc; // General-Purpose Timer Module Clock Configuration. +} hal_ll_tim_base_handle_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[ TIM_MODULE_COUNT + 1 ] = { + #ifdef TIM_MODULE_0 + {HAL_LL_TIM0_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_0}, + #endif + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1}, + #endif + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2}, + #endif + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3}, + #endif + #ifdef TIM_MODULE_4 + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4}, + #endif + #ifdef TIM_MODULE_5 + {HAL_LL_TIM5_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_5}, + #endif + #ifdef TIM_MODULE_6 + {HAL_LL_TIM6_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_6}, + #endif + #ifdef TIM_MODULE_7 + {HAL_LL_TIM7_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_7}, + #endif + + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions. */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init. + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index - TIM HW module index -- 0,1,2... + * @param[in] index - Index from the TIM pin map. + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param[in] pin - TIM pre-defined pin name. + * @param[out] index - Output parameter which is used to return pin index within the PIN map. + * @param[out] *handle_map - TIMER HAL low lever handle register. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Sets the TIM PWM period register and prescaler values. + * + * Using max_period from the map parameter it calculates values + * for the period and prescaler registers and modifies them. + * + * @param[in] *map - Object specific context handler. + * + * @return None + */ +static void _hal_ll_tim_set_period( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Enable TIM module gate clock. + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_t* map, bool hal_ll_state ); + +/** + * @brief Enables or disables TIM module 0 clock. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @return none + */ +static void _hal_ll_tim0_set_clock( bool hal_ll_state ); + +/** + * @brief Enables or disables TIM module 1 clock. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @return none + */ +static void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enables or disables TIM module 2 clock. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @return none + */ +static void _hal_ll_tim2_set_clock( bool hal_ll_state ); + +/** + * @brief Enables or disables TIM module 3 clock. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @return none + */ +static void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enables or disables TIM module 4 clock. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @return none + */ +static void _hal_ll_tim4_set_clock( bool hal_ll_state ); + +/** + * @brief Enables or disables TIM module 5 clock. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @return none + */ +static void _hal_ll_tim5_set_clock( bool hal_ll_state ); + +/** + * @brief Enables or disables TIM module 6 clock. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @return none + */ +static void _hal_ll_tim6_set_clock( bool hal_ll_state ); + +/** + * @brief Enables or disables TIM module 7 clock. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @return none + */ +static void _hal_ll_tim7_set_clock( bool hal_ll_state ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Map adequate function addresses. + * + * Function maps adequate function addresses based on] + * pin parity. + * + * @param[in] hal_ll_module_id - Module index. + * @param[in] pin_parity - CCP value (0/1). + * + * @return none + * + */ +static inline void map_pointer_functions( uint8_t hal_ll_module_id, uint8_t pin_parity ); + +/** + * @brief CCP0 duty function. + * + * Function sets duty value for CCP0 pins. + * + * @param[in] *hal_ll_hw_reg - Timer base structure. + * @param[in] duty_cycle_timeout - Duty cycle timeout value. + * @param[in] max_period - Maximum period value. + * + * @return none + * + */ +static inline void ptr_function_timer_a_duty( hal_ll_tim_base_handle_t *hal_ll_hw_reg, + uint32_t duty_cycle_timeout, + uint32_t max_period ); + +/** + * @brief CCP1 duty function. + * + * Function sets duty value for CCP1 pins. + * + * @param[in] *hal_ll_hw_reg - Timer base structure. + * @param[in] duty_cycle_timeout - Duty cycle timeout value. + * @param[in] max_period - Maximum period value. + * + * @return none + * + */ +static inline void ptr_function_timer_b_duty( hal_ll_tim_base_handle_t *hal_ll_hw_reg, + uint32_t duty_cycle_timeout, + uint32_t max_period ); + +/** + * @brief CCP0 start function. + * + * Function starts generating PWM signal on CCP0 pin. + * + * @param[in] *hal_ll_hw_reg - Timer base structure. + * + * @return none + * + */ +static inline void ptr_function_timer_a_start( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief CCP1 start function. + * + * Function starts generating PWM signal on CCP1 pin. + * + * @param[in] *hal_ll_hw_reg - Timer base structure. + * + * @return none + * + */ +static inline void ptr_function_timer_b_start( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief CCP0 stop function. + * + * Function stops PWM signal generation on CCP0 pin. + * + * @param[in] *hal_ll_hw_reg - Timer base structure. + * + * @return none + * + */ +static inline void ptr_function_timer_a_stop( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief CCP1 stop function. + * + * Function stops PWM signal generation on CCP1 pin. + * + * @param[in] *hal_ll_hw_reg - Timer base structure. + * + * @return none + * + */ +static inline void ptr_function_timer_b_stop( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief CCP0 period function. + * + * Function sets adequate period level on CCP0 pin. + * + * @param[in] *hal_ll_hw_reg - Timer base structure. + * @param[in] max_period - Maximum period value. + * + * @return none + * + */ +static inline void ptr_function_timer_a_period( hal_ll_tim_base_handle_t *hal_ll_hw_reg, + uint32_t max_period ); + +/** + * @brief CCP1 period function. + * + * Function sets adequate period level on CCP1 pin. + * + * @param[in] *hal_ll_hw_reg - Timer base structure. + * @param[in] max_period - Maximum period value. + * + * @return none + * + */ +static inline void ptr_function_timer_b_period( hal_ll_tim_base_handle_t *hal_ll_hw_reg, + uint32_t max_period ); + +/** + * @brief CCP0 control init function. + * + * Function sets adequate values in control registers + * for CCP0 pin. + * + * @param[in] *hal_ll_hw_reg - Timer base structure. + * + * @return none + * + */ +static inline void ptr_function_timer_a_hw_init_control( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief CCP1 control init function. + * + * Function sets adequate values in control registers + * for CCP1 pin. + * + * @param[in] *hal_ll_hw_reg - Timer base structure. + * + * @return none + * + */ +static inline void ptr_function_timer_b_hw_init_control( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief CCP0 timer init function. + * + * Function sets adequate values in timer registers + * for CCP0 pin. + * + * @param[in] *hal_ll_hw_reg - Timer base structure. + * + * @return none + * + */ +static inline void ptr_function_timer_a_pwm_mode_set( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief CCP1 timer init function. + * + * Function sets adequate values in timer registers + * for CCP1 pin. + * + * @param[in] *hal_ll_hw_reg - Timer base structure. + * + * @return none + * + */ +static inline void ptr_function_timer_b_pwm_mode_set( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result].config.pin != pin ) { + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + uint32_t period; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + period = ( _fosc ) / freq_hz; + + if ( period > ( UINT16_MAX * UINT8_MAX ) ) { + tmp_freq = ( _fosc ) / ( UINT16_MAX * UINT8_MAX ); + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + hal_ll_tim_hw_specifics_map_local->max_period = UINT16_MAX * UINT8_MAX; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + hal_ll_tim_hw_specifics_map_local->max_period = period; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + _hal_ll_tim_set_period( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + uint32_t duty_cycle_timeout; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + duty_cycle_timeout = hal_ll_tim_hw_specifics_map_local->max_period * ( 1.0 - duty_ratio ); + + (hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_duty) + (hal_ll_tim_hw_specifics_map_local->base, duty_cycle_timeout, hal_ll_tim_hw_specifics_map_local->max_period); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + (hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_signal_start) + (hal_ll_tim_hw_specifics_map_local->base); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + (hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_signal_stop) + (hal_ll_tim_hw_specifics_map_local->base); + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if ( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.pin_parity = HAL_LL_TIM_CCP_0; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + + map_pointer_functions(hal_ll_tim_hw_specifics_map_local->module_index, HAL_LL_TIM_CCP_0); + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state != false ) { + tim_config |= GPIO_CFG_DIGITAL_INPUT | GPIO_CFG_ALT_FUNCTION; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( pin == _tim_map[ pin_num ].pin ) { + // Get module number. + hal_ll_module_id = _tim_map[ pin_num ].module_index; + map_pointer_functions( hal_ll_module_id, pin % 2 ); + + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + hal_ll_tim_hw_specifics_map[ module_index ].config.pin_parity = _tim_map[ index ].pin % 2; +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base ) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + // Enable specific clock module. + _hal_ll_tim_set_clock( map, true ); + + // Enable specific alternate functions. + _hal_ll_tim_alternate_functions_set_state( map, true ); + + // Finally, write user-defined settings into hardware registers. + _hal_ll_tim_hw_init( map ); +} + +static void _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_t* map, bool hal_ll_state ) { + switch (map->module_index) { + #ifdef TIM_MODULE_0 + case ( TIM_MODULE_0 ): + _hal_ll_tim0_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_1 + case ( TIM_MODULE_1 ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_2 + case ( TIM_MODULE_2 ): + _hal_ll_tim2_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_3 + case ( TIM_MODULE_3 ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_4 + case ( TIM_MODULE_4 ): + _hal_ll_tim4_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_5 + case ( TIM_MODULE_5 ): + _hal_ll_tim5_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_6 + case ( TIM_MODULE_6 ): + _hal_ll_tim6_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_7 + case ( TIM_MODULE_7 ): + _hal_ll_tim7_set_clock( hal_ll_state ); + break; + #endif + + default: + break; + } +} + +static void _hal_ll_tim0_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T0 ); + } else { + clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T0); + } +} + +static void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T1 ); + } else { + clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T1); + } +} + +static void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T2 ); + } else { + clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T2); + } +} + +static void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T3 ); + } else { + clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T3); + } +} + +static void _hal_ll_tim4_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T4 ); + } else { + clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T4); + } +} + +static void _hal_ll_tim5_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T5 ); + } else { + clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T5); + } +} + +static void _hal_ll_tim6_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T6 ); + } else { + clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T6); + } +} + +static void _hal_ll_tim7_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T7 ); + } else { + clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T7); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + (hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_hw_init_control) + (hal_ll_tim_hw_specifics_map_local->base); + + hal_ll_hw_reg->cfg &= ~(hal_ll_base_addr_t)( HAL_LL_TIM_CLEAN_GLOBAL_TIM_CONFIG ); + hal_ll_hw_reg->cfg |= (hal_ll_base_addr_t)(HAL_LL_TIM_CFG_SET_16BIT_TIMER); + + (hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_hw_init_pwm_mode) + (hal_ll_tim_hw_specifics_map_local->base); +} + +static void _hal_ll_tim_set_period( hal_ll_tim_hw_specifics_map_t *map ) { + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + (hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_period) + (hal_ll_tim_hw_specifics_map_local->base, hal_ll_tim_hw_specifics_map_local->max_period); +} + +// ---------------------------------------------------- STATIC POINTER FUNCTIONS + +static inline void map_pointer_functions( uint8_t hal_ll_module_id, uint8_t pin_parity ) { + if ( pin_parity ) { + hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_duty = &ptr_function_timer_b_duty; + hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_signal_start = &ptr_function_timer_b_start; + hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_signal_stop = &ptr_function_timer_b_stop; + hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_period = &ptr_function_timer_b_period; + hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_hw_init_control = &ptr_function_timer_b_hw_init_control; + hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_hw_init_pwm_mode = &ptr_function_timer_b_pwm_mode_set; + } else { + hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_duty = &ptr_function_timer_a_duty; + hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_signal_start = &ptr_function_timer_a_start; + hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_signal_stop = &ptr_function_timer_a_stop; + hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_period = &ptr_function_timer_a_period; + hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_hw_init_control = &ptr_function_timer_a_hw_init_control; + hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_hw_init_pwm_mode = &ptr_function_timer_a_pwm_mode_set; + } +} + +static inline void ptr_function_timer_a_duty( hal_ll_tim_base_handle_t *hal_ll_hw_reg, + uint32_t duty_cycle_timeout, + uint32_t max_period ) { + /* Turns PWM off if the duty cycle is 0 (this is done because + * if duty cycle is configured to max_period it will behave the same as max duty - 100%) + */ + if ( duty_cycle_timeout == max_period ) { + clear_reg_bit(&hal_ll_hw_reg->tamr,HAL_LL_TIM_TAMR_TAAMS); + } else { + set_reg_bit(&hal_ll_hw_reg->tamr,HAL_LL_TIM_TAMR_TAAMS); + } + + // Clean TimerA Prescale Match Register. + hal_ll_hw_reg->tapmr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_REG_CLEAN_MASK1 ); + + // Insert appropriate value in this register. + hal_ll_hw_reg->tapmr |= ( hal_ll_base_addr_t )( duty_cycle_timeout >> 16 ) & HAL_LL_TIM_REG_CLEAN_MASK1; + + // Clean TimerA Match Register. + hal_ll_hw_reg->tamatchr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_REG_CLEAN_MASK2 ); + + // Insert appropriate value in this register. + hal_ll_hw_reg->tamatchr |= ( hal_ll_base_addr_t )( duty_cycle_timeout ) & HAL_LL_TIM_REG_CLEAN_MASK2; +} + +static inline void ptr_function_timer_b_duty( hal_ll_tim_base_handle_t *hal_ll_hw_reg, + uint32_t duty_cycle_timeout, + uint32_t max_period ) { + /* Turns PWM off if the duty cycle is 0 (this is done because + * if duty cycle is configured to max_period it will behave the same as max duty - 100%) + */ + if ( duty_cycle_timeout == max_period ) { + clear_reg_bit(&hal_ll_hw_reg->tbmr,HAL_LL_TIM_TBMR_TBAMS); + } else { + set_reg_bit(&hal_ll_hw_reg->tbmr,HAL_LL_TIM_TBMR_TBAMS); + } + + // Clean TimerB Prescale Match Register. + hal_ll_hw_reg->tbpmr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_REG_CLEAN_MASK1 ); + + // Insert appropriate value in this register. + hal_ll_hw_reg->tbpmr |= ( hal_ll_base_addr_t )( duty_cycle_timeout >> 16 ) & HAL_LL_TIM_REG_CLEAN_MASK1; + + // Clean TimerB Match Register. + hal_ll_hw_reg->tbmatchr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_REG_CLEAN_MASK2 ); + + // Insert appropriate value in this register. + hal_ll_hw_reg->tbmatchr |= ( hal_ll_base_addr_t )( duty_cycle_timeout ) & HAL_LL_TIM_REG_CLEAN_MASK2; +} + +static inline void ptr_function_timer_a_start( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { + set_reg_bit( &hal_ll_hw_reg->tamr, HAL_LL_TIM_TAMR_TAAMS ); + set_reg_bit( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TAEN ); +} + +static inline void ptr_function_timer_b_start( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { + set_reg_bit( &hal_ll_hw_reg->tbmr, HAL_LL_TIM_TBMR_TBAMS ); + set_reg_bit( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TBEN ); +} + +static inline void ptr_function_timer_a_stop( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { + clear_reg_bit( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TAEN ); + clear_reg_bit( &hal_ll_hw_reg->tamr, HAL_LL_TIM_TAMR_TAAMS ); +} + +static inline void ptr_function_timer_b_stop( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { + clear_reg_bit( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TBEN ); + clear_reg_bit( &hal_ll_hw_reg->tbmr, HAL_LL_TIM_TBMR_TBAMS ); +} + +static inline void ptr_function_timer_a_period( hal_ll_tim_base_handle_t *hal_ll_hw_reg, + uint32_t max_period ) { + hal_ll_hw_reg->tapr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_REG_CLEAN_MASK1 ); + hal_ll_hw_reg->tapr |= ( max_period >> 16 ) & HAL_LL_TIM_REG_CLEAN_MASK1; + hal_ll_hw_reg->tailr = max_period & HAL_LL_TIM_REG_CLEAN_MASK2; +} + +static inline void ptr_function_timer_b_period( hal_ll_tim_base_handle_t *hal_ll_hw_reg, + uint32_t max_period ) { + hal_ll_hw_reg->tbpr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_REG_CLEAN_MASK1 ); + hal_ll_hw_reg->tbpr |= ( max_period >> 16 ) & HAL_LL_TIM_REG_CLEAN_MASK1; + hal_ll_hw_reg->tbilr = max_period & HAL_LL_TIM_REG_CLEAN_MASK2; +} + +static inline void ptr_function_timer_a_hw_init_control( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { + clear_reg_bit ( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TAEN ); + clear_reg_bit ( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TAPWML ); +} + +static inline void ptr_function_timer_b_hw_init_control( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { + clear_reg_bit ( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TBEN ); + clear_reg_bit ( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TBPWML ); +} + +static inline void ptr_function_timer_a_pwm_mode_set( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->tamr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_CLEAN_MODE_TIM_CONFIG ); + hal_ll_hw_reg->tamr |= ( hal_ll_base_addr_t )( HAL_LL_TIM_PWM_MODE ); +} + +static inline void ptr_function_timer_b_pwm_mode_set( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->tbmr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_CLEAN_MODE_TIM_CONFIG ); + hal_ll_hw_reg->tbmr |= ( hal_ll_base_addr_t )( HAL_LL_TIM_PWM_MODE ); +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/uart/CMakeLists.txt b/targets/arm/mikroe/renesas/src/uart/CMakeLists.txt new file mode 100644 index 0000000000..ec6679bde1 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/uart/CMakeLists.txt @@ -0,0 +1,61 @@ +## ./targets/arm/mikroe/tiva/src/uart/CMakeLists.txt +set(hal_ll_def_list "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +# BEGIN UART +list(APPEND hal_ll_def_list "MACRO_USAGE_UART") +set(uart_subimplementation "implementation_1/hal_ll_uart.c") +set(uart_pin_map "hal_ll_uart_pin_map/implementation_1") +# END UART + +mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART + ${uart_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN UART + ../../include/uart/hal_ll_uart.h + ../../include/uart/${uart_pin_map}/hal_ll_uart_pin_map.h + # END UART +) + +target_compile_definitions(lib_hal_ll_uart PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_uart PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_uart + PRIVATE + ../../include + ../../include/gpio + # BEGIN UART + ../../include/uart + ../../include/uart/${uart_pin_map} + # END UART + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.UART) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h) diff --git a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c new file mode 100644 index 0000000000..c437267534 --- /dev/null +++ b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c @@ -0,0 +1,1286 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[ UART_MODULE_COUNT ] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address. */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address. */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure. */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle. */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Helper macro for UART module sync time */ +#define hal_ll_uart_wait_for_sync(_hal_sync_val) while( _hal_sync_val-- ) assembly(nop) + +/*!< @brief Macros used for calculating actual baud rate value and error value. */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location. */ +#define HAL_LL_UART0EN (0) +#define HAL_LL_UART1EN (1) +#define HAL_LL_UART2EN (2) +#define HAL_LL_UART3EN (3) +#define HAL_LL_UART4EN (4) +#define HAL_LL_UART5EN (5) +#define HAL_LL_UART6EN (6) +#define HAL_LL_UART7EN (7) + +#define HAL_LL_UART_CTL_UARTEN (0) +#define HAL_LL_UART_CTL_FEN (4) +#define HAL_LL_UART_CTL_TXE (8) +#define HAL_LL_UART_CTL_RXE (9) + +#define HAL_LL_UART_IT_RXIM_BIT (4) +#define HAL_LL_UART_IT_TXIM_BIT (5) +#define HAL_LL_UART_IT_OER_BIT (10) + +/*!< @brief Macros defining register bit values. */ +#define HAL_LL_UART_LCRH_MASK (0xFFUL) +#define HAL_LL_UART_CTL_MASK (0xCFBFUL) + +#define HAL_LL_UART_IT_FR_RXFE (0x10UL) +#define HAL_LL_UART_IT_FR_TXFF (0x20UL) + +#define STOP_BITS_MASK (0x8UL) +#define STOP_BITS_ONE (0x0UL) +#define STOP_BITS_TWO (STOP_BITS_MASK) + +#define DATA_BITS_MASK (0x60UL) +#define DATA_BIT_5 (0x0UL) +#define DATA_BIT_6 (0x20UL) +#define DATA_BIT_7 (0x40UL) +#define DATA_BIT_8 (DATA_BITS_MASK) + +#define PARITY_STICK (0x80UL) +#define PARITY_MASK (0x6UL) +#define PARITY_NO (0x0UL) +#define PARITY_EVEN (PARITY_MASK) +#define PARITY_ODD (0x2UL) + +#define HAL_LL_UART_CTL_HSE_BIT (0x20UL) + +#define HAL_LL_UART_ERRORS (0xF00U) +#define HAL_LL_UART_DATA (0xFFU) + +/*!< @brief Macros used for interrupts. */ +#define HAL_LL_UART_IT_CLEAR_MASK (0x360U) +#define HAL_LL_UART_IT_CR1_MASK (0x1F0UL) +#define HAL_LL_UART_IT_CR2_MASK (0x40UL) +#define HAL_LL_UART_IT_CR3_MASK (0x401UL) + +#define HAL_LL_UART_CR1_REG_INDEX (1) +#define HAL_LL_UART_CR2_REG_INDEX (2) +#define HAL_LL_UART_CR3_REG_INDEX (3) + +#define HAL_LL_UART_IT_PE (0x10000100UL) +#define HAL_LL_UART_IT_TXIM (1UL << HAL_LL_UART_IT_TXIM_BIT) +#define HAL_LL_UART_IT_TC (0x10000040UL) +#define HAL_LL_UART_IT_RXIM (1UL << HAL_LL_UART_IT_RXIM_BIT) +#define HAL_LL_UART_IT_IDLE (0x10000010UL) + +#define HAL_LL_UART_IT_LBD (0x20000040UL) + +#define HAL_LL_UART_IT_CTS (0x30000400UL) +#define HAL_LL_UART_IT_ERR (0x30000001UL) + +#define HAL_LL_UART_STATUS_RXMIS_FLAG (HAL_LL_UART_IT_RXIM) +#define HAL_LL_UART_STATUS_TXMIS_FLAG (HAL_LL_UART_IT_TXIM) + +/*!< @brief Macro used for status registed flag check. + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->mis & _flag) + +/*!< @brief Macro used for status registed flag clearing. + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit(&(((hal_ll_uart_base_handle_t *)_handle)->icr), _flag)) + +/*!< @brief UART HW register structure. */ +typedef struct { + uint32_t dr; // Data register. + uint32_t rsr_ecr; // Receive status/error clear register. + uint32_t __unused1[4]; + uint32_t fr; // Flag register. + uint32_t __unused2; + uint32_t ilpr; // IrDA low power register. + uint32_t ibrd; // Integer baud-rate register. + uint32_t fbrd; // Fractional baud rate register. + uint32_t lcrh; // Line control register. + uint32_t ctl; // Control register. + uint32_t ifls; // Interrupt FIFO level select register. + uint32_t im; // Interrupt mask register. + uint32_t ris; // Raw interrupt status register. + uint32_t mis; // Masked interrupt status register. + uint32_t icr; // Interrupt clear register. + /* Register aren't used in this source. + * Uncomment if needed. */ + /* + uint32_t dmactl; // DMA control register. + uint32_t __unused3[22]; + uint32_t nine_bitaddr; // Nine bit self addres register. + uint32_t nine_bitmask; // Nine bit self adress mask register. + */ +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure. */ +typedef struct { + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure. */ +typedef struct { + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific error values. */ +typedef enum { + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART hw specific module values. */ +typedef struct { + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART module state selection. */ +typedef enum { + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info. */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[ UART_MODULE_COUNT + 1 ] = { + #ifdef UART_MODULE_0 + {HAL_LL_UART0_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_0 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_1 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_2 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_3 + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_3 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_4 + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_4 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_5 + {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_5 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_6 + {HAL_LL_UART6_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_6 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_7 + {HAL_LL_UART7_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_7 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; +/*!< @brief UART hardware specific info. */ + +/*!< @brief Global handle variables used in functions. */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions. */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid. + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_handle_register_t *hal_handle = (hal_ll_uart_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_uart_hw_specifics_map_local->module_index; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using this implementation do not support 7 bit data. + if ( ( data_bit < HAL_LL_UART_DATA_BITS_5 ) || ( data_bit > HAL_LL_UART_DATA_BITS_8 ) ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, true); + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ){ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + set_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_RXIM_BIT ); + break; + case HAL_LL_UART_IRQ_TX: + set_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_TXIM_BIT ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) { + #if defined(UART_MODULE_0) && defined(UART0_NVIC) + case hal_ll_uart_module_num( UART_MODULE_0 ): + hal_ll_core_enable_irq( UART0_NVIC ); + break; + #endif + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num( UART_MODULE_1 ): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num( UART_MODULE_2 ): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num( UART_MODULE_3 ): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + #endif + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num( UART_MODULE_4 ): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + #endif + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num( UART_MODULE_5 ): + hal_ll_core_enable_irq( UART5_NVIC ); + break; + #endif + #if defined(UART_MODULE_6) && defined(UART6_NVIC) + case hal_ll_uart_module_num( UART_MODULE_6 ): + hal_ll_core_enable_irq( UART6_NVIC ); + break; + #endif + #if defined(UART_MODULE_7) && defined(UART7_NVIC) + case hal_ll_uart_module_num( UART_MODULE_7 ): + hal_ll_core_enable_irq( UART7_NVIC ); + break; + #endif + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + clear_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_RXIM_BIT ); + break; + case HAL_LL_UART_IRQ_TX: + clear_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_TXIM_BIT ); + break; + + default: + break; + } + + /* Check if module interrupt flags are set or not. + * ATTENTION This is a very important part in the code. + * Interrupts should be disabled ONLY in case we have + * both TX and RX interrupts disabled. + */ + if ( ( !check_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_RXIM_BIT ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_TXIM_BIT ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) { + #if defined(UART_MODULE_0) && defined(UART0_NVIC) + case hal_ll_uart_module_num( UART_MODULE_0 ): + hal_ll_core_disable_irq( UART0_NVIC ); + break; + #endif + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num( UART_MODULE_1 ): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num( UART_MODULE_2 ): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num( UART_MODULE_3 ): + hal_ll_core_disable_irq( UART3_NVIC ); + break; + #endif + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num( UART_MODULE_4 ): + hal_ll_core_disable_irq( UART4_NVIC ); + break; + #endif + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num( UART_MODULE_5 ): + hal_ll_core_disable_irq( UART5_NVIC ); + break; + #endif + #if defined(UART_MODULE_6) && defined(UART6_NVIC) + case hal_ll_uart_module_num( UART_MODULE_6 ): + hal_ll_core_disable_irq( UART6_NVIC ); + break; + #endif + #if defined(UART_MODULE_7) && defined(UART7_NVIC) + case hal_ll_uart_module_num( UART_MODULE_7 ): + hal_ll_core_disable_irq( UART7_NVIC ); + break; + #endif + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->dr = wr_data; +} + +void hal_ll_uart_write_polling( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + while ( hal_ll_hw_reg->fr & HAL_LL_UART_IT_FR_TXFF ) { + // Wait for TXFF (Until the transmitter is not full) + } + + hal_ll_hw_reg->dr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + volatile uint16_t frame = 0; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + if ( check_reg_bit( &hal_ll_hw_reg->ris, HAL_LL_UART_IT_OER_BIT ) ) { + set_reg_bit( &hal_ll_hw_reg->icr, HAL_LL_UART_IT_OER_BIT ); + } + + frame = hal_ll_hw_reg->dr; + + /** + * TODO: Error flags are set by hardware in UARTDR[11:8]. + * Error handling will be added in a future release. + * + * Code example: + * // If error is present return 0, otherwise actual data. + * return (frame & HAL_LL_UART_ERRORS) ? (0) : (frame); + */ + return frame & HAL_LL_UART_DATA; +} + +uint8_t hal_ll_uart_read_polling( handle_t *handle ) { + volatile uint16_t frame = 0; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + if ( check_reg_bit( &hal_ll_hw_reg->ris, HAL_LL_UART_IT_OER_BIT ) ) { + set_reg_bit( &hal_ll_hw_reg->icr, HAL_LL_UART_IT_OER_BIT ); + } + + while ( hal_ll_hw_reg->fr & HAL_LL_UART_IT_FR_RXFE ) { + // Wait for RXFE (Until the receiver is not empty) + } + + frame = hal_ll_hw_reg->dr; + + /** + * TODO: Error flags are set by hardware in UARTDR[11:8]. + * Error handling will be added in a future release. + * + * Code example: + * // If error is present return 0, otherwise actual data. + * return (frame & HAL_LL_UART_ERRORS) ? (0) : (frame); + */ + return frame & HAL_LL_UART_DATA; +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS +#if defined(UART_MODULE_0) && defined(UART0_NVIC) +void MARK_AS_IRQ_HANDLER UART0_IRQHandler(void) MIKROC_IV(UART0_NVIC) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART0_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART0_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_0 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART0_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART0_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_0 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined(UART_MODULE_1) && defined(UART1_NVIC) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler(void) MIKROC_IV(UART1_NVIC) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_1 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_1 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined(UART_MODULE_2) && defined(UART2_NVIC) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler(void) MIKROC_IV(UART2_NVIC) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_2 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_2 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined(UART_MODULE_3) && defined(UART3_NVIC) +void MARK_AS_IRQ_HANDLER UART3_IRQHandler(void) MIKROC_IV(UART3_NVIC) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_3 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_3 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined(UART_MODULE_4) && defined(UART4_NVIC) +void MARK_AS_IRQ_HANDLER UART4_IRQHandler(void) MIKROC_IV(UART4_NVIC) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_4 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_4 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined(UART_MODULE_5) && defined(UART5_NVIC) +void MARK_AS_IRQ_HANDLER UART5_IRQHandler(void) MIKROC_IV(UART5_NVIC) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_5 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_5 )], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined(UART_MODULE_6) && defined(UART6_NVIC) +void MARK_AS_IRQ_HANDLER UART6_IRQHandler(void) MIKROC_IV(UART6_NVIC) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART6_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART6_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_6 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART6_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART6_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_6 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined(UART_MODULE_7) && defined(UART7_NVIC) +void MARK_AS_IRQ_HANDLER UART7_IRQHandler(void) MIKROC_IV(UART7_NVIC) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART7_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART7_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_7 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART7_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART7_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_7 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number. + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names. + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken. + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) { + #ifdef UART_MODULE_0 + case ( hal_ll_uart_module_num( UART_MODULE_0 )): + ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART0EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART0EN ) ); + break; + #endif + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num( UART_MODULE_1 )): + ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART1EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART1EN ) ); + break; + #endif + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num( UART_MODULE_2 )): + ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART2EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART2EN ) ); + break; + #endif + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num( UART_MODULE_3 )): + ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART3EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART3EN ) ); + break; + #endif + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num( UART_MODULE_4 )): + ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART4EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART4EN ) ); + break; + #endif + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num( UART_MODULE_5 )): + ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART5EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART5EN ) ); + break; + #endif + #ifdef UART_MODULE_6 + case ( hal_ll_uart_module_num( UART_MODULE_6 )): + ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART6EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART6EN ) ); + break; + #endif + #ifdef UART_MODULE_7 + case ( hal_ll_uart_module_num( UART_MODULE_7 )): + ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART7EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART7EN ) ); + break; + #endif + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins. + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values. + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + uint32_t uart_config = 0; + + if ( (map->pins.rx_pin.pin_name != HAL_LL_PIN_NC) && + (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) ) + { + if( hal_ll_state != false ) { + uart_config |= GPIO_CFG_ALT_FUNCTION | GPIO_CFG_DIGITAL_ENABLE | GPIO_CFG_DRIVE_8mA; + } + + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = uart_config; + module.configs[ 1 ] = uart_config; + module.configs[ 2 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + uint8_t clk_div; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + if (hal_ll_hw_reg->ctl & HAL_LL_UART_CTL_HSE_BIT) { + clk_div = 8; + } else { + clk_div = 16; + } + + double hal_ll_baud_value = ( ( double )( hal_ll_uart_get_clock_speed( map->module_index ) ) / + ( double )( clk_div * ( map->baud_rate.baud ) ) ); + uint32_t hal_ll_baud_value_int = ( uint32_t )hal_ll_baud_value; + uint32_t hal_ll_baud_value_fract = ( uint32_t )( ( ( hal_ll_baud_value - ( double ) hal_ll_baud_value_int ) * ( double )64 ) + ( double )0.5 ); + uint32_t hal_ll_baud_real_value = ( uint32_t )( ( double )( hal_ll_uart_get_clock_speed( map->module_index ) ) / + ( double )( clk_div * ( ( double )hal_ll_baud_value_int + ( hal_ll_baud_value_fract/ + ( double )64 ) ) ) + ( double )0.5); + + // If error greater than specified, cancel setting baud rate. + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + hal_ll_hw_reg->ibrd = hal_ll_baud_value_int; + hal_ll_hw_reg->fbrd = hal_ll_baud_value_fract; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + return Get_Fosc_kHz() * 1000; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) { + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->lcrh &= ~STOP_BITS_MASK; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->lcrh |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) { + case HAL_LL_UART_DATA_BITS_5: + hal_ll_hw_reg->lcrh &= ~DATA_BITS_MASK; + break; + case HAL_LL_UART_DATA_BITS_6: + hal_ll_hw_reg->lcrh &= ~DATA_BITS_MASK; + hal_ll_hw_reg->lcrh |= DATA_BIT_6; + break; + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->lcrh &= ~DATA_BITS_MASK; + hal_ll_hw_reg->lcrh |= DATA_BIT_7; + break; + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->lcrh |= DATA_BIT_8; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->lcrh &= ~(PARITY_MASK | PARITY_STICK); + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->lcrh |= (PARITY_EVEN | PARITY_STICK); + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->lcrh &= ~PARITY_MASK; + hal_ll_hw_reg->lcrh |= (PARITY_ODD | PARITY_STICK); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->ctl ), HAL_LL_UART_CTL_UARTEN ); + break; + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->ctl ), HAL_LL_UART_CTL_UARTEN ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->ctl ), HAL_LL_UART_CTL_TXE ); + break; + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->ctl ), HAL_LL_UART_CTL_TXE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->ctl ), HAL_LL_UART_CTL_RXE ); + break; + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->ctl ), HAL_LL_UART_CTL_RXE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + clear_reg_bit( &( hal_ll_hw_reg->ctl ), HAL_LL_UART_CTL_UARTEN ); + clear_reg_bit( &( hal_ll_hw_reg->lcrh ), HAL_LL_UART_CTL_FEN ); + hal_ll_hw_reg->lcrh &= ~HAL_LL_UART_LCRH_MASK; + hal_ll_hw_reg->ctl &= ~HAL_LL_UART_CTL_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_baud_bare_metal( map ); + + /* In order for UART Transmit interrupt to + * be triggered, initial dummy data write is + * required. Writing to the register here is + * harmless as we disable TX/RX pins and the + * whole UART module in `hal_ll_uart_clear_regs` + * function. For more information on this issue, + * please have a look at the following link. + * + * + */ + ((hal_ll_uart_base_handle_t *)(map->base))->dr = 0; + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + /*!< @brief Static, because clock doesn't change during runtime */ + uint32_t hal_ll_clock_value = Get_Fosc_kHz() * 2; + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_set_clock( map, true ); + + /* There must be a delay of 3 system clocks after the UART module + * clock is enabled before any UART module registers are accessed. + * See datasheet page 1327 for more information. + * + */ + assembly( nop ); + assembly( nop ); + assembly( nop ); + + hal_ll_uart_hw_init( map ); + + hal_ll_uart_wait_for_sync(hal_ll_clock_value); +} + +// ------------------------------------------------------------------------- END diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index ad027b29c7..aa5a1ac302 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -18,6 +18,7 @@ endif() add_subdirectory(gpio) add_subdirectory(button_simulation) +add_subdirectory(renesas) ## 8K Flash and 2K RAM minimum for this test. memory_sdk_test_check(memory_issue 8192 2048) diff --git a/tests/renesas/CMakeLists.txt b/tests/renesas/CMakeLists.txt new file mode 100644 index 0000000000..b103097af0 --- /dev/null +++ b/tests/renesas/CMakeLists.txt @@ -0,0 +1,10 @@ +## ./tests/renesas/CMakeLists.txt + +add_executable(test_renesas + src/main.c + ReadMe.txt +) + +target_link_libraries(test_renesas PUBLIC + MikroC.Core +) diff --git a/tests/renesas/ReadMe.txt b/tests/renesas/ReadMe.txt new file mode 100644 index 0000000000..62f2865a92 --- /dev/null +++ b/tests/renesas/ReadMe.txt @@ -0,0 +1,9 @@ +Example is meant for testing GPIO module using mikroSDK 2.0 + +If board exists, pins can be defined using following macro template: + +* #define LED MIKROBUS_1_PWM +* #define BUTTON MIKROBUS_1_INT +* etc. + +Go step by step through the example and follow instructions for testing. diff --git a/tests/renesas/src/main.c b/tests/renesas/src/main.c new file mode 100644 index 0000000000..05b7941b2a --- /dev/null +++ b/tests/renesas/src/main.c @@ -0,0 +1,61 @@ +// ------------------------------------------------------------------ INCLUDES +/** + * Any initialization code needed for MCU to function properly. + * Do not remove this line or clock might not be set correctly. + */ +#ifdef PREINIT_SUPPORTED +#include "preinit.h" +#endif + +#include "delays.h" +#include "mcu.h" + +// -------------------------------------------------------------------- MACROS + +// ----------------------------------------------------------------- VARIABLES + +// ----------------------------------------------------------------- USER CODE + +// Initialize LED pin (P302) +void port_init(void) +{ + // Configure P302 as GPIO output + R_PFS->PORT[3].PIN[2].PmnPFS = 0x00000000; // GPIO mode + + R_PORT3->PDR_b.PDR2 = 1; // Direction: output + + R_PORT3->PODR_b.PODR2 = 0; // Initial state: low +} + +int main( void ) { + /* Do not remove this line or clock might not be set correctly. */ + #ifdef PREINIT_SUPPORTED + preinit(); + #endif + + // Initialize GPIO port + port_init(); + + R_PFS->PORT[2].PIN[5].PmnPFS = 0; + R_PFS->PORT[2].PIN[5].PmnPFS_b.PMR = 1; // peripheral + R_PFS->PORT[2].PIN[5].PmnPFS_b.PDR = 1; // output + R_PFS->PORT[2].PIN[5].PmnPFS_b.PSEL = 9; // clkout + R_PFS->PORT[2].PIN[5].PmnPFS_b.NCODR = 0; // CMOS + R_PFS->PORT[2].PIN[5].PmnPFS_b.DSCR = 1; // middle drive + + // Main loop + while (1) + { + R_PORT3->PODR |= (1 << 2); // Set P302 high + // for (volatile uint32_t i = 0; i < 10000; i++) __asm("NOP"); + Delay_ms(1000); + + R_PORT3->PODR &= ~(1 << 2); // Set P302 low + // for (volatile uint32_t i = 0; i < 10000; i++) __asm("NOP"); + Delay_ms(1000); + } + + return 0; +} + +// ----------------------------------------------------------------------- END From 287df55206ad17006f16fd5b98951efca78e78d3 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Tue, 3 Jun 2025 14:13:04 +0200 Subject: [PATCH 02/62] Revert unnecessary files --- .../lcd/lib/include/drivers/lcd_controllers.h | 2 +- .../arm/mikroe/common/include/flatten_me.h | 71 ------------------- 2 files changed, 1 insertion(+), 72 deletions(-) delete mode 100644 targets/arm/mikroe/common/include/flatten_me.h diff --git a/middleware/lcd/lib/include/drivers/lcd_controllers.h b/middleware/lcd/lib/include/drivers/lcd_controllers.h index 3f224978ce..6b02056877 100644 --- a/middleware/lcd/lib/include/drivers/lcd_controllers.h +++ b/middleware/lcd/lib/include/drivers/lcd_controllers.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** Commercial License Usage diff --git a/targets/arm/mikroe/common/include/flatten_me.h b/targets/arm/mikroe/common/include/flatten_me.h deleted file mode 100644 index 446641823e..0000000000 --- a/targets/arm/mikroe/common/include/flatten_me.h +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** -** -** Copyright (C) MikroElektronika d.o.o. -** Contact: https://www.mikroe.com/contact -** -** Commercial License Usage -** -** Licensees holding valid commercial NECTO compilers AI licenses may use this -** file in accordance with the commercial license agreement provided with the -** Software or, alternatively, in accordance with the terms contained in -** a written agreement between you and The MikroElektronika Company. -** For licensing terms and conditions see -** https://www.mikroe.com/legal/software-license-agreement. -** For further information use the contact form at -** https://www.mikroe.com/contact. -** -** -** GNU Lesser General Public License Usage -** -** Alternatively, this file may be used for -** non-commercial projects under the terms of the GNU Lesser -** General Public License version 3 as published by the Free Software -** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. -** -** The above copyright notice and this permission notice shall be -** included in all copies or substantial portions of the Software. -** -** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT -** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE -** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -** -****************************************************************************/ -/*! - * @file flatten_me.h - * @brief mikroSDK code flattener level selection. - */ - -#ifndef __FLATTEN_ME_H__ -#define __FLATTEN_ME_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Flattening levels. - * @ref FLATTEN_ME_LEVEL_NONE - no code flattening done. - * @ref FLATTEN_ME_LEVEL_LOW - flatten only HAL_LL APIs. - * @ref FLATTEN_ME_LEVEL_MID - flatten only HAL_LL and HAL APIs. - * @ref FLATTEN_ME_LEVEL_HIGH - flatten all layered APIs (HAL_LL, HAL and DRV). - */ -#define FLATTEN_ME_LEVEL_NONE (0) -#define FLATTEN_ME_LEVEL_LOW (1) -#define FLATTEN_ME_LEVEL_MID (2) -#define FLATTEN_ME_LEVEL_HIGH (3) - -// Flatten code or not? -#define FLATTEN_ME - -// Flatten level selection. -#define FLATTEN_ME_LEVEL FLATTEN_ME_LEVEL_HIGH - -#ifdef __cplusplus -} -#endif - -#endif // __FLATTEN_ME_H__ From 311353544bc982ca51a067333aa27379eb151707 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Thu, 5 Jun 2025 14:24:02 +0200 Subject: [PATCH 03/62] RA4M1 GPIO update --- .../RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 141 +--- .../include/gpio/hal_ll_gpio_constants.h | 65 +- .../gpio/implementation_1/hal_ll_gpio_port.c | 678 +++++------------- .../implementation_1/hal_ll_spi_master.c | 149 +--- .../src/tim/implementation_1/hal_ll_tim.c | 2 +- .../src/uart/implementation_1/hal_ll_uart.c | 2 +- tests/gpio/CMakeLists.txt | 2 +- tests/gpio/src/main.c | 2 +- 8 files changed, 248 insertions(+), 793 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h index 8947d45758..7928d1f717 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -75,132 +75,21 @@ //EOF TIM //GPIO -#define __PH1_CN -#define __PH0_CN -#define __PG9_CN -#define __PG8_CN -#define __PG7_CN -#define __PG6_CN -#define __PG5_CN -#define __PG4_CN -#define __PG3_CN -#define __PG2_CN -#define __PG15_CN -#define __PG14_CN -#define __PG13_CN -#define __PG12_CN -#define __PG11_CN -#define __PG10_CN -#define __PG1_CN -#define __PG0_CN -#define __PF9_CN -#define __PF8_CN -#define __PF7_CN -#define __PF6_CN -#define __PF5_CN -#define __PF4_CN -#define __PF3_CN -#define __PF2_CN -#define __PF15_CN -#define __PF14_CN -#define __PF13_CN -#define __PF12_CN -#define __PF11_CN -#define __PF10_CN -#define __PF1_CN -#define __PF0_CN -#define __PE9_CN -#define __PE8_CN -#define __PE7_CN -#define __PE6_CN -#define __PE5_CN -#define __PE4_CN -#define __PE3_CN -#define __PE2_CN -#define __PE15_CN -#define __PE14_CN -#define __PE13_CN -#define __PE12_CN -#define __PE11_CN -#define __PE10_CN -#define __PE1_CN -#define __PE0_CN -#define __PD9_CN -#define __PD8_CN -#define __PD7_CN -#define __PD6_CN -#define __PD5_CN -#define __PD4_CN -#define __PD3_CN -#define __PD2_CN -#define __PD15_CN -#define __PD14_CN -#define __PD13_CN -#define __PD12_CN -#define __PD11_CN -#define __PD10_CN -#define __PD1_CN -#define __PD0_CN -#define __PC9_CN -#define __PC8_CN -#define __PC7_CN -#define __PC6_CN -#define __PC5_CN -#define __PC4_CN -#define __PC3_CN -#define __PC2_CN -#define __PC15_CN -#define __PC14_CN -#define __PC13_CN -#define __PC12_CN -#define __PC11_CN -#define __PC10_CN -#define __PC1_CN -#define __PC0_CN -#define __PB9_CN -#define __PB8_CN -#define __PB7_CN -#define __PB6_CN -#define __PB5_CN -#define __PB4_CN -#define __PB3_CN -#define __PB2_CN -#define __PB15_CN -#define __PB14_CN -#define __PB13_CN -#define __PB12_CN -#define __PB11_CN -#define __PB10_CN -#define __PB1_CN -#define __PB0_CN -#define __PA9_CN -#define __PA8_CN -#define __PA7_CN -#define __PA6_CN -#define __PA5_CN -#define __PA4_CN -#define __PA3_CN -#define __PA2_CN -#define __PA15_CN -#define __PA14_CN -#define __PA13_CN -#define __PA12_CN -#define __PA11_CN -#define __PA10_CN -#define __PA1_CN -#define __PA0_CN - -#define __PORT_A_CN -#define __PORT_B_CN -#define __PORT_C_CN -#define __PORT_D_CN -#define __PORT_E_CN -#define __PORT_F_CN -#define __PORT_G_CN -#define __PORT_H_CN - -#define PORT_SIZE (32) -#define PORT_COUNT (8) +#define __PH1_CN // TODO + +#define __PORT_0_CN +#define __PORT_1_CN +#define __PORT_2_CN +#define __PORT_3_CN +#define __PORT_4_CN +#define __PORT_5_CN +#define __PORT_6_CN +#define __PORT_7_CN +#define __PORT_8_CN +#define __PORT_9_CN + +#define PORT_SIZE (16) +#define PORT_COUNT (10) //EOF GPIO //IVT_TABLE diff --git a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_constants.h b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_constants.h index 0585eb08a4..402a14274a 100644 --- a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_constants.h +++ b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_constants.h @@ -48,51 +48,30 @@ extern "C"{ #endif -#define GPIO_CFG_MODE_INPUT 0x0UL -#define GPIO_CFG_MODE_OUTPUT 0x1UL +#define GPIO_CFG_PORT_DIRECTION_INPUT (0x00000000) // Sets the pin direction to input (default) +#define GPIO_CFG_PORT_DIRECTION_OUTPUT (0x00000004) // Sets the pin direction to output +#define GPIO_CFG_PORT_OUTPUT_LOW (0x00000000) // Sets the pin level to low +#define GPIO_CFG_PORT_OUTPUT_HIGH (0x00000001) // Sets the pin level to high +#define GPIO_CFG_PULLUP_ENABLE (0x00000010) // Enables the pin's internal pull-up +#define GPIO_CFG_PIM_TTL (0x00000020) // Enables the pin's input mode +#define GPIO_CFG_NMOS_ENABLE (0x00000040) // Enables the pin's NMOS open-drain output +#define GPIO_CFG_PMOS_ENABLE (0x00000080) // Enables the pin's PMOS open-drain ouput +#define GPIO_CFG_DRIVE_MID (0x00000400) // Sets pin drive output to medium +#define GPIO_CFG_DRIVE_HS_HIGH (0x00000800) // Sets pin drive output to high along with supporting high speed +#define GPIO_CFG_DRIVE_MID_IIC (0x00000800) // Sets pin to drive output needed for IIC on a 20mA port +#define GPIO_CFG_DRIVE_HIGH (0x00000C00) // Sets pin drive output to high +#define GPIO_CFG_EVENT_RISING_EDGE (0x00001000) // Sets pin event trigger to rising edge +#define GPIO_CFG_EVENT_FALLING_EDGE (0x00002000) // Sets pin event trigger to falling edge +#define GPIO_CFG_EVENT_BOTH_EDGES (0x00003000) // Sets pin event trigger to both edges +#define GPIO_CFG_IRQ_ENABLE (0x00004000) // Sets pin as an IRQ pin +#define GPIO_CFG_ANALOG_ENABLE (0x00008000) // Enables pin to operate as an analog pin +#define GPIO_CFG_PERIPHERAL_PIN (0x00010000) // Enables pin to operate as a peripheral pin -#define GPIO_DIR_INPUT 0 -#define GPIO_DIR_OUTPUT 1 +#define GPIO_PRV_PFS_PSEL_OFFSET (24) // Peripheral function selection offset -#define GPIO_CFG_PULL_UP 0x1UL -#define GPIO_CFG_PULL_DOWN 0x2UL - -#define GPIO_CFG_OPEN_DRAIN 0x8UL -#define GPIO_CFG_DRIVE_2mA 0x10UL -#define GPIO_CFG_DRIVE_4mA 0x20UL -#define GPIO_CFG_DRIVE_8mA 0x40UL -#define GPIO_CFG_SLEW_RATE 0x80UL -#define GPIO_CFG_DIGITAL_ENABLE 0x100UL -#define GPIO_CFG_ISOLATION_DISABLE 0x200UL -#define GPIO_CFG_ALT_FUNCTION 0x400UL -#define GPIO_CFG_ADC_SRC_TRIGGER 0x800UL -#define GPIO_CFG_DRIVE_6mA 0x1000UL -#define GPIO_CFG_DRIVE_10mA 0x2000UL -#define GPIO_CFG_DRIVE_12mA 0x4000UL - -#define GPIO_CFG_ADV_AIN ( GPIO_CFG_ALT_FUNCTION | GPIO_CFG_ISOLATION_DISABLE ) - -#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_DIR_OUTPUT | GPIO_CFG_DIGITAL_ENABLE | GPIO_CFG_DRIVE_8mA ) -#define GPIO_CFG_DIGITAL_INPUT ( GPIO_DIR_INPUT | GPIO_CFG_DIGITAL_ENABLE | GPIO_CFG_DRIVE_8mA ) -#define GPIO_CFG_ANALOG_INPUT ( GPIO_DIR_INPUT | GPIO_CFG_ADV_AIN ) - -#define _HAL_GPIO_DIR_OFFSET ( 0x400UL / 4 ) -#define _HAL_GPIO_GPIOPC_OFFSET ( 0xFC4UL / 4 ) -#define _HAL_GPIO_GPIOODR_OFFSET ( 0x50CUL / 4 ) -#define _HAL_GPIO_GPIOPUR_OFFSET ( 0x510UL / 4 ) -#define _HAL_GPIO_GPIOPDR_OFFSET ( 0x514UL / 4 ) -#define _HAL_GPIO_GPIOSLR_OFFSET ( 0x518UL / 4 ) -#define _HAL_GPIO_GPIODEN_OFFSET ( 0x518UL / 4 ) -#define _HAL_GPIO_GPIODR2R_OFFSET ( 0x500UL / 4 ) -#define _HAL_GPIO_GPIODR4R_OFFSET ( 0x504UL / 4 ) -#define _HAL_GPIO_GPIODR8R_OFFSET ( 0x508UL / 4 ) -#define _HAL_GPIO_GPIODR12R_OFFSET ( 0x53CUL / 4 ) -#define _HAL_GPIO_GPIOAMSEL_OFFSET ( 0x528UL / 4 ) -#define _HAL_GPIO_GPIOAFSEL_OFFSET ( 0x420UL / 4 ) -#define _HAL_GPIO_GPIOADCCTL_OFFSET ( 0x530UL / 4 ) - -#define GPIO_PIN_NAME_MASK ( uint32_t )0xFF -#define GPIO_AF_MASK 0x0F +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_ANALOG_ENABLE | GPIO_CFG_PORT_DIRECTION_INPUT ) // TODO Esma +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_PORT_DIRECTION_OUTPUT ) // TODO Esma +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_PORT_DIRECTION_INPUT ) // TODO Esma #ifdef __cplusplus } diff --git a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c index 792e16a91b..c79ce511e5 100644 --- a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c @@ -44,166 +44,184 @@ #include "hal_ll_gpio_port.h" #include "hal_ll_rcc.h" -/*!< @brief Helper macro for extracting appropriate pin mask. */ -#define HAL_LL_GPIO_PIN_MASK 0xFUL - -/*!< @brief Helper macro for extracting appropriate port mask. */ -#define HAL_LL_GPIO_PORT_MASK 0xFFUL +#define hal_ll_gpio_port_get_pin_index(__index) ( __index & 0xF0 )?( ( uint8_t )__index % PORT_SIZE ): \ + ( ( uint8_t )__index % PORT_SIZE ) -/*!< @brief Helper macro for extracting appropriate alternate function. */ -#define HAL_LL_GPIO_AF_MASK 0xF00UL +#define hal_ll_gpio_port_get_port_index(__index) ( __index & 0xF0 )?( ( uint8_t )__index / PORT_SIZE ): \ + ( ( uint8_t )__index / PORT_SIZE ) -/*!< @brief Helper macro for getting appropriate alternate function mask. */ -#define HAL_LL_GPIO_AFSEL_MULTIPLIER 4 -/*!< @brief Helper macro. */ -#define HAL_LL_GPIO_GPIOCR_MASK 0xFFFFFF00 +#define GPIO_PORT0_BASE (0x40040000UL) +#define GPIO_PORT1_BASE (0x40040020UL) +#define GPIO_PORT2_BASE (0x40040040UL) +#define GPIO_PORT3_BASE (0x40040060UL) +#define GPIO_PORT4_BASE (0x40040080UL) +#define GPIO_PORT5_BASE (0x400400A0UL) +#define GPIO_PORT6_BASE (0x400400C0UL) +#define GPIO_PORT7_BASE (0x400400E0UL) +#define GPIO_PORT8_BASE (0x40040100UL) +#define GPIO_PORT9_BASE (0x40040120UL) +// According to the documentation, this MCU has 10 ports, +// but in mcu.h there are 15 port addresses +// #define GPIO_PORT10_BASE (0x40040140UL) +// #define GPIO_PORT11_BASE (0x40040160UL) +// #define GPIO_PORT12_BASE (0x40040180UL) +// #define GPIO_PORT13_BASE (0x400401A0UL) +// #define GPIO_PORT14_BASE (0x400401C0UL) + +#define PWPR_REGISTER_BASE (( uint32_t * )0x40040D03UL) -/*!< @brief Helper macro for hexadecimal number for unlocking the GPIOCR register. */ -#define HAL_LL_GPIO_GPIOCR_UNLOCK_VALUE 0x4C4F434B +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base[] = +{ + GPIO_PORT0_BASE, + GPIO_PORT1_BASE, + GPIO_PORT2_BASE, + GPIO_PORT3_BASE, + GPIO_PORT4_BASE, + GPIO_PORT5_BASE, + GPIO_PORT6_BASE, + GPIO_PORT7_BASE, + GPIO_PORT8_BASE, + GPIO_PORT9_BASE//, + // GPIO_PORT10_BASE, + // GPIO_PORT11_BASE, + // GPIO_PORT12_BASE, + // GPIO_PORT13_BASE, + // GPIO_PORT14_BASE +}; -/*!< @brief Helper macro for checking against pins GPIO_PE7 and GPIO_PD7. */ -#define HAL_LL_GPIO_PINMASK_PIN7 0x80UL +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + volatile uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + volatile uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + volatile uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + volatile uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + volatile uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + volatile uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + volatile uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + volatile uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + volatile uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + volatile uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + volatile uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + volatile uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + volatile uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + volatile uint16_t RESERVED; + + union + { + volatile uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + volatile uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + volatile uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + volatile uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + volatile uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + volatile uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + volatile uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + volatile uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + volatile uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + volatile uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + volatile uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + volatile uint16_t RESERVED1; + volatile uint8_t RESERVED2; + + union + { + volatile uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + volatile uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + volatile uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + volatile uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + volatile uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + volatile uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + volatile uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ -/*!< @brief Helper macro for checking against pins on PORTC[0:3]. */ -#define HAL_LL_GPIO_PINMASK_PIN0_3 0xFUL +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + volatile R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/*!< @brief Helper macro for checking against pins GPIO_PF0. */ -#define HAL_LL_GPIO_PINMASK_PIN0 0x01UL /** - * Defines used in source + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) */ -#ifdef TM4C123 - #define GPIOA_BASE_ADDR 0x400043FCUL - #define GPIOB_BASE_ADDR 0x400053FCUL - #define GPIOC_BASE_ADDR 0x400063FCUL - #define GPIOD_BASE_ADDR 0x400073FCUL - #define GPIOE_BASE_ADDR 0x400243FCUL - #define GPIOF_BASE_ADDR 0x400253FCUL - #define GPIOG_BASE_ADDR 0x400263FCUL - #define GPIOH_BASE_ADDR 0x400273FCUL - #define GPIOJ_BASE_ADDR 0x4003D3FCUL - #define GPIOK_BASE_ADDR 0x400613FCUL -#else - #define GPIOA_BASE_ADDR 0x400583FCUL - #define GPIOB_BASE_ADDR 0x400593FCUL - #define GPIOC_BASE_ADDR 0x4005A3FCUL - #define GPIOD_BASE_ADDR 0x4005B3FCUL - #define GPIOE_BASE_ADDR 0x4005C3FCUL - #define GPIOF_BASE_ADDR 0x4005D3FCUL - #define GPIOG_BASE_ADDR 0x4005E3FCUL - #define GPIOH_BASE_ADDR 0x4005F3FCUL - #define GPIOJ_BASE_ADDR 0x400603FCUL - #define GPIOK_BASE_ADDR 0x400613FCUL - #define GPIOL_BASE_ADDR 0x400623FCUL - #define GPIOM_BASE_ADDR 0x400633FCUL - #define GPION_BASE_ADDR 0x400643FCUL - #define GPIOP_BASE_ADDR 0x400653FCUL - #define GPIOQ_BASE_ADDR 0x400663FCUL - #define GPIOR_BASE_ADDR 0x400673FCUL - #define GPIOS_BASE_ADDR 0x400683FCUL - #define GPIOT_BASE_ADDR 0x400693FCUL -#endif - -#define RCC_GPIOCLOCK _SYSCTL_RCGCGPIO - -#define hal_ll_gpio_port_get_pin_index(__index) ( __index & 0xF0 )?( ( uint8_t )__index % PORT_SIZE ): \ - ( ( uint8_t )__index % PORT_SIZE ) +typedef struct +{ + volatile uint8_t RESERVED[389]; -#define hal_ll_gpio_port_get_port_index(__index) ( __index & 0xF0 )?( ( uint8_t )__index / PORT_SIZE ): \ - ( ( uint8_t )__index / PORT_SIZE ) + union + { + volatile uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ -#ifndef GPIOA_BASE_ADDR - #define GPIOA_BASE_ADDR 0 -#endif -#ifndef GPIOB_BASE_ADDR - #define GPIOB_BASE_ADDR 1 -#endif -#ifndef GPIOC_BASE_ADDR - #define GPIOC_BASE_ADDR 2 -#endif -#ifndef GPIOD_BASE_ADDR - #define GPIOD_BASE_ADDR 3 -#endif -#ifndef GPIOE_BASE_ADDR - #define GPIOE_BASE_ADDR 4 -#endif -#ifndef GPIOF_BASE_ADDR - #define GPIOF_BASE_ADDR 5 -#endif -#ifndef GPIOG_BASE_ADDR - #define GPIOG_BASE_ADDR 6 -#endif -#ifndef GPIOH_BASE_ADDR - #define GPIOH_BASE_ADDR 7 -#endif -#ifndef GPIOJ_BASE_ADDR - #define GPIOJ_BASE_ADDR 8 -#endif -#ifndef GPIOK_BASE_ADDR - #define GPIOK_BASE_ADDR 9 -#endif -#ifndef GPIOL_BASE_ADDR - #define GPIOL_BASE_ADDR 10 -#endif -#ifndef GPIOM_BASE_ADDR - #define GPIOM_BASE_ADDR 11 -#endif -#ifndef GPION_BASE_ADDR - #define GPION_BASE_ADDR 12 -#endif -#ifndef GPIOP_BASE_ADDR - #define GPIOP_BASE_ADDR 13 -#endif -#ifndef GPIOQ_BASE_ADDR - #define GPIOQ_BASE_ADDR 14 -#endif -#ifndef GPIOR_BASE_ADDR - #define GPIOR_BASE_ADDR 15 -#endif -#ifndef GPIOS_BASE_ADDR - #define GPIOS_BASE_ADDR 16 -#endif -#ifndef GPIOT_BASE_ADDR - #define GPIOT_BASE_ADDR 17 -#endif + struct + { + volatile uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ -/*!< @brief GPIO PORT array */ -static const uint32_t _hal_ll_gpio_port_base[] = +/** + * @brief I/O Ports-PFS (R_PFS) + */ +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ { - #ifdef TM4C123 - GPIOA_BASE_ADDR, - GPIOB_BASE_ADDR, - GPIOC_BASE_ADDR, - GPIOD_BASE_ADDR, - GPIOE_BASE_ADDR, - GPIOF_BASE_ADDR, - GPIOG_BASE_ADDR, - GPIOH_BASE_ADDR, - GPIOJ_BASE_ADDR, - GPIOK_BASE_ADDR - #else - GPIOA_BASE_ADDR, - GPIOB_BASE_ADDR, - GPIOC_BASE_ADDR, - GPIOD_BASE_ADDR, - GPIOE_BASE_ADDR, - GPIOF_BASE_ADDR, - GPIOG_BASE_ADDR, - GPIOH_BASE_ADDR, - GPIOJ_BASE_ADDR, - GPIOK_BASE_ADDR, - GPIOL_BASE_ADDR, - GPIOM_BASE_ADDR, - GPION_BASE_ADDR, - GPIOP_BASE_ADDR, - GPIOQ_BASE_ADDR, - GPIOR_BASE_ADDR, - GPIOS_BASE_ADDR, - GPIOT_BASE_ADDR - #endif -}; + union + { + volatile R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + volatile R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS /** * @brief Enable gpio port clock @@ -230,31 +248,10 @@ static void _hal_ll_gpio_config( uint32_t *port, uint8_t pin_mask, uint32_t conf */ static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); -/** - * @brief Enables write access to pins - * that were originally locked. - * @param[in] *gpio_ptr - Register list for one GPIO module. - * @param[in] port - Port base address. - * @param[in] pin - Pin mask. - * - * @return none - */ -static void hal_ll_gpio_unlock_pin( hal_ll_gpio_base_handle_t *gpio_ptr, uint32_t port, uint8_t pin_mask ); - -/** - * @brief Unlock access to generic GPIO registers - * (GPIOAFSEL, GPIOPUR, GPIOPDR and GPIODEN) - * for pin which is locked on POR -> power-on reset. - * @param[in] *gpio_ptr - Register list for one GPIO module. - * @param[in] pin_mask - GPIO pin mask. - * - * @return none - */ -static void hal_ll_gpio_commit_pin( hal_ll_gpio_base_handle_t *gpio_ptr, uint8_t pin_mask ); +// TODO Esma +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ); -static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) { - return hal_ll_gpio_port_get_pin_index( name ); -} +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) { return hal_ll_gpio_port_get_port_index( name ); @@ -281,334 +278,51 @@ void hal_ll_gpio_digital_output( uint32_t *port, uint8_t pin_mask ) { } void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) { - uint8_t index = 0; + int32_t index = 0; - while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) { + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); - index++; - } -} -/** - * @brief Enable gpio port clock - * @param port - port base address - * @return none - */ -static void hal_ll_gpio_clock_enable( uint32_t port ) { - uint8_t shift_value; - - switch ( port ) { - case GPIOA_BASE_ADDR: - shift_value = 0; - break; - case GPIOB_BASE_ADDR: - shift_value = 1; - break; - case GPIOC_BASE_ADDR: - shift_value = 2; - break; - case GPIOD_BASE_ADDR: - shift_value = 3; - break; - case GPIOE_BASE_ADDR: - shift_value = 4; - break; - case GPIOF_BASE_ADDR: - shift_value = 5; - break; - case GPIOG_BASE_ADDR: - shift_value = 6; - break; - case GPIOH_BASE_ADDR: - shift_value = 7; - break; - case GPIOJ_BASE_ADDR: - shift_value = 8; - break; - case GPIOK_BASE_ADDR: - shift_value = 9; - break; - case GPIOL_BASE_ADDR: - shift_value = 10; - break; - case GPIOM_BASE_ADDR: - shift_value = 11; - break; - case GPION_BASE_ADDR: - shift_value = 12; - break; - case GPIOP_BASE_ADDR: - shift_value = 13; - break; - case GPIOQ_BASE_ADDR: - shift_value = 14; - break; - case GPIOR_BASE_ADDR: - shift_value = 15; - break; - case GPIOS_BASE_ADDR: - shift_value = 16; - break; - case GPIOT_BASE_ADDR: - shift_value = 17; - break; - - default: - return; + index++; } - - *RCC_GPIOCLOCK |= 1UL << shift_value; } -static void hal_ll_gpio_commit_pin( hal_ll_gpio_base_handle_t *gpio_ptr, uint8_t pin_mask ) { - // Unlock GPIOCR register. - gpio_ptr->gpiolock = HAL_LL_GPIO_GPIOCR_UNLOCK_VALUE; +// ------------------------------------------------ STATIC FUNCTION DEFINITIONS - // Unlock access to generic GPIO registers (GPIOAFSEL, GPIOPUR, GPIOPDR and GPIODEN) - // for pin which is locked on POR -> power-on reset. - gpio_ptr->gpiocr = pin_mask; +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) { + return hal_ll_gpio_port_get_pin_index( name ); } -static void hal_ll_gpio_unlock_pin( hal_ll_gpio_base_handle_t *gpio_ptr, uint32_t port, uint8_t pin_mask ) { - switch ( port ) { - // JTAG/SWD pins are based on PORTC. - case GPIOC_BASE_ADDR: - if ( pin_mask == ( pin_mask & HAL_LL_GPIO_PINMASK_PIN0_3 ) ) { - hal_ll_gpio_commit_pin( gpio_ptr, pin_mask ); - } - break; - // Non-maskable interrupt pin is based on both PORTD and PORTE. - case GPIOD_BASE_ADDR: - case GPIOE_BASE_ADDR: - if ( pin_mask == HAL_LL_GPIO_PINMASK_PIN7 ) { - hal_ll_gpio_commit_pin( gpio_ptr, pin_mask ); - } - break; - case GPIOF_BASE_ADDR: - if ( pin_mask == HAL_LL_GPIO_PINMASK_PIN0 ) { - hal_ll_gpio_commit_pin( gpio_ptr, pin_mask ); - } - break; - - default: - return; - } +static void hal_ll_gpio_clock_enable( uint32_t port ) { + // TODO Esma - PORTs don't have clock enabling feature. } -/** - * @brief Configure single port pins - * @param port - port base address - * pin_mask - desired pin - * config - pin settings - * @return none - */ static void _hal_ll_gpio_config( uint32_t *port, uint8_t pin_mask, uint32_t config ) { - uint8_t i; - uint32_t tmp_code; - - hal_ll_gpio_base_handle_t *gpio_ptr = ( hal_ll_gpio_base_handle_t * )( *port ); - - hal_ll_gpio_clock_enable( *port ); - - hal_ll_gpio_unlock_pin( gpio_ptr, *port, pin_mask ); - - if ( config & GPIO_CFG_MODE_OUTPUT ) { - gpio_ptr->gpiodir |= pin_mask; - } else { - // Else, digital input. - gpio_ptr->gpiodir &= ~pin_mask; - } - - if ( config & GPIO_CFG_PULL_UP ) { - gpio_ptr->gpiopur |= pin_mask; - } else { - gpio_ptr->gpiopur &= ~pin_mask; - } - - if( config & GPIO_CFG_PULL_DOWN ) { - gpio_ptr->gpiopdr |= pin_mask; - } else { - gpio_ptr->gpiopdr &= ~pin_mask; - } + R_PFS_Type port_ptr; + // Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register. + *PWPR_REGISTER_BASE &= ~0x80; // Clear B0WI bit + // Set 1 to the PFSWE bit in the PWPR register. This enables writing to the PmnPFS register. + *PWPR_REGISTER_BASE |= 0x40; // Set PFSWE bit + + // Clear the Port Mode Control bit in the PMR for the target pin to select the general I/O port. + // TODO Esma pristup PMR registru + port_ptr.PORT[0].PIN[0].PmnPFS_b.PMR = 0; + // Specify the input/output function for the pin through the PSEL[4:0] bit settings in the PmnPFS register. + // TODO Esma pristup PMR registru + port_ptr.PORT[0].PIN[0].PmnPFS_b.PSEL = 0; + // Set the PMR to 1 as required to switch to the selected input/output function for the pin. + port_ptr.PORT[0].PIN[0].PmnPFS_b.PMR = 0; // ?? ovi koraci kao da je los AI ispisao + + // Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register. + *PWPR_REGISTER_BASE &= ~0x40; // Set PFSWE bit + // Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register + *PWPR_REGISTER_BASE |= 0x80; // Set B0WI bit - if ( config & GPIO_CFG_OPEN_DRAIN ) { - gpio_ptr->gpioodr |= pin_mask; - } else { - gpio_ptr->gpioodr &= ~pin_mask; - } - - if ( config & GPIO_CFG_DRIVE_2mA) { - gpio_ptr->gpiodr2r |= pin_mask; - } else { - gpio_ptr->gpiodr2r &= ~pin_mask; - } - - if ( config & GPIO_CFG_DRIVE_4mA ) { - gpio_ptr->gpiodr4r |= pin_mask; - } else { - gpio_ptr->gpiodr4r &= ~pin_mask; - } - - if ( config & GPIO_CFG_DRIVE_8mA) { - gpio_ptr->gpiodr8r |= pin_mask; - } else { - gpio_ptr->gpiodr8r &= ~pin_mask; - } - - if( ( 1 == ( config & GPIO_CFG_DRIVE_6mA ) ) || - ( 1 == ( config & GPIO_CFG_DRIVE_10mA ) ) || - ( 1 == ( config & GPIO_CFG_DRIVE_12mA ) ) ) - { - tmp_code = 0; - for ( i = 0; i < 8; i++ ) { - if( ( pin_mask >> i ) & 1 ) { - tmp_code |= 0x3UL << ( i * 2 ); - } - } - - gpio_ptr->gpiopc &= ~tmp_code; - gpio_ptr->gpiodr8r &= ~pin_mask; - gpio_ptr->gpiodr4r &= ~pin_mask; - gpio_ptr->gpiodr12r &= ~pin_mask; - } - - tmp_code = 0; - - if ( config & GPIO_CFG_DRIVE_6mA ) { - for( i = 0; i < 8; i++ ) { - if( ( pin_mask >> i ) & 1 ) { - tmp_code |= 0x1UL << ( i * 2 ); - } - } - - gpio_ptr->gpiopc |= tmp_code; - gpio_ptr->gpiodr8r |= pin_mask; - } - - tmp_code = 0; - - if( config & GPIO_CFG_DRIVE_10mA ) { - for( i = 0; i < 8; i++ ) { - if( ( pin_mask >> i ) & 1 ) { - tmp_code |= 0x3UL << ( i * 2 ); - } - } - - gpio_ptr->gpiopc |= tmp_code; - gpio_ptr->gpiodr8r |= pin_mask; - gpio_ptr->gpiodr12r |= pin_mask; - } - - tmp_code = 0; - - if( config & GPIO_CFG_DRIVE_12mA ) { - for( i = 0; i < 8; i++ ) { - if( ( pin_mask >> i ) & 1 ) { - tmp_code |= 0x3UL << ( i * 2 ); - } - } - - gpio_ptr->gpiopc |= tmp_code; - gpio_ptr->gpiodr8r |= pin_mask; - gpio_ptr->gpiodr4r |= pin_mask; - gpio_ptr->gpiodr12r |= pin_mask; - } - - if ( config & GPIO_CFG_SLEW_RATE ) { - if ( config & GPIO_CFG_DRIVE_8mA ) { - gpio_ptr->gpioslr |= pin_mask; - } else { - return; - } - } else { - gpio_ptr->gpioslr &= ~pin_mask; - } - - if ( config & GPIO_CFG_DIGITAL_ENABLE ) { - gpio_ptr->gpioden |= pin_mask; - } else { - gpio_ptr->gpioden &= ~pin_mask; - } - - if ( config & GPIO_CFG_ISOLATION_DISABLE ) { - if( ( GPIOE_BASE_ADDR != *port ) & ( GPIOD_BASE_ADDR != *port ) & ( GPIOB_BASE_ADDR != *port ) & - ( GPIOK_BASE_ADDR != *port ) & ( GPIOP_BASE_ADDR != *port ) ) - { - return; - } else { - gpio_ptr->gpioamsel |= pin_mask; - } - } else { - if( ( GPIOE_BASE_ADDR == *port ) | ( GPIOD_BASE_ADDR == *port ) | ( GPIOB_BASE_ADDR == *port ) | - ( GPIOK_BASE_ADDR == *port ) | ( GPIOP_BASE_ADDR == *port ) ) - { - gpio_ptr->gpioamsel &= ~pin_mask; - } - } - - if ( config & GPIO_CFG_ADC_SRC_TRIGGER ) { - gpio_ptr->gpioadcctl |= pin_mask; - } else { - gpio_ptr->gpioadcctl &= ~pin_mask; - } - - if ( config & GPIO_CFG_ALT_FUNCTION ) - gpio_ptr->gpioafsel |= pin_mask; - else - gpio_ptr->gpioafsel &= ~pin_mask; } -/** - * @brief Configure port pins alternate - * functions - * @param module_pin - desired pin - * config - pin settings - * @return none - */ static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) { - // Pin, port & alternate function mask declaration & initialization. - uint8_t pin_mask_raw = 0; - uint8_t pin_mask = 0; - uint8_t port_mask = 0; - uint32_t af_mask = 0; - uint32_t *port = 0; - - // Extract appropriate info from "module_pin" variable. - pin_mask_raw = ( ( module_pin & HAL_LL_GPIO_PIN_MASK ) % PORT_SIZE ); - pin_mask = ( 0x1UL << pin_mask_raw ); - port_mask = ( module_pin & HAL_LL_GPIO_PORT_MASK ) / PORT_SIZE; - af_mask = ( ( ( module_pin & HAL_LL_GPIO_AF_MASK ) >> 8 ) << ( pin_mask_raw * HAL_LL_GPIO_AFSEL_MULTIPLIER ) ); - - // Get appropriate GPIO module. - port = (uint32_t *)_hal_ll_gpio_port_base[port_mask]; - - // Configure basic GPIO settings. - _hal_ll_gpio_config( &port, pin_mask, module_config ); - - // Get appropriate register list. - hal_ll_gpio_base_handle_t *gpio_ptr = ( hal_ll_gpio_base_handle_t * )( port ); - - /* - * NOTE: On TM4C123 microcontrollers, the GPIO_PCTL register - * retains a non-zero value after reset. Therefore, clearing specific bits - * corresponding to the currently selected pin in the register before - * assigning new values is necessary for proper initialization. - */ - gpio_ptr->gpiopctl &= ~( HAL_LL_GPIO_PIN_MASK << ( module_pin * HAL_LL_GPIO_AFSEL_MULTIPLIER )); - - if ( state ) { - // Set appropriate bit in AFSEL register. - gpio_ptr->gpioafsel |= ( 0x1UL << pin_mask ); - - // Set appropriate bit in GPIOPCTL register. - gpio_ptr->gpiopctl |= af_mask; - } else { - // Clear appropriate bit in AFSEL register. - gpio_ptr->gpioafsel &= ~( 0x1UL << pin_mask ); - - // Clear appropriate bit in GPIOPCTL register. - gpio_ptr->gpiopctl &= ~( af_mask ); - } + } // ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c b/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c index 76bdca45fd..dd41aee90c 100644 --- a/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c +++ b/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c @@ -60,38 +60,6 @@ static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[ SPI_MOD #define hal_ll_spi_master_get_base_from_hal_handle ( ( hal_ll_spi_master_hw_specifics_map_t * )( ( hal_ll_spi_master_handle_register_t * )\ ( ( ( hal_ll_spi_master_handle_register_t * )( handle ) )->hal_ll_spi_master_handle ) )->hal_ll_spi_master_handle )->base -/*!< @brief SSI mode constants. */ -#define HAL_LL_SPI_MASTER_CLK_POLARITY (6) -#define HAL_LL_SPI_MASTER_CLK_PHASE (7) - -/*!< @brief SSI enable constants. */ -#define HAL_LL_SPI_SSI_ENABLE (1) -#define HAL_LL_SPI0_ENABLE (0) -#define HAL_LL_SPI1_ENABLE (1) -#define HAL_LL_SPI2_ENABLE (2) -#define HAL_LL_SPI3_ENABLE (3) - -/*!< @brief Status register bit check. */ -#define HAL_LL_SPI1_FIFO_NOT_EMPTY (2) - -/*!< @brief General constants. */ -#define HAL_LL_SPI_CLK_POLARITY (1) -#define HAL_LL_SPI_CLK_PHASE (0) - -/*!< @brief Default SPI Master bit-rate if no speed is set. */ -#define HAL_LL_SPI_MASTER_SPEED_100K (100000) - -/*!< @brief Data transfer mode. */ -#define HAL_LL_SPI_8_BIT (0x7) - -/*!< @brief Alternate function config macros. */ -#define HAL_LL_SPI_AF_CONFIG_SCK (GPIO_CFG_DIGITAL_OUTPUT | GPIO_CFG_ALT_FUNCTION) -#define HAL_LL_SPI_AF_CONFIG_MOSI (GPIO_CFG_DIGITAL_OUTPUT | GPIO_CFG_ALT_FUNCTION) -#define HAL_LL_SPI_AF_CONFIG_MISO (GPIO_CFG_DIGITAL_INPUT | GPIO_CFG_ALT_FUNCTION) - -/*!< @brief Helper macro for retrieving end-user's selected frequency. */ -#define _fosc (Get_Fosc_kHz()*1000ul) - // -------------------------------------------------------------- PRIVATE TYPES /*!< @brief SPI Master hw specific error values. */ @@ -105,36 +73,7 @@ typedef enum { /*!< @brief SPI register structure. */ typedef struct { - uint32_t cr0; // QSSI module Control 0 Register. - uint32_t cr1; // QSSI module Control 1 Register. - uint32_t dr; // QSSI module Data read Register. - uint32_t ssisr; // QSSI module Status Register. - uint32_t cpsdvsr; // QSSI module Clock prescale divisor Register. - uint32_t ssiim; // QSSI module Interrupt Mask Register. - uint32_t ssiris; // QSSI module Raw Interrupt Status Register. - uint32_t ssimis; // QSSI module Masked Interrupt Status Register. - uint32_t ssiicr; // QSSI module Interrupt Clear Register. - uint32_t ssidmactl; // QSSI module DMA control Register. - /* Commented out for memory optimization; - * Uncomment if needed. - */ - // uint32_t __unused1[998];// Reserved memory space. - // uint32_t ssipp; // QSSI module Peripheral properties Register. - // uint32_t __unused2; // Reserved memory space. - // uint32_t ssicc; // QSSI module Clock configuration Register. - // uint32_t __unused3[6]; // Reserved memory space. - // uint32_t ssipid4; // QSSI module Peripheral ID 4. - // uint32_t ssipid5; // QSSI module Peripheral ID 5. - // uint32_t ssipid6; // QSSI module peripheral ID 6. - // uint32_t ssipid7; // QSSI module peripheral ID 7. - // uint32_t ssipid0; // QSSI module peripheral ID 0. - // uint32_t ssipid1; // QSSI module peripheral ID 1. - // uint32_t ssipid2; // QSSI module peripheral ID 2. - // uint32_t ssipid3; // QSSI module peripheral ID 3. - // uint32_t ssipcd0; // QSSI module prime cell ID 0. - // uint32_t ssipcd1; // QSSI prime cell ID 1. - // uint32_t ssipcd2; // QSSI prime cell ID 2. - // uint32_t ssipcd3; // QSSI prime cell ID 3. + } hal_ll_spi_master_base_handle_t; /*!< @brief SPI Master hardware specific module values. */ @@ -511,7 +450,7 @@ void hal_ll_spi_master_close( handle_t* handle ) { low_level_handle->init_ll_state = false; hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; - hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + // hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; @@ -619,9 +558,9 @@ static void _hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_ module.pins[ 2 ] = VALUE( map->pins.miso.pin_name, map->pins.miso.pin_af ); module.pins[ 3 ] = GPIO_MODULE_STRUCT_END; - module.configs[ 0 ] = HAL_LL_SPI_AF_CONFIG_SCK; - module.configs[ 1 ] = HAL_LL_SPI_AF_CONFIG_MOSI; - module.configs[ 2 ] = HAL_LL_SPI_AF_CONFIG_MISO; + // module.configs[ 0 ] = HAL_LL_SPI_AF_CONFIG_SCK; + // module.configs[ 1 ] = HAL_LL_SPI_AF_CONFIG_MOSI; + // module.configs[ 2 ] = HAL_LL_SPI_AF_CONFIG_MISO; module.configs[ 3 ] = GPIO_MODULE_STRUCT_END; hal_ll_gpio_module_struct_init( &module, hal_ll_state ); @@ -658,34 +597,26 @@ static void _hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_t * static inline void _hal_ll_spi_master0_set_clock ( bool hal_ll_state ) { // Check hal_ll_state, and set the bit for the clock - hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI0_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI0_ENABLE ); + // hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI0_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI0_ENABLE ); } static inline void _hal_ll_spi_master1_set_clock( bool hal_ll_state ) { // Check hal_ll_state, and set the bit for the clock - hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI1_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI1_ENABLE ); + // hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI1_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI1_ENABLE ); } static inline void _hal_ll_spi_master2_set_clock( bool hal_ll_state ) { // Check hal_ll_state, and set the bit for the clock - hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI2_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI2_ENABLE ); + // hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI2_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI2_ENABLE ); } static inline void _hal_ll_spi_master3_set_clock( bool hal_ll_state ) { // Check hal_ll_state, and set the bit for the clock - hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI3_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI3_ENABLE ); + // hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI3_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI3_ENABLE ); } uint8_t _hal_ll_spi_master_transfer( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer ) { - // Perform a dummy transfer. - volatile uint8_t temp = hal_ll_hw_reg->dr; - - hal_ll_hw_reg->dr = data_buffer; - // Wait for the transfer to finish. - while( !( check_reg_bit ( &( hal_ll_hw_reg->ssisr ), HAL_LL_SPI1_FIFO_NOT_EMPTY ) ) ); - - return hal_ll_hw_reg->dr; } static void _hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { @@ -705,69 +636,11 @@ static void _hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t } static void _hal_ll_spi_master_mode_selection( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, hal_ll_spi_master_mode_t mode ) { - // Clock Polarity configuration. - if ( mode <= HAL_LL_SPI_MASTER_MODE_1 ) { - // Idle state for the SPI clock is low level (0). - clear_reg_bit( &(hal_ll_hw_reg->cr0), HAL_LL_SPI_MASTER_CLK_POLARITY ); - } else { - // Idle state for the SPI clock is high level (1). - set_reg_bit( &(hal_ll_hw_reg->cr0), HAL_LL_SPI_MASTER_CLK_POLARITY ); - } - - // Clock Phase configuration. - if ( mode == HAL_LL_SPI_MASTER_MODE_0 || mode == HAL_LL_SPI_MASTER_MODE_2 ) { - // Data is captured on the 1st clock edge transition. - clear_reg_bit( &(hal_ll_hw_reg->cr0), HAL_LL_SPI_MASTER_CLK_PHASE ); - } else { - // Data is captured on the 2nd clock edge transition. - set_reg_bit( &(hal_ll_hw_reg->cr0), HAL_LL_SPI_MASTER_CLK_PHASE ); - } + } static void _hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map ) { - uint32_t bitrate; - uint32_t scaler = 0; - uint32_t prescaler = 0; - uint32_t min_diff = 0xFFFFFFFF; - uint16_t scaler_counter, prescaler_value; - bool appropriate_baud_rate_found = false; - - hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = ( hal_ll_spi_master_base_handle_t* ) map->base; - - // Set 8bit transfer mode. - hal_ll_hw_reg->cr0 = HAL_LL_SPI_8_BIT; - - // SPI Mode selection process. - _hal_ll_spi_master_mode_selection( map->base, map->mode ); - - for ( scaler_counter = 2; scaler_counter < 255; scaler_counter += 2 ) { - for ( prescaler_value = 0; prescaler_value < 256; prescaler_value++ ) { - bitrate = _fosc / ( scaler_counter * ( 1 + prescaler_value ) ); - if ( map->speed >= bitrate ) { - uint32_t diff = map->speed - bitrate; - if ( min_diff > diff ) { - min_diff = diff; - prescaler = prescaler_value; - scaler = scaler_counter; - appropriate_baud_rate_found = true; - break; - } - } - } - - if( appropriate_baud_rate_found ) { - break; - } - } - // Saving scale and prescale values. - hal_ll_hw_reg->cr0 |= ( prescaler << 8 ); - hal_ll_hw_reg->cpsdvsr = scaler; - - // Enable the SSI module. - set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_SPI_SSI_ENABLE ); - - // Memorize final hardware SPI speed. - hal_ll_spi_master_hw_specifics_map->hw_actual_speed = bitrate; + } static void _hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ) { diff --git a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c index 7f463cc74f..59044163f7 100644 --- a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c @@ -721,7 +721,7 @@ static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_m if( map->config.pin != HAL_LL_PIN_NC ) { if( hal_ll_state != false ) { - tim_config |= GPIO_CFG_DIGITAL_INPUT | GPIO_CFG_ALT_FUNCTION; + // tim_config |= GPIO_CFG_DIGITAL_INPUT | GPIO_CFG_ALT_FUNCTION; } module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); diff --git a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c index c437267534..dda13c07ea 100644 --- a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c @@ -1070,7 +1070,7 @@ static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_ (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) ) { if( hal_ll_state != false ) { - uart_config |= GPIO_CFG_ALT_FUNCTION | GPIO_CFG_DIGITAL_ENABLE | GPIO_CFG_DRIVE_8mA; + // uart_config |= GPIO_CFG_ALT_FUNCTION | GPIO_CFG_DIGITAL_ENABLE | GPIO_CFG_DRIVE_8mA; } module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); diff --git a/tests/gpio/CMakeLists.txt b/tests/gpio/CMakeLists.txt index adc9b73f37..1ec26c4d6a 100644 --- a/tests/gpio/CMakeLists.txt +++ b/tests/gpio/CMakeLists.txt @@ -6,7 +6,7 @@ string(SUBSTRING ${MCU_NAME} 0 4 MCU_NAME_FIRST_4) string(SUBSTRING ${MCU_NAME} 0 5 MCU_NAME_FIRST_5) string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) -if ( ( ${MCU_NAME_FIRST_7} STREQUAL "PIC32MZ" ) OR ( ${MCU_NAME_FIRST_7} STREQUAL "PIC32MX" ) OR ( ${MCU_NAME_FIRST_5} STREQUAL "STM32" ) OR ( ${MCU_NAME} MATCHES "GD32VF103" ) OR ( ${MCU_NAME} MATCHES "^(ds)?PIC(24|30|33).*" ) ) +if ( ( ${MCU_NAME_FIRST_7} STREQUAL "PIC32MZ" ) OR ( ${MCU_NAME_FIRST_7} STREQUAL "PIC32MX" ) OR ( ${MCU_NAME_FIRST_5} STREQUAL "STM32" ) OR ( ${MCU_NAME} MATCHES "GD32VF103" ) OR ( ${MCU_NAME} MATCHES "^(ds)?PIC(24|30|33).*" ) OR ( ${MCU_NAME_FIRST_2} STREQUAL "R7" ) ) list(APPEND gpio_def_list "port_count_size=16") elseif( ( ${MCU_NAME_FIRST_5} STREQUAL "PIC18" ) OR ( ${MCU_NAME_FIRST_4} STREQUAL "TM4C" ) OR ( ${MCU_NAME_FIRST_2} STREQUAL "AT" ) ) list(APPEND gpio_def_list "port_count_size=8") diff --git a/tests/gpio/src/main.c b/tests/gpio/src/main.c index e83f08e1ce..2ecb5aca07 100644 --- a/tests/gpio/src/main.c +++ b/tests/gpio/src/main.c @@ -74,7 +74,7 @@ static port_t test_port; // PORT driver context structure. static digital_in_t input_pin; // Digital input driver context structure. static digital_out_t output_pin; // Digital output driver context structure. -static uint8_t port_counter = port_count_size; // Defined in memake file. +static uint8_t port_counter = port_count_size; // Defined in CMakeLists.txt file. // ----------------------------------------------------------------- USER CODE int main( void ) { /* Do not remove this line or clock might not be set correctly. */ From 47d809ac73e48fc5924c19387c172b5f7c436042 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Thu, 12 Jun 2025 14:40:22 +0200 Subject: [PATCH 04/62] GPIO update, port works --- .../mikroe/renesas/include/gpio/hal_ll_gpio.h | 24 +- .../renesas/include/gpio/hal_ll_gpio_port.h | 120 +++++--- .../mikroe/renesas/include/hal_ll_pin_names.h | 108 ++++---- .../renesas/include/hal_ll_target_names.h | 4 +- .../arm/mikroe/renesas/src/gpio/hal_ll_gpio.c | 18 +- .../gpio/implementation_1/hal_ll_gpio_port.c | 260 ++++++------------ .../renesas/src/one_wire/hal_ll_one_wire.c | 42 +-- 7 files changed, 271 insertions(+), 305 deletions(-) diff --git a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h index 224c946d1a..7ee0dbf26f 100644 --- a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h +++ b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h @@ -83,7 +83,7 @@ void hal_ll_gpio_configure_pin(hal_ll_gpio_pin_t *pin, hal_ll_pin_name_t name, h */ #if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) #define hal_ll_gpio_read_pin_input(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) == 0) ? \ - (0) : (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata & ((hal_ll_gpio_pin_t *)_handle)->mask) ? \ + (0) : (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->pidr & ((hal_ll_gpio_pin_t *)_handle)->mask) ? \ (1) : (0)) #else uint8_t hal_ll_gpio_read_pin_input(hal_ll_gpio_pin_t *pin); @@ -104,7 +104,7 @@ uint8_t hal_ll_gpio_read_pin_input(hal_ll_gpio_pin_t *pin); */ #if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) #define hal_ll_gpio_read_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) == 0) ? \ - (0) : (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata & ((hal_ll_gpio_pin_t *)_handle)->mask) ? \ + (0) : (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr & ((hal_ll_gpio_pin_t *)_handle)->mask) ? \ (1) : (0)) #else uint8_t hal_ll_gpio_read_pin_output(hal_ll_gpio_pin_t *pin); @@ -126,8 +126,8 @@ uint8_t hal_ll_gpio_read_pin_output(hal_ll_gpio_pin_t *pin); #if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) #define hal_ll_gpio_write_pin_output(_handle,_value) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ ((_value > 0) ? \ - (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata |= ((hal_ll_gpio_pin_t *)_handle)->mask) : \ - (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata &= ~((hal_ll_gpio_pin_t *)_handle)->mask)) : \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr |= ((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr &= ~((hal_ll_gpio_pin_t *)_handle)->mask)) : \ (0)) #else void hal_ll_gpio_write_pin_output(hal_ll_gpio_pin_t *pin, uint8_t value); @@ -146,9 +146,9 @@ void hal_ll_gpio_write_pin_output(hal_ll_gpio_pin_t *pin, uint8_t value); */ #if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) #define hal_ll_gpio_toggle_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ - ((((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata & ((hal_ll_gpio_pin_t *)_handle)->mask))) ? \ - (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata &= ~((hal_ll_gpio_pin_t *)_handle)->mask) : \ - (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata |= ((hal_ll_gpio_pin_t *)_handle)->mask)) : \ + ((((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr & ((hal_ll_gpio_pin_t *)_handle)->mask))) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr &= ~((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr |= ((hal_ll_gpio_pin_t *)_handle)->mask)) : \ (0)) #else void hal_ll_gpio_toggle_pin_output(hal_ll_gpio_pin_t *pin); @@ -166,7 +166,7 @@ void hal_ll_gpio_toggle_pin_output(hal_ll_gpio_pin_t *pin); */ #if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) #define hal_ll_gpio_set_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ - (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata |= ((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr |= ((hal_ll_gpio_pin_t *)_handle)->mask) : \ (0)) #else void hal_ll_gpio_set_pin_output(hal_ll_gpio_pin_t *pin); @@ -184,7 +184,7 @@ void hal_ll_gpio_set_pin_output(hal_ll_gpio_pin_t *pin); */ #if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) #define hal_ll_gpio_clear_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ - (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->gpiodata &= ~((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr &= ~((hal_ll_gpio_pin_t *)_handle)->mask) : \ (0)) #else void hal_ll_gpio_clear_pin_output(hal_ll_gpio_pin_t *pin); @@ -222,7 +222,7 @@ void hal_ll_gpio_configure_port(hal_ll_gpio_port_t *port, hal_ll_port_name_t nam */ #if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) #define hal_ll_gpio_read_port_input(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ - ((hal_ll_port_size_t)(((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->gpiodata) & (((hal_ll_gpio_port_t *)_handle)->mask)) : \ + ((hal_ll_port_size_t)(((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->pidr) & (((hal_ll_gpio_port_t *)_handle)->mask)) : \ (0)) #else hal_ll_port_size_t hal_ll_gpio_read_port_input(hal_ll_gpio_port_t *port); @@ -240,7 +240,7 @@ hal_ll_port_size_t hal_ll_gpio_read_port_input(hal_ll_gpio_port_t *port); */ #if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) #define hal_ll_gpio_read_port_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ - ((hal_ll_port_size_t)(((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->gpiodata) & (((hal_ll_gpio_port_t *)_handle)->mask)) : \ + ((hal_ll_port_size_t)(((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->podr) & (((hal_ll_gpio_port_t *)_handle)->mask)) : \ (0)) #else hal_ll_port_size_t hal_ll_gpio_read_port_output(hal_ll_gpio_port_t *port); @@ -261,7 +261,7 @@ hal_ll_port_size_t hal_ll_gpio_read_port_output(hal_ll_gpio_port_t *port); */ #if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) #define hal_ll_gpio_write_port_output(_handle,_value) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ - (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->gpiodata = \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->podr = \ ((hal_ll_gpio_port_t *)_handle)->mask & (hal_ll_port_size_t)_value) : \ (0)) #else diff --git a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h index 6fb710bf2d..dff0745b3a 100644 --- a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h +++ b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h @@ -55,6 +55,7 @@ extern "C"{ * Helper macros for GPIO HAL */ #define GPIO_MODULE_STRUCT_END (-1) +#define GPIO_PIN_NAME_MASK (0xFFUL) #define GPIO_AF_OFFSET 8 #define VALUE(pin, func) (pin | (func << GPIO_AF_OFFSET)) @@ -63,47 +64,92 @@ extern "C"{ */ typedef struct { - hal_ll_base_addr_t pins[13]; + union { + uint32_t pcntr1; + struct { + uint16_t pdr; + uint16_t podr; + }; + }; + union { + uint32_t pcntr2; + struct { + uint16_t pidr; + uint16_t eidr; // PORT1-4 only + }; + }; + union { + uint32_t pcntr3; + struct { + uint16_t posr; + uint16_t porr; + }; + }; + union { + uint32_t pcntr4; // PORT1-4 only + struct { + uint16_t eosr; // PORT1-4 only + uint16_t eorr; // PORT1-4 only + }; + }; +} hal_ll_gpio_base_handle_t; + +/** + * GPIO module struct defining pins and proprietary functions + */ +typedef struct +{ + uint32_t pins[13]; uint32_t configs[13]; + uint32_t gpio_remap; } module_struct; /** - * GPIO module registers access structure + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) */ typedef struct { - hal_ll_base_addr_t gpiodata; - hal_ll_base_addr_t gpiodir; - hal_ll_base_addr_t gpiois; - hal_ll_base_addr_t gpioibe; - hal_ll_base_addr_t gpioiev; - hal_ll_base_addr_t gpioim; - hal_ll_base_addr_t gpioris; - hal_ll_base_addr_t gpiomis; - hal_ll_base_addr_t gpioicr; - hal_ll_base_addr_t gpioafsel; - hal_ll_base_addr_t gpio_reserved[55]; - hal_ll_base_addr_t gpiodr2r; - hal_ll_base_addr_t gpiodr4r; - hal_ll_base_addr_t gpiodr8r; - hal_ll_base_addr_t gpioodr; - hal_ll_base_addr_t gpiopur; - hal_ll_base_addr_t gpiopdr; - hal_ll_base_addr_t gpioslr; - hal_ll_base_addr_t gpioden; - hal_ll_base_addr_t gpiolock; - hal_ll_base_addr_t gpiocr; - hal_ll_base_addr_t gpioamsel; - hal_ll_base_addr_t gpiopctl; - hal_ll_base_addr_t gpioadcctl; - hal_ll_base_addr_t gpiodmactl; - hal_ll_base_addr_t gpiosi; - hal_ll_base_addr_t gpiodr12r; - hal_ll_base_addr_t gpiowakepen; - hal_ll_base_addr_t gpiowakestat; - hal_ll_base_addr_t gpiopp; - hal_ll_base_addr_t gpiopc; -} hal_ll_gpio_base_handle_t; + union + { + volatile uint32_t pmnpfs; + + struct + { + volatile uint32_t podr : 1; + volatile uint32_t pidr : 1; + volatile uint32_t pdr : 1; + uint32_t : 1; + volatile uint32_t pcr : 1; + volatile uint32_t pim : 1; + volatile uint32_t ncodr : 1; + uint32_t : 3; + volatile uint32_t dscr : 2; + volatile uint32_t eofr : 2; + volatile uint32_t isel : 1; + volatile uint32_t asel : 1; + volatile uint32_t pmr : 1; + uint32_t : 7; + volatile uint32_t psel : 5; + uint32_t : 3; + } pmnpfs_b; + }; +} hal_ll_gpio_pfs_pin_t; + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + volatile hal_ll_gpio_pfs_pin_t pin[16]; +} hal_ll_gpio_pfs_port_t; + +/** + * @brief I/O Ports-PFS (R_PFS) + */ +typedef struct +{ + volatile hal_ll_gpio_pfs_port_t port[10]; +} hal_ll_gpio_pfs_t; /** * Handle and mask types. @@ -161,7 +207,7 @@ uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ); * @param pin_mask - pin mask acquired from hal_gpio_ll_pin_mask * @return none */ -void hal_ll_gpio_analog_input( uint32_t *port, uint8_t pin_mask ); +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ); /** * @brief Set pin as digital input @@ -169,7 +215,7 @@ void hal_ll_gpio_analog_input( uint32_t *port, uint8_t pin_mask ); * @param pin_mask - pin mask acquired from hal_gpio_ll_pin_mask * @return none */ -void hal_ll_gpio_digital_input( uint32_t *port, uint8_t pin_mask ); +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ); /** * @brief Set pin as digital output @@ -177,7 +223,7 @@ void hal_ll_gpio_digital_input( uint32_t *port, uint8_t pin_mask ); * @param pin_mask - pin mask acquired from hal_gpio_ll_pin_mask * @return none */ -void hal_ll_gpio_digital_output( uint32_t *port, uint8_t pin_mask ); +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ); /** * @brief Initialize structure of pins associated to specific peripheral diff --git a/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h b/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h index 297b95511d..5a9589a042 100644 --- a/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h +++ b/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h @@ -719,77 +719,77 @@ extern "C"{ #define GPIO_PIN_7 (0x07) #define PIN_7 GPIO_PIN_7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_7! -#ifdef __PORT_A_CN -#define GPIO_PORT_A (0x00) -#define PORT_A GPIO_PORT_A // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_A! +#ifdef __PORT_0_CN +#define GPIO_PORT_0 (0x00) +#define PORT_0 GPIO_PORT_0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_0! #endif -#ifdef __PORT_B_CN -#define GPIO_PORT_B (0x01) -#define PORT_B GPIO_PORT_B // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_B! +#ifdef __PORT_1_CN +#define GPIO_PORT_1 (0x01) +#define PORT_1 GPIO_PORT_1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_1! #endif -#ifdef __PORT_C_CN -#define GPIO_PORT_C (0x02) -#define PORT_C GPIO_PORT_C // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_C! +#ifdef __PORT_2_CN +#define GPIO_PORT_2 (0x02) +#define PORT_2 GPIO_PORT_2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_2! #endif -#ifdef __PORT_D_CN -#define GPIO_PORT_D (0x03) -#define PORT_D GPIO_PORT_D // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_D! +#ifdef __PORT_3_CN +#define GPIO_PORT_3 (0x03) +#define PORT_3 GPIO_PORT_3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_3! #endif -#ifdef __PORT_E_CN -#define GPIO_PORT_E (0x04) -#define PORT_E GPIO_PORT_E // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_E! +#ifdef __PORT_4_CN +#define GPIO_PORT_4 (0x04) +#define PORT_4 GPIO_PORT_4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_4! #endif -#ifdef __PORT_F_CN -#define GPIO_PORT_F (0x05) -#define PORT_F GPIO_PORT_F // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_F! +#ifdef __PORT_5_CN +#define GPIO_PORT_5 (0x05) +#define PORT_5 GPIO_PORT_5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_5! #endif -#ifdef __PORT_G_CN -#define GPIO_PORT_G (0x06) -#define PORT_G GPIO_PORT_G // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_G! +#ifdef __PORT_6_CN +#define GPIO_PORT_6 (0x06) +#define PORT_6 GPIO_PORT_6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_6! #endif -#ifdef __PORT_H_CN -#define GPIO_PORT_H (0x07) -#define PORT_H GPIO_PORT_H // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_H! +#ifdef __PORT_7_CN +#define GPIO_PORT_7 (0x07) +#define PORT_7 GPIO_PORT_7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_7! #endif -#ifdef __PORT_J_CN -#define GPIO_PORT_J (0x08) -#define PORT_J GPIO_PORT_J // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_J! +#ifdef __PORT_8_CN +#define GPIO_PORT_8 (0x08) +#define PORT_8 GPIO_PORT_8 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_8! #endif -#ifdef __PORT_K_CN -#define GPIO_PORT_K (0x09) -#define PORT_K GPIO_PORT_K // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_K! +#ifdef __PORT_9_CN +#define GPIO_PORT_9 (0x09) +#define PORT_9 GPIO_PORT_9 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_9! #endif -#ifdef __PORT_L_CN -#define GPIO_PORT_L (0x0A) -#define PORT_L GPIO_PORT_L // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_L! +#ifdef __PORT_10_CN +#define GPIO_PORT_10 (0x0A) +#define PORT_10 GPIO_PORT_10 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_10! #endif -#ifdef __PORT_M_CN -#define GPIO_PORT_M (0x0B) -#define PORT_M GPIO_PORT_M // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_M! +#ifdef __PORT_11_CN +#define GPIO_PORT_11 (0x0B) +#define PORT_11 GPIO_PORT_11 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_11! #endif -#ifdef __PORT_N_CN -#define GPIO_PORT_N (0x0C) -#define PORT_N GPIO_PORT_N // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_N! +#ifdef __PORT_12_CN +#define GPIO_PORT_12 (0x0C) +#define PORT_12 GPIO_PORT_12 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_12! #endif -#ifdef __PORT_P_CN -#define GPIO_PORT_P (0x0D) -#define PORT_P GPIO_PORT_P // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_P! +#ifdef __PORT_13_CN +#define GPIO_PORT_13 (0x0D) +#define PORT_13 GPIO_PORT_13 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_13! #endif -#ifdef __PORT_Q_CN -#define GPIO_PORT_Q (0x0E) -#define PORT_Q GPIO_PORT_Q // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_Q! +#ifdef __PORT_14_CN +#define GPIO_PORT_14 (0x0E) +#define PORT_14 GPIO_PORT_14 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_14! #endif -#ifdef __PORT_R_CN -#define GPIO_PORT_R (0x0F) -#define PORT_R GPIO_PORT_R // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_R! +#ifdef __PORT_15_CN +#define GPIO_PORT_15 (0x0F) +#define PORT_15 GPIO_PORT_15 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_15! #endif -#ifdef __PORT_S_CN -#define GPIO_PORT_S (0x10) -#define PORT_S GPIO_PORT_S // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_S! +#ifdef __PORT_16_CN +#define GPIO_PORT_16 (0x10) +#define PORT_16 GPIO_PORT_16 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_16! #endif -#ifdef __PORT_T_CN -#define GPIO_PORT_T (0x11) -#define PORT_T GPIO_PORT_T // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_T! +#ifdef __PORT_17_CN +#define GPIO_PORT_17 (0x11) +#define PORT_17 GPIO_PORT_17 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_17! #endif #ifdef __cplusplus diff --git a/targets/arm/mikroe/renesas/include/hal_ll_target_names.h b/targets/arm/mikroe/renesas/include/hal_ll_target_names.h index 92a59537b9..559ced4f2a 100644 --- a/targets/arm/mikroe/renesas/include/hal_ll_target_names.h +++ b/targets/arm/mikroe/renesas/include/hal_ll_target_names.h @@ -55,10 +55,10 @@ extern "C"{ #include typedef uintptr_t handle_t; -typedef uint8_t hal_ll_gpio_mask_t; +typedef uint16_t hal_ll_gpio_mask_t; typedef uint8_t hal_ll_pin_name_t; typedef uint8_t hal_ll_port_name_t; -typedef uint8_t hal_ll_port_size_t; +typedef uint16_t hal_ll_port_size_t; typedef uint32_t hal_ll_base_addr_t; typedef uint8_t hal_ll_channel_t; diff --git a/targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c b/targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c index f362122900..2a33f32449 100644 --- a/targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c +++ b/targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c @@ -63,7 +63,7 @@ void hal_ll_gpio_configure_pin(hal_ll_gpio_pin_t *pin, hal_ll_pin_name_t name, h uint8_t hal_ll_gpio_read_pin_input(hal_ll_gpio_pin_t *pin) { uint8_t gpio_data_value; - gpio_data_value = ((hal_ll_gpio_base_handle_t *)(pin->base))->gpiodata; + gpio_data_value = ((hal_ll_gpio_base_handle_t *)(pin->base))->pidr; return (gpio_data_value & pin->mask) ? 0x01 : 0x00; } #endif @@ -75,7 +75,7 @@ uint8_t hal_ll_gpio_read_pin_input(hal_ll_gpio_pin_t *pin) { uint8_t hal_ll_gpio_read_pin_output(hal_ll_gpio_pin_t *pin) { uint8_t gpio_data_value; - gpio_data_value = ((hal_ll_gpio_base_handle_t *)(pin->base))->gpiodata; + gpio_data_value = ((hal_ll_gpio_base_handle_t *)(pin->base))->podr; return (gpio_data_value & pin->mask) ? 0x01 : 0x00; } #endif @@ -86,9 +86,9 @@ uint8_t hal_ll_gpio_read_pin_output(hal_ll_gpio_pin_t *pin) { #if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) void hal_ll_gpio_write_pin_output(hal_ll_gpio_pin_t *pin, uint8_t value) { if (value) - ((hal_ll_gpio_base_handle_t *)(pin->base))->gpiodata |= pin->mask; + ((hal_ll_gpio_base_handle_t *)(pin->base))->podr |= pin->mask; else - ((hal_ll_gpio_base_handle_t *)(pin->base))->gpiodata &= ~pin->mask; + ((hal_ll_gpio_base_handle_t *)(pin->base))->podr &= ~pin->mask; } #endif @@ -107,7 +107,7 @@ void hal_ll_gpio_toggle_pin_output(hal_ll_gpio_pin_t *pin) { */ #if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) void hal_ll_gpio_set_pin_output(hal_ll_gpio_pin_t *pin) { - ((hal_ll_gpio_base_handle_t *)(pin->base))->gpiodata |= pin->mask; + ((hal_ll_gpio_base_handle_t *)(pin->base))->podr |= pin->mask; } #endif @@ -116,7 +116,7 @@ void hal_ll_gpio_set_pin_output(hal_ll_gpio_pin_t *pin) { */ #if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) void hal_ll_gpio_clear_pin_output(hal_ll_gpio_pin_t *pin) { - ((hal_ll_gpio_base_handle_t *)(pin->base))->gpiodata &= ~pin->mask; + ((hal_ll_gpio_base_handle_t *)(pin->base))->podr &= ~pin->mask; } #endif @@ -139,7 +139,7 @@ void hal_ll_gpio_configure_port(hal_ll_gpio_port_t *port, hal_ll_port_name_t nam #if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) hal_ll_port_size_t hal_ll_gpio_read_port_input(hal_ll_gpio_port_t *port) { uint8_t gpio_data_value; - return ((hal_ll_gpio_base_handle_t *)(port->base))->gpiodata & port->mask; + return ((hal_ll_gpio_base_handle_t *)(port->base))->pidr & port->mask; } #endif @@ -149,7 +149,7 @@ hal_ll_port_size_t hal_ll_gpio_read_port_input(hal_ll_gpio_port_t *port) { #if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) hal_ll_port_size_t hal_ll_gpio_read_port_output(hal_ll_gpio_port_t *port) { uint8_t gpio_data_value; - return ((hal_ll_gpio_base_handle_t *)(port->base))->gpiodata & port->mask; + return ((hal_ll_gpio_base_handle_t *)(port->base))->podr & port->mask; } #endif @@ -159,7 +159,7 @@ hal_ll_port_size_t hal_ll_gpio_read_port_output(hal_ll_gpio_port_t *port) { #if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) void hal_ll_gpio_write_port_output(hal_ll_gpio_port_t *port, hal_ll_port_size_t value) { hal_ll_gpio_base_handle_t *base_reg = (hal_ll_gpio_base_handle_t *)port->base; - base_reg->gpiodata = (uint32_t)(port->mask & value); + base_reg->podr = (uint32_t)(port->mask & value); } #endif diff --git a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c index c79ce511e5..979677128e 100644 --- a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c @@ -62,17 +62,17 @@ #define GPIO_PORT8_BASE (0x40040100UL) #define GPIO_PORT9_BASE (0x40040120UL) // According to the documentation, this MCU has 10 ports, -// but in mcu.h there are 15 port addresses +// but in mcu.h there are 15 port addresses // #define GPIO_PORT10_BASE (0x40040140UL) // #define GPIO_PORT11_BASE (0x40040160UL) // #define GPIO_PORT12_BASE (0x40040180UL) // #define GPIO_PORT13_BASE (0x400401A0UL) // #define GPIO_PORT14_BASE (0x400401C0UL) -#define PWPR_REGISTER_BASE (( uint32_t * )0x40040D03UL) +#define PWPR_REGISTER_BASE (( volatile uint8_t * )0x40040D03UL) /*!< @brief GPIO PORT array */ -static const uint32_t _hal_ll_gpio_port_base[] = +static const uint32_t hal_ll_gpio_port_base_arr[] = { GPIO_PORT0_BASE, GPIO_PORT1_BASE, @@ -91,144 +91,14 @@ static const uint32_t _hal_ll_gpio_port_base[] = // GPIO_PORT14_BASE }; -/** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) - */ -typedef struct -{ - union - { - union - { - volatile uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - - struct - { - volatile uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - volatile uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - volatile uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - volatile uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - volatile uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - volatile uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - volatile uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - volatile uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - volatile uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - volatile uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - volatile uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - volatile uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; - }; - - struct - { - union - { - struct - { - volatile uint16_t RESERVED; - - union - { - volatile uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - - struct - { - volatile uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - volatile uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - volatile uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - volatile uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - volatile uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - volatile uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - volatile uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - volatile uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - volatile uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - volatile uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; - - struct - { - volatile uint16_t RESERVED1; - volatile uint8_t RESERVED2; - - union - { - volatile uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ - - struct - { - volatile uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - volatile uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - volatile uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - volatile uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - volatile uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - volatile uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; - }; - }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_PFS_PORT [PORT] (Port [0..14]) - */ -typedef struct -{ - volatile R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ - - -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - volatile uint8_t RESERVED[389]; - - union - { - volatile uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - volatile uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - -/** - * @brief I/O Ports-PFS (R_PFS) - */ -typedef struct /*!< (@ 0x40040800) R_PFS Structure */ -{ - union - { - volatile R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - volatile R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ - // ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS -/** - * @brief Enable gpio port clock - * @param port - port base address - * @return none - */ -static void _hal_ll_gpio_clock_enable( uint32_t *port ); +// /** +// * @brief Enable gpio port clock +// * @param port - port base address +// * @return none +// */ +// static void _hal_ll_gpio_clock_enable( uint32_t *port ); // TODO Esma /** * @brief Configure port pins @@ -237,7 +107,7 @@ static void _hal_ll_gpio_clock_enable( uint32_t *port ); * config - pin settings * @return none */ -static void _hal_ll_gpio_config( uint32_t *port, uint8_t pin_mask, uint32_t config ); +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); /** * @brief Configure port pins alternate @@ -246,7 +116,7 @@ static void _hal_ll_gpio_config( uint32_t *port, uint8_t pin_mask, uint32_t conf * config - pin settings * @return none */ -static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); +static void hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); // TODO Esma static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ); @@ -262,19 +132,19 @@ uint8_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) { } uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) { - return _hal_ll_gpio_port_base[ name ]; + return hal_ll_gpio_port_base_arr[ name ]; } -void hal_ll_gpio_analog_input( uint32_t *port, uint8_t pin_mask ) { - _hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) { + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); } -void hal_ll_gpio_digital_input( uint32_t *port, uint8_t pin_mask ) { - _hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) { + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); } -void hal_ll_gpio_digital_output( uint32_t *port, uint8_t pin_mask ) { - _hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) { + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); } void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) { @@ -282,7 +152,7 @@ void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) { while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) { - _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); index++; } @@ -297,32 +167,82 @@ static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) { static void hal_ll_gpio_clock_enable( uint32_t port ) { // TODO Esma - PORTs don't have clock enabling feature. } +#include "mcu.h" -static void _hal_ll_gpio_config( uint32_t *port, uint8_t pin_mask, uint32_t config ) { - R_PFS_Type port_ptr; - // Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register. - *PWPR_REGISTER_BASE &= ~0x80; // Clear B0WI bit - // Set 1 to the PFSWE bit in the PWPR register. This enables writing to the PmnPFS register. - *PWPR_REGISTER_BASE |= 0x40; // Set PFSWE bit - - // Clear the Port Mode Control bit in the PMR for the target pin to select the general I/O port. - // TODO Esma pristup PMR registru - port_ptr.PORT[0].PIN[0].PmnPFS_b.PMR = 0; - // Specify the input/output function for the pin through the PSEL[4:0] bit settings in the PmnPFS register. - // TODO Esma pristup PMR registru - port_ptr.PORT[0].PIN[0].PmnPFS_b.PSEL = 0; - // Set the PMR to 1 as required to switch to the selected input/output function for the pin. - port_ptr.PORT[0].PIN[0].PmnPFS_b.PMR = 0; // ?? ovi koraci kao da je los AI ispisao - - // Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register. - *PWPR_REGISTER_BASE &= ~0x40; // Set PFSWE bit - // Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register - *PWPR_REGISTER_BASE |= 0x80; // Set B0WI bit +#define PmnPFS ((hal_ll_gpio_pfs_t *)0x40040800UL) // Base address of PFS + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) { + uint32_t pin_index = ( pin_mask == 0xFFFF ) ? 0xFFFF : __builtin_ctz(pin_mask); // TODO Esma + hal_ll_port_name_t port_index; + port_index = 0;//hal_ll_gpio_port_index( pin_index ); + hal_ll_gpio_pfs_t *port_pfs_ptr = &PmnPFS->port[port_index].pin[pin_index]; + hal_ll_gpio_base_handle_t *port_ptr = (hal_ll_gpio_base_handle_t *) *port; + // Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register. + // *PWPR_REGISTER_BASE &= ~0x80; // Clear B0WI bit + // // Set 1 to the PFSWE bit in the PWPR register. This enables writing to the PmnPFS register. + // *PWPR_REGISTER_BASE |= 0x40; // Set PFSWE bit + R_PMISC->PWPR_b.B0WI = 0; + R_PMISC->PWPR_b.PFSWE = 1; + + if ( pin_mask == 0xFFFF ) { + if ( GPIO_CFG_DIGITAL_OUTPUT == config ) + port_ptr->pdr = pin_mask; + else if ( GPIO_CFG_DIGITAL_INPUT == config ) + port_ptr->pdr = 0; + } else { + // Clear the Port Mode Control bit in the PMR for the target pin to select the general I/O port. + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pmr = 0; + // Specify the input/output function for the pin through the PSEL[4:0] bit settings in the PmnPFS register. + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.psel = 0; + // Set the PMR to 1 as required to switch to the selected input/output function for the pin. + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pmr = 1; + + if( GPIO_CFG_ANALOG_INPUT == config ) { + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pmr = 0; + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pdr = 0; + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.asel = 1; + } else if ( GPIO_CFG_DIGITAL_OUTPUT == config ) { + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pdr = 1; + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.asel = 0; + } else if ( GPIO_CFG_DIGITAL_INPUT == config ) { + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pdr = 0; + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.asel = 0; + } + + // // Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register. + // *PWPR_REGISTER_BASE &= ~0x40; // Set PFSWE bit + // // Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register + // *PWPR_REGISTER_BASE |= 0x80; // Set B0WI bit + R_PMISC->PWPR_b.PFSWE = 0; + R_PMISC->PWPR_b.B0WI = 1; + } } -static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) { +static void hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) { + uint8_t pin_index; + hal_ll_pin_name_t pin_name; + hal_ll_port_name_t port_name; + // hal_ll_gpio_base_handle_t *port_ptr; + hal_ll_gpio_pfs_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + pin_index = hal_ll_gpio_pin_index( pin_name ); + + port_name = hal_ll_gpio_port_index( module_pin & 0xFF ); + port_ptr = ( hal_ll_gpio_base_handle_t* )hal_ll_gpio_port_base( port_name ); + + // port_pcr_array = ( hal_ll_gpio_pcr_base_handle_t* )( GPIO_PCR_BASE_VALUE + port_name * GPIO_PCR_OFFSET_VALUE ); + + hal_ll_gpio_config( (uint32_t *)&port_ptr, hal_ll_gpio_pin_mask( pin_index ), module_config ); + + if ( true == state ) { + port_ptr->port[port_name].pin[pin_index].pmnpfs_b.psel |= module_pin & 0x1F000000; + } else { + port_ptr->port[port_name].pin[pin_index].pmnpfs_b.psel &= ~( module_pin & 0x1F000000 ); + } } // ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c b/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c index f6f5008af2..bdebcb7ead 100644 --- a/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c +++ b/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c @@ -523,35 +523,35 @@ static void hal_ll_one_wire_read_bit( uint8_t *read_data_buffer ) { } void hal_ll_one_wire_reconfigure( hal_ll_one_wire_t *obj ) { - // Local instance of One Wire pin. - hal_ll_gpio_pin_t one_wire_pin; + // // Local instance of One Wire pin. + // hal_ll_gpio_pin_t one_wire_pin; - // Get pin base address and mask. - one_wire_pin.base = (hal_ll_gpio_base_t)hal_ll_gpio_port_base(hal_ll_gpio_port_index(obj->data_pin)); - one_wire_pin.mask = hal_ll_gpio_pin_mask(obj->data_pin); + // // Get pin base address and mask. + // one_wire_pin.base = (hal_ll_gpio_base_t)hal_ll_gpio_port_base(hal_ll_gpio_port_index(obj->data_pin)); + // one_wire_pin.mask = hal_ll_gpio_pin_mask(obj->data_pin); - // The idle state for the One Wire bus is HIGH. - do { - // Make sure that we have HIGH voltage state before any actions. - hal_ll_gpio_write_pin_output( &one_wire_pin, 1 ); + // // The idle state for the One Wire bus is HIGH. + // do { + // // Make sure that we have HIGH voltage state before any actions. + // hal_ll_gpio_write_pin_output( &one_wire_pin, 1 ); - // Make sure that pin is at HIGH voltage state. - } while ( !hal_ll_gpio_read_pin_output( &one_wire_pin ) ); + // // Make sure that pin is at HIGH voltage state. + // } while ( !hal_ll_gpio_read_pin_output( &one_wire_pin ) ); - // Memorize info about pin number (for future use). - one_wire_handle.data_pin = obj->data_pin % PORT_SIZE; + // // Memorize info about pin number (for future use). + // one_wire_handle.data_pin = obj->data_pin % PORT_SIZE; - // Get all the necessary registers for appropriate PORT which holds One Wire pin. - hal_ll_gpio_base_handle_t *gpio_ptr = (hal_ll_gpio_base_handle_t *)one_wire_pin.base; + // // Get all the necessary registers for appropriate PORT which holds One Wire pin. + // hal_ll_gpio_base_handle_t *gpio_ptr = (hal_ll_gpio_base_handle_t *)one_wire_pin.base; - // MODER register 32-bit address. - one_wire_handle.direction = (uint32_t)&gpio_ptr->gpiodir; + // // MODER register 32-bit address. + // one_wire_handle.direction = (uint32_t)&gpio_ptr->gpiodir; - // Memorize info about register whose main task is to alter GPIO pin direction. - one_wire_handle.input_output = (uint32_t)&gpio_ptr->gpiodata; + // // Memorize info about register whose main task is to alter GPIO pin direction. + // one_wire_handle.input_output = (uint32_t)&gpio_ptr->gpiodata; - // Set object state to true. - obj->state = true; + // // Set object state to true. + // obj->state = true; } // ------------------------------------------------------------------------- END From 858b8ee22a913e73d3dbcb857ec38fa0a944dc43 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Thu, 12 Jun 2025 14:40:43 +0200 Subject: [PATCH 05/62] mcu_defs update --- .../mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h index 7928d1f717..d0d3256b0f 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -75,7 +75,7 @@ //EOF TIM //GPIO -#define __PH1_CN // TODO +#define __PA0_CN // TODO #define __PORT_0_CN #define __PORT_1_CN From 37069d1d891e56fb136f8dd671eca3fb569c5f33 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Tue, 17 Jun 2025 14:20:05 +0200 Subject: [PATCH 06/62] GPIO ongoing, the test in SDK works --- .../RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 82 ++- .../renesas/include/gpio/hal_ll_gpio_port.h | 10 +- .../mikroe/renesas/include/hal_ll_pin_names.h | 486 +++++++++--------- .../mikroe/renesas/src/gpio/CMakeLists.txt | 1 + .../gpio/implementation_1/hal_ll_gpio_port.c | 35 +- 5 files changed, 352 insertions(+), 262 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h index d0d3256b0f..99b26fc22f 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -75,7 +75,87 @@ //EOF TIM //GPIO -#define __PA0_CN // TODO +#define __P000_CN +#define __P001_CN +#define __P002_CN +#define __P003_CN +#define __P004_CN +#define __P005_CN +#define __P006_CN +#define __P007_CN +#define __P008_CN +#define __P009_CN +#define __P010_CN +#define __P011_CN +#define __P012_CN +#define __P013_CN +#define __P014_CN +#define __P015_CN +#define __P100_CN +#define __P101_CN +#define __P102_CN +#define __P103_CN +#define __P104_CN +#define __P105_CN +#define __P106_CN +#define __P107_CN +#define __P108_CN +#define __P109_CN +#define __P110_CN +#define __P111_CN +#define __P112_CN +#define __P113_CN +#define __P114_CN +#define __P115_CN +#define __P200_CN +#define __P201_CN +#define __P202_CN +#define __P203_CN +#define __P204_CN +#define __P205_CN +#define __P206_CN +#define __P207_CN +#define __P208_CN +#define __P209_CN +#define __P210_CN +#define __P211_CN +#define __P212_CN +#define __P213_CN +#define __P214_CN +#define __P215_CN +#define __P300_CN +#define __P301_CN +#define __P302_CN +#define __P303_CN +#define __P304_CN +#define __P305_CN +#define __P306_CN +#define __P307_CN +#define __P308_CN +#define __P309_CN +#define __P310_CN +#define __P311_CN +#define __P312_CN +#define __P313_CN +#define __P314_CN +#define __P315_CN +#define __P400_CN +#define __P401_CN +#define __P402_CN +#define __P403_CN +#define __P404_CN +#define __P405_CN +#define __P406_CN +#define __P407_CN +#define __P408_CN +#define __P409_CN +#define __P410_CN +#define __P411_CN +#define __P412_CN +#define __P413_CN +#define __P414_CN +#define __P415_CN +// TODO Esma ports 5-9 #define __PORT_0_CN #define __PORT_1_CN diff --git a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h index dff0745b3a..3add15a7b8 100644 --- a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h +++ b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h @@ -67,29 +67,29 @@ typedef struct union { uint32_t pcntr1; struct { - uint16_t pdr; uint16_t podr; + uint16_t pdr; }; }; union { uint32_t pcntr2; struct { - uint16_t pidr; uint16_t eidr; // PORT1-4 only + uint16_t pidr; }; }; union { uint32_t pcntr3; struct { - uint16_t posr; uint16_t porr; + uint16_t posr; }; }; union { uint32_t pcntr4; // PORT1-4 only struct { - uint16_t eosr; // PORT1-4 only uint16_t eorr; // PORT1-4 only + uint16_t eosr; // PORT1-4 only }; }; } hal_ll_gpio_base_handle_t; @@ -192,7 +192,7 @@ uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ); * @param name - desired pin * @return uint32_t */ -uint8_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ); +uint16_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ); /** * @brief Get base address of ports registers diff --git a/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h b/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h index 5a9589a042..420456b2e6 100644 --- a/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h +++ b/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h @@ -108,336 +108,332 @@ extern "C"{ #define GPIO_FEATURE_GROUP_18 #endif -#ifdef __PA0_CN -#define GPIO_PA0 (0x00) -#define PA0 GPIO_PA0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA0! +#ifdef __P000_CN +#define GPIO_P000 (0x00) +#define P000 GPIO_P000 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA0! #endif -#ifdef __PA1_CN -#define GPIO_PA1 (0x01) -#define PA1 GPIO_PA1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA1! +#ifdef __P001_CN +#define GPIO_P001 (0x01) +#define P001 GPIO_P001 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA1! #endif -#ifdef __PA2_CN -#define GPIO_PA2 (0x02) -#define PA2 GPIO_PA2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA2! +#ifdef __P002_CN +#define GPIO_P002 (0x02) +#define P002 GPIO_P002 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA2! #endif -#ifdef __PA3_CN -#define GPIO_PA3 (0x03) -#define PA3 GPIO_PA3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA3! +#ifdef __P003_CN +#define GPIO_P003 (0x03) +#define P003 GPIO_P003 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA3! #endif -#ifdef __PA4_CN -#define GPIO_PA4 (0x04) -#define PA4 GPIO_PA4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA4! +#ifdef __P004_CN +#define GPIO_P004 (0x04) +#define P004 GPIO_P004 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA4! #endif -#ifdef __PA5_CN -#define GPIO_PA5 (0x05) -#define PA5 GPIO_PA5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA5! +#ifdef __P005_CN +#define GPIO_P005 (0x05) +#define P005 GPIO_P005 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA5! #endif -#ifdef __PA6_CN -#define GPIO_PA6 (0x06) -#define PA6 GPIO_PA6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA6! +#ifdef __P006_CN +#define GPIO_P006 (0x06) +#define P006 GPIO_P006 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA6! #endif -#ifdef __PA7_CN -#define GPIO_PA7 (0x07) -#define PA7 GPIO_PA7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA7! +#ifdef __P007_CN +#define GPIO_P007 (0x07) +#define P007 GPIO_P007 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA7! #endif - -#ifdef __PB0_CN -#define GPIO_PB0 (0x08) -#define PB0 GPIO_PB0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB0! +#ifdef __P008_CN +#define GPIO_P008 (0x08) +#define P008 GPIO_P008 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB0! #endif -#ifdef __PB1_CN -#define GPIO_PB1 (0x09) -#define PB1 GPIO_PB1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB1! +#ifdef __P009_CN +#define GPIO_P009 (0x09) +#define P009 GPIO_P009 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB1! #endif -#ifdef __PB2_CN -#define GPIO_PB2 (0x0A) -#define PB2 GPIO_PB2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB2! +#ifdef __P010_CN +#define GPIO_P010 (0x0A) +#define P010 GPIO_P010 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB2! #endif -#ifdef __PB3_CN -#define GPIO_PB3 (0x0B) -#define PB3 GPIO_PB3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB3! +#ifdef __P011_CN +#define GPIO_P011 (0x0B) +#define P011 GPIO_P011 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB3! #endif -#ifdef __PB4_CN -#define GPIO_PB4 (0x0C) -#define PB4 GPIO_PB4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB4! +#ifdef __P012_CN +#define GPIO_P012 (0x0C) +#define P012 GPIO_P012 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB4! #endif -#ifdef __PB5_CN -#define GPIO_PB5 (0x0D) -#define PB5 GPIO_PB5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB5! +#ifdef __P013_CN +#define GPIO_P013 (0x0D) +#define P013 GPIO_P013 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB5! #endif -#ifdef __PB6_CN -#define GPIO_PB6 (0x0E) -#define PB6 GPIO_PB6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB6! +#ifdef __P014_CN +#define GPIO_P014 (0x0E) +#define P014 GPIO_P014 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB6! #endif -#ifdef __PB7_CN -#define GPIO_PB7 (0x0F) -#define PB7 GPIO_PB7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB7! +#ifdef __P015_CN +#define GPIO_P015 (0x0F) +#define P015 GPIO_P015 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB7! #endif -#ifdef __PC0_CN -#define GPIO_PC0 (0x10) -#define PC0 GPIO_PC0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC0! +#ifdef __P100_CN +#define GPIO_P100 (0x10) +#define P100 GPIO_P100 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC0! #endif -#ifdef __PC1_CN -#define GPIO_PC1 (0x11) -#define PC1 GPIO_PC1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC1! +#ifdef __P101_CN +#define GPIO_P101 (0x11) +#define P101 GPIO_P101 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC1! #endif -#ifdef __PC2_CN -#define GPIO_PC2 (0x12) -#define PC2 GPIO_PC2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC2! +#ifdef __P102_CN +#define GPIO_P102 (0x12) +#define P102 GPIO_P102 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC2! #endif -#ifdef __PC3_CN -#define GPIO_PC3 (0x13) -#define PC3 GPIO_PC3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC3! +#ifdef __P103_CN +#define GPIO_P103 (0x13) +#define P103 GPIO_P103 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC3! #endif -#ifdef __PC4_CN -#define GPIO_PC4 (0x14) -#define PC4 GPIO_PC4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC4! +#ifdef __P104_CN +#define GPIO_P104 (0x14) +#define P104 GPIO_P104 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC4! #endif -#ifdef __PC5_CN -#define GPIO_PC5 (0x15) -#define PC5 GPIO_PC5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC5! +#ifdef __P105_CN +#define GPIO_P105 (0x15) +#define P105 GPIO_P105 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC5! #endif -#ifdef __PC6_CN -#define GPIO_PC6 (0x16) -#define PC6 GPIO_PC6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC6! +#ifdef __P106_CN +#define GPIO_P106 (0x16) +#define P106 GPIO_P106 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC6! #endif -#ifdef __PC7_CN -#define GPIO_PC7 (0x17) -#define PC7 GPIO_PC7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC7! +#ifdef __P107_CN +#define GPIO_P107 (0x17) +#define P107 GPIO_P107 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC7! #endif - -#ifdef __PD0_CN -#define GPIO_PD0 (0x18) -#define PD0 GPIO_PD0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD0! +#ifdef __P108_CN +#define GPIO_P108 (0x18) +#define P108 GPIO_P108 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD0! #endif -#ifdef __PD1_CN -#define GPIO_PD1 (0x19) -#define PD1 GPIO_PD1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD1! +#ifdef __P109_CN +#define GPIO_P109 (0x19) +#define P109 GPIO_P109 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD1! #endif -#ifdef __PD2_CN -#define GPIO_PD2 (0x1A) -#define PD2 GPIO_PD2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD2! +#ifdef __P110_CN +#define GPIO_P110 (0x1A) +#define P110 GPIO_P110 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD2! #endif -#ifdef __PD3_CN -#define GPIO_PD3 (0x1B) -#define PD3 GPIO_PD3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD3! +#ifdef __P111_CN +#define GPIO_P111 (0x1B) +#define P111 GPIO_P111 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD3! #endif -#ifdef __PD4_CN -#define GPIO_PD4 (0x1C) -#define PD4 GPIO_PD4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD4! +#ifdef __P112_CN +#define GPIO_P112 (0x1C) +#define P112 GPIO_P112 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD4! #endif -#ifdef __PD5_CN -#define GPIO_PD5 (0x1D) -#define PD5 GPIO_PD5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD5! +#ifdef __P113_CN +#define GPIO_P113 (0x1D) +#define P113 GPIO_P113 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD5! #endif -#ifdef __PD6_CN -#define GPIO_PD6 (0x1E) -#define PD6 GPIO_PD6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD6! +#ifdef __P114_CN +#define GPIO_P114 (0x1E) +#define P114 GPIO_P114 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD6! #endif -#ifdef __PD7_CN -#define GPIO_PD7 (0x1F) -#define PD7 GPIO_PD7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD7! +#ifdef __P115_CN +#define GPIO_P115 (0x1F) +#define P115 GPIO_P115 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD7! #endif -#ifdef __PE0_CN -#define GPIO_PE0 (0x20) -#define PE0 GPIO_PE0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE0! +#ifdef __P200_CN +#define GPIO_P200 (0x20) +#define P200 GPIO_P200 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE0! #endif -#ifdef __PE1_CN -#define GPIO_PE1 (0x21) -#define PE1 GPIO_PE1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE1! +#ifdef __P201_CN +#define GPIO_P201 (0x21) +#define P201 GPIO_P201 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE1! #endif -#ifdef __PE2_CN -#define GPIO_PE2 (0x22) -#define PE2 GPIO_PE2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE2! +#ifdef __P202_CN +#define GPIO_P202 (0x22) +#define P202 GPIO_P202 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE2! #endif -#ifdef __PE3_CN -#define GPIO_PE3 (0x23) -#define PE3 GPIO_PE3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE3! +#ifdef __P203_CN +#define GPIO_P203 (0x23) +#define P203 GPIO_P203 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE3! #endif -#ifdef __PE4_CN -#define GPIO_PE4 (0x24) -#define PE4 GPIO_PE4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE4! +#ifdef __P204_CN +#define GPIO_P204 (0x24) +#define P204 GPIO_P204 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE4! #endif -#ifdef __PE5_CN -#define GPIO_PE5 (0x25) -#define PE5 GPIO_PE5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE5! +#ifdef __P205_CN +#define GPIO_P205 (0x25) +#define P205 GPIO_P205 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE5! #endif -#ifdef __PE6_CN -#define GPIO_PE6 (0x26) -#define PE6 GPIO_PE6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE6! +#ifdef __P206_CN +#define GPIO_P206 (0x26) +#define P206 GPIO_P206 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE6! #endif -#ifdef __PE7_CN -#define GPIO_PE7 (0x27) -#define PE7 GPIO_PE7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE7! +#ifdef __P207_CN +#define GPIO_P207 (0x27) +#define P207 GPIO_P207 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE7! #endif - -#ifdef __PF0_CN -#define GPIO_PF0 (0x28) -#define PF0 GPIO_PF0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF0! +#ifdef __P208_CN +#define GPIO_P208 (0x28) +#define P208 GPIO_P208 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF0! #endif -#ifdef __PF1_CN -#define GPIO_PF1 (0x29) -#define PF1 GPIO_PF1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF1! +#ifdef __P209_CN +#define GPIO_P209 (0x29) +#define P209 GPIO_P209 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF1! #endif -#ifdef __PF2_CN -#define GPIO_PF2 (0x2A) -#define PF2 GPIO_PF2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF2! +#ifdef __P210_CN +#define GPIO_P210 (0x2A) +#define P210 GPIO_P210 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF2! #endif -#ifdef __PF3_CN -#define GPIO_PF3 (0x2B) -#define PF3 GPIO_PF3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF3! +#ifdef __P211_CN +#define GPIO_P211 (0x2B) +#define P211 GPIO_P211 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF3! #endif -#ifdef __PF4_CN -#define GPIO_PF4 (0x2C) -#define PF4 GPIO_PF4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF4! +#ifdef __P212_CN +#define GPIO_P212 (0x2C) +#define P212 GPIO_P212 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF4! #endif -#ifdef __PF5_CN -#define GPIO_PF5 (0x2D) -#define PF5 GPIO_PF5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF5! +#ifdef __P213_CN +#define GPIO_P213 (0x2D) +#define P213 GPIO_P213 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF5! #endif -#ifdef __PF6_CN -#define GPIO_PF6 (0x2E) -#define PF6 GPIO_PF6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF6! +#ifdef __P214_CN +#define GPIO_P214 (0x2E) +#define P214 GPIO_P214 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF6! #endif -#ifdef __PF7_CN -#define GPIO_PF7 (0x2F) -#define PF7 GPIO_PF7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF7! +#ifdef __P215_CN +#define GPIO_P215 (0x2F) +#define P215 GPIO_P215 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF7! #endif -#ifdef __PG0_CN -#define GPIO_PG0 (0x30) -#define PG0 GPIO_PG0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG0! +#ifdef __P300_CN +#define GPIO_P300 (0x30) +#define P300 GPIO_P300 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG0! #endif -#ifdef __PG1_CN -#define GPIO_PG1 (0x31) -#define PG1 GPIO_PG1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG1! +#ifdef __P301_CN +#define GPIO_P301 (0x31) +#define P301 GPIO_P301 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG1! #endif -#ifdef __PG2_CN -#define GPIO_PG2 (0x32) -#define PG2 GPIO_PG2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG2! +#ifdef __P302_CN +#define GPIO_P302 (0x32) +#define P302 GPIO_P302 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG2! #endif -#ifdef __PG3_CN -#define GPIO_PG3 (0x33) -#define PG3 GPIO_PG3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG3! +#ifdef __P303_CN +#define GPIO_P303 (0x33) +#define P303 GPIO_P303 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG3! #endif -#ifdef __PG4_CN -#define GPIO_PG4 (0x34) -#define PG4 GPIO_PG4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG4! +#ifdef __P304_CN +#define GPIO_P304 (0x34) +#define P304 GPIO_P304 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG4! #endif -#ifdef __PG5_CN -#define GPIO_PG5 (0x35) -#define PG5 GPIO_PG5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG5! +#ifdef __P305_CN +#define GPIO_P305 (0x35) +#define P305 GPIO_P305 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG5! #endif -#ifdef __PG6_CN -#define GPIO_PG6 (0x36) -#define PG6 GPIO_PG6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG6! +#ifdef __P306_CN +#define GPIO_P306 (0x36) +#define P306 GPIO_P306 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG6! #endif -#ifdef __PG7_CN -#define GPIO_PG7 (0x37) -#define PG7 GPIO_PG7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG7! +#ifdef __P307_CN +#define GPIO_P307 (0x37) +#define P307 GPIO_P307 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG7! #endif - -#ifdef __PH0_CN -#define GPIO_PH0 (0x38) -#define PH0 GPIO_PH0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH0! +#ifdef __P308_CN +#define GPIO_P308 (0x38) +#define P308 GPIO_P308 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH0! #endif -#ifdef __PH1_CN -#define GPIO_PH1 (0x39) -#define PH1 GPIO_PH1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH1! +#ifdef __P309_CN +#define GPIO_P309 (0x39) +#define P309 GPIO_P309 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH1! #endif -#ifdef __PH2_CN -#define GPIO_PH2 (0x3A) -#define PH2 GPIO_PH2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH2! +#ifdef __P310_CN +#define GPIO_P310 (0x3A) +#define P310 GPIO_P310 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH2! #endif -#ifdef __PH3_CN -#define GPIO_PH3 (0x3B) -#define PH3 GPIO_PH3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH3! +#ifdef __P311_CN +#define GPIO_P311 (0x3B) +#define P311 GPIO_P311 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH3! #endif -#ifdef __PH4_CN -#define GPIO_PH4 (0x3C) -#define PH4 GPIO_PH4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH4! +#ifdef __P312_CN +#define GPIO_P312 (0x3C) +#define P312 GPIO_P312 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH4! #endif -#ifdef __PH5_CN -#define GPIO_PH5 (0x3D) -#define PH5 GPIO_PH5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH5! +#ifdef __P313_CN +#define GPIO_P313 (0x3D) +#define P313 GPIO_P313 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH5! #endif -#ifdef __PH6_CN -#define GPIO_PH6 (0x3E) -#define PH6 GPIO_PH6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH6! +#ifdef __P314_CN +#define GPIO_P314 (0x3E) +#define P314 GPIO_P314 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH6! #endif -#ifdef __PH7_CN -#define GPIO_PH7 (0x3F) -#define PH7 GPIO_PH7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH7! +#ifdef __P315_CN +#define GPIO_P315 (0x3F) +#define P315 GPIO_P315 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH7! #endif -#ifdef __PJ0_CN -#define GPIO_PJ0 (0x40) -#define PJ0 GPIO_PJ0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ0! +#ifdef __P400_CN +#define GPIO_P400 (0x40) +#define P400 GPIO_P400 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG0! #endif -#ifdef __PJ1_CN -#define GPIO_PJ1 (0x41) -#define PJ1 GPIO_PJ1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ1! +#ifdef __P401_CN +#define GPIO_P401 (0x41) +#define P401 GPIO_P401 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG1! #endif -#ifdef __PJ2_CN -#define GPIO_PJ2 (0x42) -#define PJ2 GPIO_PJ2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ2! +#ifdef __P402_CN +#define GPIO_P402 (0x42) +#define P402 GPIO_P402 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG2! #endif -#ifdef __PJ3_CN -#define GPIO_PJ3 (0x43) -#define PJ3 GPIO_PJ3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ3! +#ifdef __P403_CN +#define GPIO_P403 (0x43) +#define P403 GPIO_P403 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG3! #endif -#ifdef __PJ4_CN -#define GPIO_PJ4 (0x44) -#define PJ4 GPIO_PJ4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ4! +#ifdef __P404_CN +#define GPIO_P404 (0x44) +#define P404 GPIO_P404 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG4! #endif -#ifdef __PJ5_CN -#define GPIO_PJ5 (0x45) -#define PJ5 GPIO_PJ5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ5! +#ifdef __P405_CN +#define GPIO_P405 (0x45) +#define P405 GPIO_P405 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG5! #endif -#ifdef __PJ6_CN -#define GPIO_PJ6 (0x46) -#define PJ6 GPIO_PJ6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ6! +#ifdef __P406_CN +#define GPIO_P406 (0x46) +#define P406 GPIO_P406 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG6! #endif -#ifdef __PJ7_CN -#define GPIO_PJ7 (0x47) -#define PJ7 GPIO_PJ7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PJ7! +#ifdef __P407_CN +#define GPIO_P407 (0x47) +#define P407 GPIO_P407 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG7! #endif - -#ifdef __PK0_CN -#define GPIO_PK0 (0x48) -#define PK0 GPIO_PK0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK0! +#ifdef __P408_CN +#define GPIO_P408 (0x48) +#define P408 GPIO_P408 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH0! #endif -#ifdef __PK1_CN -#define GPIO_PK1 (0x49) -#define PK1 GPIO_PK1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK1! +#ifdef __P409_CN +#define GPIO_P409 (0x49) +#define P409 GPIO_P409 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH1! #endif -#ifdef __PK2_CN -#define GPIO_PK2 (0x4A) -#define PK2 GPIO_PK2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK2! +#ifdef __P410_CN +#define GPIO_P410 (0x4A) +#define P410 GPIO_P410 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH2! #endif -#ifdef __PK3_CN -#define GPIO_PK3 (0x4B) -#define PK3 GPIO_PK3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK3! +#ifdef __P411_CN +#define GPIO_P411 (0x4B) +#define P411 GPIO_P411 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH3! #endif -#ifdef __PK4_CN -#define GPIO_PK4 (0x4C) -#define PK4 GPIO_PK4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK4! +#ifdef __P412_CN +#define GPIO_P412 (0x4C) +#define P412 GPIO_P412 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH4! #endif -#ifdef __PK5_CN -#define GPIO_PK5 (0x4D) -#define PK5 GPIO_PK5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK5! +#ifdef __P413_CN +#define GPIO_P413 (0x4D) +#define P413 GPIO_P413 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH5! #endif -#ifdef __PK6_CN -#define GPIO_PK6 (0x4E) -#define PK6 GPIO_PK6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK6! +#ifdef __P414_CN +#define GPIO_P414 (0x4E) +#define P414 GPIO_P414 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH6! #endif -#ifdef __PK7_CN -#define GPIO_PK7 (0x4F) -#define PK7 GPIO_PK7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PK7! +#ifdef __P415_CN +#define GPIO_P415 (0x4F) +#define P415 GPIO_P415 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH7! #endif +// TODO Esma ports 5-9 #ifdef __PL0_CN #define GPIO_PL0 (0x50) #define PL0 GPIO_PL0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL0! diff --git a/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt b/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt index 101edda177..bbc85c96a3 100644 --- a/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt @@ -27,6 +27,7 @@ mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO # END GPIO ../../include/hal_ll_rcc.h ../../include/hal_ll_target.h + ../../include/hal_ll_pin_names.h # BEGIN GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_port.h diff --git a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c index 979677128e..561bc92c7d 100644 --- a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c @@ -44,12 +44,9 @@ #include "hal_ll_gpio_port.h" #include "hal_ll_rcc.h" -#define hal_ll_gpio_port_get_pin_index(__index) ( __index & 0xF0 )?( ( uint8_t )__index % PORT_SIZE ): \ - ( ( uint8_t )__index % PORT_SIZE ) - -#define hal_ll_gpio_port_get_port_index(__index) ( __index & 0xF0 )?( ( uint8_t )__index / PORT_SIZE ): \ - ( ( uint8_t )__index / PORT_SIZE ) +#define hal_ll_gpio_port_get_pin_index(__index) ( ( uint8_t )__index&0xF )//% PORT_SIZE ) +#define hal_ll_gpio_port_get_port_index(__index) ( ( uint8_t )(__index&0xF0) >> 4 ) #define GPIO_PORT0_BASE (0x40040000UL) #define GPIO_PORT1_BASE (0x40040020UL) @@ -124,11 +121,15 @@ static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ); // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) { - return hal_ll_gpio_port_get_port_index( name ); + uint16_t ret; + ret = hal_ll_gpio_port_get_port_index( name ); + return ret; } -uint8_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) { - return ( 1UL << hal_ll_gpio_pin_index( name ) ); +uint16_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) { + uint16_t ret; + ret = ( 1UL << hal_ll_gpio_pin_index( name ) ); + return ret; } uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) { @@ -167,6 +168,17 @@ static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) { static void hal_ll_gpio_clock_enable( uint32_t port ) { // TODO Esma - PORTs don't have clock enabling feature. } + +uint32_t get_port_number(uint32_t base_addr) +{ + for (int i = 0; i < sizeof(hal_ll_gpio_port_base_arr) / sizeof(hal_ll_gpio_port_base_arr[0]); i++) { + if (hal_ll_gpio_port_base_arr[i] == base_addr) { + return i; // port number + } + } + return -1; // not found +} + #include "mcu.h" #define PmnPFS ((hal_ll_gpio_pfs_t *)0x40040800UL) // Base address of PFS @@ -174,8 +186,8 @@ static void hal_ll_gpio_clock_enable( uint32_t port ) { static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) { uint32_t pin_index = ( pin_mask == 0xFFFF ) ? 0xFFFF : __builtin_ctz(pin_mask); // TODO Esma hal_ll_port_name_t port_index; - port_index = 0;//hal_ll_gpio_port_index( pin_index ); - hal_ll_gpio_pfs_t *port_pfs_ptr = &PmnPFS->port[port_index].pin[pin_index]; + port_index = get_port_number( *port ); + hal_ll_gpio_pfs_t *port_pfs_ptr = &PmnPFS->port[0].pin[0]; hal_ll_gpio_base_handle_t *port_ptr = (hal_ll_gpio_base_handle_t *) *port; // Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register. @@ -196,7 +208,8 @@ static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t conf // Specify the input/output function for the pin through the PSEL[4:0] bit settings in the PmnPFS register. port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.psel = 0; // Set the PMR to 1 as required to switch to the selected input/output function for the pin. - port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pmr = 1; + // TODO Esma zasto odmah stavljamo da nije GPIO nego peripheral? + // port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pmr = 1; if( GPIO_CFG_ANALOG_INPUT == config ) { port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pmr = 0; From 8c8323b1950daa7237ef547c2e8665258d7f6942 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Thu, 19 Jun 2025 12:43:54 +0200 Subject: [PATCH 07/62] renesas low level update --- .../mikroe/renesas/include/adc/hal_ll_adc.h | 1 - .../arm/mikroe/renesas/include/hal_ll_rcc.h | 70 -- .../arm/mikroe/renesas/src/adc/CMakeLists.txt | 1 - .../arm/mikroe/renesas/src/can/CMakeLists.txt | 54 - .../src/can/implementation_1/hal_ll_can.c | 1017 ----------------- .../arm/mikroe/renesas/src/dma/CMakeLists.txt | 56 - .../src/dma/implementation_1/hal_ll_dma.c | 759 ------------ .../mikroe/renesas/src/gpio/CMakeLists.txt | 1 - .../gpio/implementation_1/hal_ll_gpio_port.c | 1 - .../mikroe/renesas/src/hal_ll/CMakeLists.txt | 2 +- .../arm/mikroe/renesas/src/i2c/CMakeLists.txt | 1 - .../i2c/implementation_1/hal_ll_i2c_master.c | 1 - .../renesas/src/one_wire/hal_ll_one_wire.c | 380 +----- .../renesas/src/spi_master/CMakeLists.txt | 1 - .../implementation_1/hal_ll_spi_master.c | 150 +-- .../arm/mikroe/renesas/src/tim/CMakeLists.txt | 1 - .../src/tim/implementation_1/hal_ll_tim.c | 397 +------ .../mikroe/renesas/src/uart/CMakeLists.txt | 1 - .../src/uart/implementation_1/hal_ll_uart.c | 313 +---- 19 files changed, 60 insertions(+), 3147 deletions(-) delete mode 100644 targets/arm/mikroe/renesas/include/hal_ll_rcc.h delete mode 100644 targets/arm/mikroe/renesas/src/can/CMakeLists.txt delete mode 100644 targets/arm/mikroe/renesas/src/can/implementation_1/hal_ll_can.c delete mode 100644 targets/arm/mikroe/renesas/src/dma/CMakeLists.txt delete mode 100644 targets/arm/mikroe/renesas/src/dma/implementation_1/hal_ll_dma.c diff --git a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc.h b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc.h index 8bc6da174e..4980973df7 100644 --- a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc.h +++ b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc.h @@ -49,7 +49,6 @@ extern "C"{ #endif #include "hal_ll_target.h" -#include "hal_ll_rcc.h" #define HAL_ADC_6BIT_RES_VAL (0x003FU) #define HAL_ADC_8BIT_RES_VAL (0x00FFU) diff --git a/targets/arm/mikroe/renesas/include/hal_ll_rcc.h b/targets/arm/mikroe/renesas/include/hal_ll_rcc.h deleted file mode 100644 index 33664d51c0..0000000000 --- a/targets/arm/mikroe/renesas/include/hal_ll_rcc.h +++ /dev/null @@ -1,70 +0,0 @@ -/**************************************************************************** -** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. -** Contact: https://www.mikroe.com/contact -** -** This file is part of the mikroSDK package -** -** Commercial License Usage -** -** Licensees holding valid commercial NECTO compilers AI licenses may use this -** file in accordance with the commercial license agreement provided with the -** Software or, alternatively, in accordance with the terms contained in -** a written agreement between you and The MikroElektronika Company. -** For licensing terms and conditions see -** https://www.mikroe.com/legal/software-license-agreement. -** For further information use the contact form at -** https://www.mikroe.com/contact. -** -** -** GNU Lesser General Public License Usage -** -** Alternatively, this file may be used for -** non-commercial projects under the terms of the GNU Lesser -** General Public License version 3 as published by the Free Software -** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. -** -** The above copyright notice and this permission notice shall be -** included in all copies or substantial portions of the Software. -** -** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT -** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE -** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -** -****************************************************************************/ -/*! - * @file hal_ll_rcc.h - * @brief Reset and Clock control defines necessary for HAL. - */ - -#ifndef _HAL_LL_RCC_H_ -#define _HAL_LL_RCC_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -#include - -/** - * Core register addresses used in source. - */ -#define _SYSCTL_RCGCGPIO ( uint32_t * )0x400FE608 -#define _SYSCTL_GPIOHBCTL ( uint32_t * )0x400FE06C -#define _SYSCTL_RCGCSSI ( uint32_t * )0x400FE61C -#define _SYSCTL_RCGCTIMER ( uint32_t * )0x400FE604 -#define _SYSCTL_RCGCUART ( uint32_t * )0x400FE618 -#define _SYSCTL_RCGCI2C ( uint32_t * )0x400FE620 -#define _SYSCTL_RCGCADC ( uint32_t * )0x400FE638 -#define _SYSCTL_RCGCCAN ( uint32_t * )0x400FE634 - -#ifdef __cplusplus -} -#endif - -#endif // _HAL_LL_RCC_H_ -// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt b/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt index f146c6a315..5692ad375a 100644 --- a/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt @@ -21,7 +21,6 @@ set(adc_pin_map "hal_ll_adc_pin_map/implementation_1") mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC ${adc_subimplementation} - ../../include/hal_ll_rcc.h ../../include/hal_ll_target.h #BEGIN ADC ../../include/adc/hal_ll_adc.h diff --git a/targets/arm/mikroe/renesas/src/can/CMakeLists.txt b/targets/arm/mikroe/renesas/src/can/CMakeLists.txt deleted file mode 100644 index 0e6f9404ef..0000000000 --- a/targets/arm/mikroe/renesas/src/can/CMakeLists.txt +++ /dev/null @@ -1,54 +0,0 @@ -## ./targets/arm/mikroe/tiva/src/can/CMakeLists.txt -set(mcu_header_path ${MCU_NAME}) - -find_cortex(hal_ll_def_list) - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -## BEGIN CAN -set(can_subimplementation "implementation_1/hal_ll_can.c") -set(can_pin_map "hal_ll_can_pin_map") -## END CAN - -mikrosdk_add_library(lib_hal_ll_can MikroSDK.HalLowLevel.CAN - ${can_subimplementation} - - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h - # BEGIN CAN - ../../include/can/hal_ll_can.h - ../../include/can/${can_pin_map}/hal_ll_can_pin_map.h - # END CAN -) - -target_compile_definitions(lib_hal_ll_can PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_can PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_can - PRIVATE - ../../include - ../../include/gpio - # BEGIN CAN - ../../include/can - ../../include/can/${can_pin_map} - # END CAN - - INTERFACE - $ - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.CAN) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.CAN ../../include/can/hal_ll_can.h) diff --git a/targets/arm/mikroe/renesas/src/can/implementation_1/hal_ll_can.c b/targets/arm/mikroe/renesas/src/can/implementation_1/hal_ll_can.c deleted file mode 100644 index e1d1854fef..0000000000 --- a/targets/arm/mikroe/renesas/src/can/implementation_1/hal_ll_can.c +++ /dev/null @@ -1,1017 +0,0 @@ -/**************************************************************************** -** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. -** Contact: https://www.mikroe.com/contact -** -** This file is part of the mikroSDK package -** -** Commercial License Usage -** -** Licensees holding valid commercial NECTO compilers AI licenses may use this -** file in accordance with the commercial license agreement provided with the -** Software or, alternatively, in accordance with the terms contained in -** a written agreement between you and The MikroElektronika Company. -** For licensing terms and conditions see -** https://www.mikroe.com/legal/software-license-agreement. -** For further information use the contact form at -** https://www.mikroe.com/contact. -** -** -** GNU Lesser General Public License Usage -** -** Alternatively, this file may be used for -** non-commercial projects under the terms of the GNU Lesser -** General Public License version 3 as published by the Free Software -** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. -** -** The above copyright notice and this permission notice shall be -** included in all copies or substantial portions of the Software. -** -** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT -** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE -** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -** -****************************************************************************/ -/*! - * @file hal_ll_can.c - * @brief CAN HAL LOW LEVEL layer implementation. - */ - -#include "hal_ll_rcc.h" -#include "hal_ll_can.h" -#include "hal_ll_gpio.h" -#include "hal_ll_can_pin_map.h" -#include "hal_ll_bit_control.h" - -/*!< @brief Local handle list */ -static volatile hal_ll_can_handle_register_t hal_ll_module_state[CAN_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; - -// ------------------------------------------------------------- PRIVATE MACROS -/*!< @brief Helper macro for getting hal_ll_module_state address */ -#define hal_ll_can_get_module_state_address ((hal_ll_can_handle_register_t *)*handle) -/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ -#define hal_ll_can_get_handle (hal_ll_can_handle_register_t *)hal_ll_can_get_module_state_address->hal_ll_can_handle -/*!< @brief Helper macro for getting module specific control register structure */ -#define hal_ll_can_get_base_struct(_handle) ((hal_ll_can_base_handle_t *)_handle) -/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ -#define hal_ll_can_get_base_from_hal_handle ((hal_ll_can_hw_specifics_map_t *)((hal_ll_can_handle_register_t *)\ - (((hal_ll_can_handle_register_t *)(handle))->hal_ll_can_handle))->hal_ll_can_handle)->base - -#define HAL_LL_CAN_AF_CONFIG (GPIO_CFG_ALT_FUNCTION | GPIO_CFG_DIGITAL_ENABLE | GPIO_CFG_DRIVE_8mA) - -#define HAL_LL_CAN1_CLOCK_ENABLE (0) -#define HAL_LL_CAN2_CLOCK_ENABLE (1) - -#define HAL_LL_CAN_CANCTL_INIT_BIT (0) -#define HAL_LL_CAN_CANCTL_DAR_BIT (5) -#define HAL_LL_CAN_CANCTL_TEST_BIT (7) -#define HAL_LL_CAN_CANTST_LBACK_BIT (4) -#define HAL_LL_CAN_CANCTL_CCE_BIT (6) - -#define HAL_LL_CAN_IF_CRQ_BUSY_BIT (15) - -#define HAL_LL_CAN_IF_CMSK_WRNRD_MASK (0x80UL) -#define HAL_LL_CAN_IF_CMSK_MASK_MASK (0x40UL) -#define HAL_LL_CAN_IF_CMSK_ARB_MASK (0x20UL) -#define HAL_LL_CAN_IF_CMSK_CONTROL_MASK (0x10UL) -#define HAL_LL_CAN_IF_CMSK_CLRINTPND_MASK (0x8UL) -#define HAL_LL_CAN_IF_CMSK_NEWDAT_MASK (0x4UL) -#define HAL_LL_CAN_IF_CMSK_TXRQST_MASK (HAL_LL_CAN_IF_CMSK_NEWDAT_MASK) -#define HAL_LL_CAN_IF_CMSK_DATAA_MASK (0x2UL) -#define HAL_LL_CAN_IF_CMSK_DATAB_MASK (0x1UL) -#define HAL_LL_CAN_IF_CMSK_TXRQST_BIT (2) -#define HAL_LL_CAN_IF_CMSK_NEWDAT_BIT (HAL_LL_CAN_IF_CMSK_TXRQST_BIT) - -#define HAL_LL_CAN_IF_MCTL_RMTEN_BIT (9) -#define HAL_LL_CAN_IF_MCTL_TXRQST_BIT (8) -#define HAL_LL_CAN_IF_MCTL_EOB_BIT (7) -#define HAL_LL_CAN_IF_MCTL_NEWDAT_BIT (15) -#define HAL_LL_CAN_IF_MCTL_DLC_MASK (0xFUL) -#define HAL_LL_CAN_IF_MCTL_TXRQST_MASK (0x100UL) -#define HAL_LL_CAN_IF_MCTL_UMASK_BIT (12) - -#define HAL_LL_CAN_IF_ARB2_MSGVAL_BIT (15) -#define HAL_LL_CAN_IF_ARB2_XTD_BIT (14) -#define HAL_LL_CAN_IF_ARB2_DIR_BIT (13) -#define HAL_LL_CAN_IF_ARB2_ID_MASK (0x1FFFUL) -#define HAL_LL_CAN_IF_ARB2_MSGVAL_MASK (0x8000UL) -#define HAL_LL_CAN_IF_ARB2_DIR_MASK (0x2000UL) -#define HAL_LL_CAN_IF_ARB2_ID_SHIFT (2) - -#define HAL_LL_CAN_IF_MSK2_ID_SHIFT (HAL_LL_CAN_IF_ARB2_ID_SHIFT) - -#define HAL_LL_CAN_CANBIT_SJW_SHIFT (6) -#define HAL_LL_CAN_CANBIT_TSEG1_SHIFT (8) -#define HAL_LL_CAN_CANBIT_TSEG2_SHIFT (12) -#define HAL_LL_CAN_CANBRPE_PRESCALER_SHIFT (6) -#define HAL_LL_CAN_PRESCALER_BITS_5_0 (0x3FUL) -#define HAL_LL_CAN_PRESCALER_BITS_10_6 (0x3CUL) - -#define HAL_LL_CAN_SJW_CONST_VALUE (1) -#define HAL_LL_CAN_TSEG1_MAX_VAL (16) -#define HAL_LL_CAN_TSEG2_MAX_VAL (8) -#define HAL_LL_CAN_PRESCALER_MAX_VAL (1024) -#define HAL_LL_CAN_BIT_RATE_SAMPLE_POINT (0.875) - -#define HAL_LL_CAN_TRANSMIT_MESSAGE_ID (1) - -#define HAL_LL_CAN_EID_BITS_28_11 (0x3FFFF800UL) -#define HAL_LL_CAN_SID_MASK (0x7FFUL) - -#define HAL_LL_CAN_MAX_MNUM (32) - -#define HAL_LL_CAN_REG_CLEAR (0x0000UL) - -#define HAL_LL_CAN_IF_DATA_SHIFT (8) - -#define HAL_LL_CAN_TIMEOUT_VALUE (10000UL) - -/*!< @brief CAN hw specific structure */ -typedef struct -{ - hal_ll_base_addr_t base; - hal_ll_pin_name_t module_index; - hal_ll_can_pins_t pins; - hal_ll_can_mode_t mode; - uint32_t frequency; -} hal_ll_can_hw_specifics_map_t; - -/*!< @brief CAN hw specific module values */ -typedef struct -{ - hal_ll_pin_name_t pin_tx; - hal_ll_pin_name_t pin_rx; -} hal_ll_can_pin_id; - -/*!< @brief CAN IF structure */ -typedef struct -{ - hal_ll_base_addr_t crq; - hal_ll_base_addr_t cmsk; - hal_ll_base_addr_t msk1; - hal_ll_base_addr_t msk2; - hal_ll_base_addr_t arb1; - hal_ll_base_addr_t arb2; - hal_ll_base_addr_t mctl; - hal_ll_base_addr_t da1; - hal_ll_base_addr_t da2; - hal_ll_base_addr_t db1; - hal_ll_base_addr_t db2; -} hal_ll_can_if; - -/*!< @brief CAN HW register structure */ -typedef struct -{ - hal_ll_base_addr_t canctl; - hal_ll_base_addr_t cansts; - hal_ll_base_addr_t canerr; - hal_ll_base_addr_t canbit; - hal_ll_base_addr_t canint; - hal_ll_base_addr_t cantst; - hal_ll_base_addr_t canbrpe; - hal_ll_base_addr_t res0; - hal_ll_can_if can_if1; - hal_ll_base_addr_t res[13]; - hal_ll_can_if can_if2; - hal_ll_base_addr_t res1[21]; - hal_ll_base_addr_t cantxrq[2]; - hal_ll_base_addr_t res2[6]; - hal_ll_base_addr_t cannwda[2]; - hal_ll_base_addr_t res5[6]; - hal_ll_base_addr_t canmsgint[2]; - hal_ll_base_addr_t res4[6]; - hal_ll_base_addr_t canmsgval[2]; -} hal_ll_can_base_handle_t; - -/*!< @brief CAN hw specific error values */ -typedef enum -{ - HAL_LL_CAN_SUCCESS = 0, - HAL_LL_CAN_WRONG_PINS, - HAL_LL_CAN_MODULE_ERROR, - - HAL_LL_CAN_ERROR = (-1) -} hal_ll_can_err_t; -// ------------------------------------------------------------------ VARIABLES -/*!< @brief CAN hardware specific info */ -static hal_ll_can_hw_specifics_map_t hal_ll_can_hw_specifics_map[] = -{ - #ifdef CAN_MODULE_0 - { HAL_LL_CAN0_BASE_ADDRESS, hal_ll_can_module_num( CAN_MODULE_0 ), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, HAL_LL_CAN_MODE_NORMAL, 125000 }, - #endif - #ifdef CAN_MODULE_1 - { HAL_LL_CAN1_BASE_ADDRESS, hal_ll_can_module_num( CAN_MODULE_1 ), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, HAL_LL_CAN_MODE_NORMAL, 125000 }, - #endif - - { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, HAL_LL_CAN_MODE_NORMAL, 125000 } -}; - - -/*!< @brief Global handle variables used in functions */ -static volatile hal_ll_can_handle_register_t *low_level_handle; -static volatile hal_ll_can_hw_specifics_map_t *hal_ll_can_hw_specifics_map_local; -// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS -/** - * @brief Check if pins are adequate. - * - * Checks tx and rx pins the user has passed with pre-defined - * pins in tx and rx maps. Take into consideration that module - * index numbers have to be the same for both pins. - * - * @param[in] tx - TX pre-defined pin name. - * @param[in] rx - RX pre-defined pin name. - * @param[in] *index_list - Index list address - * @return hal_ll_pin_name_t Module index based on pins. - * - * Returns pre-defined module index from pin maps, if pins - * are adequate. - */ -static hal_ll_pin_name_t hal_ll_can_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, - hal_ll_can_pin_id *index_list, hal_ll_can_handle_register_t *handle_map ); - -/** - * @brief Sets CAN pin alternate function state. - * - * Sets adequate value for alternate function settings. - * This function must be called if CAN is to work. - * Based on value of hal_ll_state, alternate functions can be - * set or cleared. - * - * @param[in] map - Object specific context handler. - * @param[in] hal_ll_state - Init/De-init - * - * @return None - */ -static void hal_ll_can_alternate_functions_set_state( hal_ll_can_hw_specifics_map_t *map, bool hal_ll_state ); - -/** - * @brief Maps new-found module specific values. - * - * Maps pin names and alternate function values for - * CAN TX and RX pins. - * - * @param[in] module_index CAN HW module index -- 0,1,2... - * @param[in] *index_list Array with TX and RX map index values - * and module number - * - * @return None - */ -static void hal_ll_can_map_pins( uint8_t module_index, hal_ll_can_pin_id *index_list ); - -/** - * @brief Get local hardware specific map. - * - * Checks handle value and returns address of adequate - * hal_ll_can_hw_specifics_map array index. - * - * @param[in] handle - Object specific context handler. - * @return hal_ll_can_hw_specifics_map_t Map address. - * - * Returns pre-defined map index address based on handle value, - * if handle is adequate. - */ -static hal_ll_can_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); - -/** - * @brief Full CAN module initialization procedure. - * - * Initializes CAN module on hardware level, based on beforehand - * set configuration and module handler. Sets control and filter registers. - * Initializes module clock. - * - * @param[in] map - Object specific context handler. - * @param[in] config - CAN config structure. - * @param[in] filter_config - CAN filter config structure. - * @return hal_ll_err_t Module specific values. - * - * Returns one of pre-defined values. - * Take into consideration that this is hardware specific. - */ -static hal_ll_err_t hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config, - hal_ll_can_filter_config_t *filter_config ); - -/** - * @brief Calculates parameters for desired CAN frequency. - * - * Calculates adequate values to be written in CAN_BTR register - * in order to set appropriate baud rate. - * - * @param[in] map - Object specific context handler. - * @return hal_ll_err_t Module specific values. - * - * Returns one of pre-defined values. - * Take into consideration that this is hardware specific. - */ -static hal_ll_err_t hal_ll_can_bit_timing( hal_ll_can_hw_specifics_map_t *map ); - -/** - * @brief Initialize CAN module on hardware level. - * - * Initializes CAN module on hardware level, based on beforehand - * set configuration and module handler. - * - * @param[in] map - Object specific context handler. - * @param[in] config - CAN config structure. - * @return hal_ll_err_t Module specific values. - * - * Returns one of pre-defined values. - * Take into consideration that this is hardware specific. - */ -static hal_ll_err_t hal_ll_can_module_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config ); - -/** - * @brief Configure CAN filter. - * - * Initializes CAN filter on hardware level, based on beforehand - * set configuration and module handler. - * - * @param[in] map - Object specific context handler. - * @param[in] filter_config - CAN filter config structure. - * @return hal_ll_err_t Module specific values. - * - * Returns one of pre-defined values. - * Take into consideration that this is hardware specific. - */ -static hal_ll_err_t hal_ll_can_filter_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_filter_config_t *filter_config ); - -/** - * @brief Enable clock for CAN module on hardware level. - * - * Initializes CAN module clock on hardware level, based on beforehand - * set configuration and module handler. - * - * @param[in] map - Object specific context handler. - * @param[in] clock_enable - True(enable clock)/False(disable clock). - * - * @return None - */ -static void hal_ll_can_clock_enable( uint8_t module_index, bool clock_enable ); - -/** - * @brief Configure CAN message object. - * - * Initializes CAN message object on hardware level, based on its number and identifier. - * - * @param[in] base - CAN module base address. - * @param[in] message_object_num - Message object number. - * @return identifier Message/filter ID. - * - * Returns one of pre-defined values. - * Take into consideration that this is hardware specific. - */ -static hal_ll_err_t message_config( hal_ll_base_addr_t *base, uint8_t message_object_num, uint32_t identifier ); - -// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS -hal_ll_err_t hal_ll_can_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_can_handle_register_t *handle_map, uint8_t *hal_module_id ) { - - hal_ll_can_pin_id index_list[CAN_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; - uint16_t pin_check_result; - - // Check if pins are valid - if ( HAL_LL_PIN_NC == ( pin_check_result = hal_ll_can_check_pins( tx_pin, rx_pin, &index_list, handle_map ))) { - return HAL_LL_CAN_WRONG_PINS; - }; - - if ( (hal_ll_can_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || - (hal_ll_can_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) - { - hal_ll_can_alternate_functions_set_state( &hal_ll_can_hw_specifics_map[ pin_check_result ], false ); - - hal_ll_can_map_pins( pin_check_result, &index_list ); - - hal_ll_can_alternate_functions_set_state( &hal_ll_can_hw_specifics_map[ pin_check_result ], true ); - - handle_map[pin_check_result].init_ll_state = false; - } - - *hal_module_id = pin_check_result; - - hal_ll_module_state[pin_check_result].hal_ll_can_handle = (handle_t *)&hal_ll_can_hw_specifics_map[pin_check_result].base; - - handle_map[pin_check_result].hal_ll_can_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_can_handle; - - return HAL_LL_CAN_SUCCESS; -} - -hal_ll_err_t hal_ll_can_init( handle_t *handle, hal_ll_can_config_t *config, - hal_ll_can_filter_config_t *filter_config ) { - hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_can_get_module_state_address); - hal_ll_can_handle_register_t *hal_handle = (hal_ll_can_handle_register_t *)*handle; - uint8_t pin_check_result = hal_ll_can_hw_specifics_map_local->module_index; - - hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_local, config, filter_config ); - - hal_ll_module_state[pin_check_result].hal_ll_can_handle = (handle_t *)&hal_ll_can_hw_specifics_map[pin_check_result].base; - hal_ll_module_state[pin_check_result].init_ll_state = true; - hal_handle->init_ll_state = true; - - return HAL_LL_CAN_SUCCESS; -} - -hal_ll_err_t hal_ll_can_set_filter( handle_t *handle, hal_ll_can_config_t *config, - hal_ll_can_filter_config_t *filter_config ) { - low_level_handle = hal_ll_can_get_handle; - hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); - - low_level_handle->init_ll_state = false; - hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_local, config, filter_config ); - - low_level_handle->init_ll_state = true; - - return HAL_LL_CAN_SUCCESS; -} - -hal_ll_err_t hal_ll_can_set_frequency( handle_t *handle, hal_ll_can_config_t *config, - hal_ll_can_filter_config_t *filter_config ) { - low_level_handle = hal_ll_can_get_handle; - hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); - uint32_t original_frequency; - hal_ll_err_t result; - - low_level_handle->init_ll_state = false; - - original_frequency = hal_ll_can_hw_specifics_map_local->frequency; - - hal_ll_can_hw_specifics_map_local->frequency = config->frequency; - result = hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_local, config, filter_config ); - - // In case the desired frequency setting hasn't been achieved, there's no need to update the map. - if( HAL_LL_CAN_SUCCESS != result ) - hal_ll_can_hw_specifics_map_local->frequency = original_frequency; - - low_level_handle->init_ll_state = true; - - return result; -} - -hal_ll_err_t hal_ll_can_get_frequency( handle_t *handle ) { - hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); - - return hal_ll_can_hw_specifics_map_local->frequency; -} - -hal_ll_err_t hal_ll_can_set_mode( handle_t *handle, hal_ll_can_config_t *config, - hal_ll_can_filter_config_t *filter_config ) { - low_level_handle = hal_ll_can_get_handle; - hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); - hal_ll_err_t result; - - low_level_handle->init_ll_state = false; - - // NOTE: Changing mode won't result in an error, so saving the previous value is not needed. - hal_ll_can_hw_specifics_map_local->mode = config->mode; - result = hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_local, config, filter_config ); - - low_level_handle->init_ll_state = true; - - return result; -} - -hal_ll_err_t hal_ll_can_get_mode( handle_t *handle ) { - hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); - - return hal_ll_can_hw_specifics_map_local->mode; -} - -hal_ll_err_t hal_ll_can_transmit( handle_t *handle, hal_ll_can_transmit_message_struct *transmit_message ) { - hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_can_get_module_state_address); - hal_ll_can_base_handle_t *hal_ll_hw_reg = ( hal_ll_can_base_handle_t *)hal_ll_can_hw_specifics_map_local->base; - uint32_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; - - // Configure transmit message object - message_config( (hal_ll_base_addr_t *)hal_ll_can_hw_specifics_map_local->base, - HAL_LL_CAN_TRANSMIT_MESSAGE_ID, transmit_message->message.std_id ); - - // Wait for BUSY bit to clear. - while( check_reg_bit( &hal_ll_hw_reg->can_if1.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) - if( !timeout-- ) - return HAL_LL_CAN_ERROR; - - hal_ll_hw_reg->can_if2.cmsk = HAL_LL_CAN_IF_CMSK_CONTROL_MASK | HAL_LL_CAN_IF_CMSK_MASK_MASK | HAL_LL_CAN_IF_CMSK_ARB_MASK | - HAL_LL_CAN_IF_CMSK_DATAA_MASK | HAL_LL_CAN_IF_CMSK_DATAB_MASK; - - hal_ll_hw_reg->can_if2.crq = HAL_LL_CAN_TRANSMIT_MESSAGE_ID; - - timeout = HAL_LL_CAN_TIMEOUT_VALUE; - - // Wait for BUSY bit to clear. - while( check_reg_bit( &hal_ll_hw_reg->can_if2.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) - if( !timeout-- ) - return HAL_LL_CAN_ERROR; - - hal_ll_hw_reg->can_if1.da1 = (uint32_t)transmit_message->message.message_data[0]; - hal_ll_hw_reg->can_if1.da1 |= (uint32_t)transmit_message->message.message_data[1] << HAL_LL_CAN_IF_DATA_SHIFT; - hal_ll_hw_reg->can_if1.da2 = (uint32_t)transmit_message->message.message_data[2]; - hal_ll_hw_reg->can_if1.da2 |= (uint32_t)transmit_message->message.message_data[3] << HAL_LL_CAN_IF_DATA_SHIFT; - hal_ll_hw_reg->can_if1.db1 = (uint32_t)transmit_message->message.message_data[4]; - hal_ll_hw_reg->can_if1.db1 |= (uint32_t)transmit_message->message.message_data[5] << HAL_LL_CAN_IF_DATA_SHIFT; - hal_ll_hw_reg->can_if1.db2 = (uint32_t)transmit_message->message.message_data[6]; - hal_ll_hw_reg->can_if1.db2 |= (uint32_t)transmit_message->message.message_data[7] << HAL_LL_CAN_IF_DATA_SHIFT; - - hal_ll_hw_reg->can_if1.cmsk = HAL_LL_CAN_IF_CMSK_WRNRD_MASK | HAL_LL_CAN_IF_CMSK_DATAA_MASK | HAL_LL_CAN_IF_CMSK_DATAB_MASK | - HAL_LL_CAN_IF_CMSK_CONTROL_MASK | HAL_LL_CAN_IF_CMSK_ARB_MASK; - - hal_ll_hw_reg->can_if1.arb2 |= (( transmit_message->message.std_id << HAL_LL_CAN_IF_ARB2_ID_SHIFT ) & HAL_LL_CAN_IF_ARB2_ID_MASK ) | - HAL_LL_CAN_IF_ARB2_MSGVAL_MASK | HAL_LL_CAN_IF_ARB2_DIR_MASK; - hal_ll_hw_reg->can_if1.mctl |= ( transmit_message->message.data_len & HAL_LL_CAN_IF_MCTL_DLC_MASK ) | - HAL_LL_CAN_IF_MCTL_TXRQST_MASK; - - hal_ll_hw_reg->can_if1.crq = HAL_LL_CAN_TRANSMIT_MESSAGE_ID; - set_reg_bit( &hal_ll_hw_reg->can_if2.cmsk, HAL_LL_CAN_IF_CMSK_TXRQST_BIT ); - - return HAL_LL_CAN_SUCCESS; -} - -void hal_ll_can_transmission_stop( handle_t *handle ) { - hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_can_get_module_state_address); - hal_ll_can_base_handle_t *hal_ll_hw_reg = ( hal_ll_can_base_handle_t *)hal_ll_can_hw_specifics_map_local->base; - - // Putting CAN module in initialization mode stops all bus activities. - set_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_INIT_BIT ); -} - -hal_ll_err_t hal_ll_can_receive( handle_t *handle, hal_ll_can_receive_message_struct *receive_message ) { - hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_can_get_module_state_address); - hal_ll_can_base_handle_t *hal_ll_hw_reg = ( hal_ll_can_base_handle_t *)hal_ll_can_hw_specifics_map_local->base; - uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; - - hal_ll_hw_reg->can_if2.cmsk = HAL_LL_CAN_IF_CMSK_DATAA_MASK | HAL_LL_CAN_IF_CMSK_DATAB_MASK | HAL_LL_CAN_IF_CMSK_CONTROL_MASK | - HAL_LL_CAN_IF_CMSK_MASK_MASK | HAL_LL_CAN_IF_CMSK_ARB_MASK; - - // Configure ARB2 register. - clear_reg_bit( &hal_ll_hw_reg->can_if2.arb2, HAL_LL_CAN_IF_ARB2_XTD_BIT ); - clear_reg_bit( &hal_ll_hw_reg->can_if2.arb2, HAL_LL_CAN_IF_ARB2_DIR_BIT ); - set_reg_bit( &hal_ll_hw_reg->can_if2.arb2, HAL_LL_CAN_IF_ARB2_MSGVAL_BIT ); - - // Configure MCTL register. - set_reg_bit( &hal_ll_hw_reg->can_if2.mctl, HAL_LL_CAN_IF_MCTL_UMASK_BIT ); - clear_reg_bit( &hal_ll_hw_reg->can_if2.mctl, HAL_LL_CAN_IF_MCTL_RMTEN_BIT ); - set_reg_bit( &hal_ll_hw_reg->can_if2.mctl, HAL_LL_CAN_IF_MCTL_EOB_BIT ); - - hal_ll_hw_reg->can_if2.crq = receive_message->rx_fifo_number; - - // Wait for BUSY bit to clear. - while( check_reg_bit( &hal_ll_hw_reg->can_if2.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) - if( !timeout-- ) - return HAL_LL_CAN_ERROR; - - receive_message->message.std_id = ( hal_ll_hw_reg->can_if1.arb2 & HAL_LL_CAN_IF_ARB2_ID_MASK ) >> HAL_LL_CAN_IF_ARB2_ID_SHIFT; - - // Check for new data. - if( check_reg_bit( &hal_ll_hw_reg->can_if2.mctl, HAL_LL_CAN_IF_MCTL_NEWDAT_BIT )) { - receive_message->message.data_len = hal_ll_hw_reg->can_if2.mctl & HAL_LL_CAN_IF_MCTL_DLC_MASK; - receive_message->message.message_data[0] = hal_ll_hw_reg->can_if2.da1; - receive_message->message.message_data[1] = hal_ll_hw_reg->can_if2.da1 >> HAL_LL_CAN_IF_DATA_SHIFT; - receive_message->message.message_data[2] = hal_ll_hw_reg->can_if2.da2; - receive_message->message.message_data[3] = hal_ll_hw_reg->can_if2.da2 >> HAL_LL_CAN_IF_DATA_SHIFT; - receive_message->message.message_data[4] = hal_ll_hw_reg->can_if2.db1; - receive_message->message.message_data[5] = hal_ll_hw_reg->can_if2.db1 >> HAL_LL_CAN_IF_DATA_SHIFT; - receive_message->message.message_data[6] = hal_ll_hw_reg->can_if2.db2; - receive_message->message.message_data[7] = hal_ll_hw_reg->can_if2.db2 >> HAL_LL_CAN_IF_DATA_SHIFT; - } - - // Clear NEWDAT. - clear_reg_bit( &hal_ll_hw_reg->can_if2.mctl, HAL_LL_CAN_IF_MCTL_NEWDAT_BIT ); - set_reg_bit( &hal_ll_hw_reg->can_if2.cmsk, HAL_LL_CAN_IF_CMSK_NEWDAT_BIT ); - - hal_ll_hw_reg->can_if2.crq = receive_message->rx_fifo_number; - - timeout = HAL_LL_CAN_TIMEOUT_VALUE; - - // Wait for BUSY bit to clear. - while( check_reg_bit( &hal_ll_hw_reg->can_if2.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) - if( !timeout-- ) - return HAL_LL_CAN_ERROR; - - return HAL_LL_CAN_SUCCESS; -} - -hal_ll_err_t hal_ll_can_close( handle_t *handle ) { - low_level_handle = hal_ll_can_get_handle; - hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_can_get_module_state_address); - - if( low_level_handle->hal_ll_can_handle != NULL ) { - hal_ll_can_clock_enable(hal_ll_can_hw_specifics_map_local->module_index, true); - hal_ll_can_alternate_functions_set_state( hal_ll_can_hw_specifics_map_local, false ); - - hal_ll_can_clock_enable(hal_ll_can_hw_specifics_map_local->module_index, false); - - hal_ll_can_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; - hal_ll_can_hw_specifics_map_local->pins.tx_pin.pin_af = 0; - hal_ll_can_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; - hal_ll_can_hw_specifics_map_local->pins.rx_pin.pin_af = 0; - - hal_ll_can_hw_specifics_map_local->frequency = 500000UL; - - low_level_handle->hal_ll_can_handle = NULL; - low_level_handle->hal_drv_can_handle = NULL; - - low_level_handle->init_ll_state = false; - - return HAL_LL_CAN_SUCCESS; - } else - return HAL_LL_CAN_ERROR; -} - -// ---------------------------------------------- PRIVATE FUNCTION DEFINITIONS - -static hal_ll_pin_name_t hal_ll_can_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, - hal_ll_can_pin_id *index_list, hal_ll_can_handle_register_t *handle_map ) { - static const uint16_t tx_map_size = ( sizeof( hal_ll_can_tx_map ) / sizeof( hal_ll_can_pin_map_t ) ); - static const uint16_t rx_map_size = ( sizeof( hal_ll_can_rx_map ) / sizeof( hal_ll_can_pin_map_t ) ); - uint8_t hal_ll_module_id = 0; - uint8_t index_counter = 0; - uint16_t tx_index; - uint16_t rx_index; - - if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { - return HAL_LL_PIN_NC; - } - - for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) - { - if ( hal_ll_can_tx_map[ tx_index ].pin == tx_pin ) - { - for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) - { - if ( hal_ll_can_rx_map[ rx_index ].pin == rx_pin ) - { - if ( hal_ll_can_tx_map[ tx_index ].base == hal_ll_can_rx_map[ rx_index ].base ) { - // Get module number - hal_ll_module_id = hal_ll_can_tx_map[ tx_index ].module_index; - - // Map pin names - index_list[hal_ll_module_id].pin_tx = tx_index; - index_list[hal_ll_module_id].pin_rx = rx_index; - - // Check if module is taken - if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_can_handle ) { - return hal_ll_module_id; - } else if ( CAN_MODULE_COUNT == ++index_counter ) { - return --index_counter; - } - } - } - } - } - } - - if ( index_counter ) { - return hal_ll_module_id; - } else { - return HAL_LL_PIN_NC; - } -} - -static void hal_ll_can_alternate_functions_set_state( hal_ll_can_hw_specifics_map_t *map, bool hal_ll_state ) { - module_struct module; - - if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { - module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); - module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); - module.pins[2] = GPIO_MODULE_STRUCT_END; - - module.configs[0] = GPIO_CFG_ALT_FUNCTION | GPIO_CFG_DIGITAL_OUTPUT; - module.configs[1] = GPIO_CFG_ALT_FUNCTION | GPIO_CFG_DIGITAL_INPUT; - module.configs[2] = GPIO_MODULE_STRUCT_END; - - hal_ll_gpio_module_struct_init( &module, hal_ll_state ); - } -} - -static void hal_ll_can_map_pins( uint8_t module_index, hal_ll_can_pin_id *index_list ) { - // Map new pins - hal_ll_can_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_can_tx_map[ index_list[module_index].pin_tx ].pin; - hal_ll_can_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_can_rx_map[ index_list[module_index].pin_rx ].pin; - // TX and RX could have different alternate function settings, hence save both AF values - hal_ll_can_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_can_tx_map[ index_list[module_index].pin_tx ].af; - hal_ll_can_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_can_rx_map[ index_list[module_index].pin_rx ].af; -} - -static hal_ll_can_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { - uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_can_handle_register_t)); - static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_can_handle_register_t)); - - while( hal_ll_module_count-- ) { - if (hal_ll_can_get_base_from_hal_handle == hal_ll_can_hw_specifics_map[hal_ll_module_count].base) { - return &hal_ll_can_hw_specifics_map[hal_ll_module_count]; - } - } - - return &hal_ll_can_hw_specifics_map[hal_ll_module_error]; -} - -static void hal_ll_can_clock_enable( uint8_t module_index, bool clock_enable ) { - - switch( module_index ) { - #ifdef CAN_MODULE_0 - case ( hal_ll_can_module_num( CAN_MODULE_0 ) ): - if( true == clock_enable ) - set_reg_bit( _SYSCTL_RCGCCAN, HAL_LL_CAN1_CLOCK_ENABLE ); - else - clear_reg_bit( _SYSCTL_RCGCCAN, HAL_LL_CAN1_CLOCK_ENABLE ); - break; - #endif - #ifdef CAN_MODULE_1 - case ( hal_ll_can_module_num( CAN_MODULE_1 ) ): - if( true == clock_enable ) - set_reg_bit( _SYSCTL_RCGCCAN, HAL_LL_CAN2_CLOCK_ENABLE ); - else - clear_reg_bit( _SYSCTL_RCGCCAN, HAL_LL_CAN2_CLOCK_ENABLE ); - break; - #endif - - default: - break; - } -} - -static hal_ll_err_t hal_ll_can_bit_timing( hal_ll_can_hw_specifics_map_t *map ) { - hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct(map->base); - uint16_t prescaler = 0, tseg1 = 0, tseg2 = 0, temp = 0; - float time_quanta = 0.0, bit_time = 0.0, num_of_tq = 0.0; - uint32_t baud_rate = 0, can_clock = 0; - uint8_t sjw = 0; - - baud_rate = map->frequency; - - can_clock = Get_Fosc_kHz() * 1000; // CAN clock in Hz - - /* - * Description: This code snippet calculates the optimal settings for configuring - * the CAN bus baud rate on Tiva microcontrollers, based on the provided parameters. - * - * Initial parameters: - * - can_clock: CAN source clock frequency in Hz. - * - baud_rate: Desired CAN bus baud rate. - * - * Calculated parameters: - * - prescaler: The prescaler value to achieve the desired baud rate. - * - tseg1, tseg2: Time segment values for configuring the CAN bus. - * - * Formulas used: - * - time_quanta = 1 / can_clock - * - bit_time = 1 / baud_rate - * - num_of_tq = bit_time / time_quanta (number of time quanta) - * - (sjw + tseg1) / (sjw + tseg1 + tseg2) = 87.5% (optimal sampling for CAN) - * - baud_rate = can_clock / (prescaler * (tseg1 + tseg2 + 1)) (from Tiva Reference manuals) - * - * Note: sjw (synchronization jump width) is fixed to 1, the preferred value, but can range from 1 to 4. - */ - - sjw = HAL_LL_CAN_SJW_CONST_VALUE; - - bit_time = (float) 1 / baud_rate; - - set_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_CCE_BIT ); - for( prescaler = 1; prescaler <= HAL_LL_CAN_PRESCALER_MAX_VAL; prescaler++ ) { - time_quanta = (float) prescaler / can_clock; - num_of_tq = (float)bit_time / (float)time_quanta; - tseg1 = HAL_LL_CAN_BIT_RATE_SAMPLE_POINT * num_of_tq - sjw; - tseg2 = num_of_tq - tseg1 - sjw; - - // Time segment 1 can be anywhere between 1 and 16, while the value of time segment 2 goes from 1 to 8. - if( ( HAL_LL_CAN_TSEG1_MAX_VAL < tseg1 ) || ( HAL_LL_CAN_TSEG2_MAX_VAL < tseg2 ) || !tseg1 || !tseg2 ) continue; - - temp = prescaler * ( tseg1 + tseg2 + 1 ); - uint32_t actual_baud_rate = can_clock / temp; - - if( actual_baud_rate == baud_rate ) { - // Exact match found - uint32_t sjw_val = ((uint32_t)(sjw - 1)) << HAL_LL_CAN_CANBIT_SJW_SHIFT; - uint32_t tseg1_val = ((uint32_t)(tseg1 - 1)) << HAL_LL_CAN_CANBIT_TSEG1_SHIFT; - uint32_t tseg2_val = ((uint32_t)(tseg2 - 1)) << HAL_LL_CAN_CANBIT_TSEG2_SHIFT; - uint32_t prescaler_val_low = HAL_LL_CAN_PRESCALER_BITS_5_0 & (prescaler - 1); - uint32_t prescaler_val_high = (HAL_LL_CAN_PRESCALER_BITS_10_6 & (prescaler - 1)) >> HAL_LL_CAN_CANBRPE_PRESCALER_SHIFT; - hal_ll_hw_reg->canbit = sjw_val | tseg1_val | tseg2_val | prescaler_val_low; - hal_ll_hw_reg->canbrpe = prescaler_val_high; - clear_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_CCE_BIT ); - - return HAL_LL_CAN_SUCCESS; - } - - /* - * Note: Setting parameters that result in a baud rate that differs from the desired value is not acceptable. - * If two devices communicate over CAN, their baud rates need to be exactly the same. - */ - } - - // If this point was reached, baud rate wasn't set to the desired value and error is returned. - clear_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_CCE_BIT ); - - return HAL_LL_CAN_ERROR; -} - -static hal_ll_err_t hal_ll_can_module_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config ) { - hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct(map->base); - uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; - - // Start SW initialization. - set_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_INIT_BIT ); - - // Wait for BUSY bit to clear. - while( check_reg_bit( &hal_ll_hw_reg->can_if1.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) - if( !timeout-- ) - return HAL_LL_CAN_ERROR; - - hal_ll_hw_reg->can_if1.cmsk = HAL_LL_CAN_IF_CMSK_WRNRD_MASK | HAL_LL_CAN_IF_CMSK_ARB_MASK | HAL_LL_CAN_IF_CMSK_CONTROL_MASK; - - hal_ll_hw_reg->can_if1.arb1 = HAL_LL_CAN_REG_CLEAR; - hal_ll_hw_reg->can_if1.arb2 = HAL_LL_CAN_REG_CLEAR; - hal_ll_hw_reg->can_if1.mctl = HAL_LL_CAN_REG_CLEAR; - - timeout = HAL_LL_CAN_TIMEOUT_VALUE; - - // Loop through to program all 32 message objects. - for( uint8_t i = 1; i <= HAL_LL_CAN_MAX_MNUM; i++ ) { - hal_ll_hw_reg->can_if1.crq = i; - // Wait for BUSY bit to clear. - while( check_reg_bit( &hal_ll_hw_reg->can_if1.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) - if( !timeout-- ) - return HAL_LL_CAN_ERROR; - } - - hal_ll_hw_reg->can_if1.cmsk = HAL_LL_CAN_IF_CMSK_CLRINTPND_MASK | HAL_LL_CAN_IF_CMSK_NEWDAT_MASK; - - timeout = HAL_LL_CAN_TIMEOUT_VALUE; - - // Loop through to program all 32 message objects. - for( uint8_t i = 1; i < HAL_LL_CAN_MAX_MNUM; i++ ) { - hal_ll_hw_reg->can_if1.crq = i; - // Wait for BUSY bit to clear. - while( check_reg_bit( &hal_ll_hw_reg->can_if1.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) - if( !timeout-- ) - return HAL_LL_CAN_ERROR; - } - - // Read CANSTS register to clear message interrupts. - (void)hal_ll_hw_reg->cansts; - - if( HAL_LL_CAN_ERROR == hal_ll_can_bit_timing( map )) - return HAL_LL_CAN_ERROR; - - // Disable auto retransmission. - set_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_DAR_BIT ); - - // Start SW initialization. - set_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_INIT_BIT ); - - return HAL_LL_CAN_SUCCESS; -} - -static hal_ll_err_t hal_ll_can_filter_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_filter_config_t *filter_config ) { - hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct(map->base); - uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; - - // Mask configuration. - hal_ll_hw_reg->can_if2.cmsk |= HAL_LL_CAN_IF_CMSK_ARB_MASK | HAL_LL_CAN_IF_CMSK_CONTROL_MASK | - HAL_LL_CAN_IF_CMSK_MASK_MASK | HAL_LL_CAN_IF_CMSK_DATAA_MASK | HAL_LL_CAN_IF_CMSK_DATAB_MASK; - - hal_ll_hw_reg->can_if2.crq = filter_config->can_filter_fifo; - - // Wait for BUSY bit to clear. - while( check_reg_bit( &hal_ll_hw_reg->can_if2.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) - if( !timeout-- ) - return HAL_LL_CAN_ERROR; - - hal_ll_hw_reg->can_if1.cmsk |= HAL_LL_CAN_IF_CMSK_WRNRD_MASK | HAL_LL_CAN_IF_CMSK_CONTROL_MASK | HAL_LL_CAN_IF_CMSK_MASK_MASK; - - hal_ll_hw_reg->can_if1.msk1 = HAL_LL_CAN_REG_CLEAR; - - if ( filter_config->can_filter_id & HAL_LL_CAN_EID_BITS_28_11 ) { - // Extended filter mask ID - hal_ll_hw_reg->can_if1.msk1 = filter_config->can_filter_mask_id_low; - hal_ll_hw_reg->can_if1.msk2 = filter_config->can_filter_mask_id_high; - } else { - // Standard filter mask ID - hal_ll_hw_reg->can_if1.msk2 = ( filter_config->can_filter_mask_id_low & HAL_LL_CAN_SID_MASK ) << HAL_LL_CAN_IF_MSK2_ID_SHIFT; - } - - // Use acceptance mask - set_reg_bit( &hal_ll_hw_reg->can_if1.mctl, HAL_LL_CAN_IF_MCTL_UMASK_BIT ); - // End of mask configuration. - - // Filter configuration. - hal_ll_hw_reg->can_if2.cmsk |= HAL_LL_CAN_IF_CMSK_MASK_MASK | HAL_LL_CAN_IF_CMSK_CONTROL_MASK | - HAL_LL_CAN_IF_CMSK_ARB_MASK | HAL_LL_CAN_IF_CMSK_DATAA_MASK | - HAL_LL_CAN_IF_CMSK_DATAB_MASK; - - hal_ll_hw_reg->can_if2.crq = filter_config->can_filter_fifo; - - timeout = HAL_LL_CAN_TIMEOUT_VALUE; - - // Wait for BUSY bit to clear. - while( check_reg_bit( &hal_ll_hw_reg->can_if2.crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) - if( !timeout-- ) - return HAL_LL_CAN_ERROR; - - hal_ll_hw_reg->can_if1.cmsk = HAL_LL_CAN_IF_CMSK_WRNRD_MASK | HAL_LL_CAN_IF_CMSK_ARB_MASK; - - if ( filter_config->can_filter_id & HAL_LL_CAN_EID_BITS_28_11 ) { - // Extended filter ID - hal_ll_hw_reg->can_if1.arb1 |= filter_config->can_filter_id_low; - hal_ll_hw_reg->can_if1.arb2 |= filter_config->can_filter_id_high; - } else { - // Standard filter ID - hal_ll_hw_reg->can_if1.arb2 |= ( filter_config->can_filter_id_low & HAL_LL_CAN_SID_MASK ) << HAL_LL_CAN_IF_ARB2_ID_SHIFT; - } - - set_reg_bit( &hal_ll_hw_reg->can_if1.arb2, HAL_LL_CAN_IF_ARB2_MSGVAL_BIT ); - - hal_ll_hw_reg->can_if1.crq = filter_config->can_filter_fifo; - // End of filter configuration. - - return HAL_LL_CAN_SUCCESS; -} - -static hal_ll_err_t message_config( hal_ll_base_addr_t *base, uint8_t message_object_num, uint32_t identifier ) { - hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct(base); - volatile hal_ll_can_if *can_interface; - uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; - - // One interface is used to transmit and the other to receive data. - if ( HAL_LL_CAN_TRANSMIT_MESSAGE_ID == message_object_num ) { - can_interface = &hal_ll_hw_reg->can_if1; - } else { - can_interface = &hal_ll_hw_reg->can_if2; - } - - // Wait for BUSY bit to clear. - while( check_reg_bit( &can_interface->crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) - if( !timeout-- ) - return HAL_LL_CAN_ERROR; - - can_interface->cmsk |= HAL_LL_CAN_IF_CMSK_WRNRD_MASK | HAL_LL_CAN_IF_CMSK_CONTROL_MASK | HAL_LL_CAN_IF_CMSK_ARB_MASK; - - can_interface->crq = message_object_num; - - timeout = HAL_LL_CAN_TIMEOUT_VALUE; - - // Wait for BUSY bit to clear. - while( check_reg_bit( &can_interface->crq, HAL_LL_CAN_IF_CRQ_BUSY_BIT )) - if( !timeout-- ) - return HAL_LL_CAN_ERROR; - - if( HAL_LL_CAN_EID_BITS_28_11 & identifier ) - // Extended ID - set_reg_bit( &can_interface->arb2, HAL_LL_CAN_IF_ARB2_XTD_BIT ); - else - // Standard ID - clear_reg_bit( &can_interface->arb2, HAL_LL_CAN_IF_ARB2_XTD_BIT ); - - set_reg_bit( &can_interface->arb2, HAL_LL_CAN_IF_ARB2_MSGVAL_BIT ); - - if( HAL_LL_CAN_TRANSMIT_MESSAGE_ID == message_object_num ) { - // Transmit message object - set_reg_bit( &can_interface->arb2, HAL_LL_CAN_IF_ARB2_DIR_BIT ); // Set direction to Transmit - } else { - // Receive message object - clear_reg_bit( &can_interface->arb2, HAL_LL_CAN_IF_ARB2_DIR_BIT ); // Set direction to Receive - } - - can_interface->crq = message_object_num; - - return HAL_LL_CAN_SUCCESS; -} - -static hal_ll_err_t hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config, - hal_ll_can_filter_config_t *filter_config ) { - hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct(map->base); - hal_ll_err_t result = HAL_LL_CAN_SUCCESS; - - // Enable clock for CAN. - hal_ll_can_clock_enable( map->module_index, true ); - /* - * According to the Datasheet: - * "There must be a delay of 3 system clocks after the CAN module clock is enabled before - * any CAN module registers are accessed." - */ - assembly( nop ); - assembly( nop ); - assembly( nop ); - - if( HAL_LL_CAN_ERROR == hal_ll_can_module_init( map, config )) - return HAL_LL_CAN_ERROR; - - // Configure receive message object - if( HAL_LL_CAN_ERROR == message_config( (hal_ll_base_addr_t *)map->base, filter_config->can_filter_fifo, filter_config->can_filter_id )) - return HAL_LL_CAN_ERROR; - - if( HAL_LL_CAN_ERROR == hal_ll_can_filter_init( map, filter_config )) - return HAL_LL_CAN_ERROR; - - if( HAL_LL_CAN_MODE_LOOPBACK == config->mode ) { - set_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_TEST_BIT ); - set_reg_bit( &hal_ll_hw_reg->cantst, HAL_LL_CAN_CANTST_LBACK_BIT ); - } - - // Leave SW initialization. - clear_reg_bit( &hal_ll_hw_reg->canctl, HAL_LL_CAN_CANCTL_INIT_BIT ); - - return result; -} -// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/dma/CMakeLists.txt b/targets/arm/mikroe/renesas/src/dma/CMakeLists.txt deleted file mode 100644 index 204996e47f..0000000000 --- a/targets/arm/mikroe/renesas/src/dma/CMakeLists.txt +++ /dev/null @@ -1,56 +0,0 @@ -## ./targets/arm/mikroe/tiva/src/dma/CMakeLists.txt -set(hal_ll_def_list "") -set(mcu_header_path ${MCU_NAME}) - -find_cortex(hal_ll_def_list) - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -## BEGIN DMA -if (${CORE_NAME} EQUAL "M4EF") - list(APPEND hal_ll_def_list "__cortex_m4_fpu__") -else() - list(APPEND hal_ll_def_list "__cortex_not_supported__") -endif() -## END DMA -list(APPEND hal_ll_def_list "MACRO_USAGE_DMA") - -mikrosdk_add_library(lib_hal_ll_dma MikroSDK.HalLowLevel.DMA - - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h - # BEGIN DMA - ../../include/dma/hal_ll_dma.h - implementation_1/hal_ll_dma.c - # END DMA -) - -target_compile_definitions(lib_hal_ll_dma PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_dma PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) - -target_include_directories(lib_hal_ll_dma - PRIVATE - ../../include - # BEGIN DMA - ../../include/dma - # END DMA - - INTERFACE - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.DMA) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.DMA ../../include/dma/hal_ll_dma.h) diff --git a/targets/arm/mikroe/renesas/src/dma/implementation_1/hal_ll_dma.c b/targets/arm/mikroe/renesas/src/dma/implementation_1/hal_ll_dma.c deleted file mode 100644 index e839651832..0000000000 --- a/targets/arm/mikroe/renesas/src/dma/implementation_1/hal_ll_dma.c +++ /dev/null @@ -1,759 +0,0 @@ -/**************************************************************************** -** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. -** Contact: https://www.mikroe.com/contact -** -** This file is part of the mikroSDK package -** -** Commercial License Usage -** -** Licensees holding valid commercial NECTO compilers AI licenses may use this -** file in accordance with the commercial license agreement provided with the -** Software or, alternatively, in accordance with the terms contained in -** a written agreement between you and The MikroElektronika Company. -** For licensing terms and conditions see -** https://www.mikroe.com/legal/software-license-agreement. -** For further information use the contact form at -** https://www.mikroe.com/contact. -** -** -** GNU Lesser General Public License Usage -** -** Alternatively, this file may be used for -** non-commercial projects under the terms of the GNU Lesser -** General Public License version 3 as published by the Free Software -** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. -** -** The above copyright notice and this permission notice shall be -** included in all copies or substantial portions of the Software. -** -** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT -** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE -** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -** -****************************************************************************/ -/*! - * @file hal_ll_dma.c - * @brief DMA HAL LOW LEVEL layer implementation. - */ - -#include "hal_ll_rcc.h" -#include "hal_ll_dma.h" - -// ------------------------------------------------------------- PRIVATE MACROS - -/*!< @brief To ensure that the whole DMA channel control structure can fit into buffer after 1024 byte aligned address, the buffer must to be expanded by 1023 bytes. */ -#define HAL_LL_DMA_BASE_ADDR (0x400FF000UL) -#define HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK (0x3FFUL) - -// RCGCDMA register definitions. -#define HAL_LL_DMA_SYSCTL_RCGCDMA (*((volatile uint32_t *)0x400FE60C)) -#define HAL_LL_DMA_SYSCTL_RCGCDMA_CLOCK_DMA (0x1UL) - -// PRDMA register definitions. -#define HAL_LL_DMA_SYSCTL_PRDMA (*((volatile uint32_t *)0x400FEA0C)) -#define HAL_LL_DMA_SYSCTL_PRDMA_DMA_READY (0x1UL) - -// FLASHDMAPP register definitions. -#define HAL_LL_DMA_FLASHPP (*((volatile uint32_t *)0x400FDFC0)) -#define HAL_LL_DMA_FLASHPP_SIZE_POSITION ((uint8_t)0) -#define HAL_LL_DMA_FLASHPP_SIZE_MASK (0xFFFFUL << HAL_LL_DMA_FLASHPP_SIZE_POSITION) -#define HAL_LL_DMA_FLASHPP_DFA_POSITION ((uint8_t)28) -#define HAL_LL_DMA_FLASHPP_DFA_MASK (0x1UL << HAL_LL_DMA_FLASHPP_DFA_POSITION) -#define HAL_LL_DMA_FLASHPP_DFA HAL_LL_DMA_FLASHPP_DFA_MASK - -// FLASHDMASZ register definitions. -#define HAL_LL_DMA_FLASHDMASZ (*((volatile uint32_t *)0x400FDFD0)) -#define HAL_LL_DMA_FLASHDMASZ_SIZE_POSITION ((uint8_t)0) -#define HAL_LL_DMA_FLASHDMASZ_SIZE_MASK (0x3FFFFUL << HAL_LL_DMA_FLASHDMASZ_SIZE_POSITION) - -// FLASHDMAST register definitions. -#define HAL_LL_DMA_FLASHDMAST (*((volatile uint32_t *)0x400FDFD4)) -#define HAL_LL_DMA_FLASHDMAST_ADDR_POSITION ((uint8_t)11) -#define HAL_LL_DMA_FLASHDMAST_ADDR_MASK (0x3FFFFUL << HAL_LL_DMA_FLASHDMAST_ADDR_POSITION) - -// DMASTAT register definitions. -#define HAL_LL_DMA_DMASTAT_MASTEN (0x1UL) -// DMACFG register definitions. -#define HAL_LL_DMA_DMACFG_MASTEN (0x1UL) -// DMASWREQ register definitions. -#define HAL_LL_DMA_SWREQ (0x1UL) -// DMAUSEBURSTCLR register definitions. -#define HAL_LL_DMA_USEBURSTCLR (0x1UL) -// DMAREQMASKCLR register definitions. -#define HAL_LL_DMA_REQMASKCLR (0x1UL) -// DMAENSET register definitions. -#define HAL_LL_DMA_ENASET (0x1UL) -// DMAENCLR register definitions. -#define HAL_LL_DMA_ENACLR (0x1UL) -// Mask used to check if the DMA stream is in use. -#define HAL_LL_DMA_STREAM_ENABLED_MASK (0xFFFFFFFFUL) -// DMAALTCLR register definitions. -#define HAL_LL_DMA_ALTCLR (0x1UL) -// DMAPRIOSET register definitions. -#define HAL_LL_DMA_PRIOSET (0x1UL) -// DMAPRIOCLR register definitions. -#define HAL_LL_DMA_PRIOCLR (0x1UL) - -// DMA Channel Control Word (DMACHTL) definitions. -#define HAL_LL_DMA_DMACHCTL_XFERMODE_MASK (0x7UL) -#define HAL_LL_DMA_DMACHCTL_XFERMODE_STOP (0x0UL) -#define HAL_LL_DMA_DMACHCTL_XFERMODE_BASIC (0x1UL) -#define HAL_LL_DMA_DMACHCTL_XFERMODE_AUTO_REQUEST (0x2UL) -#define HAL_LL_DMA_DMACHCTL_XFERMODE_PING_PONG (0x3UL) -#define HAL_LL_DMA_DMACHCTL_XFERMODE_MEM_SCATTER_GATHER (0x4UL) -#define HAL_LL_DMA_DMACHCTL_XFERMODE_ALT_MEM_SCATTER_GATHER (0x5UL) -#define HAL_LL_DMA_DMACHCTL_XFERMODE_PERIPH_SCATTER_GATHER (0x6UL) -#define HAL_LL_DMA_DMACHCTL_XFERMODE_ALT_PERIPH_SCATTER_GATHER (0x7UL) -#define HAL_LL_DMA_DMACHTL_NXTUSEBURST_POSITION ((uint8_t)3) -#define HAL_LL_DMA_DMACHTL_NXTUSEBURST_MASK (0x1UL << HAL_LL_DMA_DMACHTL_NXTUSEBURST_POSITION) -#define HAL_LL_DMA_DMACHTL_NXTUSEBURST HAL_LL_DMA_DMACHTL_NXTUSEBURST_MASK -#define HAL_LL_DMA_DMACHTL_XFERSIZE_POSITION ((uint8_t)4) -#define HAL_LL_DMA_DMACHTL_XFERSIZE_MASK (0x3FFUL << HAL_LL_DMA_DMACHTL_XFERSIZE_POSITION) -#define HAL_LL_DMA_DMACHTL_ARBSIZE_POSITION ((uint8_t)14) -#define HAL_LL_DMA_DMACHTL_ARBSIZE_MASK (0xFUL << HAL_LL_DMA_DMACHTL_ARBSIZE_POSITION) -#define HAL_LL_DMA_DMACHTL_SRCSIZE_POSITION ((uint8_t)24) -#define HAL_LL_DMA_DMACHTL_SRCSIZE_MASK (0x3UL << HAL_LL_DMA_DMACHTL_SRCSIZE_POSITION) -#define HAL_LL_DMA_DMACHTL_SRCSIZE_BYTE (0x0UL) -#define HAL_LL_DMA_DMACHTL_SRCSIZE_HALF_WORD (0x1UL << HAL_LL_DMA_DMACHTL_SRCSIZE_POSITION) -#define HAL_LL_DMA_DMACHTL_SRCSIZE_WORD (0x2UL << HAL_LL_DMA_DMACHTL_SRCSIZE_POSITION) -#define HAL_LL_DMA_DMACHTL_SRCINC_POSITION ((uint8_t)26) -#define HAL_LL_DMA_DMACHTL_SRCINC_MASK (0x3UL << HAL_LL_DMA_DMACHTL_SRCINC_POSITION) -#define HAL_LL_DMA_DMACHTL_SRCINC_BYTE (0x0UL) -#define HAL_LL_DMA_DMACHTL_SRCINC_HALF_WORD (0x1UL << HAL_LL_DMA_DMACHTL_SRCINC_POSITION) -#define HAL_LL_DMA_DMACHTL_SRCINC_WORD (0x2UL << HAL_LL_DMA_DMACHTL_SRCINC_POSITION) -#define HAL_LL_DMA_DMACHTL_SRCINC_NO_INCREMENT (0x3UL << HAL_LL_DMA_DMACHTL_SRCINC_POSITION) -#define HAL_LL_DMA_DMACHTL_DSTSIZE_POSITION ((uint8_t)28) -#define HAL_LL_DMA_DMACHTL_DSTSIZE_MASK (0x3UL << HAL_LL_DMA_DMACHTL_DSTSIZE_POSITION) -#define HAL_LL_DMA_DMACHTL_DSTSIZE_BYTE (0x0UL) -#define HAL_LL_DMA_DMACHTL_DSTSIZE_HALF_WORD (0x1UL << HAL_LL_DMA_DMACHTL_DSTSIZE_POSITION) -#define HAL_LL_DMA_DMACHTL_DSTSIZE_WORD (0x2UL << HAL_LL_DMA_DMACHTL_DSTSIZE_POSITION) -#define HAL_LL_DMA_DMACHTL_DSTINC_POSITION ((uint8_t)30) -#define HAL_LL_DMA_DMACHTL_DSTINC_MASK (0x3UL << HAL_LL_DMA_DMACHTL_DSTINC_POSITION) -#define HAL_LL_DMA_DMACHTL_DSTINC_BYTE (0x0UL) -#define HAL_LL_DMA_DMACHTL_DSTINC_HALF_WORD (0x1UL << HAL_LL_DMA_DMACHTL_DSTINC_POSITION) -#define HAL_LL_DMA_DMACHTL_DSTINC_WORD (0x2UL << HAL_LL_DMA_DMACHTL_DSTINC_POSITION) -#define HAL_LL_DMA_DMACHTL_DSTINC_NO_INCREMENT (0x3UL << HAL_LL_DMA_DMACHTL_DSTINC_POSITION) - -/*!< Read Only access. */ -#ifdef __GNUC__ - #define _HAL_LL_DMA_RO volatile const -#else - #define _HAL_LL_DMA_RO volatile -#endif -/*!< Read and Write access. */ -#define _HAL_LL_DMA_RW volatile -/*!< Write Only access. */ -#define _HAL_LL_DMA_WO volatile - -/*!< @brief Macro use to determine if the DMA has access to flash memory */ -#define HAL_LL_DMA_HAS_FLASH_ACCESS (HAL_LL_DMA_FLASHPP & HAL_LL_DMA_FLASHPP_DFA) -/*!< @brief Macro use to determine the size of the flash memory */ -#define HAL_LL_DMA_FLASH_SIZE ((HAL_LL_DMA_FLASHPP & HAL_LL_DMA_FLASHPP_SIZE_MASK) >> HAL_LL_DMA_FLASHPP_SIZE_POSITION) -/*!< @brief Macro use to validate appropriate DMA access to transfer buffers located in flash memory */ -#define HAL_LL_DMA_FLASH_ACCESS_OK HAL_LL_DMA_SUCCESS - -/*!< @brief Clock enable macro. */ -#define _HAL_LL_ENABLE_CLOCK_SYS_ (HAL_LL_DMA_SYSCTL_RCGCDMA |= HAL_LL_DMA_SYSCTL_RCGCDMA_CLOCK_DMA) -/*!< @brief Clock disable macro. */ -#define _HAL_LL_DISABLE_CLOCK_SYS_ (HAL_LL_DMA_SYSCTL_RCGCDMA &= !HAL_LL_DMA_SYSCTL_RCGCDMA_CLOCK_DMA) - -/*!< @brief DMA module enable macro. */ -#define HAL_LL_DMA_MODULE_ENABLE (dma->cfg |= HAL_LL_DMA_DMACFG_MASTEN) -/*!< @brief DMA module disable macro. */ -#define HAL_LL_DMA_MODULE_DISABLE (dma->cfg &= ~HAL_LL_DMA_DMACFG_MASTEN) -/*!< @brief DMA module usage status macro. */ -#define HAL_LL_DMA_MODULE_UNUSED (0x0UL) - -/*!< @brief DMA stream enable macro. */ -#define HAL_LL_DMA_STREAM_ENABLE(_stream) (dma->ena_set |= HAL_LL_DMA_ENASET << _stream) -/*!< @brief DMA stream disable macro. */ -#define HAL_LL_DMA_STREAM_DISABLE(_stream) (dma->ena_clr |= HAL_LL_DMA_ENASET << _stream) - -/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ -#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) - -// ----------------------------------------------------------- PRIVATE TYPEDEFS - -/*!< @brief DMA HW channel control structure. */ -typedef struct dma_ch_ctl_struct -{ - _HAL_LL_DMA_RW uint32_t src_endp; /*!< DMA channel source address end pointer. */ - _HAL_LL_DMA_RW uint32_t dst_endp; /*!< DMA channel destination address end pointer. */ - _HAL_LL_DMA_RW uint32_t ch_ctl; /*!< DMA channel control word. */ - uint32_t __unused1; -} dma_ch_ctl_struct_t; - -/*!< @brief DMA HW register structure. */ -typedef struct dma_handle -{ - _HAL_LL_DMA_RO uint32_t stat; /*!< DMA status register. */ - _HAL_LL_DMA_WO uint32_t cfg; /*!< DMA configuration register. */ - _HAL_LL_DMA_RW uint32_t ctl_base; /*!< DMA channel control base pointer. */ - _HAL_LL_DMA_RO uint32_t alt_base; /*!< DMA alternate channel control base pointer. */ - _HAL_LL_DMA_RO uint32_t wait_stat; /*!< DMA channel wait-on request status register. */ - _HAL_LL_DMA_WO uint32_t sw_req; /*!< DMA channel software request register. */ - _HAL_LL_DMA_RW uint32_t use_burst_set; /*!< DMA channel useburst set register. */ - _HAL_LL_DMA_WO uint32_t use_burst_clr; /*!< DMA channel useburst clear register. */ - _HAL_LL_DMA_RW uint32_t req_mask_set; /*!< DMA channel request mask set register. */ - _HAL_LL_DMA_WO uint32_t req_mask_clr; /*!< DMA channel request mask clear register. */ - _HAL_LL_DMA_RW uint32_t ena_set; /*!< DMA channel enable set register. */ - _HAL_LL_DMA_WO uint32_t ena_clr; /*!< DMA channel enable clear register. */ - _HAL_LL_DMA_RW uint32_t alt_set; /*!< DMA channel primary alternate set register. */ - _HAL_LL_DMA_WO uint32_t alt_clr; /*!< DMA channel primary alternate clear register */ - _HAL_LL_DMA_RW uint32_t prio_set; /*!< DMA channel priority set register */ - _HAL_LL_DMA_WO uint32_t prio_clr; /*!< DMA channel priority clear register */ - uint32_t unused1[3]; - _HAL_LL_DMA_RW uint32_t err_clr; /*!< DMA bus error clear register */ - uint32_t unused2[300]; - _HAL_LL_DMA_RW uint32_t ch_asgn; /*!< DMA channel assignment register */ - uint32_t unused3[3]; - _HAL_LL_DMA_RW uint32_t ch_map[4]; /*!< DMA channel map select registers */ -} dma_handle_t; - -// ------------------------------------------------------------------ VARIABLES - -/* Note: The channel control structure buffer is created with overhead of 1023 bytes to ensure that - * there is one address aligned/divisible with 1024 inside the buffer, and there are enough - * enough bytes needed for channel control structure (sizeof(dma_ch_ctl_struct_t) * DMA_NUM_OF_STREAMS), - * after this address. - */ - /*!< @brief DMA HW channel control structure extended buffer */ -static dma_ch_ctl_struct_t dma_ch_ctl_buffer[ ( ( ( sizeof( dma_ch_ctl_struct_t ) * DMA_NUM_OF_STREAMS ) << 1 ) - + HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ) - / sizeof( dma_ch_ctl_struct_t ) ]; -/*!< @brief Pointer to 1024 byte aligned address inside dma_ch_ctl_buffer where actual channel control data will be stored */ -static dma_ch_ctl_struct_t * dma_ch_ctl; - -// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS - -/** - * @brief Initializes DMA module. - * @details Initializes DMA module, stream and channel to - * values from @ref config structure. - * @param[in] dma_obj DMA object. - * @param[in] dma DMA HW handle. - * @param[in] config DMA configuration structure. - * @return hal_ll_err_t Returns initialization state, either success or fail. - */ -static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); - -/** - * @brief Sets DMA channel. - * @details Sets appropriate value HW register for the desired @ref channel. - * @param[in] dma DMA HW handle. - * @param[in] stream DMA Stream number. - * @param[in] channel DMA Channel number. - * @return Nothing. - */ -static inline void hal_ll_dma_set_channel( dma_handle_t *dma, uint8_t stream, uint8_t channel ); - -/** - * @brief Configures DMA access to FLASH memory. - * @details If DMA has access to the flash memory, the function - * will configure the region in flash memory, - * where DMA read access is allowed, by setting the starting address and size - * starting from that address where reading is allowed. - * @return Nothing. - */ -static void hal_ll_dma_configure_flash_access(); - -/** - * @brief Gets DMA direction. - * @details Returns appropriate value to be set in HW register - * for desired @ref direction. - * @param[in] direction DMA stream direction. - * Refer to @hal_ll_dma_direction_t for possible values. - * @return uint8_t Returns actual HW register value based on @ref direction. - */ -static inline uint8_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); - -/** - * @brief Gets DMA peripheral address increment. - * @details Returns appropriate value to be set in HW register - * for desired @ref set_inc. - * @param[in] set_inc DMA stream peripheral address increment. - * Set to @b true in order to increment address. - * Set to @b false in order to keep address the same. - * @return uint16_t Returns actual HW register value based on @ref set_inc. - */ -static inline uint32_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc, hal_ll_dma_data_align_t align ); - -/** - * @brief Gets DMA memory address increment. - * @details Returns appropriate value to be set in HW register - * for desired @ref set_inc. - * @param[in] set_inc DMA stream memory address increment. - * Set to @b true in order to increment address. - * Set to @b false in order to keep address the same. - * @return uint16_t Returns actual HW register value based on @ref set_inc. - */ -static inline uint32_t hal_ll_dma_get_reg_value_src_inc( bool set_inc, hal_ll_dma_data_align_t align ); - -/** - * @brief Gets DMA memory address alignment. - * @details Returns appropriate value to be set in HW register - * for desired @ref align. - * @param[in] align DMA stream memory address increment. - * Refer to @ref hal_ll_dma_data_align_t for possible values. - * @return uint16_t Returns actual HW register value based on @ref align. - */ -static inline uint32_t hal_ll_dma_get_reg_value_src_size( hal_ll_dma_data_align_t align ); - -/** - * @brief Gets DMA peripheral address alignment. - * @details Returns appropriate value to be set in HW register - * for desired @ref align. - * @param[in] align DMA stream peripheral address increment. - * Refer to @ref hal_ll_dma_data_align_t for possible values. - * @return uint16_t Returns actual HW register value based on @ref align. - */ -static inline uint32_t hal_ll_dma_get_reg_value_dst_size( hal_ll_dma_data_align_t align ); - -/** - * @brief Sets DMA stream priority value. - * @details Sets the appropriate value in HW register - * for desired @ref priority. - * @param[in] dma DMA HW handle. - * @param[in] stream DMA Stream number. - * @param[in] priority DMA priority for object stream. - * Refer to @ref hal_ll_dma_priority_t for possible values. - * @return Nothing. - */ -static inline void hal_ll_dma_set_stream_priority( dma_handle_t *dma, uint8_t stream, hal_ll_dma_priority_t priority ); - -/** - * @brief Gets DMA burst size value. - * @details Returns appropriate value to be set in HW register - * for desired @ref burst_size. - * @param[in] burst_size DMA burst size for channel. - * Refer to @ref hal_ll_dma_burst_size_t for possible values. - * @return uint32_t Returns actual HW register value based on @ref burst_size. - */ -static inline uint32_t hal_ll_dma_get_reg_value_burst_size( hal_ll_dma_burst_size_t burst_size ); - -/** - * @brief Validates DMA flash memory access. - * @details For transfer buffers stored in flash memory, - * validates that the DMA has access to flash memory. - * @param[in] addr_src DMA source buffer address. - * @param[in] addr_dst DMA destination buffer address. - * @return hal_ll_err_t Returns DMA flash memory access status - * for transfer buffers stored in flash memory. - */ -static hal_ll_dma_err_t hal_ll_dma_check_flash_access( uint32_t addr_src, uint32_t addr_dst ); - -// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS - -hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { - hal_ll_err_t status = HAL_LL_DMA_SUCCESS; - - // Enable SYSCLK. - _HAL_LL_ENABLE_CLOCK_SYS_; - - // Wait until the DMA module is ready for access. - while ( !( HAL_LL_DMA_SYSCTL_PRDMA & HAL_LL_DMA_SYSCTL_PRDMA_DMA_READY) ); - - obj->handle = HAL_LL_DMA_BASE_ADDR; - status = hal_ll_dma_init_hw( obj, - (dma_handle_t *)obj->handle, - obj->config ); - - if ( HAL_LL_DMA_SUCCESS != status ) { - obj->handle = 0; // If initialization failed, reset handle. - } - - return status; -} - -hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { - dma_handle_t * dma = (dma_handle_t *)obj->handle; - // Disable module and module clock, only if all streams are disabled and inactive. - if ( HAL_LL_DMA_MODULE_UNUSED == ( dma->ena_set & HAL_LL_DMA_STREAM_ENABLED_MASK ) ) { - HAL_LL_DMA_MODULE_DISABLE; - _HAL_LL_DISABLE_CLOCK_SYS_; - } - - return HAL_LL_DMA_SUCCESS; -} - -hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { - hal_ll_err_t status = HAL_LL_DMA_SUCCESS; - // Get new mode. - hal_ll_dma_config_t cfg = obj->config; - cfg.mode = mode; - - // Try to set new mode. - status = hal_ll_dma_init_hw( obj, - (dma_handle_t *)obj->handle, - cfg ); - - return status; -} - -hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { - hal_ll_err_t status = HAL_LL_DMA_SUCCESS; - // Get new direction. - hal_ll_dma_config_t cfg = obj->config; - cfg.direction = direction; - - // Try to set new value. - status = hal_ll_dma_init_hw( obj, - (dma_handle_t *)obj->handle, - cfg ); - - return status; -} - -hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { - hal_ll_err_t status = HAL_LL_DMA_SUCCESS; - // Get new priority. - hal_ll_dma_config_t cfg = obj->config; - cfg.priority = priority; - - // Try to set new value. - status = hal_ll_dma_init_hw( obj, - (dma_handle_t *)obj->handle, - cfg ); - - return status; -} - -hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { - dma_handle_t *dma = ( dma_handle_t * )obj->handle; - // Set pointer to 1024 byte aligned address inside dma_ch_ctl_buffer, where actual channel control structure data will be located. - dma_ch_ctl = (dma_ch_ctl_struct_t *)( ( (uint32_t)dma_ch_ctl_buffer + HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ) & ~HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ); - uint8_t transfer_size_shift_divisor = 2; // default value for HAL_LL_DMA_DATA_ALIGN_BYTES_4 - uint8_t stream = obj->config.stream; - uint16_t endpoint_offset; - - // Memory type parameter is unused. - (void)src_mem_type; - - // Configure DMA Stream data length. - if ( HAL_LL_DMA_DATA_ALIGN_BYTES_4 != obj->config.data_align_destination ) { - transfer_size_shift_divisor = obj->config.data_align_destination; - } - - // If DMA transfer buffers are stored in flash memory, validate DMA access to the. - if (HAL_LL_DMA_FLASH_ACCESS_OK != hal_ll_dma_check_flash_access( addr_src, addr_dst ) ) { - // DMA does not have appropriate access to flash memory. - return HAL_LL_DMA_ERROR; - } else { // Proceed with the DMA channel configuration. - // Calculate the address offset of the last buffer item. - endpoint_offset = transfer_size - ( 1 << transfer_size_shift_divisor ); - // Calculate the source data buffer inclusive endpoint. - addr_src += obj->config.src_inc ? endpoint_offset : 0; - // Calculate the destination data buffer inclusive endpoint. - addr_dst += obj->config.dst_inc ? endpoint_offset : 0; - // Recalculate the transfer size. - transfer_size >>= transfer_size_shift_divisor; - --transfer_size; - - // Write calculated endpoint addresses and transfer size into channel control structure. - dma_ch_ctl[ stream ].ch_ctl |= (uint32_t)transfer_size << HAL_LL_DMA_DMACHTL_XFERSIZE_POSITION; - dma_ch_ctl[ stream ].dst_endp |= addr_dst; - dma_ch_ctl[ stream ].src_endp |= addr_src; - } - - return HAL_LL_DMA_SUCCESS; -} - -hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { - dma_handle_t *dma = (dma_handle_t *)obj->handle; - // Set pointer to 1024 byte aligned address inside dma_ch_ctl_buffer, where actual channel control structure data will be located. - dma_ch_ctl = (dma_ch_ctl_struct_t *)( ( (uint32_t)dma_ch_ctl_buffer + HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ) & ~HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ); - uint8_t stream = obj->config.stream; - - // Enable the DMA stream. - HAL_LL_DMA_STREAM_ENABLE( stream ); - // Transfer will start immediately after the channel periphery sends the request. - if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY == obj->config.direction ) { - // in case of the M2M direction start transfer using software request. - dma->sw_req = HAL_LL_DMA_SWREQ << stream; - } - - return HAL_LL_DMA_SUCCESS; -} - -hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { - dma_handle_t *dma = (dma_handle_t *)obj->handle; - uint16_t timeout = DEFAULT_TIMEOUT_VALUE; - // Set pointer to 1024 byte aligned address inside dma_ch_ctl_buffer, where actual channel control structure data will be located. - dma_ch_ctl = (dma_ch_ctl_struct_t *)( ( (uint32_t)dma_ch_ctl_buffer + HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ) & ~HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ); - - // Wait until transfer completes. - while ( dma_ch_ctl->ch_ctl & HAL_LL_DMA_DMACHCTL_XFERMODE_STOP ) { - if (0 == timeout--) { - // TODO consider forcing the stream to disable here. - return HAL_LL_DMA_ERROR; - } - } - // When transfer completes the DMA stream disables itself. - - return HAL_LL_DMA_SUCCESS; -} - -hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { - hal_ll_err_t status = HAL_LL_DMA_SUCCESS; - dma_handle_t *dma = (dma_handle_t *)obj->handle; - // Set pointer to 1024 byte aligned address inside dma_ch_ctl_buffer, where actual channel control structure data will be located. - dma_ch_ctl = (dma_ch_ctl_struct_t *)( ( (uint32_t)dma_ch_ctl_buffer + HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ) & ~HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ); - - // Disable the stream. - // Disabling the stream, just pauses it. - HAL_LL_DMA_STREAM_DISABLE( obj->config.stream ); - // Stop transfer. - dma_ch_ctl->ch_ctl &= HAL_LL_DMA_DMACHCTL_XFERMODE_STOP; - - return status; -} - -// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS - -static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { - // Set pointer to 1024 byte aligned address inside dma_ch_ctl_buffer, where actual channel control structure data will be located. - dma_ch_ctl = (dma_ch_ctl_struct_t *)( ( (uint32_t)dma_ch_ctl_buffer + HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ) & ~HAL_LL_DMA_MEMORY_ALLIGN_1024_MASK ); - uint8_t stream = config.stream; - - // Allow the DMA read access to the whole flash memory. - hal_ll_dma_configure_flash_access(); - - // Enable the DMA module. - HAL_LL_DMA_MODULE_ENABLE; - - // Disable the DMA stream first. - HAL_LL_DMA_STREAM_DISABLE( stream ); - - // Set channel control structure address. - dma->ctl_base = (uint32_t)dma_ch_ctl; - // Configure DMA to use the primary channel control structure. - dma->alt_clr = HAL_LL_DMA_ALTCLR << stream; - // Allow both single and burst requests. - dma->use_burst_clr = HAL_LL_DMA_USEBURSTCLR << stream; - // Allow channel to send requests. - dma->req_mask_clr = HAL_LL_DMA_REQMASKCLR << stream; - // Set the desired channel. - hal_ll_dma_set_channel( dma, stream, config.channel ); - // Set the desired priority. - hal_ll_dma_set_stream_priority( dma, stream, config.priority ); - - // Stream configuration. - // Clear source endpoint address. - dma_ch_ctl[ stream ].src_endp = 0; - // Clear destination endpoint address. - dma_ch_ctl[ stream ].dst_endp = 0; - // Clear the stream control word. - dma_ch_ctl[ stream ].ch_ctl = 0; - - // Set desired direction value. - dma_ch_ctl[ stream ].ch_ctl |= hal_ll_dma_get_reg_value_direction( config.direction ); - // Set desired memory increment settings. - dma_ch_ctl[ stream ].ch_ctl |= hal_ll_dma_get_reg_value_src_inc( config.src_inc, config.data_align_source ); - dma_ch_ctl[ stream ].ch_ctl |= hal_ll_dma_get_reg_value_dst_inc( config.dst_inc, config.data_align_source ); - - // Set desired data size settings. - if ( config.data_align_source != config.data_align_destination ) { - // Source and Destination Data sizes must be equal. - return HAL_LL_DMA_ERROR; - } - if ( ( HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source ) || ( HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) ) { - // Source and Destination Data sizes cannot be 3 bytes. - return HAL_LL_DMA_ERROR; - } - dma_ch_ctl[ stream ].ch_ctl |= hal_ll_dma_get_reg_value_src_size( config.data_align_source ); - dma_ch_ctl[ stream ].ch_ctl |= hal_ll_dma_get_reg_value_dst_size( config.data_align_source ); - - // Set desired burst transfer settings. - if ( config.burst_size_source != config.burst_size_destination ) { - // No multiple burst on TIVA. - return HAL_LL_DMA_ERROR; - } - // TODO On TIVA burst size can go up to 1024. Consider adding more enums to cover all of them. - dma_ch_ctl[ stream ].ch_ctl |= hal_ll_dma_get_reg_value_burst_size( config.burst_size_source ); - - // Set desired mode. - if ( HAL_LL_DMA_MODE_CIRCULAR == config.mode ) { - // TODO Implement circular mode later, during DMA peripheral synthesis. - /* NOTE: Channel control structure register do not posses the auto-reloading functionality, - * therefore they must be reloaded by software in interrupt routine. - * The DMA ISR is not used for this, instead the ISR form the peripheral that is using the DMA is used. - */ - return HAL_LL_DMA_ERROR; - } - - return HAL_LL_DMA_SUCCESS; -} - -static inline void hal_ll_dma_set_channel( dma_handle_t *dma, uint8_t stream, uint8_t channel ) { - dma->ch_map[ (uint8_t)( stream >> 3 ) ] |= (uint32_t)( channel << (uint8_t)( ( stream & 0x7 ) << 2 ) ) ; -} - -static void hal_ll_dma_configure_flash_access() { - // If DMA has access to flash memory. - if ( HAL_LL_DMA_HAS_FLASH_ACCESS ) { - // Clear the DMA flash access address, and at the same time indirectly set DMA starting access address to 0x00000000UL. - HAL_LL_DMA_FLASHDMAST &= ~HAL_LL_DMA_FLASHDMAST_ADDR_MASK; - // Clear DMA flash access size. - HAL_LL_DMA_FLASHDMASZ &= ~HAL_LL_DMA_FLASHDMASZ_SIZE_MASK; - // Set DMA access to whole flash memory. - HAL_LL_DMA_FLASHDMASZ |= ( HAL_LL_DMA_FLASH_SIZE ) << HAL_LL_DMA_FLASHDMASZ_SIZE_POSITION; - } -} - -static inline uint8_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { - volatile uint32_t direction_set = HAL_LL_DMA_DMACHCTL_XFERMODE_BASIC; - - // For M2M direction AUTO mode is used, and for all other directions, BASIC mode is used. - if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY == direction ) { - direction_set = HAL_LL_DMA_DMACHCTL_XFERMODE_AUTO_REQUEST; - } - - return direction_set; -} - -static inline uint32_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc, hal_ll_dma_data_align_t align ) { - volatile uint32_t dst_inc = HAL_LL_DMA_DMACHTL_DSTINC_NO_INCREMENT; - - if ( set_inc ) { - switch ( align ) { - case HAL_LL_DMA_DATA_ALIGN_BYTES_1: - // Source address increment. Data is 1 byte. - dst_inc = HAL_LL_DMA_DMACHTL_DSTINC_BYTE; - break; - case HAL_LL_DMA_DATA_ALIGN_BYTES_2: - // Source address increment. Data is halfword. - dst_inc = HAL_LL_DMA_DMACHTL_DSTINC_HALF_WORD; - break; - case HAL_LL_DMA_DATA_ALIGN_BYTES_4: - // Source address increment. Data is word. - dst_inc = HAL_LL_DMA_DMACHTL_DSTINC_WORD; - break; - - default: - break; - } - } - - return dst_inc; -} - -static inline uint32_t hal_ll_dma_get_reg_value_src_inc( bool set_inc, hal_ll_dma_data_align_t align ) { - volatile uint32_t src_inc = HAL_LL_DMA_DMACHTL_SRCINC_NO_INCREMENT; - - if ( set_inc ) { - switch ( align ) { - case HAL_LL_DMA_DATA_ALIGN_BYTES_1: - // Source address increment. Data is 1 byte. - src_inc = HAL_LL_DMA_DMACHTL_SRCINC_BYTE; - break; - case HAL_LL_DMA_DATA_ALIGN_BYTES_2: - // Source address increment. Data is halfword. - src_inc = HAL_LL_DMA_DMACHTL_SRCINC_HALF_WORD; - break; - case HAL_LL_DMA_DATA_ALIGN_BYTES_4: - // Source address increment. Data is word. - src_inc = HAL_LL_DMA_DMACHTL_SRCINC_WORD; - break; - - default: - break; - } - } - - return src_inc; -} - -static inline uint32_t hal_ll_dma_get_reg_value_src_size( hal_ll_dma_data_align_t align ) { - volatile uint32_t align_set; - - switch ( align ) { - case HAL_LL_DMA_DATA_ALIGN_BYTES_1: - // Data is 1 byte. - align_set = HAL_LL_DMA_DMACHTL_SRCSIZE_BYTE; - break; - case HAL_LL_DMA_DATA_ALIGN_BYTES_2: - // Data is halfword. - align_set = HAL_LL_DMA_DMACHTL_SRCSIZE_HALF_WORD; - break; - case HAL_LL_DMA_DATA_ALIGN_BYTES_4: - // Data is word. - align_set = HAL_LL_DMA_DMACHTL_SRCSIZE_WORD; - break; - - default: - break; - } - - return align_set; -} - -static inline uint32_t hal_ll_dma_get_reg_value_dst_size( hal_ll_dma_data_align_t align ) { - volatile uint32_t align_set; - - switch ( align ) { - case HAL_LL_DMA_DATA_ALIGN_BYTES_1: - // Data is 1 byte. - align_set = HAL_LL_DMA_DMACHTL_DSTSIZE_BYTE; - break; - case HAL_LL_DMA_DATA_ALIGN_BYTES_2: - // Data is halfword. - align_set = HAL_LL_DMA_DMACHTL_DSTSIZE_HALF_WORD; - break; - case HAL_LL_DMA_DATA_ALIGN_BYTES_4: - // Data is word. - align_set = HAL_LL_DMA_DMACHTL_DSTSIZE_WORD; - break; - - default: - break; - } - - return align_set; -} - -static inline void hal_ll_dma_set_stream_priority( dma_handle_t *dma, uint8_t stream, hal_ll_dma_priority_t priority ) { - switch ( priority ) { - case HAL_LL_DMA_PRIORITY_LOW: - case HAL_LL_DMA_PRIORITY_MEDIUM: - dma->prio_clr = HAL_LL_DMA_PRIOCLR << stream; - break; - case HAL_LL_DMA_PRIORITY_HIGH: - case HAL_LL_DMA_PRIORITY_VERY_HIGH: - dma->prio_set = HAL_LL_DMA_PRIOSET << stream; - break; - - default: - break; - } -} - -static inline uint32_t hal_ll_dma_get_reg_value_burst_size( hal_ll_dma_burst_size_t burst_size ) { - return ((uint32_t)burst_size << HAL_LL_DMA_DMACHTL_ARBSIZE_POSITION); -} - -static hal_ll_dma_err_t hal_ll_dma_check_flash_access( uint32_t addr_src, uint32_t addr_dst ) { - uint32_t flash_memory_end = ( ( HAL_LL_DMA_FLASH_SIZE + 1 ) << 11 ) - 1; - - // Check whether destination address is in FLASH memory. - if ( addr_dst <= flash_memory_end ) { - // DMA does not have write access to FLASH memory. - return HAL_LL_DMA_ERROR; - } - - // Check whether source address is in FLASH memory. - if ( addr_src <= flash_memory_end ) { - if ( !HAL_LL_DMA_HAS_FLASH_ACCESS ) { - // DMA does not have access to FLASH memory. - return HAL_LL_DMA_ERROR; - } - } - - return HAL_LL_DMA_SUCCESS; -} - -// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt b/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt index bbc85c96a3..03e3b173e0 100644 --- a/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt @@ -25,7 +25,6 @@ mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO hal_ll_gpio.c ${gpio_subimplementation} # END GPIO - ../../include/hal_ll_rcc.h ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h # BEGIN GPIO diff --git a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c index 561bc92c7d..a3728cbe9a 100644 --- a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c @@ -42,7 +42,6 @@ */ #include "hal_ll_gpio_port.h" -#include "hal_ll_rcc.h" #define hal_ll_gpio_port_get_pin_index(__index) ( ( uint8_t )__index&0xF )//% PORT_SIZE ) diff --git a/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt b/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt index 219b13c6a2..ad6a816326 100644 --- a/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt @@ -12,4 +12,4 @@ target_link_libraries(lib_hal_ll INTERFACE ) mikrosdk_install(MikroSDK.HalLowLevel) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_rcc.h ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) diff --git a/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt b/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt index 28ab72984c..c5bc037ab4 100644 --- a/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt @@ -31,7 +31,6 @@ endif() mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master ${i2c_subimplementation} - ../../include/hal_ll_rcc.h ../../include/hal_ll_target.h # BEGIN I2C ../../include/i2c/hal_ll_i2c_master.h diff --git a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c index c0c73ecc03..88b0bdd113 100644 --- a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c @@ -43,7 +43,6 @@ #include "hal_ll_gpio.h" #include "hal_ll_i2c_master.h" #include "hal_ll_i2c_pin_map.h" -#include "hal_ll_rcc.h" #include "delays.h" /*!< @brief Local handle list */ diff --git a/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c b/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c index bdebcb7ead..cb1a2177da 100644 --- a/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c +++ b/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c @@ -140,418 +140,56 @@ static hal_ll_err_t hal_ll_one_wire_search( hal_ll_one_wire_t *obj, hal_ll_one_w // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS void hal_ll_one_wire_open( hal_ll_one_wire_t *obj ) { - // Local instance of One Wire pin. - hal_ll_gpio_pin_t one_wire_pin; - // Enable appropriate PORT clock, set pin to be digital output. - hal_ll_gpio_configure_pin( &one_wire_pin, obj->data_pin, HAL_LL_GPIO_DIGITAL_OUTPUT ); - - /* Enables appropriate PORT clock, configures pin to have digital output functionality, - * makes sure that HIGH voltage state is applied on pin before any One Wire actions. */ - hal_ll_one_wire_reconfigure( obj ); } hal_ll_err_t hal_ll_one_wire_reset( hal_ll_one_wire_t *obj ) { - /* Variable for checking whether there are device(s) on - * One Wire data pin (0) or there aren't any devices at all (1). */ - uint8_t device_response = 1; - - uint32_t bit_location = 1 << one_wire_handle.data_pin; - - if ( !obj->state ) - return HAL_LL_ONE_WIRE_ERROR; - - *(uint32_t *)one_wire_handle.direction |= bit_location; - - // Set pin to LOW voltage level. - *(uint32_t *)one_wire_handle.input_output &= ~bit_location; - - // Timing value for reset of One Wire bus - LOW voltage level. - one_wire_timing_value_h(); - - // Release pin ( pull-up resistor will do the rest (pull the data line up) ). - *(uint32_t *)one_wire_handle.direction &= ~(bit_location); - - // Timing value for reset of One Wire bus - Master sample pulse. - one_wire_timing_value_i(); - - // Check whether there are devices on One Wire data pin. - device_response = *(uint32_t *)one_wire_handle.input_output & bit_location; - - // Provide enough time for power injection into internal power logic of devices that are present. - one_wire_timing_value_j(); - - // Return final result of device response. - return device_response; + return 0; } hal_ll_err_t hal_ll_one_wire_read_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ) { - // Initiate Reset sequence. - if ( hal_ll_one_wire_reset( obj ) != 0 ) { - return HAL_LL_ONE_WIRE_ERROR; - } - - // Initiate "Read ROM" command. - hal_ll_one_wire_write_byte( &hal_ll_one_wire_read_rom_command, 1 ); - - // Read ROM address. - hal_ll_one_wire_read_byte( &device_rom_address->address[0], 8 ); - - return HAL_LL_ONE_WIRE_SUCCESS; + return 0; } hal_ll_err_t hal_ll_one_wire_skip_rom( hal_ll_one_wire_t *obj ) { - // Initiate Reset sequence. - if ( hal_ll_one_wire_reset( obj ) != 0 ) { - return HAL_LL_ONE_WIRE_ERROR; - } - - // Initiate "Skip ROM" command. - hal_ll_one_wire_write_byte( &hal_ll_one_wire_skip_rom_command, 1 ); - - return HAL_LL_ONE_WIRE_SUCCESS; + return 0; } hal_ll_err_t hal_ll_one_wire_match_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ) { - // Initiate Reset sequence. - if ( hal_ll_one_wire_reset( obj ) != 0 ) { - return HAL_LL_ONE_WIRE_ERROR; - } - - // Initiate "Match" command. - hal_ll_one_wire_write_byte( &hal_ll_one_wire_match_rom_command, 1 ); - - // Send ROM address. - hal_ll_one_wire_write_byte( (uint32_t)device_rom_address, 8 ); - - return HAL_LL_ONE_WIRE_SUCCESS; + return 0; } static hal_ll_err_t hal_ll_one_wire_search( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) { - // Final search result variable. - uint8_t search_result = 0; - - // Initialize variables for search method. - uint8_t rom_byte_number = 0; - uint8_t rom_byte_mask = 1; - uint8_t id_bit_number = 1; - uint8_t last_zero = 0; - - // The first bit read in a bit search sequence. - // ( logical AND of all of the id_bit_number bits of the devices that are still participating in the search ). - uint8_t id_bit = 0; - - // The complement of id_bit. - // ( logical AND of the complement of all id_bit_number bits of the devices that are still participating in the search ). - uint8_t cmp_id_bit = 0; - - // Search direction ( bit-per-bit search ). - uint8_t search_direction = 0; - - // If the last call was not the last one... - if ( !last_device_flag ) { - - // If there were no any device while executing One Wire reset sequence... - if ( hal_ll_one_wire_reset( obj ) ) { - - // Reset all the important variables. - last_device_flag = 0; - last_discrepancy = 0; - last_family_discrepancy = 0; - - // Stop searching because there are no any One Wire capable devices. - return HAL_LL_ONE_WIRE_ERROR; - } - - // If device(s) has(have) been found, initiate "Search" command. - hal_ll_one_wire_write_byte( &hal_ll_one_wire_search_rom_command, 1 ); - - // Iterate until all 64 bits (8 bytes) of unique ROM 'registration' numbers have not been found. - do { - // Read a bit. - hal_ll_one_wire_read_bit( &id_bit ); - - // Then, read its complement. - hal_ll_one_wire_read_bit( &cmp_id_bit ); - - // Check whether no devices participating in current search. - if ( ( id_bit == 1 ) && ( cmp_id_bit == 1 ) ) { - break; - // Proceed, because we have found some device(s). - } else { - // We are going to check once again whether read bit and - // its complement of all the devices on the One Wire grid are not the same. - // If they are not the same, we are going to start our search with non-complement bit. - if ( id_bit != cmp_id_bit ) { - search_direction = id_bit; // Bit write value for search. - - // Otherwise, there are both binary zeros and ones in the current - // bit position of the participating ROM numbers. This is a discrepancy. - } else { - if ( id_bit_number < last_discrepancy ) { - search_direction = ( ( one_wire_device_list->address[ rom_byte_number ] & rom_byte_mask ) > 0 ); - } else { - search_direction = ( id_bit_number == last_discrepancy ); - } - - // If 0 is picked, save its position. - if ( search_direction == 0) { - last_zero = id_bit_number; - - // Check for last discrepancy in family. - if ( last_zero < 9 ) { - last_family_discrepancy = last_zero; - } - } - } - - // Set or clear bit in the ROM byte rom_byte_number with mask rom_byte_mask. - if ( search_direction == 1 ) { - one_wire_device_list->address[ rom_byte_number ] |= rom_byte_mask; - } else { - one_wire_device_list->address[ rom_byte_number ] &= ~rom_byte_mask; - } - - // Search number search direction write bit. - hal_ll_one_wire_write_bit( search_direction ); - - // Increment the byte counter "id_bit_number", and shift the mask "rom_byte_mask". - id_bit_number++; - rom_byte_mask <<= 1; - - // If the mask is zero, then go to new "serial_num" byte, "rom_byte_number" and "reset_mask". - if ( rom_byte_mask == 0 ) { - rom_byte_number++; - rom_byte_mask = 1; - } - } - } while ( rom_byte_number < HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ); - - // If the search was successful then... - if ( !( id_bit_number < 65 ) ) { - - last_discrepancy = last_zero; - - // Check for last device. - if ( last_discrepancy == 0 ) { - last_device_flag = 1; - } - search_result = 1; - } - } - // If no device found then reset counters so next "search" will be like a first. - if ( !search_result || !one_wire_device_list->address[0] ) { - last_discrepancy = 0; - last_family_discrepancy = 0; - last_device_flag = 0; - search_result = 0; - } - - // Return info whether we have found some device ID or not. - return search_result; + return 0; } hal_ll_err_t hal_ll_one_wire_search_first_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) { - // Reset the search state. - last_discrepancy = 0; - last_device_flag = 0; - last_family_discrepancy = 0; - - // Initiate search algorithm, in order to get first device on One Wire grid. - hal_ll_one_wire_search( obj, one_wire_device_list ); - - return HAL_LL_ONE_WIRE_SUCCESS; + return 0; } hal_ll_err_t hal_ll_one_wire_search_next_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) { - // Initiate search algorithm, in order to get first device on One Wire grid. - hal_ll_one_wire_search( obj, one_wire_device_list ); - - return HAL_LL_ONE_WIRE_SUCCESS; + return 0; } void hal_ll_one_wire_write_byte( uint8_t *write_data_buffer, size_t write_data_length ) { - uint8_t bit_location = 1 << one_wire_handle.data_pin; - size_t local_byte_checker = 0; - uint8_t local_bit_checker = 0; - - // For every byte to be sent... - while ( local_byte_checker != write_data_length ) { - - // ...restart bit checker... - local_bit_checker = 0; - - // For every bit in byte to be sent... - while ( local_bit_checker != HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ) { - // Set pin to be digital output. - *(uint32_t *)one_wire_handle.direction |= bit_location; - - // Set pin to LOW voltage level. - *(uint32_t *)one_wire_handle.input_output &= ~bit_location; - - // Check whether a bit is binary one. - if ( write_data_buffer[ local_byte_checker ] & hal_ll_one_wire_selected_bit[ local_bit_checker ] ) { - // Timing value "a" for writing logical '1' - LOW voltage level. - one_wire_timing_value_a(); - // Else, bit is binary zero. - } else { - // Timing value "c" for writing logical '0' - LOW voltage level. - one_wire_timing_value_c(); - } - - // Release One Wire data line ( pull-up resistor will pull the data line up ). - *(uint32_t *)one_wire_handle.direction &= ~bit_location; - - // Recommended timing after writing 1's or 0's. - if ( write_data_buffer[ local_byte_checker ] & hal_ll_one_wire_selected_bit[ local_bit_checker ] ) { - // Timing value "b" for writing logical '1' - LOW voltage level. - one_wire_timing_value_b(); - } else { - // Timing value "d" for writing logical '0' - HIGH voltage level. - one_wire_timing_value_d(); - } - // Increment so we could send another bit. - ++local_bit_checker; - } - // Increment so we could send another byte. - ++local_byte_checker; - } + } void hal_ll_one_wire_read_byte( uint8_t *read_data_buffer, size_t read_data_length ) { - size_t local_byte_checker = 0; - uint8_t local_bit_checker = 0; - uint8_t bit_location = 1 << one_wire_handle.data_pin; - uint8_t local_buffer = 0; - // For every byte to be read... - while ( local_byte_checker != read_data_length ) { - - // ...restart bit checker and buffer... - local_bit_checker = 0; - local_buffer = 0; - - // For every bit in byte to be read... - while ( local_bit_checker != HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ) { - // Set pin to be digital output. - *(uint32_t*)one_wire_handle.direction |= bit_location; - - // Set pin to LOW voltage level. - *(uint32_t*)one_wire_handle.input_output &= ~bit_location; - - // Timing value "a" for bit reading - LOW voltage level. - one_wire_timing_value_a(); - - // Release One Wire data line ( pull-up resistor will pull the data line up ). - *(uint32_t*)one_wire_handle.direction &= ~bit_location; - - // Timing value "e" for sampling read information. - one_wire_timing_value_e(); - - // Read bit. - local_buffer += ( (*(uint32_t*)one_wire_handle.input_output & bit_location)?(1):(0) ) << local_bit_checker; - - // Timing value "f" for the rest of the read operation. - one_wire_timing_value_f(); - - // Increment so we could send another bit. - ++local_bit_checker; - } - // Send back one logical level up a byte of data that has been just read. - read_data_buffer[local_byte_checker++] = local_buffer; - } } // ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS static void hal_ll_one_wire_write_bit( uint8_t write_data_buffer ) { - size_t local_byte_checker = 0; - uint8_t local_bit_checker = 0; - uint8_t bit_location = 1 << one_wire_handle.data_pin; - - // Set pin to be digital output. - *(uint32_t *)one_wire_handle.direction |= bit_location; - - // Set pin to LOW voltage level. - *(uint32_t *)one_wire_handle.input_output &= ~bit_location; - - // Check whether a bit is binary one. - if ( write_data_buffer & hal_ll_one_wire_selected_bit[ local_bit_checker ] ) { - // Timing value "a" for writing logical '1' - LOW voltage level. - one_wire_timing_value_a(); - // Else, bit is binary zero. - } else { - // Timing value "c" for writing logical '0' - LOW voltage level. - one_wire_timing_value_c(); - } - - // Release One Wire data line ( pull-up resistor will pull the data line up ). - *(uint32_t *)one_wire_handle.direction &= ~bit_location; - - // Recommended timing after writing 1's or 0's. - if ( write_data_buffer & hal_ll_one_wire_selected_bit[ local_bit_checker ] ) { - // Timing value "b" for writing logical '1' - LOW voltage level. - one_wire_timing_value_b(); - } else { - // Timing value "d" for writing logical '0' - HIGH voltage level. - one_wire_timing_value_d(); - } + } static void hal_ll_one_wire_read_bit( uint8_t *read_data_buffer ) { - uint8_t bit_location = 1 << one_wire_handle.data_pin; - - // Set pin to be digital output. - *(uint32_t *)one_wire_handle.direction |= bit_location; - - // Set pin to LOW voltage level. - *(uint32_t *)one_wire_handle.input_output &= ~bit_location; - // Timing value "a" for bit reading - LOW voltage level. - one_wire_timing_value_a(); - - // Release One Wire data line ( pull-up resistor will pull the data line up ). - *(uint32_t *)one_wire_handle.direction &= ~bit_location; - - // Timing value "e" for sampling read information. - one_wire_timing_value_e(); - - // Read bit. - read_data_buffer[ 0 ] = ( *(uint32_t *)one_wire_handle.input_output & bit_location ) ? 0x01 : 0x00; - - // Timing value "f" for the rest of the read operation. - one_wire_timing_value_f(); } void hal_ll_one_wire_reconfigure( hal_ll_one_wire_t *obj ) { - // // Local instance of One Wire pin. - // hal_ll_gpio_pin_t one_wire_pin; - - // // Get pin base address and mask. - // one_wire_pin.base = (hal_ll_gpio_base_t)hal_ll_gpio_port_base(hal_ll_gpio_port_index(obj->data_pin)); - // one_wire_pin.mask = hal_ll_gpio_pin_mask(obj->data_pin); - - // // The idle state for the One Wire bus is HIGH. - // do { - // // Make sure that we have HIGH voltage state before any actions. - // hal_ll_gpio_write_pin_output( &one_wire_pin, 1 ); - - // // Make sure that pin is at HIGH voltage state. - // } while ( !hal_ll_gpio_read_pin_output( &one_wire_pin ) ); - - // // Memorize info about pin number (for future use). - // one_wire_handle.data_pin = obj->data_pin % PORT_SIZE; - - // // Get all the necessary registers for appropriate PORT which holds One Wire pin. - // hal_ll_gpio_base_handle_t *gpio_ptr = (hal_ll_gpio_base_handle_t *)one_wire_pin.base; - - // // MODER register 32-bit address. - // one_wire_handle.direction = (uint32_t)&gpio_ptr->gpiodir; - - // // Memorize info about register whose main task is to alter GPIO pin direction. - // one_wire_handle.input_output = (uint32_t)&gpio_ptr->gpiodata; - // // Set object state to true. - // obj->state = true; } // ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt b/targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt index 07cbb37ff6..1dd1af53dd 100644 --- a/targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt @@ -25,7 +25,6 @@ set( spi_pin_map "hal_ll_spi_master_pin_map/implementation_1" ) mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master ${spi_subimplementation} - ../../include/hal_ll_rcc.h ../../include/hal_ll_target.h # BEGIN SPI ../../include/spi_master/hal_ll_spi_master.h diff --git a/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c b/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c index dd41aee90c..b26175ddbe 100644 --- a/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c +++ b/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c @@ -43,7 +43,6 @@ #include "hal_ll_spi_master.h" #include "hal_ll_spi_master_pin_map.h" #include "hal_ll_gpio_port.h" -#include "hal_ll_rcc.h" /*!< @brief Local handle list */ static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[ SPI_MODULE_COUNT ] = { ( handle_t * )NULL, ( handle_t * )NULL, false }; @@ -73,7 +72,7 @@ typedef enum { /*!< @brief SPI register structure. */ typedef struct { - + } hal_ll_spi_master_base_handle_t; /*!< @brief SPI Master hardware specific module values. */ @@ -470,188 +469,63 @@ void hal_ll_spi_master_close( handle_t* handle ) { // ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS static hal_ll_pin_name_t _hal_ll_spi_master_check_pins( hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ) { - static uint16_t sck_map_size = ( sizeof( _spi_sck_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) ); - static uint16_t miso_map_size = ( sizeof( _spi_miso_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) ); - static uint16_t mosi_map_size = ( sizeof( _spi_mosi_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) ); - - uint8_t hal_ll_module_id = 0; - uint8_t index_counter = 0; - uint16_t miso_index; - uint16_t mosi_index; - uint16_t sck_index; - - if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { - return HAL_LL_PIN_NC; - } - - // Check pins from the specific pin maps with the user defined pins. - for( sck_index = 0; sck_index < sck_map_size; sck_index++ ) { - if( _spi_sck_map[ sck_index ].pin == sck_pin ) { - for( miso_index = 0; miso_index < miso_map_size; miso_index++ ) { - if( _spi_miso_map[ miso_index ].pin == miso_pin ) { - if( _spi_sck_map[ sck_index ].module_index == _spi_miso_map[ miso_index ].module_index ) { - for( mosi_index = 0; mosi_index < mosi_map_size; mosi_index++ ) { - if( _spi_mosi_map[ mosi_index ].pin == mosi_pin ) { - if( _spi_sck_map[ sck_index ].module_index == _spi_mosi_map[ mosi_index ].module_index ) { - hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; - - index_list[ hal_ll_module_id ].pin_sck = sck_index; - index_list[ hal_ll_module_id ].pin_miso = miso_index; - index_list[ hal_ll_module_id ].pin_mosi = mosi_index; - - if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { - return hal_ll_module_id; - } else if ( SPI_MODULE_COUNT == ++index_counter ) { - return --index_counter; - } - - } - } - } - } - } - } - } - } - - if ( index_counter ) { - return hal_ll_module_id; - } else { - return HAL_LL_PIN_NC; - } - - return HAL_LL_SPI_MASTER_SUCCESS; + return 0; } static hal_ll_spi_master_hw_specifics_map_t *_hal_ll_get_specifics( handle_t handle ) { - uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_spi_master_handle_register_t ) ); - static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_spi_master_handle_register_t ) ); - - while ( hal_ll_module_count-- ) { - if ( hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[ hal_ll_module_count ].base ) { - return &hal_ll_spi_master_hw_specifics_map[ hal_ll_module_count ]; - } - } - - // If NOK, return pointer to the last row of this map ( point to null pointer ). - return &hal_ll_spi_master_hw_specifics_map[ hal_ll_module_error ]; + return 0; } static void _hal_ll_spi_master_map_pins( uint8_t module_index, hal_ll_spi_pin_id *index_list ) { - // If every single pin is OK, insert them into this new map, and use this map in all low level functions. - hal_ll_spi_master_hw_specifics_map[ module_index ].pins.sck.pin_name = _spi_sck_map[ index_list[ module_index ].pin_sck ].pin; - hal_ll_spi_master_hw_specifics_map[ module_index ].pins.miso.pin_name = _spi_miso_map[ index_list[ module_index ].pin_miso ].pin; - hal_ll_spi_master_hw_specifics_map[ module_index ].pins.mosi.pin_name = _spi_mosi_map[ index_list[ module_index ].pin_mosi ].pin; - - //SCK, MISO and MOSI pin could have different alternate function settings, hence save all of the AF-s. - hal_ll_spi_master_hw_specifics_map[ module_index ].pins.sck.pin_af = _spi_sck_map[ index_list[ module_index ].pin_sck ].af; - hal_ll_spi_master_hw_specifics_map[ module_index ].pins.miso.pin_af = _spi_miso_map[ index_list[ module_index ].pin_miso ].af; - hal_ll_spi_master_hw_specifics_map[ module_index ].pins.mosi.pin_af = _spi_mosi_map[ index_list[ module_index ].pin_mosi ].af; + } static void _hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ) { - module_struct module; - - if ( ( map->pins.sck.pin_name != HAL_LL_PIN_NC ) && ( map->pins.miso.pin_name != HAL_LL_PIN_NC ) && ( map->pins.mosi.pin_name != HAL_LL_PIN_NC ) ) { - module.pins[ 0 ] = VALUE( map->pins.sck.pin_name, map->pins.sck.pin_af ); - module.pins[ 1 ] = VALUE( map->pins.mosi.pin_name, map->pins.mosi.pin_af ); - module.pins[ 2 ] = VALUE( map->pins.miso.pin_name, map->pins.miso.pin_af ); - module.pins[ 3 ] = GPIO_MODULE_STRUCT_END; - - // module.configs[ 0 ] = HAL_LL_SPI_AF_CONFIG_SCK; - // module.configs[ 1 ] = HAL_LL_SPI_AF_CONFIG_MOSI; - // module.configs[ 2 ] = HAL_LL_SPI_AF_CONFIG_MISO; - module.configs[ 3 ] = GPIO_MODULE_STRUCT_END; - hal_ll_gpio_module_struct_init( &module, hal_ll_state ); - } } static void _hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ) { - switch( map->module_index ) { - #if defined ( SPI_MODULE_0 ) - case ( hal_ll_spi_master_module_num( SPI_MODULE_0 ) ): - _hal_ll_spi_master0_set_clock( hal_ll_state ); - break; - #endif - #if defined ( SPI_MODULE_1 ) - case ( hal_ll_spi_master_module_num( SPI_MODULE_1 ) ): - _hal_ll_spi_master1_set_clock( hal_ll_state ); - break; - #endif - #if defined ( SPI_MODULE_2 ) - case ( hal_ll_spi_master_module_num( SPI_MODULE_2 ) ): - _hal_ll_spi_master2_set_clock( hal_ll_state ); - break; - #endif - #if defined ( SPI_MODULE_3 ) - case ( hal_ll_spi_master_module_num( SPI_MODULE_3 ) ): - _hal_ll_spi_master3_set_clock( hal_ll_state ); - break; - #endif - - default: - break; - } + } static inline void _hal_ll_spi_master0_set_clock ( bool hal_ll_state ) { - // Check hal_ll_state, and set the bit for the clock - // hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI0_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI0_ENABLE ); + } static inline void _hal_ll_spi_master1_set_clock( bool hal_ll_state ) { - // Check hal_ll_state, and set the bit for the clock - // hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI1_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI1_ENABLE ); + } static inline void _hal_ll_spi_master2_set_clock( bool hal_ll_state ) { - // Check hal_ll_state, and set the bit for the clock - // hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI2_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI2_ENABLE ); + } static inline void _hal_ll_spi_master3_set_clock( bool hal_ll_state ) { - // Check hal_ll_state, and set the bit for the clock - // hal_ll_state ? set_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI3_ENABLE ) : clear_reg_bit( _SYSCTL_RCGCSSI, HAL_LL_SPI3_ENABLE ); + } uint8_t _hal_ll_spi_master_transfer( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer ) { - + return 0; } static void _hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { - size_t transfer_counter = 0; - for ( transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++ ) { - _hal_ll_spi_master_transfer( hal_ll_hw_reg, write_data_buffer[ transfer_counter ] ); - } } static void _hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data ) { - size_t transfer_counter = 0; - for( transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++ ) { - read_data_buffer[ transfer_counter ] = _hal_ll_spi_master_transfer( hal_ll_hw_reg, dummy_data ); - } } static void _hal_ll_spi_master_mode_selection( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, hal_ll_spi_master_mode_t mode ) { - + } static void _hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map ) { - + } static void _hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ) { - //Enable specific clock module. - _hal_ll_spi_master_set_clock( map, true ); - - //Enable specific alternate functions. - _hal_ll_spi_master_alternate_functions_set_state( map, true ); - //Finally, write user-defined settings into hardware registers. - _hal_ll_spi_master_hw_init( map ); } // ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/tim/CMakeLists.txt b/targets/arm/mikroe/renesas/src/tim/CMakeLists.txt index 3cfad235a8..3d8bddbff7 100644 --- a/targets/arm/mikroe/renesas/src/tim/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/tim/CMakeLists.txt @@ -24,7 +24,6 @@ set( tim_pin_map "hal_ll_tim_pin_map/implementation_1" ) mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM ${tim_subimplementation} - ../../include/hal_ll_rcc.h ../../include/hal_ll_target.h # BEGIN TIM ../../include/tim/hal_ll_tim.h diff --git a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c index 59044163f7..5f3a288505 100644 --- a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c @@ -41,7 +41,6 @@ * @brief TIM HAL LOW LEVEL layer implementation. */ -#include "hal_ll_rcc.h" #include "hal_ll_tim.h" #include "hal_ll_gpio.h" #include "hal_ll_tim_pin_map.h" @@ -63,56 +62,6 @@ static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COU #define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base -/*!< @brief Helper macros for choosing CCP based on pin parity. */ -#define HAL_LL_TIM_CCP_0 (0) -#define HAL_LL_TIM_CCP_1 (1) - -/*!< @brief Helper macros for getting TIMER clocks operational. */ -#define HAL_LL_TIM_RCGCTIMER_T0 (0) -#define HAL_LL_TIM_RCGCTIMER_T1 (1) -#define HAL_LL_TIM_RCGCTIMER_T2 (2) -#define HAL_LL_TIM_RCGCTIMER_T3 (3) -#define HAL_LL_TIM_RCGCTIMER_T4 (4) -#define HAL_LL_TIM_RCGCTIMER_T5 (5) -#define HAL_LL_TIM_RCGCTIMER_T6 (6) -#define HAL_LL_TIM_RCGCTIMER_T7 (7) - -/*!< @brief Helper macro for getting TIMER clock in on/off state - TIMER A. */ -#define HAL_LL_TIM_CTL_TAEN (0) - -/*!< @brief Helper macro for PWM Output Level (output non-inverted/inverted) - TIMER A. */ -#define HAL_LL_TIM_CTL_TAPWML (6) - -/*!< @brief Helper macro for applying PWM mode in TIMER A module. */ -#define HAL_LL_TIM_TAMR_TAAMS (3) - -/*!< @brief Helper macro for getting TIMER clock in on/off state - TIMER B. */ -#define HAL_LL_TIM_CTL_TBEN (8) - -/*!< @brief Helper macro for PWM Output Level (output non-inverted/inverted) - TIMER A. */ -#define HAL_LL_TIM_CTL_TBPWML (14) - -/*!< @brief Helper macro for applying PWM mode in TIMER B module. */ -#define HAL_LL_TIM_TBMR_TBAMS (3) - -/*!< @brief Helper macro for configuring TIMER module as a 16-bit timer. */ -#define HAL_LL_TIM_CFG_SET_16BIT_TIMER (4) - -/*!< @brief Helper macro for configuring basic TIMER module settings for PWM capability. */ -#define HAL_LL_TIM_PWM_MODE (10) - -/*!< @brief Helper macro for cleaning global operation of General Purpose Timer Module Register. */ -#define HAL_LL_TIM_CLEAN_GLOBAL_TIM_CONFIG (7) - -/*!< @brief Helper macro for cleaning General Purpose Timer Module Mode Register. */ -#define HAL_LL_TIM_CLEAN_MODE_TIM_CONFIG (15) - -/*!< @brief Helper macro for regulating configuration of duty cycle. */ -#define HAL_LL_TIM_REG_CLEAN_MASK1 (0xFF) -#define HAL_LL_TIM_REG_CLEAN_MASK2 (0xFFFF) - -/*!< @brief Helper macro for retrieving user-defined MCU (Necto Setups Wizard) frequency. */ -#define _fosc ( Get_Fosc_kHz() * 1000 ) // -------------------------------------------------------------- PRIVATE TYPES /*!< @brief TIM hw specific error values. */ @@ -155,41 +104,7 @@ typedef struct { } hal_ll_tim_hw_specifics_map_t; typedef struct { - hal_ll_base_addr_t cfg; // General-Purpose Timer Module Config Register. - hal_ll_base_addr_t tamr; // General-Purpose Timer Module timer A Register. - hal_ll_base_addr_t tbmr; // General-Purpose Timer Module timer B Register. - hal_ll_base_addr_t ctl; // General-Purpose Timer Module Control Register. - hal_ll_base_addr_t sync; // General-Purpose Timer Module Sync Register. - hal_ll_base_addr_t __unused1; // Reserved memory space. - hal_ll_base_addr_t imr; // General-Purpose Timer Module Interrupt Mask Register. - hal_ll_base_addr_t ris; // General-Purpose Timer Module Raw Interrupt Status Register. - hal_ll_base_addr_t mis; // General-Purpose Timer Module Masked Interrupt Status Register. - hal_ll_base_addr_t icr; // General-Purpose Timer Module Interrupt Clear Register. - hal_ll_base_addr_t tailr; // General-Purpose Timer Module timer A Interval Load Register. - hal_ll_base_addr_t tbilr; // General-Purpose Timer Module timer B Interval Load Register. - hal_ll_base_addr_t tamatchr; // General-Purpose Timer Module timer A Match Register. - hal_ll_base_addr_t tbmatchr; // General-Purpose Timer Module timer B Match Register. - hal_ll_base_addr_t tapr; // General-Purpose Timer Module timer A Prescale Register. - hal_ll_base_addr_t tbpr; // General-Purpose Timer Module timer B Prescale Register. - hal_ll_base_addr_t tapmr; // General-Purpose Timer Module timer A Prescale Match Register. - hal_ll_base_addr_t tbpmr; // General-Purpose Timer Module timer B Prescale Match Register. - hal_ll_base_addr_t tar; // General-Purpose Timer Module timer A Register. - hal_ll_base_addr_t tbr; // General-Purpose Timer Module timer B Register. - hal_ll_base_addr_t tav; // General-Purpose Timer Module timer A Value Register. - hal_ll_base_addr_t tbv; // General-Purpose Timer Module timer B Value Register. - hal_ll_base_addr_t rtcpd; // General-Purpose Timer Module RTC Predivide Register. - hal_ll_base_addr_t taps; // General-Purpose Timer Module timer A Prescale Snapshot Register. - hal_ll_base_addr_t tbps; // General-Purpose Timer Module timer B Prescale Snapshot Register. - /* Commented out for memory optimization; - * Uncomment if needed. - */ - // hal_ll_base_addr_t __unused2[2]; // Reserved memory space. - // hal_ll_base_addr_t dmaev; // General-Purpose Timer Module DMA Event Register. - // hal_ll_base_addr_t adcev; // General-Purpose Timer Module ADC Event Register. - // hal_ll_base_addr_t __unused4[979]; // Reserved memory space. - // hal_ll_base_addr_t mpp; // General-Purpose Timer Module Peripheral Properties. - // hal_ll_base_addr_t __unused5; // Reserved memory space. - // hal_ll_base_addr_t mcc; // General-Purpose Timer Module Clock Configuration. + } hal_ll_tim_base_handle_t; // ------------------------------------------------------------------ VARIABLES @@ -610,37 +525,7 @@ hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { } uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { - uint32_t period; - uint32_t tmp_freq; - - low_level_handle = hal_ll_tim_get_handle; - hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); - - hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); - - low_level_handle->init_ll_state = false; - - hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; - - period = ( _fosc ) / freq_hz; - - if ( period > ( UINT16_MAX * UINT8_MAX ) ) { - tmp_freq = ( _fosc ) / ( UINT16_MAX * UINT8_MAX ); - hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; - hal_ll_tim_hw_specifics_map_local->max_period = UINT16_MAX * UINT8_MAX; - } else { - tmp_freq = freq_hz; - hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; - hal_ll_tim_hw_specifics_map_local->max_period = period; - } - - _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); - - _hal_ll_tim_set_period( hal_ll_tim_hw_specifics_map_local ); - - low_level_handle->init_ll_state = true; - - return tmp_freq; + return 0; } hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { @@ -689,368 +574,132 @@ hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { } void hal_ll_tim_close( handle_t *handle ) { - low_level_handle = hal_ll_tim_get_handle; - hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); - - if ( low_level_handle->hal_ll_tim_handle != NULL ) { - low_level_handle->hal_ll_tim_handle = NULL; - low_level_handle->hal_drv_tim_handle = NULL; - - low_level_handle->init_ll_state = false; - - hal_ll_tim_hw_specifics_map_local->max_period = 0; - hal_ll_tim_hw_specifics_map_local->freq_hz = 0; - - _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local, true ); - _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); - _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local, false ); - hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; - hal_ll_tim_hw_specifics_map_local->config.pin_parity = HAL_LL_TIM_CCP_0; - hal_ll_tim_hw_specifics_map_local->config.af = NULL; - - map_pointer_functions(hal_ll_tim_hw_specifics_map_local->module_index, HAL_LL_TIM_CCP_0); - } } // ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { - module_struct module; - uint32_t tim_config = 0; - - if( map->config.pin != HAL_LL_PIN_NC ) { - if( hal_ll_state != false ) { - // tim_config |= GPIO_CFG_DIGITAL_INPUT | GPIO_CFG_ALT_FUNCTION; - } - - module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); - module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; - module.configs[ 0 ] = tim_config; - module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; - - hal_ll_gpio_module_struct_init( &module, hal_ll_state ); - } } static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { - hal_ll_pin_name_t pin_num; - uint8_t index_counter = 0; - uint8_t hal_ll_module_id = 0; - uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); - - if ( HAL_LL_PIN_NC == pin ) { - return HAL_LL_PIN_NC; - } - - // Check if the selected pin is valid. - for ( pin_num = 0; pin_num < map_size; pin_num++ ) { - if ( pin == _tim_map[ pin_num ].pin ) { - // Get module number. - hal_ll_module_id = _tim_map[ pin_num ].module_index; - map_pointer_functions( hal_ll_module_id, pin % 2 ); - - if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_tim_handle ) { - *index = pin_num; - return hal_ll_module_id; - } else if( TIM_MODULE_COUNT == ++index_counter ) { - return --index_counter; - } - } - } - // By default return last error msg. - if ( index_counter ) { - return hal_ll_module_id; - } else { - return HAL_LL_PIN_NC; - } + return 0; } static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { - hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; - hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; - hal_ll_tim_hw_specifics_map[ module_index ].config.pin_parity = _tim_map[ index ].pin % 2; } static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { - uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); - static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); - - while( hal_ll_module_count-- ) { - if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base ) { - return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; - } - } - - return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; + return 0; } static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { - // Enable specific clock module. - _hal_ll_tim_set_clock( map, true ); - // Enable specific alternate functions. - _hal_ll_tim_alternate_functions_set_state( map, true ); - - // Finally, write user-defined settings into hardware registers. - _hal_ll_tim_hw_init( map ); } static void _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_t* map, bool hal_ll_state ) { - switch (map->module_index) { - #ifdef TIM_MODULE_0 - case ( TIM_MODULE_0 ): - _hal_ll_tim0_set_clock( hal_ll_state ); - break; - #endif - #ifdef TIM_MODULE_1 - case ( TIM_MODULE_1 ): - _hal_ll_tim1_set_clock( hal_ll_state ); - break; - #endif - #ifdef TIM_MODULE_2 - case ( TIM_MODULE_2 ): - _hal_ll_tim2_set_clock( hal_ll_state ); - break; - #endif - #ifdef TIM_MODULE_3 - case ( TIM_MODULE_3 ): - _hal_ll_tim3_set_clock( hal_ll_state ); - break; - #endif - #ifdef TIM_MODULE_4 - case ( TIM_MODULE_4 ): - _hal_ll_tim4_set_clock( hal_ll_state ); - break; - #endif - #ifdef TIM_MODULE_5 - case ( TIM_MODULE_5 ): - _hal_ll_tim5_set_clock( hal_ll_state ); - break; - #endif - #ifdef TIM_MODULE_6 - case ( TIM_MODULE_6 ): - _hal_ll_tim6_set_clock( hal_ll_state ); - break; - #endif - #ifdef TIM_MODULE_7 - case ( TIM_MODULE_7 ): - _hal_ll_tim7_set_clock( hal_ll_state ); - break; - #endif - default: - break; - } } static void _hal_ll_tim0_set_clock( bool hal_ll_state ) { - if ( hal_ll_state ) { - set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T0 ); - } else { - clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T0); - } + } static void _hal_ll_tim1_set_clock( bool hal_ll_state ) { - if ( hal_ll_state ) { - set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T1 ); - } else { - clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T1); - } + } static void _hal_ll_tim2_set_clock( bool hal_ll_state ) { - if ( hal_ll_state ) { - set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T2 ); - } else { - clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T2); - } + } static void _hal_ll_tim3_set_clock( bool hal_ll_state ) { - if ( hal_ll_state ) { - set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T3 ); - } else { - clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T3); - } + } static void _hal_ll_tim4_set_clock( bool hal_ll_state ) { - if ( hal_ll_state ) { - set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T4 ); - } else { - clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T4); - } + } static void _hal_ll_tim5_set_clock( bool hal_ll_state ) { - if ( hal_ll_state ) { - set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T5 ); - } else { - clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T5); - } + } static void _hal_ll_tim6_set_clock( bool hal_ll_state ) { - if ( hal_ll_state ) { - set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T6 ); - } else { - clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T6); - } + } static void _hal_ll_tim7_set_clock( bool hal_ll_state ) { - if ( hal_ll_state ) { - set_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T7 ); - } else { - clear_reg_bit(_SYSCTL_RCGCTIMER, HAL_LL_TIM_RCGCTIMER_T7); - } + } static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { - hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); - - (hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_hw_init_control) - (hal_ll_tim_hw_specifics_map_local->base); - - hal_ll_hw_reg->cfg &= ~(hal_ll_base_addr_t)( HAL_LL_TIM_CLEAN_GLOBAL_TIM_CONFIG ); - hal_ll_hw_reg->cfg |= (hal_ll_base_addr_t)(HAL_LL_TIM_CFG_SET_16BIT_TIMER); - (hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_hw_init_pwm_mode) - (hal_ll_tim_hw_specifics_map_local->base); } static void _hal_ll_tim_set_period( hal_ll_tim_hw_specifics_map_t *map ) { - hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); - (hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_period) - (hal_ll_tim_hw_specifics_map_local->base, hal_ll_tim_hw_specifics_map_local->max_period); } // ---------------------------------------------------- STATIC POINTER FUNCTIONS static inline void map_pointer_functions( uint8_t hal_ll_module_id, uint8_t pin_parity ) { - if ( pin_parity ) { - hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_duty = &ptr_function_timer_b_duty; - hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_signal_start = &ptr_function_timer_b_start; - hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_signal_stop = &ptr_function_timer_b_stop; - hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_period = &ptr_function_timer_b_period; - hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_hw_init_control = &ptr_function_timer_b_hw_init_control; - hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_hw_init_pwm_mode = &ptr_function_timer_b_pwm_mode_set; - } else { - hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_duty = &ptr_function_timer_a_duty; - hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_signal_start = &ptr_function_timer_a_start; - hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_signal_stop = &ptr_function_timer_a_stop; - hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_period = &ptr_function_timer_a_period; - hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_hw_init_control = &ptr_function_timer_a_hw_init_control; - hal_ll_tim_hw_specifics_map[hal_ll_module_id].mapped_functions.mapped_function_hw_init_pwm_mode = &ptr_function_timer_a_pwm_mode_set; - } + } static inline void ptr_function_timer_a_duty( hal_ll_tim_base_handle_t *hal_ll_hw_reg, uint32_t duty_cycle_timeout, uint32_t max_period ) { - /* Turns PWM off if the duty cycle is 0 (this is done because - * if duty cycle is configured to max_period it will behave the same as max duty - 100%) - */ - if ( duty_cycle_timeout == max_period ) { - clear_reg_bit(&hal_ll_hw_reg->tamr,HAL_LL_TIM_TAMR_TAAMS); - } else { - set_reg_bit(&hal_ll_hw_reg->tamr,HAL_LL_TIM_TAMR_TAAMS); - } - - // Clean TimerA Prescale Match Register. - hal_ll_hw_reg->tapmr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_REG_CLEAN_MASK1 ); - - // Insert appropriate value in this register. - hal_ll_hw_reg->tapmr |= ( hal_ll_base_addr_t )( duty_cycle_timeout >> 16 ) & HAL_LL_TIM_REG_CLEAN_MASK1; - // Clean TimerA Match Register. - hal_ll_hw_reg->tamatchr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_REG_CLEAN_MASK2 ); - - // Insert appropriate value in this register. - hal_ll_hw_reg->tamatchr |= ( hal_ll_base_addr_t )( duty_cycle_timeout ) & HAL_LL_TIM_REG_CLEAN_MASK2; } static inline void ptr_function_timer_b_duty( hal_ll_tim_base_handle_t *hal_ll_hw_reg, uint32_t duty_cycle_timeout, uint32_t max_period ) { - /* Turns PWM off if the duty cycle is 0 (this is done because - * if duty cycle is configured to max_period it will behave the same as max duty - 100%) - */ - if ( duty_cycle_timeout == max_period ) { - clear_reg_bit(&hal_ll_hw_reg->tbmr,HAL_LL_TIM_TBMR_TBAMS); - } else { - set_reg_bit(&hal_ll_hw_reg->tbmr,HAL_LL_TIM_TBMR_TBAMS); - } - // Clean TimerB Prescale Match Register. - hal_ll_hw_reg->tbpmr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_REG_CLEAN_MASK1 ); - - // Insert appropriate value in this register. - hal_ll_hw_reg->tbpmr |= ( hal_ll_base_addr_t )( duty_cycle_timeout >> 16 ) & HAL_LL_TIM_REG_CLEAN_MASK1; - - // Clean TimerB Match Register. - hal_ll_hw_reg->tbmatchr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_REG_CLEAN_MASK2 ); - - // Insert appropriate value in this register. - hal_ll_hw_reg->tbmatchr |= ( hal_ll_base_addr_t )( duty_cycle_timeout ) & HAL_LL_TIM_REG_CLEAN_MASK2; } static inline void ptr_function_timer_a_start( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { - set_reg_bit( &hal_ll_hw_reg->tamr, HAL_LL_TIM_TAMR_TAAMS ); - set_reg_bit( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TAEN ); + } static inline void ptr_function_timer_b_start( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { - set_reg_bit( &hal_ll_hw_reg->tbmr, HAL_LL_TIM_TBMR_TBAMS ); - set_reg_bit( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TBEN ); + } static inline void ptr_function_timer_a_stop( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { - clear_reg_bit( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TAEN ); - clear_reg_bit( &hal_ll_hw_reg->tamr, HAL_LL_TIM_TAMR_TAAMS ); + } static inline void ptr_function_timer_b_stop( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { - clear_reg_bit( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TBEN ); - clear_reg_bit( &hal_ll_hw_reg->tbmr, HAL_LL_TIM_TBMR_TBAMS ); + } static inline void ptr_function_timer_a_period( hal_ll_tim_base_handle_t *hal_ll_hw_reg, uint32_t max_period ) { - hal_ll_hw_reg->tapr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_REG_CLEAN_MASK1 ); - hal_ll_hw_reg->tapr |= ( max_period >> 16 ) & HAL_LL_TIM_REG_CLEAN_MASK1; - hal_ll_hw_reg->tailr = max_period & HAL_LL_TIM_REG_CLEAN_MASK2; + } static inline void ptr_function_timer_b_period( hal_ll_tim_base_handle_t *hal_ll_hw_reg, uint32_t max_period ) { - hal_ll_hw_reg->tbpr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_REG_CLEAN_MASK1 ); - hal_ll_hw_reg->tbpr |= ( max_period >> 16 ) & HAL_LL_TIM_REG_CLEAN_MASK1; - hal_ll_hw_reg->tbilr = max_period & HAL_LL_TIM_REG_CLEAN_MASK2; + } static inline void ptr_function_timer_a_hw_init_control( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { - clear_reg_bit ( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TAEN ); - clear_reg_bit ( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TAPWML ); + } static inline void ptr_function_timer_b_hw_init_control( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { - clear_reg_bit ( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TBEN ); - clear_reg_bit ( &hal_ll_hw_reg->ctl, HAL_LL_TIM_CTL_TBPWML ); + } static inline void ptr_function_timer_a_pwm_mode_set( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { - hal_ll_hw_reg->tamr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_CLEAN_MODE_TIM_CONFIG ); - hal_ll_hw_reg->tamr |= ( hal_ll_base_addr_t )( HAL_LL_TIM_PWM_MODE ); + } static inline void ptr_function_timer_b_pwm_mode_set( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { - hal_ll_hw_reg->tbmr &= ~( hal_ll_base_addr_t )( HAL_LL_TIM_CLEAN_MODE_TIM_CONFIG ); - hal_ll_hw_reg->tbmr |= ( hal_ll_base_addr_t )( HAL_LL_TIM_PWM_MODE ); + } // ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/uart/CMakeLists.txt b/targets/arm/mikroe/renesas/src/uart/CMakeLists.txt index ec6679bde1..a6a543a6f8 100644 --- a/targets/arm/mikroe/renesas/src/uart/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/uart/CMakeLists.txt @@ -21,7 +21,6 @@ set(uart_pin_map "hal_ll_uart_pin_map/implementation_1") mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART ${uart_subimplementation} - ../../include/hal_ll_rcc.h ../../include/hal_ll_target.h # BEGIN UART ../../include/uart/hal_ll_uart.h diff --git a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c index dda13c07ea..6ffc5c3aae 100644 --- a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c @@ -41,7 +41,6 @@ * @brief UART HAL LOW LEVEL layer implementation. */ -#include "hal_ll_rcc.h" #include "hal_ll_uart.h" #include "hal_ll_gpio.h" #include "hal_ll_core.h" @@ -71,77 +70,6 @@ static volatile hal_ll_uart_handle_register_t hal_ll_module_state[ UART_MODULE_C #define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud))) #define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) -/*!< @brief Macros defining bit location. */ -#define HAL_LL_UART0EN (0) -#define HAL_LL_UART1EN (1) -#define HAL_LL_UART2EN (2) -#define HAL_LL_UART3EN (3) -#define HAL_LL_UART4EN (4) -#define HAL_LL_UART5EN (5) -#define HAL_LL_UART6EN (6) -#define HAL_LL_UART7EN (7) - -#define HAL_LL_UART_CTL_UARTEN (0) -#define HAL_LL_UART_CTL_FEN (4) -#define HAL_LL_UART_CTL_TXE (8) -#define HAL_LL_UART_CTL_RXE (9) - -#define HAL_LL_UART_IT_RXIM_BIT (4) -#define HAL_LL_UART_IT_TXIM_BIT (5) -#define HAL_LL_UART_IT_OER_BIT (10) - -/*!< @brief Macros defining register bit values. */ -#define HAL_LL_UART_LCRH_MASK (0xFFUL) -#define HAL_LL_UART_CTL_MASK (0xCFBFUL) - -#define HAL_LL_UART_IT_FR_RXFE (0x10UL) -#define HAL_LL_UART_IT_FR_TXFF (0x20UL) - -#define STOP_BITS_MASK (0x8UL) -#define STOP_BITS_ONE (0x0UL) -#define STOP_BITS_TWO (STOP_BITS_MASK) - -#define DATA_BITS_MASK (0x60UL) -#define DATA_BIT_5 (0x0UL) -#define DATA_BIT_6 (0x20UL) -#define DATA_BIT_7 (0x40UL) -#define DATA_BIT_8 (DATA_BITS_MASK) - -#define PARITY_STICK (0x80UL) -#define PARITY_MASK (0x6UL) -#define PARITY_NO (0x0UL) -#define PARITY_EVEN (PARITY_MASK) -#define PARITY_ODD (0x2UL) - -#define HAL_LL_UART_CTL_HSE_BIT (0x20UL) - -#define HAL_LL_UART_ERRORS (0xF00U) -#define HAL_LL_UART_DATA (0xFFU) - -/*!< @brief Macros used for interrupts. */ -#define HAL_LL_UART_IT_CLEAR_MASK (0x360U) -#define HAL_LL_UART_IT_CR1_MASK (0x1F0UL) -#define HAL_LL_UART_IT_CR2_MASK (0x40UL) -#define HAL_LL_UART_IT_CR3_MASK (0x401UL) - -#define HAL_LL_UART_CR1_REG_INDEX (1) -#define HAL_LL_UART_CR2_REG_INDEX (2) -#define HAL_LL_UART_CR3_REG_INDEX (3) - -#define HAL_LL_UART_IT_PE (0x10000100UL) -#define HAL_LL_UART_IT_TXIM (1UL << HAL_LL_UART_IT_TXIM_BIT) -#define HAL_LL_UART_IT_TC (0x10000040UL) -#define HAL_LL_UART_IT_RXIM (1UL << HAL_LL_UART_IT_RXIM_BIT) -#define HAL_LL_UART_IT_IDLE (0x10000010UL) - -#define HAL_LL_UART_IT_LBD (0x20000040UL) - -#define HAL_LL_UART_IT_CTS (0x30000400UL) -#define HAL_LL_UART_IT_ERR (0x30000001UL) - -#define HAL_LL_UART_STATUS_RXMIS_FLAG (HAL_LL_UART_IT_RXIM) -#define HAL_LL_UART_STATUS_TXMIS_FLAG (HAL_LL_UART_IT_TXIM) - /*!< @brief Macro used for status registed flag check. * Used in interrupt handlers. */ @@ -154,29 +82,7 @@ static volatile hal_ll_uart_handle_register_t hal_ll_module_state[ UART_MODULE_C /*!< @brief UART HW register structure. */ typedef struct { - uint32_t dr; // Data register. - uint32_t rsr_ecr; // Receive status/error clear register. - uint32_t __unused1[4]; - uint32_t fr; // Flag register. - uint32_t __unused2; - uint32_t ilpr; // IrDA low power register. - uint32_t ibrd; // Integer baud-rate register. - uint32_t fbrd; // Fractional baud rate register. - uint32_t lcrh; // Line control register. - uint32_t ctl; // Control register. - uint32_t ifls; // Interrupt FIFO level select register. - uint32_t im; // Interrupt mask register. - uint32_t ris; // Raw interrupt status register. - uint32_t mis; // Masked interrupt status register. - uint32_t icr; // Interrupt clear register. - /* Register aren't used in this source. - * Uncomment if needed. */ - /* - uint32_t dmactl; // DMA control register. - uint32_t __unused3[22]; - uint32_t nine_bitaddr; // Nine bit self addres register. - uint32_t nine_bitmask; // Nine bit self adress mask register. - */ + } hal_ll_uart_base_handle_t; /*!< @brief UART baud rate structure. */ @@ -636,10 +542,10 @@ void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { switch ( irq ) { case HAL_LL_UART_IRQ_RX: - set_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_RXIM_BIT ); + // TODO break; case HAL_LL_UART_IRQ_TX: - set_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_TXIM_BIT ); + // TODO break; default: @@ -701,10 +607,10 @@ void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) { switch ( irq ) { case HAL_LL_UART_IRQ_RX: - clear_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_RXIM_BIT ); + // TODO break; case HAL_LL_UART_IRQ_TX: - clear_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_TXIM_BIT ); + // TODO break; default: @@ -716,8 +622,11 @@ void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) { * Interrupts should be disabled ONLY in case we have * both TX and RX interrupts disabled. */ - if ( ( !check_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_RXIM_BIT ) ) && - ( !check_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_TXIM_BIT ) ) ) + if ( + // ( !check_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_RXIM_BIT ) ) && + // ( !check_reg_bit( &hal_ll_hw_reg->im, HAL_LL_UART_IT_TXIM_BIT ) ) + 1 // TODO + ) { switch ( hal_ll_uart_hw_specifics_map_local->module_index ) { #if defined(UART_MODULE_0) && defined(UART0_NVIC) @@ -770,19 +679,13 @@ void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) { void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; - - hal_ll_hw_reg->dr = wr_data; + // TODO } void hal_ll_uart_write_polling( handle_t *handle, uint8_t wr_data) { hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; - - while ( hal_ll_hw_reg->fr & HAL_LL_UART_IT_FR_TXFF ) { - // Wait for TXFF (Until the transmitter is not full) - } - - hal_ll_hw_reg->dr = wr_data; + // TODO } uint8_t hal_ll_uart_read( handle_t *handle ) { @@ -790,21 +693,7 @@ uint8_t hal_ll_uart_read( handle_t *handle ) { hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; - if ( check_reg_bit( &hal_ll_hw_reg->ris, HAL_LL_UART_IT_OER_BIT ) ) { - set_reg_bit( &hal_ll_hw_reg->icr, HAL_LL_UART_IT_OER_BIT ); - } - - frame = hal_ll_hw_reg->dr; - - /** - * TODO: Error flags are set by hardware in UARTDR[11:8]. - * Error handling will be added in a future release. - * - * Code example: - * // If error is present return 0, otherwise actual data. - * return (frame & HAL_LL_UART_ERRORS) ? (0) : (frame); - */ - return frame & HAL_LL_UART_DATA; + return 0; // TODO } uint8_t hal_ll_uart_read_polling( handle_t *handle ) { @@ -812,25 +701,7 @@ uint8_t hal_ll_uart_read_polling( handle_t *handle ) { hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; - if ( check_reg_bit( &hal_ll_hw_reg->ris, HAL_LL_UART_IT_OER_BIT ) ) { - set_reg_bit( &hal_ll_hw_reg->icr, HAL_LL_UART_IT_OER_BIT ); - } - - while ( hal_ll_hw_reg->fr & HAL_LL_UART_IT_FR_RXFE ) { - // Wait for RXFE (Until the receiver is not empty) - } - - frame = hal_ll_hw_reg->dr; - - /** - * TODO: Error flags are set by hardware in UARTDR[11:8]. - * Error handling will be added in a future release. - * - * Code example: - * // If error is present return 0, otherwise actual data. - * return (frame & HAL_LL_UART_ERRORS) ? (0) : (frame); - */ - return frame & HAL_LL_UART_DATA; + return 0; // TODO } // ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS @@ -1086,34 +957,7 @@ static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_ } static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { - uint32_t reg = 0; - uint32_t integer_divider = 0; - uint32_t fractional_divider = 0; - uint8_t clk_div; - hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); - - if (hal_ll_hw_reg->ctl & HAL_LL_UART_CTL_HSE_BIT) { - clk_div = 8; - } else { - clk_div = 16; - } - double hal_ll_baud_value = ( ( double )( hal_ll_uart_get_clock_speed( map->module_index ) ) / - ( double )( clk_div * ( map->baud_rate.baud ) ) ); - uint32_t hal_ll_baud_value_int = ( uint32_t )hal_ll_baud_value; - uint32_t hal_ll_baud_value_fract = ( uint32_t )( ( ( hal_ll_baud_value - ( double ) hal_ll_baud_value_int ) * ( double )64 ) + ( double )0.5 ); - uint32_t hal_ll_baud_real_value = ( uint32_t )( ( double )( hal_ll_uart_get_clock_speed( map->module_index ) ) / - ( double )( clk_div * ( ( double )hal_ll_baud_value_int + ( hal_ll_baud_value_fract/ - ( double )64 ) ) ) + ( double )0.5); - - // If error greater than specified, cancel setting baud rate. - if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { - map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); - } else { - map->baud_rate.real_baud = hal_ll_baud_real_value; - hal_ll_hw_reg->ibrd = hal_ll_baud_value_int; - hal_ll_hw_reg->fbrd = hal_ll_baud_value_fract; - } } static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { @@ -1121,166 +965,39 @@ static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { } static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { - hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); - switch ( map->stop_bit ) { - case HAL_LL_UART_STOP_BITS_ONE: - hal_ll_hw_reg->lcrh &= ~STOP_BITS_MASK; - break; - case HAL_LL_UART_STOP_BITS_TWO: - hal_ll_hw_reg->lcrh |= STOP_BITS_TWO; - break; - - default: - break; - } } static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { - hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); - switch ( map->data_bit ) { - case HAL_LL_UART_DATA_BITS_5: - hal_ll_hw_reg->lcrh &= ~DATA_BITS_MASK; - break; - case HAL_LL_UART_DATA_BITS_6: - hal_ll_hw_reg->lcrh &= ~DATA_BITS_MASK; - hal_ll_hw_reg->lcrh |= DATA_BIT_6; - break; - case HAL_LL_UART_DATA_BITS_7: - hal_ll_hw_reg->lcrh &= ~DATA_BITS_MASK; - hal_ll_hw_reg->lcrh |= DATA_BIT_7; - break; - case HAL_LL_UART_DATA_BITS_8: - hal_ll_hw_reg->lcrh |= DATA_BIT_8; - break; - - default: - break; - } } static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { - hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); - switch ( map->parity ) { - case HAL_LL_UART_PARITY_NONE: - hal_ll_hw_reg->lcrh &= ~(PARITY_MASK | PARITY_STICK); - break; - case HAL_LL_UART_PARITY_EVEN: - hal_ll_hw_reg->lcrh |= (PARITY_EVEN | PARITY_STICK); - break; - case HAL_LL_UART_PARITY_ODD: - hal_ll_hw_reg->lcrh &= ~PARITY_MASK; - hal_ll_hw_reg->lcrh |= (PARITY_ODD | PARITY_STICK); - break; - - default: - break; - } } static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { - switch ( pin_state ) { - case HAL_LL_UART_DISABLE: - clear_reg_bit( &( hal_ll_hw_reg->ctl ), HAL_LL_UART_CTL_UARTEN ); - break; - case HAL_LL_UART_ENABLE: - set_reg_bit( &( hal_ll_hw_reg->ctl ), HAL_LL_UART_CTL_UARTEN ); - break; - default: - break; - } } static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { - switch ( pin_state ) { - case HAL_LL_UART_DISABLE: - clear_reg_bit( &( hal_ll_hw_reg->ctl ), HAL_LL_UART_CTL_TXE ); - break; - case HAL_LL_UART_ENABLE: - set_reg_bit( &( hal_ll_hw_reg->ctl ), HAL_LL_UART_CTL_TXE ); - break; - default: - break; - } } static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { - switch ( pin_state ) { - case HAL_LL_UART_DISABLE: - clear_reg_bit( &( hal_ll_hw_reg->ctl ), HAL_LL_UART_CTL_RXE ); - break; - case HAL_LL_UART_ENABLE: - set_reg_bit( &( hal_ll_hw_reg->ctl ), HAL_LL_UART_CTL_RXE ); - break; - default: - break; - } } static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { - clear_reg_bit( &( hal_ll_hw_reg->ctl ), HAL_LL_UART_CTL_UARTEN ); - clear_reg_bit( &( hal_ll_hw_reg->lcrh ), HAL_LL_UART_CTL_FEN ); - hal_ll_hw_reg->lcrh &= ~HAL_LL_UART_LCRH_MASK; - hal_ll_hw_reg->ctl &= ~HAL_LL_UART_CTL_MASK; + } static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { - hal_ll_uart_clear_regs( map->base ); - - hal_ll_uart_set_baud_bare_metal( map ); - - /* In order for UART Transmit interrupt to - * be triggered, initial dummy data write is - * required. Writing to the register here is - * harmless as we disable TX/RX pins and the - * whole UART module in `hal_ll_uart_clear_regs` - * function. For more information on this issue, - * please have a look at the following link. - * - * - */ - ((hal_ll_uart_base_handle_t *)(map->base))->dr = 0; - - hal_ll_uart_set_data_bits_bare_metal( map ); - - hal_ll_uart_set_parity_bare_metal( map ); - hal_ll_uart_set_stop_bits_bare_metal( map ); - - hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); - - hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); - - hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); } static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { - /*!< @brief Static, because clock doesn't change during runtime */ - uint32_t hal_ll_clock_value = Get_Fosc_kHz() * 2; - - hal_ll_uart_alternate_functions_set_state( map, true ); - - hal_ll_uart_set_clock( map, true ); - - /* There must be a delay of 3 system clocks after the UART module - * clock is enabled before any UART module registers are accessed. - * See datasheet page 1327 for more information. - * - */ - assembly( nop ); - assembly( nop ); - assembly( nop ); - - hal_ll_uart_hw_init( map ); - hal_ll_uart_wait_for_sync(hal_ll_clock_value); } // ------------------------------------------------------------------------- END From 0643842c835dcf059df4e6d545ae630132cebf5d Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Thu, 19 Jun 2025 14:37:50 +0200 Subject: [PATCH 08/62] pin names update --- .../mikroe/renesas/include/hal_ll_pin_names.h | 670 ++++++++++-------- 1 file changed, 362 insertions(+), 308 deletions(-) diff --git a/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h b/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h index 420456b2e6..ceecd4deb7 100644 --- a/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h +++ b/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h @@ -108,594 +108,664 @@ extern "C"{ #define GPIO_FEATURE_GROUP_18 #endif +// PORT 0 #ifdef __P000_CN #define GPIO_P000 (0x00) -#define P000 GPIO_P000 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA0! +#define P000 GPIO_P000 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P000! #endif #ifdef __P001_CN #define GPIO_P001 (0x01) -#define P001 GPIO_P001 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA1! +#define P001 GPIO_P001 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P001! #endif #ifdef __P002_CN #define GPIO_P002 (0x02) -#define P002 GPIO_P002 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA2! +#define P002 GPIO_P002 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P002! #endif #ifdef __P003_CN #define GPIO_P003 (0x03) -#define P003 GPIO_P003 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA3! +#define P003 GPIO_P003 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P003! #endif #ifdef __P004_CN #define GPIO_P004 (0x04) -#define P004 GPIO_P004 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA4! +#define P004 GPIO_P004 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P004! #endif #ifdef __P005_CN #define GPIO_P005 (0x05) -#define P005 GPIO_P005 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA5! +#define P005 GPIO_P005 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P005! #endif #ifdef __P006_CN #define GPIO_P006 (0x06) -#define P006 GPIO_P006 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA6! +#define P006 GPIO_P006 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P006! #endif #ifdef __P007_CN #define GPIO_P007 (0x07) -#define P007 GPIO_P007 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA7! +#define P007 GPIO_P007 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P007! #endif #ifdef __P008_CN #define GPIO_P008 (0x08) -#define P008 GPIO_P008 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB0! +#define P008 GPIO_P008 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P008! #endif #ifdef __P009_CN #define GPIO_P009 (0x09) -#define P009 GPIO_P009 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB1! +#define P009 GPIO_P009 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P009! #endif #ifdef __P010_CN #define GPIO_P010 (0x0A) -#define P010 GPIO_P010 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB2! +#define P010 GPIO_P010 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P010! #endif #ifdef __P011_CN #define GPIO_P011 (0x0B) -#define P011 GPIO_P011 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB3! +#define P011 GPIO_P011 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P011! #endif #ifdef __P012_CN #define GPIO_P012 (0x0C) -#define P012 GPIO_P012 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB4! +#define P012 GPIO_P012 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P012! #endif #ifdef __P013_CN #define GPIO_P013 (0x0D) -#define P013 GPIO_P013 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB5! +#define P013 GPIO_P013 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P013! #endif #ifdef __P014_CN #define GPIO_P014 (0x0E) -#define P014 GPIO_P014 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB6! +#define P014 GPIO_P014 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P014! #endif #ifdef __P015_CN #define GPIO_P015 (0x0F) -#define P015 GPIO_P015 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB7! +#define P015 GPIO_P015 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P015! #endif +// PORT 1 #ifdef __P100_CN #define GPIO_P100 (0x10) -#define P100 GPIO_P100 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC0! +#define P100 GPIO_P100 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P100! #endif #ifdef __P101_CN #define GPIO_P101 (0x11) -#define P101 GPIO_P101 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC1! +#define P101 GPIO_P101 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P101! #endif #ifdef __P102_CN #define GPIO_P102 (0x12) -#define P102 GPIO_P102 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC2! +#define P102 GPIO_P102 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P102! #endif #ifdef __P103_CN #define GPIO_P103 (0x13) -#define P103 GPIO_P103 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC3! +#define P103 GPIO_P103 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P103! #endif #ifdef __P104_CN #define GPIO_P104 (0x14) -#define P104 GPIO_P104 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC4! +#define P104 GPIO_P104 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P104! #endif #ifdef __P105_CN #define GPIO_P105 (0x15) -#define P105 GPIO_P105 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC5! +#define P105 GPIO_P105 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P105! #endif #ifdef __P106_CN #define GPIO_P106 (0x16) -#define P106 GPIO_P106 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC6! +#define P106 GPIO_P106 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P106! #endif #ifdef __P107_CN #define GPIO_P107 (0x17) -#define P107 GPIO_P107 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC7! +#define P107 GPIO_P107 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P107! #endif #ifdef __P108_CN #define GPIO_P108 (0x18) -#define P108 GPIO_P108 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD0! +#define P108 GPIO_P108 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P108! #endif #ifdef __P109_CN #define GPIO_P109 (0x19) -#define P109 GPIO_P109 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD1! +#define P109 GPIO_P109 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P109! #endif #ifdef __P110_CN #define GPIO_P110 (0x1A) -#define P110 GPIO_P110 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD2! +#define P110 GPIO_P110 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P110! #endif #ifdef __P111_CN #define GPIO_P111 (0x1B) -#define P111 GPIO_P111 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD3! +#define P111 GPIO_P111 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P111! #endif #ifdef __P112_CN #define GPIO_P112 (0x1C) -#define P112 GPIO_P112 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD4! +#define P112 GPIO_P112 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P112! #endif #ifdef __P113_CN #define GPIO_P113 (0x1D) -#define P113 GPIO_P113 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD5! +#define P113 GPIO_P113 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P113! #endif #ifdef __P114_CN #define GPIO_P114 (0x1E) -#define P114 GPIO_P114 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD6! +#define P114 GPIO_P114 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P114! #endif #ifdef __P115_CN #define GPIO_P115 (0x1F) -#define P115 GPIO_P115 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD7! +#define P115 GPIO_P115 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P115! #endif +// PORT 2 #ifdef __P200_CN #define GPIO_P200 (0x20) -#define P200 GPIO_P200 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE0! +#define P200 GPIO_P200 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P200! #endif #ifdef __P201_CN #define GPIO_P201 (0x21) -#define P201 GPIO_P201 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE1! +#define P201 GPIO_P201 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P201! #endif #ifdef __P202_CN #define GPIO_P202 (0x22) -#define P202 GPIO_P202 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE2! +#define P202 GPIO_P202 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P202! #endif #ifdef __P203_CN #define GPIO_P203 (0x23) -#define P203 GPIO_P203 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE3! +#define P203 GPIO_P203 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P203! #endif #ifdef __P204_CN #define GPIO_P204 (0x24) -#define P204 GPIO_P204 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE4! +#define P204 GPIO_P204 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P204! #endif #ifdef __P205_CN #define GPIO_P205 (0x25) -#define P205 GPIO_P205 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE5! +#define P205 GPIO_P205 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P205! #endif #ifdef __P206_CN #define GPIO_P206 (0x26) -#define P206 GPIO_P206 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE6! +#define P206 GPIO_P206 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P206! #endif #ifdef __P207_CN #define GPIO_P207 (0x27) -#define P207 GPIO_P207 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE7! +#define P207 GPIO_P207 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P207! #endif #ifdef __P208_CN #define GPIO_P208 (0x28) -#define P208 GPIO_P208 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF0! +#define P208 GPIO_P208 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P208! #endif #ifdef __P209_CN #define GPIO_P209 (0x29) -#define P209 GPIO_P209 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF1! +#define P209 GPIO_P209 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P209! #endif #ifdef __P210_CN #define GPIO_P210 (0x2A) -#define P210 GPIO_P210 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF2! +#define P210 GPIO_P210 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P210! #endif #ifdef __P211_CN #define GPIO_P211 (0x2B) -#define P211 GPIO_P211 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF3! +#define P211 GPIO_P211 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P211! #endif #ifdef __P212_CN #define GPIO_P212 (0x2C) -#define P212 GPIO_P212 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF4! +#define P212 GPIO_P212 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P212! #endif #ifdef __P213_CN #define GPIO_P213 (0x2D) -#define P213 GPIO_P213 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF5! +#define P213 GPIO_P213 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P213! #endif #ifdef __P214_CN #define GPIO_P214 (0x2E) -#define P214 GPIO_P214 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF6! +#define P214 GPIO_P214 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P214! #endif #ifdef __P215_CN #define GPIO_P215 (0x2F) -#define P215 GPIO_P215 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PF7! +#define P215 GPIO_P215 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P215! #endif +// PORT 3 #ifdef __P300_CN #define GPIO_P300 (0x30) -#define P300 GPIO_P300 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG0! +#define P300 GPIO_P300 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P300! #endif #ifdef __P301_CN #define GPIO_P301 (0x31) -#define P301 GPIO_P301 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG1! +#define P301 GPIO_P301 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P301! #endif #ifdef __P302_CN #define GPIO_P302 (0x32) -#define P302 GPIO_P302 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG2! +#define P302 GPIO_P302 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P302! #endif #ifdef __P303_CN #define GPIO_P303 (0x33) -#define P303 GPIO_P303 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG3! +#define P303 GPIO_P303 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P303! #endif #ifdef __P304_CN #define GPIO_P304 (0x34) -#define P304 GPIO_P304 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG4! +#define P304 GPIO_P304 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P304! #endif #ifdef __P305_CN #define GPIO_P305 (0x35) -#define P305 GPIO_P305 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG5! +#define P305 GPIO_P305 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P305! #endif #ifdef __P306_CN #define GPIO_P306 (0x36) -#define P306 GPIO_P306 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG6! +#define P306 GPIO_P306 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P306! #endif #ifdef __P307_CN #define GPIO_P307 (0x37) -#define P307 GPIO_P307 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG7! +#define P307 GPIO_P307 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P307! #endif #ifdef __P308_CN #define GPIO_P308 (0x38) -#define P308 GPIO_P308 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH0! +#define P308 GPIO_P308 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P308! #endif #ifdef __P309_CN #define GPIO_P309 (0x39) -#define P309 GPIO_P309 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH1! +#define P309 GPIO_P309 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P309! #endif #ifdef __P310_CN #define GPIO_P310 (0x3A) -#define P310 GPIO_P310 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH2! +#define P310 GPIO_P310 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P310! #endif #ifdef __P311_CN #define GPIO_P311 (0x3B) -#define P311 GPIO_P311 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH3! +#define P311 GPIO_P311 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P311! #endif #ifdef __P312_CN #define GPIO_P312 (0x3C) -#define P312 GPIO_P312 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH4! +#define P312 GPIO_P312 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P312! #endif #ifdef __P313_CN #define GPIO_P313 (0x3D) -#define P313 GPIO_P313 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH5! +#define P313 GPIO_P313 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P313! #endif #ifdef __P314_CN #define GPIO_P314 (0x3E) -#define P314 GPIO_P314 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH6! +#define P314 GPIO_P314 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P314! #endif #ifdef __P315_CN #define GPIO_P315 (0x3F) -#define P315 GPIO_P315 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH7! +#define P315 GPIO_P315 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P315! #endif +// PORT 4 #ifdef __P400_CN #define GPIO_P400 (0x40) -#define P400 GPIO_P400 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG0! +#define P400 GPIO_P400 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P400! #endif #ifdef __P401_CN #define GPIO_P401 (0x41) -#define P401 GPIO_P401 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG1! +#define P401 GPIO_P401 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P401! #endif #ifdef __P402_CN #define GPIO_P402 (0x42) -#define P402 GPIO_P402 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG2! +#define P402 GPIO_P402 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P402! #endif #ifdef __P403_CN #define GPIO_P403 (0x43) -#define P403 GPIO_P403 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG3! +#define P403 GPIO_P403 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P403! #endif #ifdef __P404_CN #define GPIO_P404 (0x44) -#define P404 GPIO_P404 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG4! +#define P404 GPIO_P404 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P404! #endif #ifdef __P405_CN #define GPIO_P405 (0x45) -#define P405 GPIO_P405 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG5! +#define P405 GPIO_P405 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P405! #endif #ifdef __P406_CN #define GPIO_P406 (0x46) -#define P406 GPIO_P406 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG6! +#define P406 GPIO_P406 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P406! #endif #ifdef __P407_CN #define GPIO_P407 (0x47) -#define P407 GPIO_P407 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PG7! +#define P407 GPIO_P407 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P407! #endif #ifdef __P408_CN #define GPIO_P408 (0x48) -#define P408 GPIO_P408 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH0! +#define P408 GPIO_P408 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P408! #endif #ifdef __P409_CN #define GPIO_P409 (0x49) -#define P409 GPIO_P409 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH1! +#define P409 GPIO_P409 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P409! #endif #ifdef __P410_CN #define GPIO_P410 (0x4A) -#define P410 GPIO_P410 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH2! +#define P410 GPIO_P410 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P410! #endif #ifdef __P411_CN #define GPIO_P411 (0x4B) -#define P411 GPIO_P411 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH3! +#define P411 GPIO_P411 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P411! #endif #ifdef __P412_CN #define GPIO_P412 (0x4C) -#define P412 GPIO_P412 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH4! +#define P412 GPIO_P412 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P412! #endif #ifdef __P413_CN #define GPIO_P413 (0x4D) -#define P413 GPIO_P413 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH5! +#define P413 GPIO_P413 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P413! #endif #ifdef __P414_CN #define GPIO_P414 (0x4E) -#define P414 GPIO_P414 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH6! +#define P414 GPIO_P414 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P414! #endif #ifdef __P415_CN #define GPIO_P415 (0x4F) -#define P415 GPIO_P415 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PH7! +#define P415 GPIO_P415 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P415! #endif -// TODO Esma ports 5-9 -#ifdef __PL0_CN -#define GPIO_PL0 (0x50) -#define PL0 GPIO_PL0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL0! +// PORT 5 +#ifdef __P500_CN +#define GPIO_P500 (0x50) +#define P500 GPIO_P500 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P500! #endif -#ifdef __PL1_CN -#define GPIO_PL1 (0x51) -#define PL1 GPIO_PL1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL1! +#ifdef __P501_CN +#define GPIO_P501 (0x51) +#define P501 GPIO_P501 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P501! #endif -#ifdef __PL2_CN -#define GPIO_PL2 (0x52) -#define PL2 GPIO_PL2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL2! +#ifdef __P502_CN +#define GPIO_P502 (0x52) +#define P502 GPIO_P502 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P502! #endif -#ifdef __PL3_CN -#define GPIO_PL3 (0x53) -#define PL3 GPIO_PL3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL3! +#ifdef __P503_CN +#define GPIO_P503 (0x53) +#define P503 GPIO_P503 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P503! #endif -#ifdef __PL4_CN -#define GPIO_PL4 (0x54) -#define PL4 GPIO_PL4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL4! +#ifdef __P504_CN +#define GPIO_P504 (0x54) +#define P504 GPIO_P504 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P504! #endif -#ifdef __PL5_CN -#define GPIO_PL5 (0x55) -#define PL5 GPIO_PL5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL5! +#ifdef __P505_CN +#define GPIO_P505 (0x55) +#define P505 GPIO_P505 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P505! #endif -#ifdef __PL6_CN -#define GPIO_PL6 (0x56) -#define PL6 GPIO_PL6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL6! +#ifdef __P506_CN +#define GPIO_P506 (0x56) +#define P506 GPIO_P506 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P506! #endif -#ifdef __PL7_CN -#define GPIO_PL7 (0x57) -#define PL7 GPIO_PL7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PL7! +#ifdef __P507_CN +#define GPIO_P507 (0x57) +#define P507 GPIO_P507 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P507! #endif - -#ifdef __PM0_CN -#define GPIO_PM0 (0x58) -#define PM0 GPIO_PM0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM0! +#ifdef __P508_CN +#define GPIO_P508 (0x58) +#define P508 GPIO_P508 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P508! #endif -#ifdef __PM1_CN -#define GPIO_PM1 (0x59) -#define PM1 GPIO_PM1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM1! +#ifdef __P509_CN +#define GPIO_P509 (0x59) +#define P509 GPIO_P509 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P509! #endif -#ifdef __PM2_CN -#define GPIO_PM2 (0x5A) -#define PM2 GPIO_PM2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM2! +#ifdef __P510_CN +#define GPIO_P510(0x5A) +#define P510 GPIO_P510 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P510! #endif -#ifdef __PM3_CN -#define GPIO_PM3 (0x5B) -#define PM3 GPIO_PM3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM3! +#ifdef __P511_CN +#define GPIO_P511(0x5B) +#define P511 GPIO_P511 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P511! #endif -#ifdef __PM4_CN -#define GPIO_PM4 (0x5C) -#define PM4 GPIO_PM4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM4! +#ifdef __P512_CN +#define GPIO_P512(0x5C) +#define P512 GPIO_P512 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P512! #endif -#ifdef __PM5_CN -#define GPIO_PM5 (0x5D) -#define PM5 GPIO_PM5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM5! +#ifdef __P513_CN +#define GPIO_P513(0x5D) +#define P513 GPIO_P513 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P513! #endif -#ifdef __PM6_CN -#define GPIO_PM6 (0x5E) -#define PM6 GPIO_PM6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM6! +#ifdef __P514_CN +#define GPIO_P514(0x5E) +#define P514 GPIO_P514 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P514! #endif -#ifdef __PM7_CN -#define GPIO_PM7 (0x5F) -#define PM7 GPIO_PM7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PM7! +#ifdef __P515_CN +#define GPIO_P515(0x5F) +#define P515 GPIO_P515 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P515! #endif -#ifdef __PN0_CN -#define GPIO_PN0 (0x60) -#define PN0 GPIO_PN0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN0! +// PORT 6 +#ifdef __P600_CN +#define GPIO_P600 (0x60) +#define P600 GPIO_P600 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P600! #endif -#ifdef __PN1_CN -#define GPIO_PN1 (0x61) -#define PN1 GPIO_PN1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN1! +#ifdef __P601_CN +#define GPIO_P601 (0x61) +#define P601 GPIO_P601 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P601! #endif -#ifdef __PN2_CN -#define GPIO_PN2 (0x62) -#define PN2 GPIO_PN2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN2! +#ifdef __P602_CN +#define GPIO_P602 (0x62) +#define P602 GPIO_P602 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P602! #endif -#ifdef __PN3_CN -#define GPIO_PN3 (0x63) -#define PN3 GPIO_PN3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN3! +#ifdef __P603_CN +#define GPIO_P603 (0x63) +#define P603 GPIO_P603 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P603! #endif -#ifdef __PN4_CN -#define GPIO_PN4 (0x64) -#define PN4 GPIO_PN4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN4! +#ifdef __P604_CN +#define GPIO_P604 (0x64) +#define P604 GPIO_P604 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P604! #endif -#ifdef __PN5_CN -#define GPIO_PN5 (0x65) -#define PN5 GPIO_PN5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN5! +#ifdef __P605_CN +#define GPIO_P605 (0x65) +#define P605 GPIO_P605 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P605! #endif -#ifdef __PN6_CN -#define GPIO_PN6 (0x66) -#define PN6 GPIO_PN6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN6! +#ifdef __P606_CN +#define GPIO_P606 (0x66) +#define P606 GPIO_P606 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P606! #endif -#ifdef __PN7_CN -#define GPIO_PN7 (0x67) -#define PN7 GPIO_PN7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PN7! +#ifdef __P607_CN +#define GPIO_P607 (0x67) +#define P607 GPIO_P607 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P607! #endif - -#ifdef __PP0_CN -#define GPIO_PP0 (0x68) -#define PP0 GPIO_PP0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP0! +#ifdef __P608_CN +#define GPIO_P608 (0x68) +#define P608 GPIO_P608 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P608! #endif -#ifdef __PP1_CN -#define GPIO_PP1 (0x69) -#define PP1 GPIO_PP1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP1! +#ifdef __P609_CN +#define GPIO_P609 (0x69) +#define P609 GPIO_P609 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P609! #endif -#ifdef __PP2_CN -#define GPIO_PP2 (0x6A) -#define PP2 GPIO_PP2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP2! +#ifdef __P610_CN +#define GPIO_P610 (0x6A) +#define P610 GPIO_P610 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P610! #endif -#ifdef __PP3_CN -#define GPIO_PP3 (0x6B) -#define PP3 GPIO_PP3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP3! +#ifdef __P611_CN +#define GPIO_P611 (0x6B) +#define P611 GPIO_P611 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P611! #endif -#ifdef __PP4_CN -#define GPIO_PP4 (0x6C) -#define PP4 GPIO_PP4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP4! +#ifdef __P612_CN +#define GPIO_P612 (0x6C) +#define P612 GPIO_P612 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P612! #endif -#ifdef __PP5_CN -#define GPIO_PP5 (0x6D) -#define PP5 GPIO_PP5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP5! +#ifdef __P613_CN +#define GPIO_P613 (0x6D) +#define P613 GPIO_P613 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P613! #endif -#ifdef __PP6_CN -#define GPIO_PP6 (0x6E) -#define PP6 GPIO_PP6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP6! +#ifdef __P614_CN +#define GPIO_P614 (0x6E) +#define P614 GPIO_P614 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P614! #endif -#ifdef __PP7_CN -#define GPIO_PP7 (0x6F) -#define PP7 GPIO_PP7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PP7! +#ifdef __P615_CN +#define GPIO_P615 (0x6F) +#define P615 GPIO_P615 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P615! #endif -#ifdef __PQ0_CN -#define GPIO_PQ0 (0x70) -#define PQ0 GPIO_PQ0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ0! +// PORT 7 +#ifdef __P700_CN +#define GPIO_P700 (0x70) +#define P700 GPIO_P700 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P700! #endif -#ifdef __PQ1_CN -#define GPIO_PQ1 (0x71) -#define PQ1 GPIO_PQ1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ1! +#ifdef __P701_CN +#define GPIO_P701 (0x71) +#define P701 GPIO_P701 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P701! #endif -#ifdef __PQ2_CN -#define GPIO_PQ2 (0x72) -#define PQ2 GPIO_PQ2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ2! +#ifdef __P702_CN +#define GPIO_P702 (0x72) +#define P702 GPIO_P702 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P702! #endif -#ifdef __PQ3_CN -#define GPIO_PQ3 (0x73) -#define PQ3 GPIO_PQ3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ3! +#ifdef __P703_CN +#define GPIO_P703 (0x73) +#define P703 GPIO_P703 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P703! #endif -#ifdef __PQ4_CN -#define GPIO_PQ4 (0x74) -#define PQ4 GPIO_PQ4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ4! +#ifdef __P704_CN +#define GPIO_P704 (0x74) +#define P704 GPIO_P704 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P704! #endif -#ifdef __PQ5_CN -#define GPIO_PQ5 (0x75) -#define PQ5 GPIO_PQ5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ5! +#ifdef __P705_CN +#define GPIO_P705 (0x75) +#define P705 GPIO_P705 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P705! #endif -#ifdef __PQ6_CN -#define GPIO_PQ6 (0x76) -#define PQ6 GPIO_PQ6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ6! +#ifdef __P706_CN +#define GPIO_P706 (0x76) +#define P706 GPIO_P706 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P706! #endif -#ifdef __PQ7_CN -#define GPIO_PQ7 (0x77) -#define PQ7 GPIO_PQ7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PQ7! +#ifdef __P707_CN +#define GPIO_P707 (0x77) +#define P707 GPIO_P707 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P707! #endif - -#ifdef __PR0_CN -#define GPIO_PR0 (0x78) -#define PR0 GPIO_PR0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR0! +#ifdef __P708_CN +#define GPIO_P708 (0x78) +#define P708 GPIO_P708 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P708! #endif -#ifdef __PR1_CN -#define GPIO_PR1 (0x79) -#define PR1 GPIO_PR1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR1! +#ifdef __P709_CN +#define GPIO_P709 (0x79) +#define P709 GPIO_P709 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P709! #endif -#ifdef __PR2_CN -#define GPIO_PR2 (0x7A) -#define PR2 GPIO_PR2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR2! +#ifdef __P710_CN +#define GPIO_P710 (0x7A) +#define P710 GPIO_P710 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P710! #endif -#ifdef __PR3_CN -#define GPIO_PR3 (0x7B) -#define PR3 GPIO_PR3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR3! +#ifdef __P711_CN +#define GPIO_P711 (0x7B) +#define P711 GPIO_P711 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P711! #endif -#ifdef __PR4_CN -#define GPIO_PR4 (0x7C) -#define PR4 GPIO_PR4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR4! +#ifdef __P712_CN +#define GPIO_P712 (0x7C) +#define P712 GPIO_P712 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P712! #endif -#ifdef __PR5_CN -#define GPIO_PR5 (0x7D) -#define PR5 GPIO_PR5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR5! +#ifdef __P713_CN +#define GPIO_P713 (0x7D) +#define P713 GPIO_P713 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P713! #endif -#ifdef __PR6_CN -#define GPIO_PR6 (0x7E) -#define PR6 GPIO_PR6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR6! +#ifdef __P714_CN +#define GPIO_P714 (0x7E) +#define P714 GPIO_P714 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P714! #endif -#ifdef __PR7_CN -#define GPIO_PR7 (0x7F) -#define PR7 GPIO_PR7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PR7! +#ifdef __P715_CN +#define GPIO_P715 (0x7F) +#define P715 GPIO_P715 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P715! #endif -#ifdef __PS0_CN -#define GPIO_PS0 (0x80) -#define PS0 GPIO_PS0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS0! +// PORT 8 +#ifdef __P800_CN +#define GPIO_P800 (0x80) +#define P800 GPIO_P800 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P800! +#endif +#ifdef __P801_CN +#define GPIO_P801 (0x81) +#define P801 GPIO_P801 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P801! +#endif +#ifdef __P802_CN +#define GPIO_P802 (0x82) +#define P802 GPIO_P802 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P802! +#endif +#ifdef __P803_CN +#define GPIO_P803 (0x83) +#define P803 GPIO_P803 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P803! +#endif +#ifdef __P804_CN +#define GPIO_P804 (0x84) +#define P804 GPIO_P804 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P804! #endif -#ifdef __PS1_CN -#define GPIO_PS1 (0x81) -#define PS1 GPIO_PS1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS1! +#ifdef __P805_CN +#define GPIO_P805 (0x85) +#define P805 GPIO_P805 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P805! #endif -#ifdef __PS2_CN -#define GPIO_PS2 (0x82) -#define PS2 GPIO_PS2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS2! +#ifdef __P806_CN +#define GPIO_P806 (0x86) +#define P806 GPIO_P806 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P806! #endif -#ifdef __PS3_CN -#define GPIO_PS3 (0x83) -#define PS3 GPIO_PS3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS3! +#ifdef __P807_CN +#define GPIO_P807 (0x87) +#define P807 GPIO_P807 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P807! #endif -#ifdef __PS4_CN -#define GPIO_PS4 (0x84) -#define PS4 GPIO_PS4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS4! +#ifdef __P808_CN +#define GPIO_P808 (0x88) +#define P808 GPIO_P808 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P808! #endif -#ifdef __PS5_CN -#define GPIO_PS5 (0x85) -#define PS5 GPIO_PS5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS5! +#ifdef __P809_CN +#define GPIO_P809 (0x89) +#define P809 GPIO_P809 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P809! #endif -#ifdef __PS6_CN -#define GPIO_PS6 (0x86) -#define PS6 GPIO_PS6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS6! +#ifdef __P810_CN +#define GPIO_P810 (0x8A) +#define P810 GPIO_P810 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P810! #endif -#ifdef __PS7_CN -#define GPIO_PS7 (0x87) -#define PS7 GPIO_PS7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PS7! +#ifdef __P811_CN +#define GPIO_P811 (0x8B) +#define P811 GPIO_P811 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P811! +#endif +#ifdef __P812_CN +#define GPIO_P812 (0x8C) +#define P812 GPIO_P812 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P812! +#endif +#ifdef __P813_CN +#define GPIO_P813 (0x8D) +#define P813 GPIO_P813 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P813! +#endif +#ifdef __P814_CN +#define GPIO_P814 (0x8E) +#define P814 GPIO_P814 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P814! +#endif +#ifdef __P815_CN +#define GPIO_P815 (0x8F) +#define P815 GPIO_P815 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P815! #endif -#ifdef __PT0_CN -#define GPIO_PT0 (0x88) -#define PT0 GPIO_PT0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT0! +// PORT 9 +#ifdef __P900_CN +#define GPIO_P900 (0x90) +#define P900 GPIO_P900 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P900! +#endif +#ifdef __P901_CN +#define GPIO_P901 (0x91) +#define P901 GPIO_P901 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P901! +#endif +#ifdef __P902_CN +#define GPIO_P902 (0x92) +#define P902 GPIO_P902 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P902! +#endif +#ifdef __P903_CN +#define GPIO_P903 (0x93) +#define P903 GPIO_P903 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P903! #endif -#ifdef __PT1_CN -#define GPIO_PT1 (0x89) -#define PT1 GPIO_PT1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT1! +#ifdef __P904_CN +#define GPIO_P904 (0x94) +#define P904 GPIO_P904 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P904! #endif -#ifdef __PT2_CN -#define GPIO_PT2 (0x8A) -#define PT2 GPIO_PT2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT2! +#ifdef __P905_CN +#define GPIO_P905 (0x95) +#define P905 GPIO_P905 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P905! #endif -#ifdef __PT3_CN -#define GPIO_PT3 (0x8B) -#define PT3 GPIO_PT3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT3! +#ifdef __P906_CN +#define GPIO_P906 (0x96) +#define P906 GPIO_P906 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P906! #endif -#ifdef __PT4_CN -#define GPIO_PT4 (0x8C) -#define PT4 GPIO_PT4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT4! +#ifdef __P907_CN +#define GPIO_P907 (0x97) +#define P907 GPIO_P907 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P907! #endif -#ifdef __PT5_CN -#define GPIO_PT5 (0x8D) -#define PT5 GPIO_PT5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT5! +#ifdef __P908_CN +#define GPIO_P908 (0x98) +#define P908 GPIO_P908 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P908! #endif -#ifdef __PT6_CN -#define GPIO_PT6 (0x8E) -#define PT6 GPIO_PT6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT6! +#ifdef __P909_CN +#define GPIO_P909 (0x99) +#define P909 GPIO_P909 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P909! #endif -#ifdef __PT7_CN -#define GPIO_PT7 (0x8F) -#define PT7 GPIO_PT7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PT7! +#ifdef __P910_CN +#define GPIO_P910 (0x9A) +#define P910 GPIO_P910 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P910! +#endif +#ifdef __P911_CN +#define GPIO_P911 (0x9B) +#define P911 GPIO_P911 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P911! +#endif +#ifdef __P912_CN +#define GPIO_P912 (0x9C) +#define P912 GPIO_P912 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P912! +#endif +#ifdef __P913_CN +#define GPIO_P913 (0x9D) +#define P913 GPIO_P913 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P913! +#endif +#ifdef __P914_CN +#define GPIO_P914 (0x9E) +#define P914 GPIO_P914 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P914! +#endif +#ifdef __P915_CN +#define GPIO_P915 (0x9F) +#define P915 GPIO_P915 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P915! #endif #define GPIO_PIN_0 (0x00) @@ -714,6 +784,22 @@ extern "C"{ #define PIN_6 GPIO_PIN_6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_6! #define GPIO_PIN_7 (0x07) #define PIN_7 GPIO_PIN_7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_7! +#define GPIO_PIN_8 (0x08) +#define PIN_8 GPIO_PIN_8 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_8! +#define GPIO_PIN_9 (0x09) +#define PIN_9 GPIO_PIN_9 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_9! +#define GPIO_PIN_10 (0x10) +#define PIN_10 GPIO_PIN_10 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_10! +#define GPIO_PIN_11 (0x11) +#define PIN_11 GPIO_PIN_11 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_11! +#define GPIO_PIN_12 (0x12) +#define PIN_12 GPIO_PIN_12 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_12! +#define GPIO_PIN_13 (0x13) +#define PIN_13 GPIO_PIN_13 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_13! +#define GPIO_PIN_14 (0x14) +#define PIN_14 GPIO_PIN_14 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_14! +#define GPIO_PIN_15 (0x15) +#define PIN_15 GPIO_PIN_15 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_15! #ifdef __PORT_0_CN #define GPIO_PORT_0 (0x00) @@ -755,38 +841,6 @@ extern "C"{ #define GPIO_PORT_9 (0x09) #define PORT_9 GPIO_PORT_9 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_9! #endif -#ifdef __PORT_10_CN -#define GPIO_PORT_10 (0x0A) -#define PORT_10 GPIO_PORT_10 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_10! -#endif -#ifdef __PORT_11_CN -#define GPIO_PORT_11 (0x0B) -#define PORT_11 GPIO_PORT_11 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_11! -#endif -#ifdef __PORT_12_CN -#define GPIO_PORT_12 (0x0C) -#define PORT_12 GPIO_PORT_12 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_12! -#endif -#ifdef __PORT_13_CN -#define GPIO_PORT_13 (0x0D) -#define PORT_13 GPIO_PORT_13 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_13! -#endif -#ifdef __PORT_14_CN -#define GPIO_PORT_14 (0x0E) -#define PORT_14 GPIO_PORT_14 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_14! -#endif -#ifdef __PORT_15_CN -#define GPIO_PORT_15 (0x0F) -#define PORT_15 GPIO_PORT_15 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_15! -#endif -#ifdef __PORT_16_CN -#define GPIO_PORT_16 (0x10) -#define PORT_16 GPIO_PORT_16 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_16! -#endif -#ifdef __PORT_17_CN -#define GPIO_PORT_17 (0x11) -#define PORT_17 GPIO_PORT_17 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_17! -#endif #ifdef __cplusplus } From 834d0a862c1ed7841ef94db570975492e45caaef Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Thu, 26 Jun 2025 13:41:57 +0200 Subject: [PATCH 09/62] gpio update --- .../gpio/implementation_1/hal_ll_gpio_port.c | 148 +++++++++++------- .../i2c/implementation_1/hal_ll_i2c_master.c | 67 +++++--- 2 files changed, 138 insertions(+), 77 deletions(-) diff --git a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c index a3728cbe9a..03067ad103 100644 --- a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c @@ -47,55 +47,108 @@ #define hal_ll_gpio_port_get_port_index(__index) ( ( uint8_t )(__index&0xF0) >> 4 ) +#ifdef GPIO_PORT_0 #define GPIO_PORT0_BASE (0x40040000UL) +#endif +#ifdef GPIO_PORT_1 #define GPIO_PORT1_BASE (0x40040020UL) +#endif +#ifdef GPIO_PORT_2 #define GPIO_PORT2_BASE (0x40040040UL) +#endif +#ifdef GPIO_PORT_3 #define GPIO_PORT3_BASE (0x40040060UL) +#endif +#ifdef GPIO_PORT_4 #define GPIO_PORT4_BASE (0x40040080UL) +#endif +#ifdef GPIO_PORT_5 #define GPIO_PORT5_BASE (0x400400A0UL) +#endif +#ifdef GPIO_PORT_6 #define GPIO_PORT6_BASE (0x400400C0UL) +#endif +#ifdef GPIO_PORT_7 #define GPIO_PORT7_BASE (0x400400E0UL) +#endif +#ifdef GPIO_PORT_8 #define GPIO_PORT8_BASE (0x40040100UL) +#endif +#ifdef GPIO_PORT_9 #define GPIO_PORT9_BASE (0x40040120UL) -// According to the documentation, this MCU has 10 ports, -// but in mcu.h there are 15 port addresses -// #define GPIO_PORT10_BASE (0x40040140UL) -// #define GPIO_PORT11_BASE (0x40040160UL) -// #define GPIO_PORT12_BASE (0x40040180UL) -// #define GPIO_PORT13_BASE (0x400401A0UL) -// #define GPIO_PORT14_BASE (0x400401C0UL) - -#define PWPR_REGISTER_BASE (( volatile uint8_t * )0x40040D03UL) +#endif +#ifdef GPIO_PORT_PORT10 +#define GPIO_PORT10_BASE (0x40040140UL) +#endif +#ifdef GPIO_PORT_PORT11 +#define GPIO_PORT11_BASE (0x40040160UL) +#endif +#ifdef GPIO_PORT_PORT12 +#define GPIO_PORT12_BASE (0x40040180UL) +#endif +#ifdef GPIO_PORT_PORT13 +#define GPIO_PORT13_BASE (0x400401A0UL) +#endif +#ifdef GPIO_PORT_PORT14 +#define GPIO_PORT14_BASE (0x400401C0UL) +#endif + +#define PWPR_REGISTER_BASE (* ( volatile uint8_t * )0x40040D03UL) +#define PFS_REGISTER_ADDR (0x4004D000UL) +#define PFS_PSEL_MASK (0x1F000000UL) /*!< @brief GPIO PORT array */ static const uint32_t hal_ll_gpio_port_base_arr[] = { + #ifdef GPIO_PORT0_BASE GPIO_PORT0_BASE, + #endif + #ifdef GPIO_PORT1_BASE GPIO_PORT1_BASE, + #endif + #ifdef GPIO_PORT2_BASE GPIO_PORT2_BASE, + #endif + #ifdef GPIO_PORT3_BASE GPIO_PORT3_BASE, + #endif + #ifdef GPIO_PORT4_BASE GPIO_PORT4_BASE, + #endif + #ifdef GPIO_PORT5_BASE GPIO_PORT5_BASE, + #endif + #ifdef GPIO_PORT6_BASE GPIO_PORT6_BASE, + #endif + #ifdef GPIO_PORT7_BASE GPIO_PORT7_BASE, + #endif + #ifdef GPIO_PORT8_BASE GPIO_PORT8_BASE, - GPIO_PORT9_BASE//, - // GPIO_PORT10_BASE, - // GPIO_PORT11_BASE, - // GPIO_PORT12_BASE, - // GPIO_PORT13_BASE, - // GPIO_PORT14_BASE + #endif + #ifdef GPIO_PORT9_BASE + GPIO_PORT9_BASE, + #endif + #ifdef GPIO_PORT10_BASE + GPIO_PORT10_BASE, + #endif + #ifdef GPIO_PORT11_BASE + GPIO_PORT11_BASE, + #endif + #ifdef GPIO_PORT12_BASE + GPIO_PORT12_BASE, + #endif + #ifdef GPIO_PORT13_BASE + GPIO_PORT13_BASE, + #endif + #ifdef GPIO_PORT14_BASE + GPIO_PORT14_BASE + #endif }; // ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS -// /** -// * @brief Enable gpio port clock -// * @param port - port base address -// * @return none -// */ -// static void _hal_ll_gpio_clock_enable( uint32_t *port ); // TODO Esma - /** * @brief Configure port pins * @param port - port base address @@ -114,7 +167,12 @@ static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t conf */ static void hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); -// TODO Esma +/** + * @brief Retrieve the index of the + * provided pin + * @param hal_ll_pin_name_t - pin + * @return uint8_t - the index of the pin + */ static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ); // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS @@ -164,11 +222,7 @@ static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) { return hal_ll_gpio_port_get_pin_index( name ); } -static void hal_ll_gpio_clock_enable( uint32_t port ) { - // TODO Esma - PORTs don't have clock enabling feature. -} - -uint32_t get_port_number(uint32_t base_addr) +static uint32_t hal_ll_gpio_get_port_number(uint32_t base_addr) { for (int i = 0; i < sizeof(hal_ll_gpio_port_base_arr) / sizeof(hal_ll_gpio_port_base_arr[0]); i++) { if (hal_ll_gpio_port_base_arr[i] == base_addr) { @@ -178,23 +232,17 @@ uint32_t get_port_number(uint32_t base_addr) return -1; // not found } -#include "mcu.h" - -#define PmnPFS ((hal_ll_gpio_pfs_t *)0x40040800UL) // Base address of PFS - static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) { uint32_t pin_index = ( pin_mask == 0xFFFF ) ? 0xFFFF : __builtin_ctz(pin_mask); // TODO Esma hal_ll_port_name_t port_index; - port_index = get_port_number( *port ); - hal_ll_gpio_pfs_t *port_pfs_ptr = &PmnPFS->port[0].pin[0]; + port_index = hal_ll_gpio_get_port_number( *port ); + hal_ll_gpio_pfs_t *port_pfs_ptr = PFS_REGISTER_ADDR; hal_ll_gpio_base_handle_t *port_ptr = (hal_ll_gpio_base_handle_t *) *port; // Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register. - // *PWPR_REGISTER_BASE &= ~0x80; // Clear B0WI bit - // // Set 1 to the PFSWE bit in the PWPR register. This enables writing to the PmnPFS register. - // *PWPR_REGISTER_BASE |= 0x40; // Set PFSWE bit - R_PMISC->PWPR_b.B0WI = 0; - R_PMISC->PWPR_b.PFSWE = 1; + PWPR_REGISTER_BASE &= ~0x80; // Clear B0WI bit + // Set 1 to the PFSWE bit in the PWPR register. This enables writing to the PmnPFS register. + PWPR_REGISTER_BASE |= 0x40; // Set PFSWE bit if ( pin_mask == 0xFFFF ) { if ( GPIO_CFG_DIGITAL_OUTPUT == config ) @@ -206,9 +254,6 @@ static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t conf port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pmr = 0; // Specify the input/output function for the pin through the PSEL[4:0] bit settings in the PmnPFS register. port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.psel = 0; - // Set the PMR to 1 as required to switch to the selected input/output function for the pin. - // TODO Esma zasto odmah stavljamo da nije GPIO nego peripheral? - // port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pmr = 1; if( GPIO_CFG_ANALOG_INPUT == config ) { port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pmr = 0; @@ -222,12 +267,10 @@ static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t conf port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.asel = 0; } - // // Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register. - // *PWPR_REGISTER_BASE &= ~0x40; // Set PFSWE bit - // // Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register - // *PWPR_REGISTER_BASE |= 0x80; // Set B0WI bit - R_PMISC->PWPR_b.PFSWE = 0; - R_PMISC->PWPR_b.B0WI = 1; + // Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register. + PWPR_REGISTER_BASE &= ~0x40; // Set PFSWE bit + // Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register + PWPR_REGISTER_BASE |= 0x80; // Set B0WI bit } } @@ -235,8 +278,7 @@ static void hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32 uint8_t pin_index; hal_ll_pin_name_t pin_name; hal_ll_port_name_t port_name; - // hal_ll_gpio_base_handle_t *port_ptr; - hal_ll_gpio_pfs_t *port_ptr; + hal_ll_gpio_pfs_t *port_ptr = PFS_REGISTER_ADDR; pin_name = module_pin & GPIO_PIN_NAME_MASK; @@ -246,14 +288,12 @@ static void hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32 port_ptr = ( hal_ll_gpio_base_handle_t* )hal_ll_gpio_port_base( port_name ); - // port_pcr_array = ( hal_ll_gpio_pcr_base_handle_t* )( GPIO_PCR_BASE_VALUE + port_name * GPIO_PCR_OFFSET_VALUE ); - hal_ll_gpio_config( (uint32_t *)&port_ptr, hal_ll_gpio_pin_mask( pin_index ), module_config ); if ( true == state ) { - port_ptr->port[port_name].pin[pin_index].pmnpfs_b.psel |= module_pin & 0x1F000000; + port_ptr->port[port_name].pin[pin_index].pmnpfs_b.psel |= module_pin & PFS_PSEL_MASK; } else { - port_ptr->port[port_name].pin[pin_index].pmnpfs_b.psel &= ~( module_pin & 0x1F000000 ); + port_ptr->port[port_name].pin[pin_index].pmnpfs_b.psel &= ~( module_pin & PFS_PSEL_MASK ); } } diff --git a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c index 88b0bdd113..120ead4a59 100644 --- a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c @@ -59,6 +59,8 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU #define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base +#define HAL_LL_I2C_AF_CONFIG 0xFF // TODO Esma + /*!< @brief Default I2C bit-rate if no speed is set */ #define HAL_LL_I2C_MASTER_SPEED_100K (100000UL) #define HAL_LL_I2C_MASTER_SPEED_400K (400000UL) @@ -222,25 +224,6 @@ static void hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); -/** - * @brief Check if pins are adequate. - * - * Checks scl and sda pins the user has passed with pre-defined - * pins in scl and sda maps. Take into consideration that module - * index numbers have to be the same for both pins. - * - * @param[in] scl - SCL pre-defined pin name. - * @param[in] sda - SDA pre-defined pin name. - * @param[in] *index_list - Index list address - * @return hal_ll_pin_name_t Module index based on pins. - * - * Returns pre-defined module index from pin maps, if pins - * are adequate. - */ -static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, - hal_ll_pin_name_t sda, - hal_ll_i2c_pin_id *index_list ); - /** * @brief Get local hardware specific map. * @@ -270,7 +253,7 @@ static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); * Returns pre-defined module index from pin maps, if pins * are adequate. */ -static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list ); +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); /** * @brief Maps new-found module specific values. @@ -365,7 +348,33 @@ static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_ // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { - return 0; + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; } hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { @@ -414,7 +423,19 @@ static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, boo } static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { - return; + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; // TODO + module.configs[1] = HAL_LL_I2C_AF_CONFIG; // TODO + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } } static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { @@ -429,7 +450,7 @@ static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { return 0; } -static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list ) { +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { return 0; } From a6cb9b6abd50abcd1c4e9a0eabad1d29b4859e4b Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Mon, 30 Jun 2025 08:01:55 +0200 Subject: [PATCH 10/62] gpio test wip --- tests/gpio/src/main.c | 48 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 41 insertions(+), 7 deletions(-) diff --git a/tests/gpio/src/main.c b/tests/gpio/src/main.c index 2ecb5aca07..b9a9c2d936 100644 --- a/tests/gpio/src/main.c +++ b/tests/gpio/src/main.c @@ -24,8 +24,8 @@ // -------------------------------------------------------------------- MACROS // TODO -#define TEST_CLOCK true -#define CLOCK_TEST_PORT HAL_PORT_NC +#define TEST_CLOCK false +#define CLOCK_TEST_PORT PORT_4 #define TEST_FLATTENER false @@ -38,7 +38,7 @@ #else #define PIN_TEST false #define PORT_TEST false -#define BUTTON_TEST false +#define BUTTON_TEST true #endif // TODO // Define port used for signaling errors. @@ -61,20 +61,24 @@ // TODO // Define port used for testing. -#define PORT_NAME HAL_PORT_NC // Example: GPIO_PORT_B +#define PORT_NAME PORT_4 // Example: GPIO_PORT_B #define PORT_MASK (port_size_t)0xFFFFFFFF #define PORT_READ_VALUE 0xAA #define SINGLE_LED_DELAY 300 // Delay LED single shift test. // TODO // Define pins used for testing digital in/out. -#define LED HAL_PIN_NC // Example: GPIO_PA0 -#define BUTTON HAL_PIN_NC // Example: GPIO_PB0 +#define LED GPIO_P409 // Example: GPIO_PA0 +#define BUTTON GPIO_P301 // Example: GPIO_PB0 // ----------------------------------------------------------------- VARIABLES static port_t test_port; // PORT driver context structure. static digital_in_t input_pin; // Digital input driver context structure. static digital_out_t output_pin; // Digital output driver context structure. static uint8_t port_counter = port_count_size; // Defined in CMakeLists.txt file. + +#define PWPR_REGISTER_BASE (*( volatile uint8_t * )0x40040D03UL) +#include "mcu.h" + // ----------------------------------------------------------------- USER CODE int main( void ) { /* Do not remove this line or clock might not be set correctly. */ @@ -82,11 +86,41 @@ int main( void ) { preinit(); #endif + + // // Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register. + // // PWPR_REGISTER_BASE &= ~0x80; // Clear B0WI bit + // R_PMISC->PWPR_b.B0WI = 0; + // // Set 1 to the PFSWE bit in the PWPR register. This enables writing to the PmnPFS register. + // // PWPR_REGISTER_BASE |= 0x40; // Set PFSWE bit + // R_PMISC->PWPR_b.PFSWE = 1; + + // // R_PFS->PORT[0].PIN[0].PmnPFS_b.PDR = 1; + // // R_PFS->PORT[0].PIN[0].PmnPFS_b.PMR = 0; + // // R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR = 1; + + // R_PFS->PORT[0].PIN[0].PmnPFS = 0x00000000; // GPIO mode + // R_PORT0->PDR_b.PDR0 = 1; // Direction: output + // R_PORT0->PODR_b.PODR0 = 0; // Initial state: low + // R_PORT0->PODR |= 1; + // while(1); + + // // Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register. + // R_PMISC->PWPR_b.PFSWE = 0; + // // Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register + // R_PMISC->PWPR_b.B0WI = 1; + volatile pin_name_t fetch_pin = hal_gpio_fetch_pin(LED); volatile port_name_t fetch_port = hal_gpio_fetch_port(LED); #if TEST_CLOCK - CLOCK_TEST( CLOCK_TEST_PORT ); + // CLOCK_TEST( CLOCK_TEST_PORT ); + port_init( &test_port, CLOCK_TEST_PORT, 0xFFFF, PIN_DIRECTION_DIGITAL_OUTPUT ); \ + while(1) { \ + port_write( &test_port, 0xFFFF ); \ + Delay_1sec(); \ + port_write( &test_port, 0x00 ); \ + Delay_1sec(); \ + } #endif #if TEST_FLATTENER From bfe5768078e450baab92be0fdf72cc1f8f7a4ba1 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Thu, 3 Jul 2025 11:46:38 +0200 Subject: [PATCH 11/62] I2C write initial --- tests/i2c/main.c | 245 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 245 insertions(+) diff --git a/tests/i2c/main.c b/tests/i2c/main.c index 15bc92bd52..f31d4668a9 100644 --- a/tests/i2c/main.c +++ b/tests/i2c/main.c @@ -1,3 +1,4 @@ +#if 0 // ------------------------------------------------------------------ INCLUDES /** @@ -221,3 +222,247 @@ int main( void ) { } // ----------------------------------------------------------------------- END + +#else +/* + * Simplified I2C Master Library (Polling, Repeated Start, 7/10-bit Addressing) + * For RA4M1 or compatible Renesas MCU + */ + +#include +#include +#include "mcu.h" // Replace with correct MCU register definitions + +#define I2C_MASTER_OK (0) +#define I2C_MASTER_ERR (-1) + +// User must define these macros appropriately +// #define IIC1_BASE (R_IIC1) +// #define IIC_ICCR1 (IIC1_BASE->ICCR1) +// #define IIC_ICCR2 (IIC1_BASE->ICCR2) +// #define IIC_ICMR3 (IIC1_BASE->ICMR3) +// #define IIC_ICDRT (IIC1_BASE->ICDRT) +// #define IIC_ICDRR (IIC1_BASE->ICDRR) +// #define IIC_ICSR2 (IIC1_BASE->ICSR2) +// #define IIC_ICSR1 (IIC1_BASE->ICSR1) +// #define IIC_ICFER (IIC1_BASE->ICFER) +// #define IIC_ICIER (IIC1_BASE->ICIER) +// #define IIC_ICSER (IIC1_BASE->ICSER) +// #define IIC_ICMR1 (IIC1_BASE->ICMR1) +// #define IIC_ICMR2 (IIC1_BASE->ICMR2) +// #define IIC_ICBRL (IIC1_BASE->ICBRL) +// #define IIC_ICBRH (IIC1_BASE->ICBRH) + +static void i2c_master_wait_for_tend(void) +{ + while (!(R_IIC1->ICSR2_b.TEND)) {} // TEND bit + R_IIC1->ICSR2 &= ~(1 << 6); // Clear TEND +} + +static void i2c_master_wait_for_txi(void) +{ + while (R_IIC1->ICSR2 & (1 << 7)) {} // Wait while no transmit data + R_IIC1->ICSR2 &= ~(1 << 7); +} + +static void i2c_master_wait_for_rxi(void) +{ + while (!(R_IIC1->ICSR2 & (1 << 5))) {} // RXI + R_IIC1->ICSR2 &= ~(1 << 5); +} + +static void i2c_master_send_start(void) +{ + R_IIC1->ICCR2 |= (1 << 1); // Set ST bit + while (!(R_IIC1->ICCR2 & (1 << 1))) {} // Wait for ST cleared +} + +static void i2c_master_send_stop(void) +{ + R_IIC1->ICCR2 |= (1 << 3); // Set SP bit + while (R_IIC1->ICCR2 & (1 << 3)) {} // Wait for SP cleared +} + +static void i2c_master_send_address(uint16_t address, bool read) +{ + if (address > 0x7F) { + // 10-bit address mode + uint8_t high = 0xF0 | ((address >> 7) & 0x06) | (read ? 1 : 0); + uint8_t low = address & 0xFF; + R_IIC1->ICDRT = high; + i2c_master_wait_for_tend(); + R_IIC1->ICDRT = low; + } else { + // 7-bit address mode + R_IIC1->ICDRT = (address << 1) | (read ? 1 : 0); + } + // i2c_master_wait_for_tend(); +} + +int i2c_master_init(uint32_t bitrate_hz) +{ + // Simplified fixed init + R_IIC1->ICCR1 = 0; // Stop I2C + + R_IIC1->ICMR1 = 0x00; + R_IIC1->ICMR2 = 0x00; + R_IIC1->ICMR3 = 0x00; + + R_IIC1->ICBRL = 20; // Tune these for bitrate + R_IIC1->ICBRH = 20; + + R_IIC1->ICFER = 0x77; + R_IIC1->ICIER = 0x00; + R_IIC1->ICCR1 = 0x80; // Enable I2C + + return I2C_MASTER_OK; +} + +int i2c_master_write(uint16_t address, const uint8_t *data, uint32_t length, bool send_stop) +{ + i2c_master_send_start(); + i2c_master_send_address(address, false); + + for (uint32_t i = 0; i < length; i++) { + R_IIC1->ICDRT = data[i]; + // i2c_master_wait_for_tend(); + } + + i2c_master_wait_for_tend(); + if (send_stop) { + i2c_master_send_stop(); + } + return I2C_MASTER_OK; +} + +int i2c_master_read(uint16_t address, uint8_t *data, uint32_t length, bool send_stop) +{ + i2c_master_send_start(); + i2c_master_send_address(address, true); + + for (uint32_t i = 0; i < length; i++) { + if (i == (length - 1)) { + R_IIC1->ICMR3 |= (1 << 2); // NACK + } + i2c_master_wait_for_rxi(); + data[i] = R_IIC1->ICDRR; + } + + i2c_master_wait_for_tend(); + if (send_stop) { + i2c_master_send_stop(); + } + return I2C_MASTER_OK; +} + +int main() { + #if 0 + // Enable IIC1 peripheral + R_MSTP->MSTPCRB &= ~(1U << 8); + __asm volatile("dsb"); + + // Configure IIC0 pins (SCL = P205, SDA = P206) + // === 1. Enable write to PFS registers === + R_PMISC->PWPR = 0x00; // Clear B0WI and PFSWE + R_PMISC->PWPR = 0x40; // Set PFSWE = 1, B0WI = 0 + + // === 2. Set pin functions === + // P205 ? IIC0_SCL (PSEL = 0x0F), PMR = 1 (peripheral) + // R_PFS->P205PFS = (0x0F << 24) | (1 << 16); // PSEL[4:0] = 0x0F, PMR = 1 + R_PFS->PORT[2].PIN[5].PmnPFS = (0x7 << 24) | (1 << 16); // PSEL[4:0] = 0x7, PMR = 1 + + // P206 ? IIC0_SDA (PSEL = 0x7), PMR = 1 (peripheral) + // R_PFS->P206PFS = (0x7 << 24) | (1 << 16); // PSEL[4:0] = 0x7, PMR = 1 + R_PFS->PORT[2].PIN[6].PmnPFS = (0x7 << 24) | (1 << 16); // PSEL[4:0] = 0x7, PMR = 1 + + // === 3. Disable write === + R_PMISC->PWPR = 0x80; // Lock with B0WI = 1 + + // Example data to write + uint8_t write_data[] = { 0x00, 0x10, 0xA5 }; // Example: register 0x10 = 0xA5 + uint8_t read_data[2] = {0}; + + // Initialize I2C with desired bitrate (100kHz for example) + i2c_master_init(100000); + + // Write data to device 0x50 (register + value) + i2c_master_write(0x50, write_data, sizeof(write_data), false); // No STOP ? repeated start + + // Read back 2 bytes starting from register 0x10 + i2c_master_read(0x50, read_data, 2, true); // STOP after read + + // You can now inspect read_data[0] and read_data[1] + while (1) + { + // Do nothing ? loop forever + } + + return 0; + #else + + // Enable IIC1 peripheral + R_MSTP->MSTPCRB &= ~(1U << 8); + __asm volatile("dsb"); + + // Pin initialization + R_PMISC->PWPR = 0x00; // Clear B0WI and PFSWE + R_PMISC->PWPR = 0x40; // Set PFSWE = 1, B0WI = 0 + + R_PFS->PORT[2].PIN[5].PmnPFS = (0x7 << 24) | (1 << 16); // PSEL[4:0] = 0x7, PMR = 1 + R_PFS->PORT[2].PIN[6].PmnPFS = (0x7 << 24) | (1 << 16); // PSEL[4:0] = 0x7, PMR = 1 + + R_PMISC->PWPR = 0x80; // Lock with B0WI = 1 + + // I2C initialization + R_IIC1->ICCR1_b.ICE = 0; // 1. Set the ICCR1.ICE bit set to 0 to set the SCLn and SDAn pins to the inactive state. + R_IIC1->ICCR1_b.IICRST = 1; // 2. Set the ICCR1.IICRST bit to 1 to initiate IIC reset + R_IIC1->ICCR1_b.ICE = 1; // 3. Set the ICCR1.ICE bit to 1 to initiate internal reset. + + // 4. Set the SARLy, SARUy, ICSER, ICMR1, ICBRH, and ICBRL registers + // (y = 0 to 2), and set the other registers as required. + R_IIC1->SAR[1].U_b.FS = 0; + R_IIC1->SAR[1].L_b.SVA = 0x50 << 1; + R_IIC1->ICSER = 0; + // Bit rate? + R_IIC1->ICBRL = 20; // Tune these for bitrate + R_IIC1->ICBRH = 20; + // Bit rate? + + // Set ICIER // HOW? + + // 5. When the required register settings are complete, set the ICCR1.IICRST bit to 0 to release the IIC reset. + R_IIC1->ICCR1_b.IICRST = 0; + + while(R_IIC1->ICCR2_b.BBSY); // Wait while the bus is busy + + R_IIC1->ICCR2_b.ST = 1; // Start condition + + // while(!(R_IIC1->ICSR2_b.NACKF)) { + if(R_IIC1->ICSR2_b.TDRE) { + R_IIC1->ICDRT = 0x50 << 1; + } + if(R_IIC1->ICSR2_b.NACKF) // No slave device recognized + R_IIC1->ICCR2_b.SP = 1; // Stop condition + + uint8_t dat = 50; + while(dat) + while(R_IIC1->ICSR2_b.TDRE) + R_IIC1->ICDRT = dat--; + + while(!(R_IIC1->ICSR2_b.TEND)); + + // } + + R_IIC1->ICSR2_b.STOP = 0; + R_IIC1->ICCR2_b.SP = 1; + + while(!(R_IIC1->ICSR2_b.STOP)); + + R_IIC1->ICSR2_b.NACKF = 1; + R_IIC1->ICSR2_b.STOP = 0; + + return 0; + #endif +} + +#endif \ No newline at end of file From 0e959505f9993c3a2179ce22348d04fc45525153 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Mon, 7 Jul 2025 16:32:01 +0200 Subject: [PATCH 12/62] I2C update --- .../RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 7 +- .../renesas/include/hal_ll_target_names.h | 2 +- .../implementation_1/hal_ll_i2c_pin_map.h | 235 +--------------- .../gpio/implementation_1/hal_ll_gpio_port.c | 21 +- .../i2c/implementation_1/hal_ll_i2c_master.c | 254 ++++++++++++++++-- 5 files changed, 268 insertions(+), 251 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h index 99b26fc22f..8e6694e784 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -51,8 +51,13 @@ //EOF ADC //I2C +#define I2C_MODULE_0 (1) +#define I2C_MODULE_1 (2) -#define I2C_MODULE_COUNT 3 +#define I2C0_SCL_P205 +#define I2C0_SDA_P206 + +#define I2C_MODULE_COUNT (2) //EOF I2C //UART diff --git a/targets/arm/mikroe/renesas/include/hal_ll_target_names.h b/targets/arm/mikroe/renesas/include/hal_ll_target_names.h index 559ced4f2a..153d7befc1 100644 --- a/targets/arm/mikroe/renesas/include/hal_ll_target_names.h +++ b/targets/arm/mikroe/renesas/include/hal_ll_target_names.h @@ -59,7 +59,7 @@ typedef uint16_t hal_ll_gpio_mask_t; typedef uint8_t hal_ll_pin_name_t; typedef uint8_t hal_ll_port_name_t; typedef uint16_t hal_ll_port_size_t; -typedef uint32_t hal_ll_base_addr_t; +typedef uint8_t hal_ll_base_addr_t; typedef uint8_t hal_ll_channel_t; typedef int32_t hal_ll_err_t; diff --git a/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h index 3bccd109c5..197cd387d6 100644 --- a/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h +++ b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h @@ -56,34 +56,10 @@ extern "C"{ #define hal_ll_i2c_module_num(_module_num) (_module_num - 1) #ifdef I2C_MODULE_0 -static const hal_ll_base_addr_t HAL_LL_I2C0_BASE_ADDR = 0x40020000; +static const uint32_t HAL_LL_I2C0_BASE_ADDR = 0x40053000UL; #endif #ifdef I2C_MODULE_1 -static const hal_ll_base_addr_t HAL_LL_I2C1_BASE_ADDR = 0x40021000; -#endif -#ifdef I2C_MODULE_2 -static const hal_ll_base_addr_t HAL_LL_I2C2_BASE_ADDR = 0x40022000; -#endif -#ifdef I2C_MODULE_3 -static const hal_ll_base_addr_t HAL_LL_I2C3_BASE_ADDR = 0x40023000; -#endif -#ifdef I2C_MODULE_4 -static const hal_ll_base_addr_t HAL_LL_I2C4_BASE_ADDR = 0x400C0000; -#endif -#ifdef I2C_MODULE_5 -static const hal_ll_base_addr_t HAL_LL_I2C5_BASE_ADDR = 0x400C1000; -#endif -#ifdef I2C_MODULE_6 -static const hal_ll_base_addr_t HAL_LL_I2C6_BASE_ADDR = 0x400C2000; -#endif -#ifdef I2C_MODULE_7 -static const hal_ll_base_addr_t HAL_LL_I2C7_BASE_ADDR = 0x400C3000; -#endif -#ifdef I2C_MODULE_8 -static const hal_ll_base_addr_t HAL_LL_I2C8_BASE_ADDR = 0x400B8000; -#endif -#ifdef I2C_MODULE_9 -static const hal_ll_base_addr_t HAL_LL_I2C9_BASE_ADDR = 0x400B9000; +static const uint32_t HAL_LL_I2C1_BASE_ADDR = 0x40053100UL; #endif /*!< @brief I2C pin structure. */ @@ -96,215 +72,18 @@ typedef struct { /*!< I2C SCL Pins. */ static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = { - #ifdef I2C0_SCL_PB2_AF3 - {GPIO_PB2, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_0), 3}, - #endif - #ifdef I2C1_SCL_PA6_AF3 - {GPIO_PA6, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 3}, - #endif - #ifdef I2C1_SCL_PG4_AF3 - {GPIO_PG4, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 3}, - #endif - #ifdef I2C2_SCL_PE4_AF3 - {GPIO_PE4, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 3}, - #endif - #ifdef I2C3_SCL_PD0_AF3 - {GPIO_PD0, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 3}, - #endif - #ifdef I2C3_SCL_PG0_AF3 - {GPIO_PG0, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 3}, - #endif - #ifdef I2C4_SCL_PG2_AF3 - {GPIO_PG2, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, - #endif - #ifdef I2C5_SCL_PB6_AF3 - {GPIO_PB6, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 3}, - #endif - #ifdef I2C2_SCL_PF6_AF3 - {GPIO_PF6, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 3}, - #endif - #ifdef I2C5_SCL_PG6_AF3 - {GPIO_PG6, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 3}, - #endif - #ifdef I2C0_SCL_PB2_AF2 - {GPIO_PB2, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_0), 2}, - #endif - #ifdef I2C1_SCL_PG0_AF2 - {GPIO_PG0, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 2}, - #endif - #ifdef I2C2_SCL_PG2_AF2 - {GPIO_PG2, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, - #endif - #ifdef I2C2_SCL_PL1_AF2 - {GPIO_PL1, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, - #endif - #ifdef I2C2_SCL_PN5_AF3 - {GPIO_PN5, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 3}, - #endif - #ifdef I2C2_SCL_PP5_AF2 - {GPIO_PP5, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, - #endif - #ifdef I2C3_SCL_PG4_AF2 - {GPIO_PG4, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, - #endif - #ifdef I2C3_SCL_PK4_AF2 - {GPIO_PK4, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, - #endif - #ifdef I2C4_SCL_PG6_AF2 - {GPIO_PG6, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 2}, - #endif - #ifdef I2C4_SCL_PK6_AF2 - {GPIO_PK6, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 2}, - #endif - #ifdef I2C5_SCL_PB0_AF2 - {GPIO_PB0, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 2}, - #endif - #ifdef I2C5_SCL_PB4_AF2 - {GPIO_PB4, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 2}, - #endif - #ifdef I2C6_SCL_PA6_AF2 - {GPIO_PA6, HAL_LL_I2C6_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_6), 2}, - #endif - #ifdef I2C7_SCL_PA4_AF2 - {GPIO_PA4, HAL_LL_I2C7_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_7), 2}, - #endif - #ifdef I2C7_SCL_PD0_AF2 - {GPIO_PD0, HAL_LL_I2C7_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_7), 2}, - #endif - #ifdef I2C8_SCL_PA2_AF2 - {GPIO_PA2, HAL_LL_I2C8_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_8), 2}, - #endif - #ifdef I2C8_SCL_PD2_AF2 - {GPIO_PD2, HAL_LL_I2C8_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_8), 2}, - #endif - #ifdef I2C9_SCL_PA0_AF2 - {GPIO_PA0, HAL_LL_I2C9_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_9), 2}, - #endif - #ifdef I2C1_SCL_PR0_AF2 - {GPIO_PR0, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 2}, - #endif - #ifdef I2C2_SCL_PR2_AF2 - {GPIO_PR2, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, - #endif - #ifdef I2C3_SCL_PR4_AF2 - {GPIO_PR4, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, - #endif - #ifdef I2C4_SCL_PR6_AF2 - {GPIO_PR6, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 2}, - #endif - #ifdef I2C6_SCL_PB6_AF2 - {GPIO_PB6, HAL_LL_I2C6_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_6), 2}, - #endif - #ifdef I2C9_SCL_PE6_AF2 - {GPIO_PE6, HAL_LL_I2C9_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_9), 2}, + #ifdef I2C0_SCL_P205 + {GPIO_P205, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 7}, #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; /*!< I2C SDA Pins. */ static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = { - #ifdef I2C0_SDA_PB3_AF3 - {GPIO_PB3, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_0), 3}, - #endif - #ifdef I2C1_SDA_PA7_AF3 - {GPIO_PA7, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 3}, - #endif - #ifdef I2C1_SDA_PG5_AF3 - {GPIO_PG5, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 3}, - #endif - #ifdef I2C2_SDA_PE5_AF3 - {GPIO_PE5, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 3}, - #endif - #ifdef I2C3_SDA_PD1_AF3 - {GPIO_PD1, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 3}, - #endif - #ifdef I2C3_SDA_PG1_AF3 - {GPIO_PG1, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 3}, - #endif - #ifdef I2C4_SDA_PG3_AF3 - {GPIO_PG3, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, - #endif - #ifdef I2C5_SDA_PB7_AF3 - {GPIO_PB7, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 3}, - #endif - #ifdef I2C2_SDA_PF7_AF3 - {GPIO_PF7, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 3}, - #endif - #ifdef I2C5_SDA_PG7_AF3 - {GPIO_PG7, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 3}, - #endif - #ifdef I2C0_SDA_PB3_AF2 - {GPIO_PB3, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_0), 2}, - #endif - #ifdef I2C1_SDA_PG1_AF2 - {GPIO_PG1, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 2}, - #endif - #ifdef I2C2_SDA_PG3_AF2 - {GPIO_PG3, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, - #endif - #ifdef I2C2_SDA_PL0_AF2 - {GPIO_PL0, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, - #endif - #ifdef I2C2_SDA_PN4_AF3 - {GPIO_PN4, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 3}, - #endif - #ifdef I2C3_SDA_PG5_AF2 - {GPIO_PG5, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, - #endif - #ifdef I2C3_SDA_PK5_AF2 - {GPIO_PK5, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, - #endif - #ifdef I2C4_SDA_PG7_AF2 - {GPIO_PG7, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 2}, - #endif - #ifdef I2C4_SDA_PK7_AF2 - {GPIO_PK7, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 2}, - #endif - #ifdef I2C5_SDA_PB1_AF2 - {GPIO_PB1, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 2}, - #endif - #ifdef I2C5_SDA_PB5_AF2 - {GPIO_PB5, HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_5), 2}, - #endif - #ifdef I2C6_SDA_PA7_AF2 - {GPIO_PA7, HAL_LL_I2C6_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_6), 2}, - #endif - #ifdef I2C7_SDA_PA5_AF2 - {GPIO_PA5, HAL_LL_I2C7_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_7), 2}, - #endif - #ifdef I2C7_SDA_PD1_AF2 - {GPIO_PD1, HAL_LL_I2C7_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_7), 2}, - #endif - #ifdef I2C8_SDA_PA3_AF2 - {GPIO_PA3, HAL_LL_I2C8_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_8), 2}, - #endif - #ifdef I2C8_SDA_PD3_AF2 - {GPIO_PD3, HAL_LL_I2C8_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_8), 2}, - #endif - #ifdef I2C9_SDA_PA1_AF2 - {GPIO_PA1, HAL_LL_I2C9_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_9), 2}, - #endif - #ifdef I2C1_SDA_PR1_AF2 - {GPIO_PR1, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 2}, - #endif - #ifdef I2C2_SDA_PP6_AF2 - {GPIO_PP6, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, - #endif - #ifdef I2C2_SDA_PR3_AF2 - {GPIO_PR3, HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, - #endif - #ifdef I2C3_SDA_PR5_AF2 - {GPIO_PR5, HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, - #endif - #ifdef I2C4_SDA_PR7_AF2 - {GPIO_PR7, HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), 2}, - #endif - #ifdef I2C6_SDA_PB7_AF2 - {GPIO_PB7, HAL_LL_I2C6_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_6), 2}, - #endif - #ifdef I2C9_SDA_PE7_AF2 - {GPIO_PE7, HAL_LL_I2C9_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_9), 2}, + #ifdef I2C0_SDA_P206 + {GPIO_P206, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 7}, #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} diff --git a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c index 03067ad103..1df40970cf 100644 --- a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c @@ -94,7 +94,7 @@ #endif #define PWPR_REGISTER_BASE (* ( volatile uint8_t * )0x40040D03UL) -#define PFS_REGISTER_ADDR (0x4004D000UL) +#define PFS_REGISTER_ADDR (0x40040800UL) #define PFS_PSEL_MASK (0x1F000000UL) /*!< @brief GPIO PORT array */ @@ -274,6 +274,8 @@ static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t conf } } +#include "mcu.h" + static void hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) { uint8_t pin_index; hal_ll_pin_name_t pin_name; @@ -286,15 +288,24 @@ static void hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32 port_name = hal_ll_gpio_port_index( module_pin & 0xFF ); - port_ptr = ( hal_ll_gpio_base_handle_t* )hal_ll_gpio_port_base( port_name ); - hal_ll_gpio_config( (uint32_t *)&port_ptr, hal_ll_gpio_pin_mask( pin_index ), module_config ); + // Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register. + PWPR_REGISTER_BASE &= ~0x80; // Clear B0WI bit + // Set 1 to the PFSWE bit in the PWPR register. This enables writing to the PmnPFS register. + PWPR_REGISTER_BASE |= 0x40; // Set PFSWE bit + if ( true == state ) { - port_ptr->port[port_name].pin[pin_index].pmnpfs_b.psel |= module_pin & PFS_PSEL_MASK; + port_ptr->port[port_name].pin[pin_index].pmnpfs_b.psel = (( module_pin & 0xFF00 ) >> 8 ); + port_ptr->port[port_name].pin[pin_index].pmnpfs_b.pmr = 1; // Peripheral mode } else { - port_ptr->port[port_name].pin[pin_index].pmnpfs_b.psel &= ~( module_pin & PFS_PSEL_MASK ); + port_ptr->port[port_name].pin[pin_index].pmnpfs_b.psel &= 0; } + + // Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register. + PWPR_REGISTER_BASE &= ~0x40; // Set PFSWE bit + // Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register + PWPR_REGISTER_BASE |= 0x80; // Set B0WI bit } // ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c index 120ead4a59..b9fe138af4 100644 --- a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c @@ -44,6 +44,7 @@ #include "hal_ll_i2c_master.h" #include "hal_ll_i2c_pin_map.h" #include "delays.h" +#include "mcu.h" // TODO Esma /*!< @brief Local handle list */ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; @@ -61,6 +62,10 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU #define HAL_LL_I2C_AF_CONFIG 0xFF // TODO Esma +/*!< @brief Bit positions and masks */ +#define HAL_LL_I2C_ICCR2_BBSY (7) +#define HAL_LL_I2C_ICCR2_ST (1) + /*!< @brief Default I2C bit-rate if no speed is set */ #define HAL_LL_I2C_MASTER_SPEED_100K (100000UL) #define HAL_LL_I2C_MASTER_SPEED_400K (400000UL) @@ -71,12 +76,31 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU /*!< @brief I2C register structure */ typedef struct { - hal_ll_base_addr_t TODO; + hal_ll_base_addr_t iccr1; // IIC0.ICCR1 4005 3000h, IIC1.ICCR1 4005 3100h + hal_ll_base_addr_t iccr2; // IIC0.ICCR2 4005 3001h, IIC1.ICCR2 4005 3101h + hal_ll_base_addr_t icmr1; // IIC0.ICCR2 4005 3002h, IIC1.ICCR2 4005 3102h + hal_ll_base_addr_t icmr2; // IIC0.ICCR2 4005 3003h, IIC1.ICCR2 4005 3103h + hal_ll_base_addr_t icmr3; // IIC0.ICCR2 4005 3004h, IIC1.ICCR2 4005 3104h + hal_ll_base_addr_t icfer; // IIC0.ICCR2 4005 3005h, IIC1.ICCR2 4005 3105h + hal_ll_base_addr_t icser; // IIC0.ICCR2 4005 3006h, IIC1.ICCR2 4005 3106h + hal_ll_base_addr_t icier; // IIC0.ICCR2 4005 3007h, IIC1.ICCR2 4005 3107h + hal_ll_base_addr_t icsr1; // IIC0.ICCR2 4005 3008h, IIC1.ICCR2 4005 3108h + hal_ll_base_addr_t icsr2; // IIC0.ICCR2 4005 3009h, IIC1.ICCR2 4005 3109h + hal_ll_base_addr_t sarl[3]; // ? + hal_ll_base_addr_t saru[3]; // ? + hal_ll_base_addr_t icbrl; // IIC0.ICCR2 4005 3010h, IIC1.ICCR2 4005 3110h + hal_ll_base_addr_t icbrh; // IIC0.ICCR2 4005 3011h, IIC1.ICCR2 4005 3111h + hal_ll_base_addr_t icdrt; // IIC0.ICCR2 4005 3012h, IIC1.ICCR2 4005 3112h + hal_ll_base_addr_t icdrr; // IIC0.ICCR2 4005 3013h, IIC1.ICCR2 4005 3113h + // hal_ll_base_addr_t icdrs; // ? + hal_ll_base_addr_t reserved[2]; + hal_ll_base_addr_t icwur; // IIC0.ICCR2 4005 3016h // ? , IIC1.ICCR2 4005 3109h + hal_ll_base_addr_t icwur2; // IIC0.ICCR2 4005 3017h // ? , IIC1.ICCR2 4005 3109h } hal_ll_i2c_base_handle_t; /*!< @brief I2C hw specific structure */ typedef struct { - hal_ll_base_addr_t base; + uint32_t base; hal_ll_pin_name_t module_index; hal_ll_i2c_pins_t pins; uint32_t speed; @@ -127,10 +151,10 @@ typedef enum { // ------------------------------------------------------------------ VARIABLES static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[ I2C_MODULE_COUNT + 1 ] = { #ifdef I2C_MODULE_0 - {HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + {0x40053000UL, hal_ll_i2c_module_num( I2C_MODULE_0 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, #endif #ifdef I2C_MODULE_1 - {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + {0x40053100UL, hal_ll_i2c_module_num( I2C_MODULE_1 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, #endif #ifdef I2C_MODULE_2 {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_2 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, @@ -378,39 +402,147 @@ hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pi } hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { - return 0; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_i2c_master_handle = ( handle_t * )&hal_ll_i2c_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; } hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { - return 0; + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + + low_level_handle->init_ll_state = false; + hal_ll_i2c_hw_specifics_map_local->speed = hal_ll_i2c_get_speed( speed ); + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; } void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { - return; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( HAL_LL_MODULE_ERROR != hal_ll_i2c_hw_specifics_map_local->base ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } } void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { - return; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( HAL_LL_MODULE_ERROR != hal_ll_i2c_hw_specifics_map_local->base ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } } hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { - return 0; + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); } hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { - return 0; + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); } hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { - return 0; + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + + if( NULL != hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( NULL != hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; } void hal_ll_i2c_master_close( handle_t *handle ) { - return; + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( NULL != low_level_handle->hal_ll_i2c_master_handle ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_local, true ); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_local, false ); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } } // ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS - static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ){ + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + uint16_t time_counter = map->timeout; + + // while(R_IIC1->ICCR2_b.BBSY); // Wait while the bus is busy + // provera = R_IIC1->ICCR2; + // Delay_100ms(); + // provera = hal_ll_hw_reg->iccr2; + while( check_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_BBSY )); + + // R_IIC1->ICCR2_b.ST = 1; // Start condition + set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_ST ); + + while (!R_IIC1->ICSR2_b.TDRE); // Wait until transmit data register is empty + + R_IIC1->ICDRT = 0x50 << 1; // Write the address + + while(!(R_IIC1->ICSR2_b.TDRE)); + + if(R_IIC1->ICSR2_b.NACKF) // No slave device recognized + R_IIC1->ICCR2_b.SP = 1; // Stop condition + + uint8_t dat = 50; + for( uint8_t i = 0; i < len_write_data; i++ ) + while(R_IIC1->ICSR2_b.TDRE) { + R_IIC1->ICDRT = write_data_buf[i]; + } + + while(!(R_IIC1->ICSR2_b.TEND)); + + R_IIC1->ICSR2_b.STOP = 0; + R_IIC1->ICCR2_b.SP = 1; + + while(!(R_IIC1->ICSR2_b.STOP)); + + R_IIC1->ICSR2_b.NACKF = 1; + R_IIC1->ICSR2_b.STOP = 0; + return 0; } @@ -439,7 +571,12 @@ static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_speci } static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { - return; + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; } static uint32_t hal_ll_i2c_get_speed( uint32_t bit_rate ) { @@ -447,11 +584,58 @@ static uint32_t hal_ll_i2c_get_speed( uint32_t bit_rate ) { } static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { - return 0; + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / (sizeof( hal_ll_i2c_master_handle_register_t )); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if ( hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[ hal_ll_module_count ].base ) { + return &hal_ll_i2c_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_i2c_hw_specifics_map[ hal_ll_module_error ]; } static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { - return 0; + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } } static bool hal_ll_i2c_master_is_idle( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { @@ -467,6 +651,44 @@ static void hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { } static void hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + // Enable IIC1 peripheral + R_MSTP->MSTPCRB &= ~(1U << 8); + __asm volatile("dsb"); + + // Pin initialization + // R_PMISC->PWPR = 0x00; // Clear B0WI and PFSWE + // R_PMISC->PWPR = 0x40; // Set PFSWE = 1, B0WI = 0 + + // R_PFS->PORT[2].PIN[5].PmnPFS = (0x7 << 24) | (1 << 16); // PSEL[4:0] = 0x7, PMR = 1 + // R_PFS->PORT[2].PIN[6].PmnPFS = (0x7 << 24) | (1 << 16); // PSEL[4:0] = 0x7, PMR = 1 + + // R_PMISC->PWPR = 0x80; // Lock with B0WI = 1 + + // I2C initialization + R_IIC1->ICCR1_b.ICE = 0; // 1. Set the ICCR1.ICE bit set to 0 to set the SCLn and SDAn pins to the inactive state. + R_IIC1->ICCR1_b.IICRST = 1; // 2. Set the ICCR1.IICRST bit to 1 to initiate IIC reset + R_IIC1->ICCR1_b.ICE = 1; // 3. Set the ICCR1.ICE bit to 1 to initiate internal reset. + + // 4. Set the SARLy, SARUy, ICSER, ICMR1, ICBRH, and ICBRL registers + // (y = 0 to 2), and set the other registers as required. + volatile uint8_t device_addr = 0x50; + R_IIC1->SAR[1].L_b.SVA = device_addr << 1; + R_IIC1->SAR[1].U_b.FS = 0; + Delay_ms(100); + R_IIC1->ICSER = 0; + // Bit rate - fixed for 32MHz clock and 100kbps + R_IIC1->ICMR1_b.CKS = 3; + R_IIC1->ICFER_b.SCLE = 1; + R_IIC1->ICFER_b.NFE = 1; + R_IIC1->ICBRL = 0xF2; // Tune these for bitrate + R_IIC1->ICBRH = 0xF0; + + + // Set ICIER // HOW? + + // 5. When the required register settings are complete, set the ICCR1.IICRST bit to 0 to release the IIC reset. + R_IIC1->ICCR1_b.IICRST = 0; + return; } From 4ab3baf7880cde462a7370206aafd6e4f3d37932 Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Thu, 10 Jul 2025 16:26:18 +0200 Subject: [PATCH 13/62] Added initial UART implementation -> RX works --- CMakeLists.txt | 2 +- tests/CMakeLists.txt | 42 +++++++------- tests/renesas/src/main.c | 119 ++++++++++++++++++++++++++++++--------- 3 files changed, 115 insertions(+), 48 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 6d64bb8250..13ee6da2c5 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -56,8 +56,8 @@ if (NOT ${IS_BARE_METAL}) add_subdirectory(thirdparty) endif() -if(${MSDK_TEST_EXAMPLES} MATCHES "true") add_subdirectory(tests) +if(${MSDK_TEST_EXAMPLES} MATCHES "true") endif() ## Deploy build is used for testing compiler specific issues. diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index aa5a1ac302..8ae42e1322 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -17,14 +17,14 @@ if (${_MSDK_BOARD_NAME_} MATCHES "^MIKROMEDIA(.+)$") endif() add_subdirectory(gpio) -add_subdirectory(button_simulation) +# add_subdirectory(button_simulation) add_subdirectory(renesas) ## 8K Flash and 2K RAM minimum for this test. memory_sdk_test_check(memory_issue 8192 2048) if (${memory_issue} STREQUAL "FALSE") - add_subdirectory(adc) + # add_subdirectory(adc) else() message(INFO ": ${MCU_NAME} does not have enough memory for \"adc\" test.") endif() @@ -33,7 +33,7 @@ endif() memory_sdk_test_check(memory_issue 8192 2048) if (${memory_issue} STREQUAL "FALSE") - add_subdirectory(i2c) + # add_subdirectory(i2c) else() message(INFO ": ${MCU_NAME} does not have enough memory for \"i2c\" test.") endif() @@ -42,7 +42,7 @@ endif() memory_sdk_test_check(memory_issue 8192 4096) if (${memory_issue} STREQUAL "FALSE") - add_subdirectory(pwm) + # add_subdirectory(pwm) else() message(INFO ": ${MCU_NAME} does not have enough memory for \"pwm\" test.") endif() @@ -51,7 +51,7 @@ endif() memory_sdk_test_check(memory_issue 8192 2048) if (${memory_issue} STREQUAL "FALSE") - add_subdirectory(spi) + # add_subdirectory(spi) else() message(INFO ": ${MCU_NAME} does not have enough memory for \"spi\" test.") endif() @@ -60,7 +60,7 @@ endif() memory_sdk_test_check(memory_issue 8192 4096) if (${memory_issue} STREQUAL "FALSE") - add_subdirectory(uart) + # add_subdirectory(uart) else() message(INFO ": ${MCU_NAME} does not have enough memory for \"uart\" test.") endif() @@ -68,13 +68,13 @@ endif() if (NOT _MSDK_DIP_SOCKET_TYPE_) if (_HAS_MIKROBUS_) if (${_HAS_MIKROBUS_} STREQUAL TRUE) - add_subdirectory(mikrobus) + # add_subdirectory(mikrobus) endif() endif() endif() if (${_MSDK_BOARD_NAME_} MATCHES "CLICKER") - add_subdirectory(clicker_buttons) + # add_subdirectory(clicker_buttons) endif() ## Initial mikroSDK 2.9.0 release shall only @@ -88,7 +88,7 @@ if(${TOOLCHAIN_LANGUAGE} STREQUAL "GNU") if((${has_usb} STREQUAL "true") AND (${has_usb_interrupts} STREQUAL "true")) check_usb_requirements(memory_requirements_passed) if(${memory_requirements_passed} STREQUAL "true") - add_subdirectory(usb) + # add_subdirectory(usb) endif() endif() endif() @@ -99,7 +99,7 @@ if(${TOOLCHAIN_ID} STREQUAL "gcc_arm_none_eabi" OR ${TOOLCHAIN_ID} STREQUAL "mch if(${has_eth} STREQUAL "true") check_eth_requirements(memory_requirements_passed) if(${memory_requirements_passed} STREQUAL "true") - add_subdirectory(ethernet) + # add_subdirectory(ethernet) endif() endif() endif() @@ -110,15 +110,15 @@ memory_sdk_test_check(memory_issue 12288 2048) find_package(MikroSDK.Driver.CAN) if(MikroSDK.Driver.CAN\_FOUND) if (${memory_issue} STREQUAL "FALSE") - add_subdirectory(can) + # add_subdirectory(can) else() message(INFO ": ${MCU_NAME} does not have enough memory for \"can\" test.") endif() endif() -add_subdirectory(one_wire) +# add_subdirectory(one_wire) -add_subdirectory(lcd) +# add_subdirectory(lcd) if (_MSDK_TFT_BOARD_) ## MikroE GL @@ -126,22 +126,22 @@ if (_MSDK_TFT_BOARD_) if (MikroSDK.GraphicLibrary\_FOUND) find_package(Components.TftBoard8) if (Components.TftBoard8\_FOUND) - add_subdirectory(gl) + # add_subdirectory(gl) endif() endif() ## LVGL if(${TOOLCHAIN_LANGUAGE} STREQUAL "GNU") - add_subdirectory(lvgl) + # add_subdirectory(lvgl) endif() endif() if (clickTests) - add_subdirectory(clicks) + # add_subdirectory(clicks) endif() if (tftTests) if(tftJigTest) - add_subdirectory(tft_jig) + # add_subdirectory(tft_jig) endif() endif() @@ -151,7 +151,7 @@ memory_sdk_test_check(memory_issue 12288 2048) find_package(MikroSDK.Driver.DMA) if(MikroSDK.Driver.DMA\_FOUND) if (${memory_issue} STREQUAL "FALSE") - add_subdirectory(dma) + # add_subdirectory(dma) else() message(INFO ": ${MCU_NAME} does not have enough memory for \"dma\" test.") endif() @@ -159,12 +159,12 @@ endif() check_rtc(has_rtc) if(${has_rtc} STREQUAL "true") - add_subdirectory(rtc) + # add_subdirectory(rtc) endif() memory_test_check(enough_memory) if(${enough_memory} STREQUAL "true") - add_subdirectory(file_system) + # add_subdirectory(file_system) endif() -add_subdirectory(sprint) +# add_subdirectory(sprint) diff --git a/tests/renesas/src/main.c b/tests/renesas/src/main.c index 05b7941b2a..235bb986b3 100644 --- a/tests/renesas/src/main.c +++ b/tests/renesas/src/main.c @@ -7,24 +7,100 @@ #include "preinit.h" #endif -#include "delays.h" #include "mcu.h" +#define PWPR_REGISTER_BASE (* ( volatile uint8_t * )0x40040D03UL) -// -------------------------------------------------------------------- MACROS +void uart_init(void) +{ + // 1. Enable SCI0 in the Module Stop Register + R_SYSTEM->PRCR = 0xa502; + R_MSTP->MSTPCRB_b.MSTPB31 = 0; // Enable SCI0 (MSTPB31 = 0) + R_SYSTEM->PRCR = 0xa500; + + // 2. Configure P411 as TXD0 and P410 as RXD0 via IOPORT + // TXD0 (P411) = Peripheral function: 0x0A + // RXD0 (P410) = Peripheral function: 0x0A + + // Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register. + PWPR_REGISTER_BASE &= ~0x80; // Clear B0WI bit + // Set 1 to the PFSWE bit in the PWPR register. This enables writing to the PmnPFS register. + PWPR_REGISTER_BASE |= 0x40; // Set PFSWE bit + + // Write PFS registers directly (PFS write-protected by default) + // ra_gpio_config(pin, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_LOW_POWER, af); + R_PFS->PORT[4].PIN[11].PmnPFS_b.PMR = 0; // TXD0 + R_PFS->PORT[4].PIN[11].PmnPFS_b.PDR = 1; // TXD0 + R_PFS->PORT[4].PIN[11].PmnPFS_b.PSEL = 0x04; // TXD0 + R_PFS->PORT[4].PIN[11].PmnPFS_b.PMR = 1; // TXD0 + + // ra_gpio_config(pin, GPIO_MODE_INPUT, GPIO_PULLUP, GPIO_LOW_POWER, af); + R_PFS->PORT[4].PIN[10].PmnPFS_b.PMR = 0; // RXD0 + R_PFS->PORT[4].PIN[10].PmnPFS_b.PCR = 1; // RXD0 + R_PFS->PORT[4].PIN[10].PmnPFS_b.PSEL = 0x04; // RXD0 + R_PFS->PORT[4].PIN[10].PmnPFS_b.PMR = 1; // RXD0 + + // Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register. + PWPR_REGISTER_BASE &= ~0x40; // Set PFSWE bit + // Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register + PWPR_REGISTER_BASE |= 0x80; // Set B0WI bit + + // 3. Initialize SCI1 registers + + // Disable TE and RE + R_SCI0->SCR = 0x00; + while (R_SCI0->SCR != 0); + + R_SCI0->SMR = 0x00; + R_SCI0->SCMR = 0xF3; + R_SCI0->SEMR = 0xC0; + + // R_SCI0->FCR_b.FM = 1; + // R_SCI0->FCR_b.TFRST = 1; + // R_SCI0->FCR_b.RFRST = 1; + // R_SCI0->FCR_b.TTRG = 0; + // R_SCI0->FCR_b.RTRG = 0; + // R_SCI0->FCR_b.RSTRG = 0; -// ----------------------------------------------------------------- VARIABLES + R_SCI0->SCR_b.CKE = 0x00; + R_SCI0->SMR_b.CKS = 0x00; + R_SCI0->BRR = 106; + + // Async, 8N1, PCLK/1 + -// ----------------------------------------------------------------- USER CODE -// Initialize LED pin (P302) -void port_init(void) + // R_SCI0->FCR_b.TFRST = 0; + // R_SCI0->FCR_b.RFRST = 0; + + + // Delay at least 1 bit time (~8.6 us at 115200 baud) + // for (volatile int i = 0; i < 1000; ++i) { __asm__("nop"); } + + // Enable transmit and receive + R_SCI0->SCR_b.RE = 0x01; + R_SCI0->SCR_b.TE = 0x01; +} + +void uart_send_char(char c) { - // Configure P302 as GPIO output - R_PFS->PORT[3].PIN[2].PmnPFS = 0x00000000; // GPIO mode + // Wait until there is space in the transmit FIFO (TDFE = 1) + while (!(R_SCI0->SSR_b.TDRE)); + R_SCI0->TDR = c; - R_PORT3->PDR_b.PDR2 = 1; // Direction: output + // Clear TDFE by writing 0 + R_SCI0->SSR_b.TDRE = 0; +} + +char uart_receive_char(void) +{ + // Wait until there is data in the receive FIFO (RDF = 1) + while (!(R_SCI0->SSR_b.RDRF)); + char c = R_SCI0->RDR; - R_PORT3->PODR_b.PODR2 = 0; // Initial state: low + // Clear RDF by writing 0 + R_SCI0->SSR_b.RDRF = 0; + + return c; } int main( void ) { @@ -33,26 +109,17 @@ int main( void ) { preinit(); #endif - // Initialize GPIO port - port_init(); + uart_init(); - R_PFS->PORT[2].PIN[5].PmnPFS = 0; - R_PFS->PORT[2].PIN[5].PmnPFS_b.PMR = 1; // peripheral - R_PFS->PORT[2].PIN[5].PmnPFS_b.PDR = 1; // output - R_PFS->PORT[2].PIN[5].PmnPFS_b.PSEL = 9; // clkout - R_PFS->PORT[2].PIN[5].PmnPFS_b.NCODR = 0; // CMOS - R_PFS->PORT[2].PIN[5].PmnPFS_b.DSCR = 1; // middle drive + uart_send_char('H'); + uart_send_char('i'); + uart_send_char('\r'); + uart_send_char('\n'); - // Main loop while (1) { - R_PORT3->PODR |= (1 << 2); // Set P302 high - // for (volatile uint32_t i = 0; i < 10000; i++) __asm("NOP"); - Delay_ms(1000); - - R_PORT3->PODR &= ~(1 << 2); // Set P302 low - // for (volatile uint32_t i = 0; i < 10000; i++) __asm("NOP"); - Delay_ms(1000); + char c = uart_receive_char(); + uart_send_char(c); // Echo received char } return 0; From bd815a9cecd0c273087d1baf7b8f0395efd11817 Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Thu, 10 Jul 2025 16:29:05 +0200 Subject: [PATCH 14/62] Polling UART works -> interrupts TODO --- tests/renesas/src/main.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/renesas/src/main.c b/tests/renesas/src/main.c index 235bb986b3..d7b6280c47 100644 --- a/tests/renesas/src/main.c +++ b/tests/renesas/src/main.c @@ -29,7 +29,7 @@ void uart_init(void) // Write PFS registers directly (PFS write-protected by default) // ra_gpio_config(pin, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_LOW_POWER, af); R_PFS->PORT[4].PIN[11].PmnPFS_b.PMR = 0; // TXD0 - R_PFS->PORT[4].PIN[11].PmnPFS_b.PDR = 1; // TXD0 + R_PFS->PORT[4].PIN[11].PmnPFS_b.PCR = 1; // TXD0 R_PFS->PORT[4].PIN[11].PmnPFS_b.PSEL = 0x04; // TXD0 R_PFS->PORT[4].PIN[11].PmnPFS_b.PMR = 1; // TXD0 @@ -50,9 +50,9 @@ void uart_init(void) R_SCI0->SCR = 0x00; while (R_SCI0->SCR != 0); - R_SCI0->SMR = 0x00; - R_SCI0->SCMR = 0xF3; - R_SCI0->SEMR = 0xC0; + // R_SCI0->SMR = 0x00; + // R_SCI0->SCMR = 0xF3; + // R_SCI0->SEMR = 0xC0; // R_SCI0->FCR_b.FM = 1; // R_SCI0->FCR_b.TFRST = 1; From fbf9551b57062d1c3e843cac2f98fd11291fd6d5 Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Thu, 10 Jul 2025 19:51:41 +0200 Subject: [PATCH 15/62] Added startup info --- tests/renesas/src/main.c | 449 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 440 insertions(+), 9 deletions(-) diff --git a/tests/renesas/src/main.c b/tests/renesas/src/main.c index d7b6280c47..f541961e45 100644 --- a/tests/renesas/src/main.c +++ b/tests/renesas/src/main.c @@ -8,8 +8,402 @@ #endif #include "mcu.h" +#include "interrupts_mcu.h" #define PWPR_REGISTER_BASE (* ( volatile uint8_t * )0x40040D03UL) +// Startup file should have this (from bsp_elc.h file) +// void NMI_Handler(void) WEAK_REF_ATTRIBUTE; +// void HardFault_Handler(void) WEAK_REF_ATTRIBUTE; +// void MemManage_Handler(void) WEAK_REF_ATTRIBUTE; +// void BusFault_Handler(void) WEAK_REF_ATTRIBUTE; +// void UsageFault_Handler(void) WEAK_REF_ATTRIBUTE; +// void SecureFault_Handler(void) WEAK_REF_ATTRIBUTE; +// void SVC_Handler(void) WEAK_REF_ATTRIBUTE; +// void DebugMon_Handler(void) WEAK_REF_ATTRIBUTE; +// void PendSV_Handler(void) WEAK_REF_ATTRIBUTE; +// void SysTick_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_IRQ0_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_IRQ1_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_IRQ2_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_IRQ3_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_IRQ4_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_IRQ5_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_IRQ6_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_IRQ7_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_IRQ8_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_IRQ9_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_IRQ10_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_IRQ11_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_IRQ12_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_IRQ14_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_IRQ15_Handler(void) WEAK_REF_ATTRIBUTE; +// void DMAC0_INT_Handler(void) WEAK_REF_ATTRIBUTE; +// void DMAC1_INT_Handler(void) WEAK_REF_ATTRIBUTE; +// void DMAC2_INT_Handler(void) WEAK_REF_ATTRIBUTE; +// void DMAC3_INT_Handler(void) WEAK_REF_ATTRIBUTE; +// void DTC_COMPLETE_Handler(void) WEAK_REF_ATTRIBUTE; +// void DTC_END_Handler(void) WEAK_REF_ATTRIBUTE; +// void ICU_SNOOZE_CANCEL_Handler(void) WEAK_REF_ATTRIBUTE; +// void FCU_FRDYI_Handler(void) WEAK_REF_ATTRIBUTE; +// void LVD_LVD1_Handler(void) WEAK_REF_ATTRIBUTE; +// void LVD_LVD2_Handler(void) WEAK_REF_ATTRIBUTE; +// void LVD_VBATT_Handler(void) WEAK_REF_ATTRIBUTE; +// void CGC_MOSC_STOP_Handler(void) WEAK_REF_ATTRIBUTE; +// void LPM_SNOOZE_REQUEST_Handler(void) WEAK_REF_ATTRIBUTE; +// void AGT0_INT_Handler(void) WEAK_REF_ATTRIBUTE; +// void AGT0_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; +// void AGT0_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; +// void AGT1_INT_Handler(void) WEAK_REF_ATTRIBUTE; +// void AGT1_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; +// void AGT1_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; +// void IWDT_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void WDT_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void RTC_ALARM_Handler(void) WEAK_REF_ATTRIBUTE; +// void RTC_PERIOD_Handler(void) WEAK_REF_ATTRIBUTE; +// void RTC_CARRY_Handler(void) WEAK_REF_ATTRIBUTE; +// void ADC0_SCAN_END_Handler(void) WEAK_REF_ATTRIBUTE; +// void ADC0_SCAN_END_B_Handler(void) WEAK_REF_ATTRIBUTE; +// void ADC0_WINDOW_A_Handler(void) WEAK_REF_ATTRIBUTE; +// void ADC0_WINDOW_B_Handler(void) WEAK_REF_ATTRIBUTE; +// void ADC0_COMPARE_MATCH_Handler(void) WEAK_REF_ATTRIBUTE; +// void ADC0_COMPARE_MISMATCH_Handler(void) WEAK_REF_ATTRIBUTE; +// void ACMPLP0_INT_Handler(void) WEAK_REF_ATTRIBUTE; +// void ACMPLP1_INT_Handler(void) WEAK_REF_ATTRIBUTE; +// void USBFS_FIFO_0_Handler(void) WEAK_REF_ATTRIBUTE; +// void USBFS_FIFO_1_Handler(void) WEAK_REF_ATTRIBUTE; +// void USBFS_INT_Handler(void) WEAK_REF_ATTRIBUTE; +// void USBFS_RESUME_Handler(void) WEAK_REF_ATTRIBUTE; +// void IIC0_RXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void IIC0_TXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void IIC0_TEI_Handler(void) WEAK_REF_ATTRIBUTE; +// void IIC0_ERI_Handler(void) WEAK_REF_ATTRIBUTE; +// void IIC0_WUI_Handler(void) WEAK_REF_ATTRIBUTE; +// void IIC1_RXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void IIC1_TXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void IIC1_TEI_Handler(void) WEAK_REF_ATTRIBUTE; +// void IIC1_ERI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SSI0_TXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SSI0_RXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SSI0_INT_Handler(void) WEAK_REF_ATTRIBUTE; +// void CTSU_WRITE_Handler(void) WEAK_REF_ATTRIBUTE; +// void CTSU_READ_Handler(void) WEAK_REF_ATTRIBUTE; +// void CTSU_END_Handler(void) WEAK_REF_ATTRIBUTE; +// void KEY_INT_Handler(void) WEAK_REF_ATTRIBUTE; +// void DOC_INT_Handler(void) WEAK_REF_ATTRIBUTE; +// void CAC_FREQUENCY_ERROR_Handler(void) WEAK_REF_ATTRIBUTE; +// void CAC_MEASUREMENT_END_Handler(void) WEAK_REF_ATTRIBUTE; +// void CAC_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void CAN0_ERROR_Handler(void) WEAK_REF_ATTRIBUTE; +// void CAN0_FIFO_RX_Handler(void) WEAK_REF_ATTRIBUTE; +// void CAN0_FIFO_TX_Handler(void) WEAK_REF_ATTRIBUTE; +// void CAN0_MAILBOX_RX_Handler(void) WEAK_REF_ATTRIBUTE; +// void CAN0_MAILBOX_TX_Handler(void) WEAK_REF_ATTRIBUTE; +// void IOPORT_EVENT_1_Handler(void) WEAK_REF_ATTRIBUTE; +// void IOPORT_EVENT_2_Handler(void) WEAK_REF_ATTRIBUTE; +// void IOPORT_EVENT_3_Handler(void) WEAK_REF_ATTRIBUTE; +// void IOPORT_EVENT_4_Handler(void) WEAK_REF_ATTRIBUTE; +// void ELC_SOFTWARE_EVENT_0_Handler(void) WEAK_REF_ATTRIBUTE; +// void ELC_SOFTWARE_EVENT_1_Handler(void) WEAK_REF_ATTRIBUTE; +// void POEG0_EVENT_Handler(void) WEAK_REF_ATTRIBUTE; +// void POEG1_EVENT_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT0_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT0_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT0_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT0_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT0_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT0_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT0_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT0_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT1_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT1_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT1_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT1_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT1_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT1_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT1_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT1_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT2_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT2_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT2_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT2_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT2_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT2_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT2_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT2_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT3_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT3_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT3_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT3_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT3_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT3_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT3_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT3_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT4_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT4_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT4_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT4_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT4_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT4_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT4_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT4_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT5_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT5_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT5_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT5_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT5_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT5_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT5_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT5_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT6_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT6_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT6_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT6_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT6_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT6_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT6_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT6_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT7_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT7_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT7_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT7_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT7_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT7_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT7_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void GPT7_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; +// void OPS_UVW_EDGE_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI0_RXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI0_TXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI0_TEI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI0_ERI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI0_AM_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI0_RXI_OR_ERI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI1_RXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI1_TXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI1_TEI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI1_ERI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI1_AM_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI2_RXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI2_TXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI2_TEI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI2_ERI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI2_AM_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI9_RXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI9_TXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI9_TEI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI9_ERI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SCI9_AM_Handler(void) WEAK_REF_ATTRIBUTE; +// void SPI0_RXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SPI0_TXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SPI0_IDLE_Handler(void) WEAK_REF_ATTRIBUTE; +// void SPI0_ERI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SPI0_TEI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SPI1_RXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SPI1_TXI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SPI1_IDLE_Handler(void) WEAK_REF_ATTRIBUTE; +// void SPI1_ERI_Handler(void) WEAK_REF_ATTRIBUTE; +// void SPI1_TEI_Handler(void) WEAK_REF_ATTRIBUTE; + +// BSP_DONT_REMOVE const exc_ptr_t __Vectors[196] BSP_PLACE_IN_SECTION( +// BSP_SECTION_FIXED_VECTORS) = +// { +// (exc_ptr_t) (&g_main_stack[0] + BSP_CFG_STACK_MAIN_BYTES), /* Initial Stack Pointer */ +// Reset_Handler, /* Reset Handler */ +// NMI_Handler, /* NMI Handler */ +// HardFault_Handler, /* Hard Fault Handler */ +// MemManage_Handler, /* MPU Fault Handler */ +// BusFault_Handler, /* Bus Fault Handler */ +// UsageFault_Handler, /* Usage Fault Handler */ +// SecureFault_Handler, /* Secure Fault Handler */ +// 0, /* Reserved */ +// 0, /* Reserved */ +// 0, /* Reserved */ +// SVC_Handler, /* SVCall Handler */ +// DebugMon_Handler, /* Debug Monitor Handler */ +// 0, /* Reserved */ +// PendSV_Handler, /* PendSV Handler */ +// SysTick_Handler, /* SysTick Handler */ +// ICU_IRQ0_Handler, /* External pin interrupt 0 */ +// ICU_IRQ1_Handler, /* External pin interrupt 1 */ +// ICU_IRQ2_Handler, /* External pin interrupt 2 */ +// ICU_IRQ3_Handler, /* External pin interrupt 3 */ +// ICU_IRQ4_Handler, /* External pin interrupt 4 */ +// ICU_IRQ5_Handler, /* External pin interrupt 5 */ +// ICU_IRQ6_Handler, /* External pin interrupt 6 */ +// ICU_IRQ7_Handler, /* External pin interrupt 7 */ +// ICU_IRQ8_Handler, /* External pin interrupt 8 */ +// ICU_IRQ9_Handler, /* External pin interrupt 9 */ +// ICU_IRQ10_Handler, /* External pin interrupt 10 */ +// ICU_IRQ11_Handler, /* External pin interrupt 11 */ +// ICU_IRQ12_Handler, /* External pin interrupt 12 */ +// ICU_IRQ14_Handler, /* External pin interrupt 14 */ +// ICU_IRQ15_Handler, /* External pin interrupt 15 */ +// DMAC0_INT_Handler, /* DMAC0 transfer end */ +// DMAC1_INT_Handler, /* DMAC1 transfer end */ +// DMAC2_INT_Handler, /* DMAC2 transfer end */ +// DMAC3_INT_Handler, /* DMAC3 transfer end */ +// DTC_COMPLETE_Handler, /* DTC transfer complete */ +// DTC_END_Handler, /* DTC transfer end */ +// ICU_SNOOZE_CANCEL_Handler, /* Canceling from Snooze mode */ +// FCU_FRDYI_Handler, /* Flash ready interrupt */ +// LVD_LVD1_Handler, /* Voltage monitor 1 interrupt */ +// LVD_LVD2_Handler, /* Voltage monitor 2 interrupt */ +// LVD_VBATT_Handler, /* VBATT low voltage detect */ +// CGC_MOSC_STOP_Handler, /* Main Clock oscillation stop */ +// LPM_SNOOZE_REQUEST_Handler, /* Snooze entry */ +// AGT0_INT_Handler, /* AGT interrupt */ +// AGT0_COMPARE_A_Handler, /* Compare match A */ +// AGT0_COMPARE_B_Handler, /* Compare match B */ +// AGT1_INT_Handler, /* AGT interrupt */ +// AGT1_COMPARE_A_Handler, /* Compare match A */ +// AGT1_COMPARE_B_Handler, /* Compare match B */ +// IWDT_UNDERFLOW_Handler, /* IWDT underflow */ +// WDT_UNDERFLOW_Handler, /* WDT underflow */ +// RTC_ALARM_Handler, /* Alarm interrupt */ +// RTC_PERIOD_Handler, /* Periodic interrupt */ +// RTC_CARRY_Handler, /* Carry interrupt */ +// ADC0_SCAN_END_Handler, /* End of A/D scanning operation */ +// ADC0_SCAN_END_B_Handler, /* A/D scan end interrupt for group B */ +// ADC0_WINDOW_A_Handler, /* Window A Compare match interrupt */ +// ADC0_WINDOW_B_Handler, /* Window B Compare match interrupt */ +// ADC0_COMPARE_MATCH_Handler, /* Compare match */ +// ADC0_COMPARE_MISMATCH_Handler, /* Compare mismatch */ +// ACMPLP0_INT_Handler, /* Low Power Comparator channel 0 interrupt */ +// ACMPLP1_INT_Handler, /* Low Power Comparator channel 1 interrupt */ +// USBFS_FIFO_0_Handler, /* DMA/DTC transfer request 0 */ +// USBFS_FIFO_1_Handler, /* DMA/DTC transfer request 1 */ +// USBFS_INT_Handler, /* USBFS interrupt */ +// USBFS_RESUME_Handler, /* USBFS resume interrupt */ +// IIC0_RXI_Handler, /* Receive data full */ +// IIC0_TXI_Handler, /* Transmit data empty */ +// IIC0_TEI_Handler, /* Transmit end */ +// IIC0_ERI_Handler, /* Transfer error */ +// IIC0_WUI_Handler, /* Wakeup interrupt */ +// IIC1_RXI_Handler, /* Receive data full */ +// IIC1_TXI_Handler, /* Transmit data empty */ +// IIC1_TEI_Handler, /* Transmit end */ +// IIC1_ERI_Handler, /* Transfer error */ +// SSI0_TXI_Handler, /* Transmit data empty */ +// SSI0_RXI_Handler, /* Receive data full */ +// SSI0_INT_Handler, /* Error interrupt */ +// CTSU_WRITE_Handler, /* Write request interrupt */ +// CTSU_READ_Handler, /* Measurement data transfer request interrupt */ +// CTSU_END_Handler, /* Measurement end interrupt */ +// KEY_INT_Handler, /* Key interrupt */ +// DOC_INT_Handler, /* Data operation circuit interrupt */ +// CAC_FREQUENCY_ERROR_Handler, /* Frequency error interrupt */ +// CAC_MEASUREMENT_END_Handler, /* Measurement end interrupt */ +// CAC_OVERFLOW_Handler, /* Overflow interrupt */ +// CAN0_ERROR_Handler, /* Error interrupt */ +// CAN0_FIFO_RX_Handler, /* Receive FIFO interrupt */ +// CAN0_FIFO_TX_Handler, /* Transmit FIFO interrupt */ +// CAN0_MAILBOX_RX_Handler, /* Reception complete interrupt */ +// CAN0_MAILBOX_TX_Handler, /* Transmission complete interrupt */ +// IOPORT_EVENT_1_Handler, /* Port 1 event */ +// IOPORT_EVENT_2_Handler, /* Port 2 event */ +// IOPORT_EVENT_3_Handler, /* Port 3 event */ +// IOPORT_EVENT_4_Handler, /* Port 4 event */ +// ELC_SOFTWARE_EVENT_0_Handler, /* Software event 0 */ +// ELC_SOFTWARE_EVENT_1_Handler, /* Software event 1 */ +// POEG0_EVENT_Handler, /* Port Output disable 0 interrupt */ +// POEG1_EVENT_Handler, /* Port Output disable 1 interrupt */ +// GPT0_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ +// GPT0_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ +// GPT0_COMPARE_C_Handler, /* Compare match C */ +// GPT0_COMPARE_D_Handler, /* Compare match D */ +// GPT0_COMPARE_E_Handler, /* Compare match E */ +// GPT0_COMPARE_F_Handler, /* Compare match F */ +// GPT0_COUNTER_OVERFLOW_Handler, /* Overflow */ +// GPT0_COUNTER_UNDERFLOW_Handler, /* Underflow */ +// GPT1_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ +// GPT1_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ +// GPT1_COMPARE_C_Handler, /* Compare match C */ +// GPT1_COMPARE_D_Handler, /* Compare match D */ +// GPT1_COMPARE_E_Handler, /* Compare match E */ +// GPT1_COMPARE_F_Handler, /* Compare match F */ +// GPT1_COUNTER_OVERFLOW_Handler, /* Overflow */ +// GPT1_COUNTER_UNDERFLOW_Handler, /* Underflow */ +// GPT2_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ +// GPT2_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ +// GPT2_COMPARE_C_Handler, /* Compare match C */ +// GPT2_COMPARE_D_Handler, /* Compare match D */ +// GPT2_COMPARE_E_Handler, /* Compare match E */ +// GPT2_COMPARE_F_Handler, /* Compare match F */ +// GPT2_COUNTER_OVERFLOW_Handler, /* Overflow */ +// GPT2_COUNTER_UNDERFLOW_Handler, /* Underflow */ +// GPT3_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ +// GPT3_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ +// GPT3_COMPARE_C_Handler, /* Compare match C */ +// GPT3_COMPARE_D_Handler, /* Compare match D */ +// GPT3_COMPARE_E_Handler, /* Compare match E */ +// GPT3_COMPARE_F_Handler, /* Compare match F */ +// GPT3_COUNTER_OVERFLOW_Handler, /* Overflow */ +// GPT3_COUNTER_UNDERFLOW_Handler, /* Underflow */ +// GPT4_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ +// GPT4_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ +// GPT4_COMPARE_C_Handler, /* Compare match C */ +// GPT4_COMPARE_D_Handler, /* Compare match D */ +// GPT4_COMPARE_E_Handler, /* Compare match E */ +// GPT4_COMPARE_F_Handler, /* Compare match F */ +// GPT4_COUNTER_OVERFLOW_Handler, /* Overflow */ +// GPT4_COUNTER_UNDERFLOW_Handler, /* Underflow */ +// GPT5_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ +// GPT5_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ +// GPT5_COMPARE_C_Handler, /* Compare match C */ +// GPT5_COMPARE_D_Handler, /* Compare match D */ +// GPT5_COMPARE_E_Handler, /* Compare match E */ +// GPT5_COMPARE_F_Handler, /* Compare match F */ +// GPT5_COUNTER_OVERFLOW_Handler, /* Overflow */ +// GPT5_COUNTER_UNDERFLOW_Handler, /* Underflow */ +// GPT6_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ +// GPT6_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ +// GPT6_COMPARE_C_Handler, /* Compare match C */ +// GPT6_COMPARE_D_Handler, /* Compare match D */ +// GPT6_COMPARE_E_Handler, /* Compare match E */ +// GPT6_COMPARE_F_Handler, /* Compare match F */ +// GPT6_COUNTER_OVERFLOW_Handler, /* Overflow */ +// GPT6_COUNTER_UNDERFLOW_Handler, /* Underflow */ +// GPT7_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ +// GPT7_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ +// GPT7_COMPARE_C_Handler, /* Compare match C */ +// GPT7_COMPARE_D_Handler, /* Compare match D */ +// GPT7_COMPARE_E_Handler, /* Compare match E */ +// GPT7_COMPARE_F_Handler, /* Compare match F */ +// GPT7_COUNTER_OVERFLOW_Handler, /* Overflow */ +// GPT7_COUNTER_UNDERFLOW_Handler, /* Underflow */ +// OPS_UVW_EDGE_Handler, /* UVW edge event */ +// SCI0_RXI_Handler, /* Receive data full */ +// SCI0_TXI_Handler, /* Transmit data empty */ +// SCI0_TEI_Handler, /* Transmit end */ +// SCI0_ERI_Handler, /* Receive error */ +// SCI0_AM_Handler, /* Address match event */ +// SCI0_RXI_OR_ERI_Handler, /* Receive data full/Receive error */ +// SCI1_RXI_Handler, /* Receive data full */ +// SCI1_TXI_Handler, /* Transmit data empty */ +// SCI1_TEI_Handler, /* Transmit end */ +// SCI1_ERI_Handler, /* Receive error */ +// SCI1_AM_Handler, /* Address match event */ +// SCI2_RXI_Handler, /* Receive data full */ +// SCI2_TXI_Handler, /* Transmit data empty */ +// SCI2_TEI_Handler, /* Transmit end */ +// SCI2_ERI_Handler, /* Receive error */ +// SCI2_AM_Handler, /* Address match event */ +// SCI9_RXI_Handler, /* Receive data full */ +// SCI9_TXI_Handler, /* Transmit data empty */ +// SCI9_TEI_Handler, /* Transmit end */ +// SCI9_ERI_Handler, /* Receive error */ +// SCI9_AM_Handler, /* Address match event */ +// SPI0_RXI_Handler, /* Receive buffer full */ +// SPI0_TXI_Handler, /* Transmit buffer empty */ +// SPI0_IDLE_Handler, /* Idle */ +// SPI0_ERI_Handler, /* Error */ +// SPI0_TEI_Handler, /* Transmission complete event */ +// SPI1_RXI_Handler, /* Receive buffer full */ +// SPI1_TXI_Handler, /* Transmit buffer empty */ +// SPI1_IDLE_Handler, /* Idle */ +// SPI1_ERI_Handler, /* Error */ +// SPI1_TEI_Handler /* Transmission complete event */ +// }; + void uart_init(void) { // 1. Enable SCI0 in the Module Stop Register @@ -54,12 +448,12 @@ void uart_init(void) // R_SCI0->SCMR = 0xF3; // R_SCI0->SEMR = 0xC0; - // R_SCI0->FCR_b.FM = 1; - // R_SCI0->FCR_b.TFRST = 1; - // R_SCI0->FCR_b.RFRST = 1; - // R_SCI0->FCR_b.TTRG = 0; - // R_SCI0->FCR_b.RTRG = 0; - // R_SCI0->FCR_b.RSTRG = 0; + R_SCI0->FCR_b.FM = 1; + R_SCI0->FCR_b.TFRST = 1; + R_SCI0->FCR_b.RFRST = 1; + R_SCI0->FCR_b.TTRG = 0; + R_SCI0->FCR_b.RTRG = 0; + R_SCI0->FCR_b.RSTRG = 0; R_SCI0->SCR_b.CKE = 0x00; R_SCI0->SMR_b.CKS = 0x00; @@ -69,8 +463,8 @@ void uart_init(void) - // R_SCI0->FCR_b.TFRST = 0; - // R_SCI0->FCR_b.RFRST = 0; + R_SCI0->FCR_b.TFRST = 0; + R_SCI0->FCR_b.RFRST = 0; // Delay at least 1 bit time (~8.6 us at 115200 baud) @@ -79,6 +473,12 @@ void uart_init(void) // Enable transmit and receive R_SCI0->SCR_b.RE = 0x01; R_SCI0->SCR_b.TE = 0x01; + + R_SCI0->SCR_b.TIE = 1; // Transmit Interrupt Enable (TXI0) + R_SCI0->SCR_b.RIE = 1; // Receive Interrupt Enable (RXI0) + NVIC_EnableIRQ(INTERRUPTS_IELSR22); // Transmit interrupt + NVIC_EnableIRQ(INTERRUPTS_IELSR23); // Receive interrupt + __enable_irq(); } void uart_send_char(char c) @@ -103,6 +503,37 @@ char uart_receive_char(void) return c; } +void SCI0_RXI_Handler(void) +{ + if (R_SCI0->SSR_b.RDRF) + { + char received = R_SCI0->RDR; + R_SCI0->SSR_b.RDRF = 0; // Clear RDRF + // Echo back or process + uart_send_char(received); + } +} + +volatile const char *tx_buffer = "Hello World\r\n"; +volatile uint8_t tx_index = 0; + +void SCI0_TXI_Handler(void) +{ + if (R_SCI0->SSR_b.TDRE) + { + if (tx_buffer[tx_index] != '\0') + { + R_SCI0->TDR = tx_buffer[tx_index++]; + R_SCI0->SSR_b.TDRE = 0; // Clear TDRE + } + else + { + R_SCI0->SCR_b.TIE = 0; // Disable TX interrupt + tx_index = 0; + } + } +} + int main( void ) { /* Do not remove this line or clock might not be set correctly. */ #ifdef PREINIT_SUPPORTED @@ -113,7 +544,7 @@ int main( void ) { uart_send_char('H'); uart_send_char('i'); - uart_send_char('\r'); + uart_send_char('!'); uart_send_char('\n'); while (1) From 85b5c0404bf92c528b6281164c41d0c1e019071e Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Mon, 14 Jul 2025 16:06:00 +0200 Subject: [PATCH 16/62] Fully functional write and read --- .../i2c/implementation_1/hal_ll_i2c_master.c | 101 +++++-- tests/i2c/main.c | 249 +----------------- 2 files changed, 78 insertions(+), 272 deletions(-) diff --git a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c index b9fe138af4..64b3f4e633 100644 --- a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c @@ -65,6 +65,15 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU /*!< @brief Bit positions and masks */ #define HAL_LL_I2C_ICCR2_BBSY (7) #define HAL_LL_I2C_ICCR2_ST (1) +#define HAL_LL_I2C_ICCR2_SP (3) +#define HAL_LL_I2C_ICSR2_TDRE (7) +#define HAL_LL_I2C_ICSR2_NACKF (4) +#define HAL_LL_I2C_ICSR2_TEND (6) +#define HAL_LL_I2C_ICSR2_STOP (3) +#define HAL_LL_I2C_ICSR2_RDRF (5) +#define HAL_LL_I2C_ICMR3_WAIT (6) +#define HAL_LL_I2C_ICMR3_ACKBT (3) +#define HAL_LL_I2C_ICMR3_ACKWP (4) /*!< @brief Default I2C bit-rate if no speed is set */ #define HAL_LL_I2C_MASTER_SPEED_100K (100000UL) @@ -509,45 +518,87 @@ static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_ hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); uint16_t time_counter = map->timeout; - // while(R_IIC1->ICCR2_b.BBSY); // Wait while the bus is busy - // provera = R_IIC1->ICCR2; - // Delay_100ms(); - // provera = hal_ll_hw_reg->iccr2; while( check_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_BBSY )); - // R_IIC1->ICCR2_b.ST = 1; // Start condition set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_ST ); - while (!R_IIC1->ICSR2_b.TDRE); // Wait until transmit data register is empty + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )); - R_IIC1->ICDRT = 0x50 << 1; // Write the address + write_reg( &hal_ll_hw_reg->icdrt, map->address << 1 ); - while(!(R_IIC1->ICSR2_b.TDRE)); + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )); - if(R_IIC1->ICSR2_b.NACKF) // No slave device recognized - R_IIC1->ICCR2_b.SP = 1; // Stop condition + if( check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_NACKF )) + set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_SP ); - uint8_t dat = 50; - for( uint8_t i = 0; i < len_write_data; i++ ) - while(R_IIC1->ICSR2_b.TDRE) { - R_IIC1->ICDRT = write_data_buf[i]; - } + for( uint8_t i = 0; i < len_write_data; i++ ) { + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )); + write_reg( &hal_ll_hw_reg->icdrt, write_data_buf[i] ); + } - while(!(R_IIC1->ICSR2_b.TEND)); + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TEND )); - R_IIC1->ICSR2_b.STOP = 0; - R_IIC1->ICCR2_b.SP = 1; + clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); + set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_SP ); - while(!(R_IIC1->ICSR2_b.STOP)); + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP )); - R_IIC1->ICSR2_b.NACKF = 1; - R_IIC1->ICSR2_b.STOP = 0; + set_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_NACKF ); + clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); - return 0; + return HAL_LL_I2C_MASTER_SUCCESS; // TODO ESMA: add timeout and returning errors } static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ){ - return 0; + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + uint8_t dummy_read; + uint16_t time_counter = map->timeout; + + while( check_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_BBSY )); + + set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_ST ); + + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )); + + write_reg( &hal_ll_hw_reg->icdrt, ( map->address << 1 ) | 1 ); + + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )); + + if( check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_NACKF )) { + // Error + clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); + set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_SP ); + dummy_read = read_reg( &hal_ll_hw_reg->icdrr ); + } else { + set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_WAIT ); + if( len_read_data != 1 ) { + for( uint8_t i = 0; i < len_read_data - 2; i++ ) { + read_data_buf[i] = read_reg( &hal_ll_hw_reg->icdrr ); + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )); + } + } + + set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_ACKWP ); + set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_ACKBT ); + clear_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_ACKWP ); + + read_data_buf[len_read_data - 2] = read_reg( &hal_ll_hw_reg->icdrr ); + + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )); + + clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); + set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_SP ); + + read_data_buf[len_read_data - 1] = read_reg( &hal_ll_hw_reg->icdrr ); + clear_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_WAIT ); + } + + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP )); + + clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_NACKF ); + clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); + + return HAL_LL_I2C_MASTER_SUCCESS; } static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { @@ -659,8 +710,8 @@ static void hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { // R_PMISC->PWPR = 0x00; // Clear B0WI and PFSWE // R_PMISC->PWPR = 0x40; // Set PFSWE = 1, B0WI = 0 - // R_PFS->PORT[2].PIN[5].PmnPFS = (0x7 << 24) | (1 << 16); // PSEL[4:0] = 0x7, PMR = 1 - // R_PFS->PORT[2].PIN[6].PmnPFS = (0x7 << 24) | (1 << 16); // PSEL[4:0] = 0x7, PMR = 1 + // R_PFS->PORT[2].PIN[5].PmnPFS = (0x7 << 24) | (1 << 16) | (1<<2) | (1<<6); // PSEL[4:0] = 0x7, PMR = 1 + // R_PFS->PORT[2].PIN[6].PmnPFS = (0x7 << 24) | (1 << 16)| (1<<6); // PSEL[4:0] = 0x7, PMR = 1 // R_PMISC->PWPR = 0x80; // Lock with B0WI = 1 diff --git a/tests/i2c/main.c b/tests/i2c/main.c index e17816f79e..0e8bc19bd7 100644 --- a/tests/i2c/main.c +++ b/tests/i2c/main.c @@ -1,4 +1,3 @@ -#if 0 // ------------------------------------------------------------------ INCLUDES /** @@ -19,8 +18,8 @@ #endif // -------------------------------------------------------------------- MACROS -#define TEST_PIN_I2C_SCL HAL_PIN_NC // TODO define I2C SCL pin -#define TEST_PIN_I2C_SDA HAL_PIN_NC // TODO define I2C SDA pin +#define TEST_PIN_I2C_SCL GPIO_P205 // TODO define I2C SCL pin//MIKROBUS_1_SCL// +#define TEST_PIN_I2C_SDA GPIO_P206 // TODO define I2C SDA pin//MIKROBUS_1_SDA// // TODO // Define an existing pin to check the accuracy of write and read functions @@ -222,247 +221,3 @@ int main( void ) { } // ----------------------------------------------------------------------- END - -#else -/* - * Simplified I2C Master Library (Polling, Repeated Start, 7/10-bit Addressing) - * For RA4M1 or compatible Renesas MCU - */ - -#include -#include -#include "mcu.h" // Replace with correct MCU register definitions - -#define I2C_MASTER_OK (0) -#define I2C_MASTER_ERR (-1) - -// User must define these macros appropriately -// #define IIC1_BASE (R_IIC1) -// #define IIC_ICCR1 (IIC1_BASE->ICCR1) -// #define IIC_ICCR2 (IIC1_BASE->ICCR2) -// #define IIC_ICMR3 (IIC1_BASE->ICMR3) -// #define IIC_ICDRT (IIC1_BASE->ICDRT) -// #define IIC_ICDRR (IIC1_BASE->ICDRR) -// #define IIC_ICSR2 (IIC1_BASE->ICSR2) -// #define IIC_ICSR1 (IIC1_BASE->ICSR1) -// #define IIC_ICFER (IIC1_BASE->ICFER) -// #define IIC_ICIER (IIC1_BASE->ICIER) -// #define IIC_ICSER (IIC1_BASE->ICSER) -// #define IIC_ICMR1 (IIC1_BASE->ICMR1) -// #define IIC_ICMR2 (IIC1_BASE->ICMR2) -// #define IIC_ICBRL (IIC1_BASE->ICBRL) -// #define IIC_ICBRH (IIC1_BASE->ICBRH) - -static void i2c_master_wait_for_tend(void) -{ - while (!(R_IIC1->ICSR2_b.TEND)) {} // TEND bit - R_IIC1->ICSR2 &= ~(1 << 6); // Clear TEND -} - -static void i2c_master_wait_for_txi(void) -{ - while (R_IIC1->ICSR2 & (1 << 7)) {} // Wait while no transmit data - R_IIC1->ICSR2 &= ~(1 << 7); -} - -static void i2c_master_wait_for_rxi(void) -{ - while (!(R_IIC1->ICSR2 & (1 << 5))) {} // RXI - R_IIC1->ICSR2 &= ~(1 << 5); -} - -static void i2c_master_send_start(void) -{ - R_IIC1->ICCR2 |= (1 << 1); // Set ST bit - while (!(R_IIC1->ICCR2 & (1 << 1))) {} // Wait for ST cleared -} - -static void i2c_master_send_stop(void) -{ - R_IIC1->ICCR2 |= (1 << 3); // Set SP bit - while (R_IIC1->ICCR2 & (1 << 3)) {} // Wait for SP cleared -} - -static void i2c_master_send_address(uint16_t address, bool read) -{ - if (address > 0x7F) { - // 10-bit address mode - uint8_t high = 0xF0 | ((address >> 7) & 0x06) | (read ? 1 : 0); - uint8_t low = address & 0xFF; - R_IIC1->ICDRT = high; - i2c_master_wait_for_tend(); - R_IIC1->ICDRT = low; - } else { - // 7-bit address mode - R_IIC1->ICDRT = (address << 1) | (read ? 1 : 0); - } - // i2c_master_wait_for_tend(); -} - -int i2c_master_init(uint32_t bitrate_hz) -{ - // Simplified fixed init - R_IIC1->ICCR1 = 0; // Stop I2C - - R_IIC1->ICMR1 = 0x00; - R_IIC1->ICMR2 = 0x00; - R_IIC1->ICMR3 = 0x00; - - R_IIC1->ICBRL = 20; // Tune these for bitrate - R_IIC1->ICBRH = 20; - - R_IIC1->ICFER = 0x77; - R_IIC1->ICIER = 0x00; - R_IIC1->ICCR1 = 0x80; // Enable I2C - - return I2C_MASTER_OK; -} - -int i2c_master_write(uint16_t address, const uint8_t *data, uint32_t length, bool send_stop) -{ - i2c_master_send_start(); - i2c_master_send_address(address, false); - - for (uint32_t i = 0; i < length; i++) { - R_IIC1->ICDRT = data[i]; - // i2c_master_wait_for_tend(); - } - - i2c_master_wait_for_tend(); - if (send_stop) { - i2c_master_send_stop(); - } - return I2C_MASTER_OK; -} - -int i2c_master_read(uint16_t address, uint8_t *data, uint32_t length, bool send_stop) -{ - i2c_master_send_start(); - i2c_master_send_address(address, true); - - for (uint32_t i = 0; i < length; i++) { - if (i == (length - 1)) { - R_IIC1->ICMR3 |= (1 << 2); // NACK - } - i2c_master_wait_for_rxi(); - data[i] = R_IIC1->ICDRR; - } - - i2c_master_wait_for_tend(); - if (send_stop) { - i2c_master_send_stop(); - } - return I2C_MASTER_OK; -} - -int main() { - #if 0 - // Enable IIC1 peripheral - R_MSTP->MSTPCRB &= ~(1U << 8); - __asm volatile("dsb"); - - // Configure IIC0 pins (SCL = P205, SDA = P206) - // === 1. Enable write to PFS registers === - R_PMISC->PWPR = 0x00; // Clear B0WI and PFSWE - R_PMISC->PWPR = 0x40; // Set PFSWE = 1, B0WI = 0 - - // === 2. Set pin functions === - // P205 ? IIC0_SCL (PSEL = 0x0F), PMR = 1 (peripheral) - // R_PFS->P205PFS = (0x0F << 24) | (1 << 16); // PSEL[4:0] = 0x0F, PMR = 1 - R_PFS->PORT[2].PIN[5].PmnPFS = (0x7 << 24) | (1 << 16); // PSEL[4:0] = 0x7, PMR = 1 - - // P206 ? IIC0_SDA (PSEL = 0x7), PMR = 1 (peripheral) - // R_PFS->P206PFS = (0x7 << 24) | (1 << 16); // PSEL[4:0] = 0x7, PMR = 1 - R_PFS->PORT[2].PIN[6].PmnPFS = (0x7 << 24) | (1 << 16); // PSEL[4:0] = 0x7, PMR = 1 - - // === 3. Disable write === - R_PMISC->PWPR = 0x80; // Lock with B0WI = 1 - - // Example data to write - uint8_t write_data[] = { 0x00, 0x10, 0xA5 }; // Example: register 0x10 = 0xA5 - uint8_t read_data[2] = {0}; - - // Initialize I2C with desired bitrate (100kHz for example) - i2c_master_init(100000); - - // Write data to device 0x50 (register + value) - i2c_master_write(0x50, write_data, sizeof(write_data), false); // No STOP ? repeated start - - // Read back 2 bytes starting from register 0x10 - i2c_master_read(0x50, read_data, 2, true); // STOP after read - - // You can now inspect read_data[0] and read_data[1] - while (1) - { - // Do nothing ? loop forever - } - - return 0; - #else - - // Enable IIC1 peripheral - R_MSTP->MSTPCRB &= ~(1U << 8); - __asm volatile("dsb"); - - // Pin initialization - R_PMISC->PWPR = 0x00; // Clear B0WI and PFSWE - R_PMISC->PWPR = 0x40; // Set PFSWE = 1, B0WI = 0 - - R_PFS->PORT[2].PIN[5].PmnPFS = (0x7 << 24) | (1 << 16); // PSEL[4:0] = 0x7, PMR = 1 - R_PFS->PORT[2].PIN[6].PmnPFS = (0x7 << 24) | (1 << 16); // PSEL[4:0] = 0x7, PMR = 1 - - R_PMISC->PWPR = 0x80; // Lock with B0WI = 1 - - // I2C initialization - R_IIC1->ICCR1_b.ICE = 0; // 1. Set the ICCR1.ICE bit set to 0 to set the SCLn and SDAn pins to the inactive state. - R_IIC1->ICCR1_b.IICRST = 1; // 2. Set the ICCR1.IICRST bit to 1 to initiate IIC reset - R_IIC1->ICCR1_b.ICE = 1; // 3. Set the ICCR1.ICE bit to 1 to initiate internal reset. - - // 4. Set the SARLy, SARUy, ICSER, ICMR1, ICBRH, and ICBRL registers - // (y = 0 to 2), and set the other registers as required. - R_IIC1->SAR[1].U_b.FS = 0; - R_IIC1->SAR[1].L_b.SVA = 0x50 << 1; - R_IIC1->ICSER = 0; - // Bit rate? - R_IIC1->ICBRL = 20; // Tune these for bitrate - R_IIC1->ICBRH = 20; - // Bit rate? - - // Set ICIER // HOW? - - // 5. When the required register settings are complete, set the ICCR1.IICRST bit to 0 to release the IIC reset. - R_IIC1->ICCR1_b.IICRST = 0; - - while(R_IIC1->ICCR2_b.BBSY); // Wait while the bus is busy - - R_IIC1->ICCR2_b.ST = 1; // Start condition - - // while(!(R_IIC1->ICSR2_b.NACKF)) { - if(R_IIC1->ICSR2_b.TDRE) { - R_IIC1->ICDRT = 0x50 << 1; - } - if(R_IIC1->ICSR2_b.NACKF) // No slave device recognized - R_IIC1->ICCR2_b.SP = 1; // Stop condition - - uint8_t dat = 50; - while(dat) - while(R_IIC1->ICSR2_b.TDRE) - R_IIC1->ICDRT = dat--; - - while(!(R_IIC1->ICSR2_b.TEND)); - - // } - - R_IIC1->ICSR2_b.STOP = 0; - R_IIC1->ICCR2_b.SP = 1; - - while(!(R_IIC1->ICSR2_b.STOP)); - - R_IIC1->ICSR2_b.NACKF = 1; - R_IIC1->ICSR2_b.STOP = 0; - - return 0; - #endif -} - -#endif \ No newline at end of file From 68b4ca4a261dc19988fc00f0b65d159f633a7add Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Mon, 14 Jul 2025 16:06:16 +0200 Subject: [PATCH 17/62] removed line --- .../mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c index 1df40970cf..ff10d025d9 100644 --- a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c @@ -274,8 +274,6 @@ static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t conf } } -#include "mcu.h" - static void hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) { uint8_t pin_index; hal_ll_pin_name_t pin_name; From 0e19559824efe606e0ad23784676822329045bdd Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 16 Jul 2025 10:47:02 +0200 Subject: [PATCH 18/62] I2C removed hardcoded parts --- .../mikroe/renesas/include/hal_ll_mstpcr.h | 100 ++++++++ .../mikroe/renesas/src/hal_ll/CMakeLists.txt | 2 +- .../arm/mikroe/renesas/src/i2c/CMakeLists.txt | 1 + .../i2c/implementation_1/hal_ll_i2c_master.c | 218 ++++++++++-------- 4 files changed, 230 insertions(+), 91 deletions(-) create mode 100644 targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h diff --git a/targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h b/targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h new file mode 100644 index 0000000000..fc76792c40 --- /dev/null +++ b/targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h @@ -0,0 +1,100 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_mstpcr.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_MSTPCR_H_ +#define _HAL_LL_MSTPCR_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#if defined(R7FA4M1AB3CFM) // || TODO + #define _MSTPCRA ( uint32_t * )0x4001E01C + #define _MSTPCRB ( uint32_t * )0x40047000 + #define _MSTPCRC ( uint32_t * )0x40047004 + #define _MSTPCRD ( uint32_t * )0x40047008 +#endif + +#define MSTPCRA_MSTPA0_POS 0 // SRAM0 +#define MSTPCRA_MSTPA6_POS 6 // ECCSRAM +#define MSTPCRA_MSTPA22_POS 22 // DMA/DTC +#define MSTPCRB_MSTPB2_POS 2 // CAN0 +#define MSTPCRB_MSTPB8_POS 8 // I2C1 +#define MSTPCRB_MSTPB9_POS 9 // I2C0 +#define MSTPCRB_MSTPB11_POS 11 // USBFS +#define MSTPCRB_MSTPB18_POS 18 // SPI1 +#define MSTPCRB_MSTPB19_POS 19 // SPI0 +#define MSTPCRB_MSTPB22_POS 22 // SCI9 +#define MSTPCRB_MSTPB29_POS 29 // SCI2 +#define MSTPCRB_MSTPB30_POS 30 // SCI1 +#define MSTPCRB_MSTPB31_POS 31 // SCI0 +#define MSTPCRC_MSTPC0_POS 0 // CAC +#define MSTPCRC_MSTPC1_POS 1 // CRC +#define MSTPCRC_MSTPC3_POS 3 // CTSU +#define MSTPCRC_MSTPC4_POS 4 // SLCDC +#define MSTPCRC_MSTPC8_POS 8 // SSIE0 +#define MSTPCRC_MSTPC13_POS 13 // DOC +#define MSTPCRC_MSTPC14_POS 14 // ELC +#define MSTPCRC_MSTPC31_POS 31 // SCE5 +#define MSTPCRD_MSTPD2_POS 2 // AGT1 +#define MSTPCRD_MSTPD3_POS 3 // AGT0 +#define MSTPCRD_MSTPD5_POS 5 // GPT321 to GPT320 +#define MSTPCRD_MSTPD6_POS 6 // GPT167 to GPT162 +#define MSTPCRD_MSTPD14_POS 14 // POEG +#define MSTPCRD_MSTPD16_POS 16 // ADC140 +#define MSTPCRD_MSTPD19_POS 19 // DAC8 +#define MSTPCRD_MSTPD20_POS 20 // DAC12 +#define MSTPCRD_MSTPD29_POS 29 // ACMPLP +#define MSTPCRD_MSTPD31_POS 31 // OPAMP + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_MSTPCR_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt b/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt index ad6a816326..381c7fdfd4 100644 --- a/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt @@ -12,4 +12,4 @@ target_link_libraries(lib_hal_ll INTERFACE ) mikrosdk_install(MikroSDK.HalLowLevel) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_mstpcr.h ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) diff --git a/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt b/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt index c5bc037ab4..5dfac15560 100644 --- a/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt @@ -31,6 +31,7 @@ endif() mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master ${i2c_subimplementation} + ../../include/hal_ll_mstpcr.h ../../include/hal_ll_target.h # BEGIN I2C ../../include/i2c/hal_ll_i2c_master.h diff --git a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c index 64b3f4e633..482e67cbe5 100644 --- a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c @@ -43,6 +43,7 @@ #include "hal_ll_gpio.h" #include "hal_ll_i2c_master.h" #include "hal_ll_i2c_pin_map.h" +#include "hal_ll_mstpcr.h" #include "delays.h" #include "mcu.h" // TODO Esma @@ -63,6 +64,8 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU #define HAL_LL_I2C_AF_CONFIG 0xFF // TODO Esma /*!< @brief Bit positions and masks */ +#define HAL_LL_I2C_ICCR1_IICRST (6) +#define HAL_LL_I2C_ICCR1_ICE (7) #define HAL_LL_I2C_ICCR2_BBSY (7) #define HAL_LL_I2C_ICCR2_ST (1) #define HAL_LL_I2C_ICCR2_SP (3) @@ -74,6 +77,8 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU #define HAL_LL_I2C_ICMR3_WAIT (6) #define HAL_LL_I2C_ICMR3_ACKBT (3) #define HAL_LL_I2C_ICMR3_ACKWP (4) +#define HAL_LL_I2C_ICFER_SCLE (6) +#define HAL_LL_I2C_ICFER_NFE (5) /*!< @brief Default I2C bit-rate if no speed is set */ #define HAL_LL_I2C_MASTER_SPEED_100K (100000UL) @@ -198,19 +203,6 @@ static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; // ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS -/** - * @brief Enable clock for I2C module on hardware level. - * - * Initializes I2C module clock on hardware level, based on beforehand - * set configuration and module handler. - * - * @param[in] *map - Object specific context handler. - * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). - * - * @return None - */ -static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, - bool hal_ll_state ); /** * @brief Initialize I2C module on hardware level. @@ -226,6 +218,9 @@ static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, */ static void hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); +// TODO Esma +static void hal_ll_i2c_calculate_speed( hal_ll_i2c_hw_specifics_map_t *map, uint32_t clock_value ); + /** * @brief Full I2C module initialization procedure. * @@ -286,7 +281,10 @@ static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); * Returns pre-defined module index from pin maps, if pins * are adequate. */ -static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, + hal_ll_pin_name_t sda, + hal_ll_i2c_pin_id *index_list, + hal_ll_i2c_master_handle_register_t *handle_map ); /** * @brief Maps new-found module specific values. @@ -301,17 +299,6 @@ static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, ha */ static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); -/** - * @brief Get I2C busy bit value. - * - * Checks I2C busy bit value and returns true if device is in operation. - * Else returns false. - * - * @param[in] *hal_ll_hw_reg - Object specific context handler. - * @return bool State of register busy bit. - */ -static bool hal_ll_i2c_master_is_idle( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); - /** * @brief Waits until device is free to operate. * @@ -380,7 +367,10 @@ static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_ size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS -hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, + hal_ll_pin_name_t sda, + hal_ll_i2c_master_handle_register_t *handle_map, + uint8_t *hal_module_id ) { hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; uint16_t pin_check_result; @@ -403,9 +393,11 @@ hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pi *hal_module_id = pin_check_result; - hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = + (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; - handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + handle_map[pin_check_result].hal_ll_i2c_master_handle = + (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; return HAL_LL_I2C_MASTER_SUCCESS; } @@ -417,7 +409,9 @@ hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); - hal_ll_module_state[ pin_check_result ].hal_ll_i2c_master_handle = ( handle_t * )&hal_ll_i2c_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].hal_ll_i2c_master_handle = + ( handle_t * )&hal_ll_i2c_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; hal_handle->init_ll_state = true; @@ -456,21 +450,34 @@ hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, s low_level_handle = hal_ll_i2c_get_handle; hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); - return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, + read_data_buf, + len_read_data, + HAL_LL_I2C_MASTER_END_MODE_STOP ); } hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { low_level_handle = hal_ll_i2c_get_handle; hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); - return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, + write_data_buf, + len_write_data, + HAL_LL_I2C_MASTER_END_MODE_STOP ); } -hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, + uint8_t *write_data_buf, + size_t len_write_data, + uint8_t *read_data_buf, + size_t len_read_data ) { low_level_handle = hal_ll_i2c_get_handle; hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); - if( NULL != hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + if( NULL != hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, + write_data_buf, + len_write_data, + HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; } @@ -482,7 +489,10 @@ hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write Delay_22us(); #endif - if( NULL != hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + if( NULL != hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, + read_data_buf, + len_read_data, + HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { return HAL_LL_I2C_MASTER_TIMEOUT_READ; } @@ -503,9 +513,7 @@ void hal_ll_i2c_master_close( handle_t *handle ) { hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; - hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_local, true ); hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); - hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_local, false ); hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; @@ -514,11 +522,14 @@ void hal_ll_i2c_master_close( handle_t *handle ) { } } // ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS -static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ){ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, + uint8_t *write_data_buf, + size_t len_write_data, + hal_ll_i2c_master_end_mode_t mode ) { hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); uint16_t time_counter = map->timeout; - while( check_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_BBSY )); + hal_ll_i2c_master_wait_for_idle( map ); set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_ST ); @@ -549,12 +560,15 @@ static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_ return HAL_LL_I2C_MASTER_SUCCESS; // TODO ESMA: add timeout and returning errors } -static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ){ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, + uint8_t *read_data_buf, + size_t len_read_data, + hal_ll_i2c_master_end_mode_t mode ) { hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); - uint8_t dummy_read; uint16_t time_counter = map->timeout; + uint8_t dummy_read; - while( check_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_BBSY )); + hal_ll_i2c_master_wait_for_idle( map ); set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_ST ); @@ -571,7 +585,7 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m dummy_read = read_reg( &hal_ll_hw_reg->icdrr ); } else { set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_WAIT ); - if( len_read_data != 1 ) { + if( 1 != len_read_data ) { for( uint8_t i = 0; i < len_read_data - 2; i++ ) { read_data_buf[i] = read_reg( &hal_ll_hw_reg->icdrr ); while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )); @@ -601,10 +615,6 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m return HAL_LL_I2C_MASTER_SUCCESS; } -static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { - return; -} - static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { module_struct module; @@ -623,15 +633,40 @@ static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_speci static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { // Map new pins - hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; - hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; - // SCL and SDA could have different alternate function settings, hence save both AF values - hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; - hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = + hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = + hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, + // hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = + hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = + hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; } static uint32_t hal_ll_i2c_get_speed( uint32_t bit_rate ) { - return 0; + if ( bit_rate <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( bit_rate <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + return HAL_LL_I2C_MASTER_SPEED_100K; + } else if ( bit_rate <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + return HAL_LL_I2C_MASTER_SPEED_400K; + } else if ( bit_rate <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + return HAL_LL_I2C_MASTER_SPEED_1M; + } else { + return HAL_LL_I2C_MASTER_SPEED_100K; + } + } else { + if ( bit_rate <= HAL_LL_I2C_MASTER_SPEED_100K ) { + return HAL_LL_I2C_MASTER_SPEED_100K; + } else if ( bit_rate <= HAL_LL_I2C_MASTER_SPEED_400K ) { + return HAL_LL_I2C_MASTER_SPEED_400K; + } else if ( bit_rate <= HAL_LL_I2C_MASTER_SPEED_1M ) { + return HAL_LL_I2C_MASTER_SPEED_1M; + } else { + return HAL_LL_I2C_MASTER_SPEED_1M; + } + } } static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { @@ -647,7 +682,10 @@ static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { return &hal_ll_i2c_hw_specifics_map[ hal_ll_module_error ]; } -static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, + hal_ll_pin_name_t sda, + hal_ll_i2c_pin_id *index_list, + hal_ll_i2c_master_handle_register_t *handle_map ) { static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); uint8_t hal_ll_module_id = 0; @@ -689,56 +727,56 @@ static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, ha } } -static bool hal_ll_i2c_master_is_idle( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { +static hal_ll_err_t hal_ll_i2c_master_wait_for_idle( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + + while( check_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_BBSY )); + return 0; } -static hal_ll_err_t hal_ll_i2c_master_wait_for_idle( hal_ll_i2c_hw_specifics_map_t *map ) { - return 0; +static void hal_ll_i2c_calculate_speed( hal_ll_i2c_hw_specifics_map_t *map, uint32_t clock_value ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + // 32MHz on PCLKB, 100kbps I2C + + write_reg( &hal_ll_hw_reg->icmr1, 0x3 << 4 ); + set_reg_bit( &hal_ll_hw_reg->icfer, HAL_LL_I2C_ICFER_SCLE ); + set_reg_bit( &hal_ll_hw_reg->icfer, HAL_LL_I2C_ICFER_NFE ); + write_reg( &hal_ll_hw_reg->icbrl, 0xF2 ); + write_reg( &hal_ll_hw_reg->icbrh, 0xF0 ); } static void hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { - return; + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + + // I2C initialization + // Set the ICCR1.ICE bit set to 0 to set the SCLn and SDAn pins to the inactive state. + clear_reg_bit( &hal_ll_hw_reg->iccr1, HAL_LL_I2C_ICCR1_ICE ); + // Set the ICCR1.IICRST bit to 1 to initiate IIC reset + set_reg_bit( &hal_ll_hw_reg->iccr1, HAL_LL_I2C_ICCR1_IICRST ); + // Set the ICCR1.ICE bit to 1 to initiate internal reset. + set_reg_bit( &hal_ll_hw_reg->iccr1, HAL_LL_I2C_ICCR1_ICE ); + + clear_reg( &hal_ll_hw_reg->icser ); } static void hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { - // Enable IIC1 peripheral - R_MSTP->MSTPCRB &= ~(1U << 8); - __asm volatile("dsb"); + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + uint32_t clock_value; // TODO Esma get source clock value - // Pin initialization - // R_PMISC->PWPR = 0x00; // Clear B0WI and PFSWE - // R_PMISC->PWPR = 0x40; // Set PFSWE = 1, B0WI = 0 + // Enable IIC peripheral + if( hal_ll_i2c_module_num( I2C_MODULE_0 ) == map->module_index ) + clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB9_POS ); + else if( hal_ll_i2c_module_num( I2C_MODULE_1 ) == map->module_index ) + clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB8_POS ); - // R_PFS->PORT[2].PIN[5].PmnPFS = (0x7 << 24) | (1 << 16) | (1<<2) | (1<<6); // PSEL[4:0] = 0x7, PMR = 1 - // R_PFS->PORT[2].PIN[6].PmnPFS = (0x7 << 24) | (1 << 16)| (1<<6); // PSEL[4:0] = 0x7, PMR = 1 + hal_ll_i2c_hw_init( map ); - // R_PMISC->PWPR = 0x80; // Lock with B0WI = 1 + hal_ll_i2c_calculate_speed( map, clock_value ); - // I2C initialization - R_IIC1->ICCR1_b.ICE = 0; // 1. Set the ICCR1.ICE bit set to 0 to set the SCLn and SDAn pins to the inactive state. - R_IIC1->ICCR1_b.IICRST = 1; // 2. Set the ICCR1.IICRST bit to 1 to initiate IIC reset - R_IIC1->ICCR1_b.ICE = 1; // 3. Set the ICCR1.ICE bit to 1 to initiate internal reset. - - // 4. Set the SARLy, SARUy, ICSER, ICMR1, ICBRH, and ICBRL registers - // (y = 0 to 2), and set the other registers as required. - volatile uint8_t device_addr = 0x50; - R_IIC1->SAR[1].L_b.SVA = device_addr << 1; - R_IIC1->SAR[1].U_b.FS = 0; - Delay_ms(100); - R_IIC1->ICSER = 0; - // Bit rate - fixed for 32MHz clock and 100kbps - R_IIC1->ICMR1_b.CKS = 3; - R_IIC1->ICFER_b.SCLE = 1; - R_IIC1->ICFER_b.NFE = 1; - R_IIC1->ICBRL = 0xF2; // Tune these for bitrate - R_IIC1->ICBRH = 0xF0; - - - // Set ICIER // HOW? - - // 5. When the required register settings are complete, set the ICCR1.IICRST bit to 0 to release the IIC reset. - R_IIC1->ICCR1_b.IICRST = 0; + // When the required register settings are complete, + // set the ICCR1.IICRST bit to 0 to release the IIC reset. + clear_reg_bit( &hal_ll_hw_reg->iccr1, HAL_LL_I2C_ICCR1_IICRST ); return; } From 9eba3a38de53d1395a96f825dcfb20e91af5f2db Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 16 Jul 2025 12:56:07 +0200 Subject: [PATCH 19/62] ADC initial commit (set for P000; works) --- .../RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 3 + .../implementation_1/hal_ll_adc_pin_map.h | 234 +--------------- .../src/adc/implementation_1/hal_ll_adc.c | 252 ++++++++++++++++-- 3 files changed, 242 insertions(+), 247 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h index 8e6694e784..eec601acb8 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -46,6 +46,9 @@ //ADC +#define ADC_MODULE_0 (1) + +#define ADC_AN000_P000 #define ADC_MODULE_COUNT 3 //EOF ADC diff --git a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h index 75ed529fac..6d25b17f95 100644 --- a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h +++ b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h @@ -58,10 +58,7 @@ extern "C"{ /*!< ADC module base addresses. */ #ifdef ADC_MODULE_0 -static const hal_ll_base_addr_t ADC0_BASE_ADDR = 0x40038000; -#endif -#ifdef ADC_MODULE_1 -static const hal_ll_base_addr_t ADC1_BASE_ADDR = 0x40039000; +static const hal_ll_base_addr_t ADC0_BASE_ADDR = 0x4005C000; #endif /** @@ -108,233 +105,8 @@ typedef struct static const hal_ll_pin_channel_list_t hal_ll_analog_in_register_list[] = { - #ifdef ADC0_PE3_AIN0 - {GPIO_PE3, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_0}, - #endif - #ifdef ADC1_PE3_AIN0 - {GPIO_PE3, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0}, - #endif - #ifdef ADC0_PE2_AIN1 - {GPIO_PE2, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_1}, - #endif - #ifdef ADC1_PE2_AIN1 - {GPIO_PE2, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, - #endif - #ifdef ADC0_PE1_AIN2 - {GPIO_PE1, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_2}, - #endif - #ifdef ADC1_PE1_AIN2 - {GPIO_PE1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, - #endif - #ifdef ADC0_PE0_AIN3 - {GPIO_PE0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_3}, - #endif - #ifdef ADC1_PE0_AIN3 - {GPIO_PE0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, - #endif - #ifdef ADC0_PD3_AIN4 - {GPIO_PD3, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4}, - #endif - #ifdef ADC1_PD3_AIN4 - {GPIO_PD3, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, - #endif - #ifdef ADC0_PD2_AIN5 - {GPIO_PD2, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_5}, - #endif - #ifdef ADC1_PD2_AIN5 - {GPIO_PD2, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, - #endif - #ifdef ADC0_PD1_AIN6 - {GPIO_PD1, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_6}, - #endif - #ifdef ADC1_PD1_AIN6 - {GPIO_PD1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, - #endif - #ifdef ADC0_PD0_AIN7 - {GPIO_PD0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7}, - #endif - #ifdef ADC1_PD0_AIN7 - {GPIO_PD0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, - #endif - #ifdef ADC0_PE5_AIN8 - {GPIO_PE5, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_8}, - #endif - #ifdef ADC1_PE5_AIN8 - {GPIO_PE5, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, - #endif - #ifdef ADC0_PE4_AIN9 - {GPIO_PE4, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_9}, - #endif - #ifdef ADC1_PE4_AIN9 - {GPIO_PE4, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, - #endif - #ifdef ADC0_PB4_AIN10 - {GPIO_PB4, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_10}, - #endif - #ifdef ADC1_PB4_AIN10 - {GPIO_PB4, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, - #endif - #ifdef ADC0_PB5_AIN11 - {GPIO_PB5, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_11}, - #endif - #ifdef ADC1_PB5_AIN11 - {GPIO_PB5, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, - #endif - #ifdef ADC0_PD7_AIN4 - {GPIO_PD7, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4}, - #endif - #ifdef ADC1_PD7_AIN4 - {GPIO_PD7, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, - #endif - #ifdef ADC0_PD6_AIN5 - {GPIO_PD6, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_5}, - #endif - #ifdef ADC1_PD6_AIN5 - {GPIO_PD6, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, - #endif - #ifdef ADC0_PD5_AIN6 - {GPIO_PD5, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_6}, - #endif - #ifdef ADC1_PD5_AIN6 - {GPIO_PD5, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, - #endif - #ifdef ADC0_PD4_AIN7 - {GPIO_PD4, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7}, - #endif - #ifdef ADC1_PD4_AIN7 - {GPIO_PD4, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, - #endif - #ifdef ADC0_PD3_AIN12 - {GPIO_PD3, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_12}, - #endif - #ifdef ADC1_PD3_AIN12 - {GPIO_PD3, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12}, - #endif - #ifdef ADC0_PD2_AIN13 - {GPIO_PD2, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_13}, - #endif - #ifdef ADC1_PD2_AIN13 - {GPIO_PD2, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_13}, - #endif - #ifdef ADC0_PD1_AIN14 - {GPIO_PD1, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_14}, - #endif - #ifdef ADC1_PD1_AIN14 - {GPIO_PD1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14}, - #endif - #ifdef ADC0_PD0_AIN15 - {GPIO_PD0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_15}, - #endif - #ifdef ADC1_PD0_AIN15 - {GPIO_PD0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, - #endif - #ifdef ADC0_PH0_AIN16 - {GPIO_PH0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_16}, - #endif - #ifdef ADC1_PH0_AIN16 - {GPIO_PH0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_16}, - #endif - #ifdef ADC0_PH1_AIN17 - {GPIO_PH1, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_17}, - #endif - #ifdef ADC1_PH1_AIN17 - {GPIO_PH1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_17}, - #endif - #ifdef ADC0_PH2_AIN18 - {GPIO_PH2, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_18}, - #endif - #ifdef ADC1_PH2_AIN18 - {GPIO_PH2, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_18}, - #endif - #ifdef ADC0_PH3_AIN19 - {GPIO_PH3, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_19}, - #endif - #ifdef ADC1_PH3_AIN19 - {GPIO_PH3, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_19}, - #endif - #ifdef ADC0_PE7_AIN20 - {GPIO_PE7, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_20}, - #endif - #ifdef ADC1_PE7_AIN20 - {GPIO_PE7, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_20}, - #endif - #ifdef ADC0_PE6_AIN21 - {GPIO_PE6, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_21}, - #endif - #ifdef ADC1_PE6_AIN21 - {GPIO_PE6, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_21}, - #endif - #ifdef ADC0_PK0_AIN16 - {GPIO_PK0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_16}, - #endif - #ifdef ADC1_PK0_AIN16 - {GPIO_PK0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_16}, - #endif - #ifdef ADC0_PK1_AIN17 - {GPIO_PK1, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_17}, - #endif - #ifdef ADC1_PK1_AIN17 - {GPIO_PK1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_17}, - #endif - #ifdef ADC0_PK2_AIN18 - {GPIO_PK2, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_18}, - #endif - #ifdef ADC1_PK2_AIN18 - {GPIO_PK2, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_18}, - #endif - #ifdef ADC0_PK3_AIN19 - {GPIO_PK3, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_19}, - #endif - #ifdef ADC1_PK3_AIN19 - {GPIO_PK3, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_19}, - #endif - #ifdef ADC0_PP1_AIN22 - {GPIO_PP1, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_22}, - #endif - #ifdef ADC1_PP1_AIN22 - {GPIO_PP1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_22}, - #endif - #ifdef ADC0_PP0_AIN23 - {GPIO_PP0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_23}, - #endif - #ifdef ADC1_PP0_AIN23 - {GPIO_PP0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_23}, - #endif - #ifdef ADC0_PN1_AIN22 - {GPIO_PN1, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_22}, - #endif - #ifdef ADC1_PN1_AIN22 - {GPIO_PN1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_22}, - #endif - #ifdef ADC0_PN0_AIN23 - {GPIO_PN0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_23}, - #endif - #ifdef ADC1_PN0_AIN23 - {GPIO_PN0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_23}, - #endif - #ifdef ADC0_PE6_AIN20 - {GPIO_PE6, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_20}, - #endif - #ifdef ADC1_PE6_AIN20 - {GPIO_PE6, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_20}, - #endif - #ifdef ADC0_PE7_AIN21 - {GPIO_PE7, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_21}, - #endif - #ifdef ADC1_PE7_AIN21 - {GPIO_PE7, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_21}, - #endif - #ifdef ADC0_PP7_AIN22 - {GPIO_PP7, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_22}, - #endif - #ifdef ADC1_PP7_AIN22 - {GPIO_PP7, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_22}, - #endif - #ifdef ADC0_PP6_AIN23 - {GPIO_PP6, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_23}, - #endif - #ifdef ADC1_PP6_AIN23 - {GPIO_PP6, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_23}, + #ifdef ADC_AN000_P000 + {GPIO_P000, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_0}, #endif { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR } diff --git a/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c index 35c3b6b21e..0dbe2479e5 100644 --- a/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c +++ b/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c @@ -44,6 +44,7 @@ #include "hal_ll_adc.h" #include "hal_ll_gpio.h" #include "hal_ll_adc_pin_map.h" +#include "mcu.h" // ------------------------------------------------------------- PRIVATE MACROS @@ -68,7 +69,23 @@ static hal_ll_adc_handle_register_t hal_ll_module_state[ ADC_MODULE_COUNT ] = { /*!< @brief ADC register structure. */ typedef struct { - volatile uint32_t TODO; + volatile uint16_t adcsr; // 0 + volatile uint8_t adref; // 2 + volatile uint8_t adexref; //3 + volatile uint16_t adansa[2]; // 4 + volatile uint16_t adads[2]; // 8 + volatile uint8_t adadc; // c + volatile uint8_t reserved; // d + volatile uint16_t adcer; // e + volatile uint16_t adstrgr; // 10 + volatile uint16_t adexicr; // 12 + volatile uint16_t adansb[2]; // 14 + volatile uint16_t addbldr; // 18 + volatile uint16_t adtsdr; // 1a + volatile uint16_t adocdr; // 1c + volatile uint16_t adrd; // 1e + volatile uint16_t addr[29]; // 20 + // TODO ako zatreba jos registara } hal_ll_adc_base_handle_t; /** @@ -174,51 +191,254 @@ static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS -hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, - hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id){ - return 0; - } +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, + hal_ll_adc_voltage_reference_t vref_input, + hal_ll_adc_resolution_t resolution, + hal_ll_adc_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + uint16_t pin_check_result; + hal_ll_adc_pin_id index = { HAL_LL_PIN_NC }; + + if (( pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + } + + switch ( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_ADC_12BIT_RES_VAL; + break; + case HAL_LL_ADC_RESOLUTION_14_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_ADC_14BIT_RES_VAL; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_EXTERNAL; + break; + case HAL_LL_ADC_VREF_INTERNAL: + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_INTERNAL; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[ pin_check_result ].pin != pin ) { + hal_ll_adc_map_pin( pin_check_result, &index ); + handle_map[ pin_check_result ].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_adc_handle = + ( handle_t* )&hal_ll_adc_hw_specifics_map[ pin_check_result ].base; + handle_map[ pin_check_result ].hal_ll_adc_handle = + ( handle_t* )&hal_ll_module_state[ pin_check_result ].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ){ - return 0; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init(hal_ll_adc_hw_specifics_map_local); + + hal_ll_module_state[ pin_check_result ].hal_ll_adc_handle = ( handle_t* )&hal_ll_adc_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; } hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution){ - return 0; + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); + + if( low_level_handle->hal_ll_adc_handle == NULL ) { + return HAL_LL_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + switch ( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_ADC_12BIT_RES_VAL; + break; + case HAL_LL_ADC_RESOLUTION_14_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_ADC_16BIT_RES_VAL; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; } hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) { - return 0; + hal_ll_adc_handle_register_t *low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); + + if( low_level_handle->hal_ll_adc_handle == NULL ) { + return HAL_LL_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_EXTERNAL; + break; + case HAL_LL_ADC_VREF_INTERNAL: + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_INTERNAL; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; } void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value){ - return; + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); + + if( low_level_handle->hal_ll_adc_handle != NULL ) { + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; + } } hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ){ - return 0; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + if( low_level_handle->hal_ll_adc_handle == NULL ) { + return HAL_LL_MODULE_ERROR; + } + + + R_ADC0->ADCSR_b.ADCS = 0; // scan mode selection - single + + R_ADC0->ADCSR_b.ADST = 1; // start + + *readDatabuf = ( uint16_t )R_ADC0->ADDR[0]; + + // base->sc1a = hal_ll_adc_hw_specifics_map_local->channel & HAL_LL_ADC_MASK_CHANNEL; + + // while ( 0 == ( base->sc1a & HAL_LL_ADC_COCO_FLAG ) ); + + // *readDatabuf = ( uint16_t )base->ra; + + return HAL_LL_ADC_SUCCESS; } void hal_ll_adc_close( handle_t *handle ){ - return; + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } } // ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS -static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) { - return 0; +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, + hal_ll_adc_pin_id *index, + hal_ll_adc_handle_register_t *handle_map ) { + static const uint16_t adc_map_size = ( sizeof( hal_ll_analog_in_register_list ) / sizeof( hal_ll_pin_channel_list_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == hal_ll_analog_in_register_list[pin_index].pin ) + { + // Get module number + hal_ll_module_id = hal_ll_analog_in_register_list[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } } -static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) {} +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = hal_ll_analog_in_register_list[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = hal_ll_analog_in_register_list[ index->pin_an[module_index] ].channel; +} static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { - return 0; + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_adc_handle_register_t )); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_adc_handle_register_t )); + + while( hal_ll_module_count-- ) { + if ( hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[ hal_ll_module_count ].base ) { + return &hal_ll_adc_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_adc_hw_specifics_map[ hal_ll_module_error ]; } static void adc_clock_enable( uint8_t module_index , bool state ) {} static void hal_ll_adc_hw_init(hal_ll_adc_hw_specifics_map_t *map) {} -static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) {} +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + R_PFS->PORT[0].PIN[0].PmnPFS_b.PDR = 1; // output + R_PFS->PORT[0].PIN[0].PmnPFS_b.ASEL = 1; // analog + R_PFS->PORT[0].PIN[0].PmnPFS_b.PMR = 1; // peripheral + + R_MSTP->MSTPCRD_b.MSTPD16 = 0; // unstop ADC0 module + + R_ADC0->ADANSA_b->ANSA0 = 1; // select AN000 + + R_ADC0->ADCER_b.ADPRC = 3; // 14-bit resolution + + +} // ------------------------------------------------------------------------- END From 8d7bc325b48e954b429be874967dc25f13654b3f Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Thu, 17 Jul 2025 16:33:38 +0200 Subject: [PATCH 20/62] adc update --- .../RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 2 +- .../implementation_1/hal_ll_adc_pin_map.h | 4 +- .../renesas/include/hal_ll_target_names.h | 2 +- .../implementation_1/hal_ll_i2c_pin_map.h | 6 +- .../arm/mikroe/renesas/src/adc/CMakeLists.txt | 1 + .../src/adc/implementation_1/hal_ll_adc.c | 99 ++++++++++++------- .../i2c/implementation_1/hal_ll_i2c_master.c | 42 ++++---- 7 files changed, 92 insertions(+), 64 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h index eec601acb8..d9d304da46 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -50,7 +50,7 @@ #define ADC_AN000_P000 -#define ADC_MODULE_COUNT 3 +#define ADC_MODULE_COUNT 1 //EOF ADC //I2C diff --git a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h index 6d25b17f95..661ee23adb 100644 --- a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h +++ b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h @@ -58,7 +58,7 @@ extern "C"{ /*!< ADC module base addresses. */ #ifdef ADC_MODULE_0 -static const hal_ll_base_addr_t ADC0_BASE_ADDR = 0x4005C000; +static const hal_ll_base_addr_t ADC0_BASE_ADDR = ( hal_ll_base_addr_t ) 0x4005C000; #endif /** @@ -90,6 +90,8 @@ typedef enum HAL_LL_ADC_CHANNEL_21, HAL_LL_ADC_CHANNEL_22, HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, HAL_LL_ADC_CHANNEL_NC = 0xFFFF } hal_ll_adc_channel_t; diff --git a/targets/arm/mikroe/renesas/include/hal_ll_target_names.h b/targets/arm/mikroe/renesas/include/hal_ll_target_names.h index 153d7befc1..559ced4f2a 100644 --- a/targets/arm/mikroe/renesas/include/hal_ll_target_names.h +++ b/targets/arm/mikroe/renesas/include/hal_ll_target_names.h @@ -59,7 +59,7 @@ typedef uint16_t hal_ll_gpio_mask_t; typedef uint8_t hal_ll_pin_name_t; typedef uint8_t hal_ll_port_name_t; typedef uint16_t hal_ll_port_size_t; -typedef uint8_t hal_ll_base_addr_t; +typedef uint32_t hal_ll_base_addr_t; typedef uint8_t hal_ll_channel_t; typedef int32_t hal_ll_err_t; diff --git a/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h index 197cd387d6..05eca3c89b 100644 --- a/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h +++ b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h @@ -56,10 +56,10 @@ extern "C"{ #define hal_ll_i2c_module_num(_module_num) (_module_num - 1) #ifdef I2C_MODULE_0 -static const uint32_t HAL_LL_I2C0_BASE_ADDR = 0x40053000UL; +static const hal_ll_base_addr_t HAL_LL_I2C0_BASE_ADDR = 0x40053000UL; #endif #ifdef I2C_MODULE_1 -static const uint32_t HAL_LL_I2C1_BASE_ADDR = 0x40053100UL; +static const hal_ll_base_addr_t HAL_LL_I2C1_BASE_ADDR = 0x40053100UL; #endif /*!< @brief I2C pin structure. */ @@ -75,7 +75,7 @@ static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = { #ifdef I2C0_SCL_P205 {GPIO_P205, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 7}, #endif - + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; diff --git a/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt b/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt index 5692ad375a..31b7bc2909 100644 --- a/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt @@ -21,6 +21,7 @@ set(adc_pin_map "hal_ll_adc_pin_map/implementation_1") mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC ${adc_subimplementation} + ../../include/hal_ll_mstpcr.h ../../include/hal_ll_target.h #BEGIN ADC ../../include/adc/hal_ll_adc.h diff --git a/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c index 0dbe2479e5..d1e0c9cf73 100644 --- a/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c +++ b/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c @@ -44,6 +44,7 @@ #include "hal_ll_adc.h" #include "hal_ll_gpio.h" #include "hal_ll_adc_pin_map.h" +#include "hal_ll_mstpcr.h" #include "mcu.h" // ------------------------------------------------------------- PRIVATE MACROS @@ -61,7 +62,17 @@ /*!< @brief Helper macro for getting adequate module index number. */ #define hal_ll_adc_module_num(_module_num) (_module_num - 1) -// TODO +#define HAL_LL_ADC_ADCER_ADPCR_MASK (0x6UL) +#define HAL_LL_ADC_ADCER_ADPCR_12_bit (0) +#define HAL_LL_ADC_ADCER_ADPCR_14_bit (3) +#define HAL_LL_ADC_ADCSR_ADCS_MASK (0x6000UL) +#define HAL_LL_ADC_ADCSR_ADCS_SINGLE_SCAN (0) +#define HAL_LL_ADC_ADCSR_ADST (15) +#define HAL_LL_ADC0_ADHVREFCNT_HVSEL_MASK (0x3UL) +#define HAL_LL_ADC0_ADHVREFCNT_HVSEL_VREFH0 (0x1UL) +#define HAL_LL_ADC0_ADHVREFCNT_HVSEL_INTERNAL (0x2UL) + +#define HAL_LL_ADC0_ADHVREFCNT_REG_ADDR ( uint8_t * )0x4005C08AUL // -------------------------------------------------------------- PRIVATE TYPES /*!< @brief Local handle list. */ @@ -107,19 +118,21 @@ typedef struct { } hal_ll_adc_pin_id; // ---------------------------------------------------------- PRIVATE VARIABLES - /** * @brief Array of maps holding information for configuring hardware. */ static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[ADC_MODULE_COUNT + 1] = { #ifdef ADC_MODULE_0 - {ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + {ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_PIN_NC, + HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, #endif #ifdef ADC_MODULE_1 - {ADC1_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_1 ), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + {ADC1_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_1 ), HAL_LL_PIN_NC, + HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, #endif - {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_DEFAULT, 0xFF} + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, + 0, HAL_LL_ADC_RESOLUTION_DEFAULT, 0xFF} }; // ------------------------------------------------------------------ VARIABLES @@ -163,14 +176,6 @@ static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) */ static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); -/** - * @brief Enable ADC module gate clock. - * @param module_index - ADC HW module index -- 0,1,2... - * @param state - true/false - * @return None - */ -static void adc_clock_enable(uint8_t module_index , bool state ); - /** * @brief Initialize hardware ADC module. * @details Hardware initialization of Tiva. @@ -242,15 +247,18 @@ hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, return HAL_LL_ADC_SUCCESS; } -hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ){ +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) { hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; - hal_ll_adc_init(hal_ll_adc_hw_specifics_map_local); + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_adc_handle = + ( handle_t* )&hal_ll_adc_hw_specifics_map[ pin_check_result ].base; - hal_ll_module_state[ pin_check_result ].hal_ll_adc_handle = ( handle_t* )&hal_ll_adc_hw_specifics_map[ pin_check_result ].base; hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; return HAL_LL_ADC_SUCCESS; @@ -330,18 +338,15 @@ hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ){ return HAL_LL_MODULE_ERROR; } + // R_ADC0->ADCSR_b.ADCS = 0; // scan mode selection - single + base->adcsr &= ~HAL_LL_ADC_ADCSR_ADCS_MASK; + base->adcsr |= HAL_LL_ADC_ADCSR_ADCS_SINGLE_SCAN; - R_ADC0->ADCSR_b.ADCS = 0; // scan mode selection - single + // R_ADC0->ADCSR_b.ADST = 1; // start + set_reg_bit( &base->adcsr, HAL_LL_ADC_ADCSR_ADST); - R_ADC0->ADCSR_b.ADST = 1; // start - - *readDatabuf = ( uint16_t )R_ADC0->ADDR[0]; - - // base->sc1a = hal_ll_adc_hw_specifics_map_local->channel & HAL_LL_ADC_MASK_CHANNEL; - - // while ( 0 == ( base->sc1a & HAL_LL_ADC_COCO_FLAG ) ); - - // *readDatabuf = ( uint16_t )base->ra; + // *readDatabuf = ( uint16_t )R_ADC0->ADDR[0]; + *readDatabuf = ( uint16_t )base->addr[ hal_ll_adc_hw_specifics_map_local->channel ]; return HAL_LL_ADC_SUCCESS; } @@ -423,22 +428,42 @@ static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { return &hal_ll_adc_hw_specifics_map[ hal_ll_module_error ]; } -static void adc_clock_enable( uint8_t module_index , bool state ) {} - -static void hal_ll_adc_hw_init(hal_ll_adc_hw_specifics_map_t *map) {} +static void hal_ll_adc_hw_init( hal_ll_adc_hw_specifics_map_t *map ) { + // hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )map->base; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t* )hal_ll_adc_get_base_struct( map->base ); + + // R_ADC0->ADANSA_b->ANSA0 = 1; // select AN000 + if( 0 <= map->channel && 14 >= map->channel ) + set_reg_bit( &base->adansa[0], map->channel ); + else if( 16 <= map->channel && 25 >= map->channel ) + set_reg_bit( &base->adansa[1], map->channel ); + + // The only supported resolutions are 12-bit and 14-bit. 12-bit resolution is set by default. + base->adcer &= ~HAL_LL_ADC_ADCER_ADPCR_MASK; + if( HAL_ADC_12BIT_RES_VAL == map->resolution ) + base->adcer |= HAL_LL_ADC_ADCER_ADPCR_12_bit; + else if( HAL_ADC_14BIT_RES_VAL == map->resolution ) + base->adcer |= HAL_LL_ADC_ADCER_ADPCR_14_bit; + + // Voltage reference settings. + clear_reg_bits( HAL_LL_ADC0_ADHVREFCNT_REG_ADDR, HAL_LL_ADC0_ADHVREFCNT_HVSEL_MASK); + if( HAL_LL_ADC_VREF_EXTERNAL == map->vref_input ) + set_reg_bits( HAL_LL_ADC0_ADHVREFCNT_REG_ADDR, HAL_LL_ADC0_ADHVREFCNT_HVSEL_VREFH0 ); + else if( HAL_LL_ADC_VREF_INTERNAL == map->vref_input ) { + set_reg_bits( HAL_LL_ADC0_ADHVREFCNT_REG_ADDR, HAL_LL_ADC0_ADHVREFCNT_HVSEL_MASK ); + Delay_us(5); + set_reg_bits( HAL_LL_ADC0_ADHVREFCNT_REG_ADDR, HAL_LL_ADC0_ADHVREFCNT_HVSEL_INTERNAL ); + } +} static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { - R_PFS->PORT[0].PIN[0].PmnPFS_b.PDR = 1; // output - R_PFS->PORT[0].PIN[0].PmnPFS_b.ASEL = 1; // analog - R_PFS->PORT[0].PIN[0].PmnPFS_b.PMR = 1; // peripheral - - R_MSTP->MSTPCRD_b.MSTPD16 = 0; // unstop ADC0 module - - R_ADC0->ADANSA_b->ANSA0 = 1; // select AN000 - R_ADC0->ADCER_b.ADPRC = 3; // 14-bit resolution + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD16_POS ); + hal_ll_adc_hw_init( map ); } // ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c index 482e67cbe5..c9967f464d 100644 --- a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c @@ -90,31 +90,31 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU /*!< @brief I2C register structure */ typedef struct { - hal_ll_base_addr_t iccr1; // IIC0.ICCR1 4005 3000h, IIC1.ICCR1 4005 3100h - hal_ll_base_addr_t iccr2; // IIC0.ICCR2 4005 3001h, IIC1.ICCR2 4005 3101h - hal_ll_base_addr_t icmr1; // IIC0.ICCR2 4005 3002h, IIC1.ICCR2 4005 3102h - hal_ll_base_addr_t icmr2; // IIC0.ICCR2 4005 3003h, IIC1.ICCR2 4005 3103h - hal_ll_base_addr_t icmr3; // IIC0.ICCR2 4005 3004h, IIC1.ICCR2 4005 3104h - hal_ll_base_addr_t icfer; // IIC0.ICCR2 4005 3005h, IIC1.ICCR2 4005 3105h - hal_ll_base_addr_t icser; // IIC0.ICCR2 4005 3006h, IIC1.ICCR2 4005 3106h - hal_ll_base_addr_t icier; // IIC0.ICCR2 4005 3007h, IIC1.ICCR2 4005 3107h - hal_ll_base_addr_t icsr1; // IIC0.ICCR2 4005 3008h, IIC1.ICCR2 4005 3108h - hal_ll_base_addr_t icsr2; // IIC0.ICCR2 4005 3009h, IIC1.ICCR2 4005 3109h - hal_ll_base_addr_t sarl[3]; // ? - hal_ll_base_addr_t saru[3]; // ? - hal_ll_base_addr_t icbrl; // IIC0.ICCR2 4005 3010h, IIC1.ICCR2 4005 3110h - hal_ll_base_addr_t icbrh; // IIC0.ICCR2 4005 3011h, IIC1.ICCR2 4005 3111h - hal_ll_base_addr_t icdrt; // IIC0.ICCR2 4005 3012h, IIC1.ICCR2 4005 3112h - hal_ll_base_addr_t icdrr; // IIC0.ICCR2 4005 3013h, IIC1.ICCR2 4005 3113h - // hal_ll_base_addr_t icdrs; // ? - hal_ll_base_addr_t reserved[2]; - hal_ll_base_addr_t icwur; // IIC0.ICCR2 4005 3016h // ? , IIC1.ICCR2 4005 3109h - hal_ll_base_addr_t icwur2; // IIC0.ICCR2 4005 3017h // ? , IIC1.ICCR2 4005 3109h + uint8_t iccr1; // IIC0.ICCR1 4005 3000h, IIC1.ICCR1 4005 3100h + uint8_t iccr2; // IIC0.ICCR2 4005 3001h, IIC1.ICCR2 4005 3101h + uint8_t icmr1; // IIC0.ICCR2 4005 3002h, IIC1.ICCR2 4005 3102h + uint8_t icmr2; // IIC0.ICCR2 4005 3003h, IIC1.ICCR2 4005 3103h + uint8_t icmr3; // IIC0.ICCR2 4005 3004h, IIC1.ICCR2 4005 3104h + uint8_t icfer; // IIC0.ICCR2 4005 3005h, IIC1.ICCR2 4005 3105h + uint8_t icser; // IIC0.ICCR2 4005 3006h, IIC1.ICCR2 4005 3106h + uint8_t icier; // IIC0.ICCR2 4005 3007h, IIC1.ICCR2 4005 3107h + uint8_t icsr1; // IIC0.ICCR2 4005 3008h, IIC1.ICCR2 4005 3108h + uint8_t icsr2; // IIC0.ICCR2 4005 3009h, IIC1.ICCR2 4005 3109h + uint8_t sarl[3]; // ? + uint8_t saru[3]; // ? + uint8_t icbrl; // IIC0.ICCR2 4005 3010h, IIC1.ICCR2 4005 3110h + uint8_t icbrh; // IIC0.ICCR2 4005 3011h, IIC1.ICCR2 4005 3111h + uint8_t icdrt; // IIC0.ICCR2 4005 3012h, IIC1.ICCR2 4005 3112h + uint8_t icdrr; // IIC0.ICCR2 4005 3013h, IIC1.ICCR2 4005 3113h + // uint8_t icdrs; // ? + uint8_t reserved[2]; + uint8_t icwur; // IIC0.ICCR2 4005 3016h // ? , IIC1.ICCR2 4005 3109h + uint8_t icwur2; // IIC0.ICCR2 4005 3017h // ? , IIC1.ICCR2 4005 3109h } hal_ll_i2c_base_handle_t; /*!< @brief I2C hw specific structure */ typedef struct { - uint32_t base; + hal_ll_base_addr_t base; hal_ll_pin_name_t module_index; hal_ll_i2c_pins_t pins; uint32_t speed; From 4f911305699f0834ca5c852a249d78c190d315aa Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Mon, 21 Jul 2025 09:47:11 +0200 Subject: [PATCH 21/62] ADC implementation finished --- .../RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 84 ++++++++++++++++++- .../implementation_1/hal_ll_adc_pin_map.h | 6 ++ .../src/adc/implementation_1/hal_ll_adc.c | 35 ++++---- 3 files changed, 109 insertions(+), 16 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h index d9d304da46..78af813508 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -49,6 +49,9 @@ #define ADC_MODULE_0 (1) #define ADC_AN000_P000 +#define ADC_AN007_P012 +#define ADC_AN018_P502 + #define ADC_MODULE_COUNT 1 //EOF ADC @@ -163,7 +166,86 @@ #define __P413_CN #define __P414_CN #define __P415_CN -// TODO Esma ports 5-9 +#define __P500_CN +#define __P501_CN +#define __P502_CN +#define __P503_CN +#define __P504_CN +#define __P505_CN +#define __P506_CN +#define __P507_CN +#define __P508_CN +#define __P509_CN +#define __P510_CN +#define __P511_CN +#define __P512_CN +#define __P513_CN +#define __P514_CN +#define __P515_CN +#define __P600_CN +#define __P601_CN +#define __P602_CN +#define __P603_CN +#define __P604_CN +#define __P605_CN +#define __P606_CN +#define __P607_CN +#define __P608_CN +#define __P609_CN +#define __P610_CN +#define __P611_CN +#define __P612_CN +#define __P613_CN +#define __P614_CN +#define __P615_CN +#define __P700_CN +#define __P701_CN +#define __P702_CN +#define __P703_CN +#define __P704_CN +#define __P705_CN +#define __P706_CN +#define __P707_CN +#define __P708_CN +#define __P709_CN +#define __P710_CN +#define __P711_CN +#define __P712_CN +#define __P713_CN +#define __P714_CN +#define __P715_CN +#define __P800_CN +#define __P801_CN +#define __P802_CN +#define __P803_CN +#define __P804_CN +#define __P805_CN +#define __P806_CN +#define __P807_CN +#define __P808_CN +#define __P809_CN +#define __P810_CN +#define __P811_CN +#define __P812_CN +#define __P813_CN +#define __P814_CN +#define __P815_CN +#define __P900_CN +#define __P901_CN +#define __P902_CN +#define __P903_CN +#define __P904_CN +#define __P905_CN +#define __P906_CN +#define __P907_CN +#define __P908_CN +#define __P909_CN +#define __P910_CN +#define __P911_CN +#define __P912_CN +#define __P913_CN +#define __P914_CN +#define __P915_CN #define __PORT_0_CN #define __PORT_1_CN diff --git a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h index 661ee23adb..80fa0d3f97 100644 --- a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h +++ b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h @@ -110,6 +110,12 @@ static const hal_ll_pin_channel_list_t hal_ll_analog_in_register_list[] = #ifdef ADC_AN000_P000 {GPIO_P000, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_0}, #endif + #ifdef ADC_AN007_P012 + {GPIO_P012, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC_AN018_P502 + {GPIO_P502, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_18}, + #endif { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR } //------------ END diff --git a/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c index d1e0c9cf73..51d754136a 100644 --- a/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c +++ b/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c @@ -153,11 +153,13 @@ static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local * Returns pre-defined module index from pin maps, if pin * is adequate. */ -static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, + hal_ll_adc_handle_register_t *handle_map ); /** * @brief Maps new-found module specific values. - * @details Maps pin name, register address and channel from analog register list to module in hardware specific map. + * @details Maps pin name, register address and channel from + * analog register list to module in hardware specific map. * @param[in] module_index ADC HW module index -- 0,1,2... Index in hal_ll_adc_hw_specifics_map, * destination of copying. * @param[in] index Pointer with ADC pin map index value. Index in hal_ll_analog_in_register_list @@ -332,27 +334,27 @@ void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value){ hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ){ hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); low_level_handle = hal_ll_adc_get_handle; - hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base; if( low_level_handle->hal_ll_adc_handle == NULL ) { return HAL_LL_MODULE_ERROR; } - // R_ADC0->ADCSR_b.ADCS = 0; // scan mode selection - single + // Single scan mode. base->adcsr &= ~HAL_LL_ADC_ADCSR_ADCS_MASK; base->adcsr |= HAL_LL_ADC_ADCSR_ADCS_SINGLE_SCAN; - // R_ADC0->ADCSR_b.ADST = 1; // start + // Start conversion. set_reg_bit( &base->adcsr, HAL_LL_ADC_ADCSR_ADST); - // *readDatabuf = ( uint16_t )R_ADC0->ADDR[0]; *readDatabuf = ( uint16_t )base->addr[ hal_ll_adc_hw_specifics_map_local->channel ]; return HAL_LL_ADC_SUCCESS; } void hal_ll_adc_close( handle_t *handle ){ - hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = + hal_ll_get_specifics(hal_ll_adc_get_module_state_address); low_level_handle = hal_ll_adc_get_handle; if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { @@ -375,7 +377,8 @@ void hal_ll_adc_close( handle_t *handle ){ static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) { - static const uint16_t adc_map_size = ( sizeof( hal_ll_analog_in_register_list ) / sizeof( hal_ll_pin_channel_list_t ) ); + static const uint16_t adc_map_size = + ( sizeof( hal_ll_analog_in_register_list ) / sizeof( hal_ll_pin_channel_list_t ) ); uint16_t pin_index = 0; uint8_t index_counter = 0; uint8_t hal_ll_module_id = 0; @@ -411,8 +414,10 @@ static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { // Map new pins - hal_ll_adc_hw_specifics_map[module_index].pin = hal_ll_analog_in_register_list[ index->pin_an[module_index] ].pin; - hal_ll_adc_hw_specifics_map[module_index].channel = hal_ll_analog_in_register_list[ index->pin_an[module_index] ].channel; + hal_ll_adc_hw_specifics_map[module_index].pin = + hal_ll_analog_in_register_list[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = + hal_ll_analog_in_register_list[ index->pin_an[module_index] ].channel; } static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { @@ -429,16 +434,15 @@ static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { } static void hal_ll_adc_hw_init( hal_ll_adc_hw_specifics_map_t *map ) { - // hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )map->base; hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t* )hal_ll_adc_get_base_struct( map->base ); - // R_ADC0->ADANSA_b->ANSA0 = 1; // select AN000 + // Select channel. if( 0 <= map->channel && 14 >= map->channel ) set_reg_bit( &base->adansa[0], map->channel ); else if( 16 <= map->channel && 25 >= map->channel ) - set_reg_bit( &base->adansa[1], map->channel ); + set_reg_bit( &base->adansa[1], map->channel - 16 ); - // The only supported resolutions are 12-bit and 14-bit. 12-bit resolution is set by default. + // Resolution settings. NOTE: The only supported resolutions are 12-bit and 14-bit. base->adcer &= ~HAL_LL_ADC_ADCER_ADPCR_MASK; if( HAL_ADC_12BIT_RES_VAL == map->resolution ) base->adcer |= HAL_LL_ADC_ADCER_ADPCR_12_bit; @@ -451,7 +455,7 @@ static void hal_ll_adc_hw_init( hal_ll_adc_hw_specifics_map_t *map ) { set_reg_bits( HAL_LL_ADC0_ADHVREFCNT_REG_ADDR, HAL_LL_ADC0_ADHVREFCNT_HVSEL_VREFH0 ); else if( HAL_LL_ADC_VREF_INTERNAL == map->vref_input ) { set_reg_bits( HAL_LL_ADC0_ADHVREFCNT_REG_ADDR, HAL_LL_ADC0_ADHVREFCNT_HVSEL_MASK ); - Delay_us(5); + Delay_us(5); // Documentation specifies a small delay is required. set_reg_bits( HAL_LL_ADC0_ADHVREFCNT_REG_ADDR, HAL_LL_ADC0_ADHVREFCNT_HVSEL_INTERNAL ); } } @@ -461,6 +465,7 @@ static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), hal_ll_gpio_pin_mask( map->pin ) ); + // Enable ADC operation. clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD16_POS ); hal_ll_adc_hw_init( map ); From 276209943306f91232a54812e4c38defb88c5cae Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Mon, 21 Jul 2025 16:30:35 +0200 Subject: [PATCH 22/62] RA4M1 PWM proof of concept --- .../RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 3 + .../mikroe/renesas/include/hal_ll_pin_names.h | 12 +- .../implementation_1/hal_ll_tim_pin_map.h | 347 +-------- .../src/tim/implementation_1/hal_ll_tim.c | 684 +++++++----------- tests/pwm/default/main.c | 142 +++- 5 files changed, 385 insertions(+), 803 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h index 78af813508..d77b696227 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -81,6 +81,9 @@ //EOF SPI //TIM +#define TIM_MODULE_4 5 + +#define TIM4_P302 #define TIM_MODULE_COUNT 12 //EOF TIM diff --git a/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h b/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h index ceecd4deb7..d608a109ba 100644 --- a/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h +++ b/targets/arm/mikroe/renesas/include/hal_ll_pin_names.h @@ -480,27 +480,27 @@ extern "C"{ #define P509 GPIO_P509 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P509! #endif #ifdef __P510_CN -#define GPIO_P510(0x5A) +#define GPIO_P510 (0x5A) #define P510 GPIO_P510 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P510! #endif #ifdef __P511_CN -#define GPIO_P511(0x5B) +#define GPIO_P511 (0x5B) #define P511 GPIO_P511 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P511! #endif #ifdef __P512_CN -#define GPIO_P512(0x5C) +#define GPIO_P512 (0x5C) #define P512 GPIO_P512 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P512! #endif #ifdef __P513_CN -#define GPIO_P513(0x5D) +#define GPIO_P513 (0x5D) #define P513 GPIO_P513 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P513! #endif #ifdef __P514_CN -#define GPIO_P514(0x5E) +#define GPIO_P514 (0x5E) #define P514 GPIO_P514 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P514! #endif #ifdef __P515_CN -#define GPIO_P515(0x5F) +#define GPIO_P515 (0x5F) #define P515 GPIO_P515 // Notice: Will be removed in one of the upcoming releases. Use GPIO_P515! #endif diff --git a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h index 564031e1be..9d1725791a 100644 --- a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h +++ b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h @@ -56,37 +56,8 @@ extern "C"{ #define hal_ll_tim_module_num(_module_num) (_module_num - 1) /*!< @brief TIMER module base addresses. */ -#ifdef TIM_MODULE_0 -static const hal_ll_base_addr_t HAL_LL_TIM0_BASE_ADDR = 0x40030000; -#endif -#ifdef TIM_MODULE_1 -static const hal_ll_base_addr_t HAL_LL_TIM1_BASE_ADDR = 0x40031000; -#endif -#ifdef TIM_MODULE_2 -static const hal_ll_base_addr_t HAL_LL_TIM2_BASE_ADDR = 0x40032000; -#endif -#ifdef TIM_MODULE_3 -static const hal_ll_base_addr_t HAL_LL_TIM3_BASE_ADDR = 0x40033000; -#endif #ifdef TIM_MODULE_4 -static const hal_ll_base_addr_t HAL_LL_TIM4_BASE_ADDR = 0x40034000; -#endif -#ifdef TIM_MODULE_5 -static const hal_ll_base_addr_t HAL_LL_TIM5_BASE_ADDR = 0x40035000; -#endif -#ifdef TIM_MODULE_6 -#ifdef TM4C129 -static const hal_ll_base_addr_t HAL_LL_TIM6_BASE_ADDR = 0x400E0000; -#else -static const hal_ll_base_addr_t HAL_LL_TIM6_BASE_ADDR = 0x4003E000; -#endif -#endif -#ifdef TIM_MODULE_7 -#ifdef TM4C129 -static const hal_ll_base_addr_t HAL_LL_TIM7_BASE_ADDR = 0x400E1000; -#else -static const hal_ll_base_addr_t HAL_LL_TIM7_BASE_ADDR = 0x4003E100; -#endif +static const hal_ll_base_addr_t HAL_LL_TIM4_BASE_ADDR = 0x40078400; #endif /*!< @brief TIM pin structure. */ @@ -98,319 +69,11 @@ typedef struct { } hal_ll_tim_pin_map_t; /*!< TIM pins. */ -static const hal_ll_tim_pin_map_t _tim_map[] = { - #ifdef TIM0_CCP0_PB6_AF7 - {GPIO_PB6, HAL_LL_TIM0_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_0)}, - #endif - #ifdef TIM0_CCP0_PF0_AF7 - {GPIO_PF0, HAL_LL_TIM0_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_0)}, - #endif - #ifdef TIM0_CCP1_PB7_AF7 - {GPIO_PB7, HAL_LL_TIM0_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_0)}, - #endif - #ifdef TIM0_CCP1_PF1_AF7 - {GPIO_PF1, HAL_LL_TIM0_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_0)}, - #endif - #ifdef TIM1_CCP0_PB4_AF7 - {GPIO_PB4, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM1_CCP0_PF2_AF7 - {GPIO_PF2, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM1_CCP1_PB5_AF7 - {GPIO_PB5, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM1_CCP1_PF3_AF7 - {GPIO_PF3, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM2_CCP0_PB0_AF7 - {GPIO_PB0, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, - #endif - #ifdef TIM2_CCP0_PF4_AF7 - {GPIO_PF4, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, - #endif - #ifdef TIM2_CCP1_PB1_AF7 - {GPIO_PB1, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, - #endif - #ifdef TIM3_CCP0_PB2_AF7 - {GPIO_PB2, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM3_CCP1_PB3_AF7 - {GPIO_PB3, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM4_CCP0_PC0_AF7 - {GPIO_PC0, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM4_CCP0_PG0_AF7 - {GPIO_PG0, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM4_CCP1_PC1_AF7 - {GPIO_PC1, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM4_CCP1_PG1_AF7 - {GPIO_PG1, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM5_CCP0_PC2_AF7 - {GPIO_PC2, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, - #endif - #ifdef TIM5_CCP0_PG2_AF7 - {GPIO_PG2, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, - #endif - #ifdef TIM5_CCP1_PC3_AF7 - {GPIO_PC3, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, - #endif - #ifdef TIM5_CCP1_PG3_AF7 - {GPIO_PG3, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, - #endif - #ifdef TIM1_CCP0_PJ0_AF7 - {GPIO_PJ0, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM1_CCP1_PJ1_AF7 - {GPIO_PJ1, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM2_CCP0_PJ2_AF7 - {GPIO_PJ2, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, - #endif - #ifdef TIM2_CCP1_PF5_AF7 - {GPIO_PF5, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, - #endif - #ifdef TIM3_CCP0_PF6_AF7 - {GPIO_PF6, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM3_CCP1_PF7_AF7 - {GPIO_PF7, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM0_CCP0_PL0_AF7 - {GPIO_PL0, HAL_LL_TIM0_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_0)}, - #endif - #ifdef TIM0_CCP1_PL1_AF7 - {GPIO_PL1, HAL_LL_TIM0_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_0)}, - #endif - #ifdef TIM1_CCP0_PL2_AF7 - {GPIO_PL2, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM1_CCP1_PL3_AF7 - {GPIO_PL3, HAL_LL_TIM1_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM2_CCP0_PL4_AF7 - {GPIO_PL4, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, - #endif - #ifdef TIM2_CCP1_PJ3_AF7 - {GPIO_PJ3, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, - #endif - #ifdef TIM2_CCP1_PL5_AF7 - {GPIO_PL5, HAL_LL_TIM2_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_2)}, - #endif - #ifdef TIM3_CCP0_PJ4_AF7 - {GPIO_PJ4, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM3_CCP0_PL6_AF7 - {GPIO_PL6, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM3_CCP1_PJ5_AF7 - {GPIO_PJ5, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM3_CCP1_PL7_AF7 - {GPIO_PL7, HAL_LL_TIM3_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM4_CCP0_PM0_AF7 - {GPIO_PM0, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM4_CCP0_PP0_AF7 - {GPIO_PP0, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM4_CCP1_PM1_AF7 - {GPIO_PM1, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM4_CCP1_PP1_AF7 - {GPIO_PP1, HAL_LL_TIM4_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM5_CCP0_PM2_AF7 - {GPIO_PM2, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, - #endif - #ifdef TIM5_CCP0_PP2_AF7 - {GPIO_PP2, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, - #endif - #ifdef TIM5_CCP1_PM3_AF7 - {GPIO_PM3, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, - #endif - #ifdef TIM5_CCP1_PP3_AF7 - {GPIO_PP3, HAL_LL_TIM5_BASE_ADDR, 7, hal_ll_tim_module_num(TIM_MODULE_5)}, - #endif - #ifdef TIM0_CCP0_PA0_AF3 - {GPIO_PA0, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, - #endif - #ifdef TIM0_CCP0_PD0_AF3 - {GPIO_PD0, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, - #endif - #ifdef TIM0_CCP0_PL4_AF3 - {GPIO_PL4, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, - #endif - #ifdef TIM0_CCP1_PA1_AF3 - {GPIO_PA1, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, - #endif - #ifdef TIM0_CCP1_PD1_AF3 - {GPIO_PD1, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, - #endif - #ifdef TIM0_CCP1_PL5_AF3 - {GPIO_PL5, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, - #endif - #ifdef TIM1_CCP0_PA2_AF3 - {GPIO_PA2, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM1_CCP0_PD2_AF3 - {GPIO_PD2, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM1_CCP0_PL6_AF3 - {GPIO_PL6, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM1_CCP1_PA3_AF3 - {GPIO_PA3, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM1_CCP1_PD3_AF3 - {GPIO_PD3, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM1_CCP1_PL7_AF3 - {GPIO_PL7, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM2_CCP0_PA4_AF3 - {GPIO_PA4, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_2)}, - #endif - #ifdef TIM2_CCP0_PM0_AF3 - {GPIO_PM0, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_2)}, - #endif - #ifdef TIM2_CCP1_PA5_AF3 - {GPIO_PA5, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_2)}, - #endif - #ifdef TIM2_CCP1_PM1_AF3 - {GPIO_PM1, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_2)}, - #endif - #ifdef TIM3_CCP0_PA6_AF3 - {GPIO_PA6, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM3_CCP0_PD4_AF3 - {GPIO_PD4, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM3_CCP0_PM2_AF3 - {GPIO_PM2, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM3_CCP1_PA7_AF3 - {GPIO_PA7, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM3_CCP1_PD5_AF3 - {GPIO_PD5, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM3_CCP1_PM3_AF3 - {GPIO_PM3, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM4_CCP0_PB0_AF3 - {GPIO_PB0, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM4_CCP0_PD6_AF3 - {GPIO_PD6, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM4_CCP0_PM4_AF3 - {GPIO_PM4, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM4_CCP1_PB1_AF3 - {GPIO_PB1, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM4_CCP1_PD7_AF3 - {GPIO_PD7, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM4_CCP1_PM5_AF3 - {GPIO_PM5, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM5_CCP0_PB2_AF3 - {GPIO_PB2, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_5)}, - #endif - #ifdef TIM5_CCP0_PM6_AF3 - {GPIO_PM6, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_5)}, - #endif - #ifdef TIM5_CCP1_PB3_AF3 - {GPIO_PB3, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_5)}, - #endif - #ifdef TIM5_CCP1_PM7_AF3 - {GPIO_PM7, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_5)}, - #endif - #ifdef TIM0_CCP0_PR4_AF3 - {GPIO_PR4, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, - #endif - #ifdef TIM0_CCP1_PR5_AF3 - {GPIO_PR5, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0)}, - #endif - #ifdef TIM1_CCP0_PR6_AF3 - {GPIO_PR6, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM1_CCP1_PR7_AF3 - {GPIO_PR7, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, - #endif - #ifdef TIM2_CCP0_PS0_AF3 - {GPIO_PS0, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_2)}, - #endif - #ifdef TIM2_CCP1_PS1_AF3 - {GPIO_PS1, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_2)}, - #endif - #ifdef TIM3_CCP0_PS2_AF3 - {GPIO_PS2, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM3_CCP1_PS3_AF3 - {GPIO_PS3, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif - #ifdef TIM4_CCP0_PS4_AF3 - {GPIO_PS4, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM4_CCP1_PS5_AF3 - {GPIO_PS5, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, - #endif - #ifdef TIM5_CCP0_PS6_AF3 - {GPIO_PS6, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_5)}, - #endif - #ifdef TIM5_CCP1_PS7_AF3 - {GPIO_PS7, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_5)}, - #endif - #ifdef TIM6_CCP0_PB6_AF3 - {GPIO_PB6, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_6)}, - #endif - #ifdef TIM6_CCP0_PP0_AF5 - {GPIO_PP0, HAL_LL_TIM6_BASE_ADDR, 5, hal_ll_tim_module_num(TIM_MODULE_6)}, - #endif - #ifdef TIM6_CCP0_PQ0_AF3 - {GPIO_PQ0, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_6)}, - #endif - #ifdef TIM6_CCP0_PT0_AF3 - {GPIO_PT0, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_6)}, - #endif - #ifdef TIM6_CCP1_PB7_AF3 - {GPIO_PB7, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_6)}, - #endif - #ifdef TIM6_CCP1_PP1_AF5 - {GPIO_PP1, HAL_LL_TIM6_BASE_ADDR, 5, hal_ll_tim_module_num(TIM_MODULE_6)}, - #endif - #ifdef TIM6_CCP1_PQ1_AF3 - {GPIO_PQ1, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_6)}, - #endif - #ifdef TIM6_CCP1_PT1_AF3 - {GPIO_PT1, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_6)}, - #endif - #ifdef TIM7_CCP0_PC4_AF3 - {GPIO_PC4, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_7)}, - #endif - #ifdef TIM7_CCP0_PQ2_AF3 - {GPIO_PQ2, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_7)}, - #endif - #ifdef TIM7_CCP0_PT2_AF3 - {GPIO_PT2, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_7)}, - #endif - #ifdef TIM7_CCP1_PC5_AF3 - {GPIO_PC5, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_7)}, - #endif - #ifdef TIM7_CCP1_PQ3_AF3 - {GPIO_PQ3, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_7)}, - #endif - #ifdef TIM7_CCP1_PT3_AF3 - {GPIO_PT3, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_7)}, +static const hal_ll_tim_pin_map_t hal_ll_tim_pin_map[] = { + #ifdef TIM4_P302 + {GPIO_P302, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } }; diff --git a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c index 5f3a288505..c341054144 100644 --- a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c @@ -41,14 +41,17 @@ * @brief TIM HAL LOW LEVEL layer implementation. */ -#include "hal_ll_tim.h" #include "hal_ll_gpio.h" +#include "hal_ll_tim.h" #include "hal_ll_tim_pin_map.h" +#include "mcu.h" /*!< @brief Local handle list */ -static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ] = {(handle_t *)NULL, (handle_t *)NULL, false}; +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; // ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ + /*!< @brief Helper macro for getting module specific control register structure */ #define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) @@ -62,236 +65,124 @@ static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COU #define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base - // -------------------------------------------------------------- PRIVATE TYPES -/*!< @brief TIM hw specific error values. */ -typedef enum { - HAL_LL_TIM_SUCCESS = 0, - HAL_LL_TIM_MODULE_ERROR, - HAL_LL_TIM_WRONG_PIN, - - HAL_LL_TIM_ERROR = (-1) -} hal_ll_tim_err_t; +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t todo; +} hal_ll_tim_base_handle_t; -/*!< @brief TIM hw specific config structure. */ -typedef struct { +/*!< @brief TIM pin structure */ +typedef struct +{ hal_ll_pin_name_t pin; - uint8_t pin_parity; + hal_ll_channel_t channel; uint32_t af; } hal_ll_tim_t; -/*!< @brief TIM hw specific pin parity pointers to functions. */ -typedef struct { - void ( *mapped_function_duty )( struct hal_ll_tim_base_handle_t *, uint32_t, uint32_t ); - void ( *mapped_function_signal_start )( struct hal_ll_tim_base_handle_t * ); - void ( *mapped_function_signal_stop )( struct hal_ll_tim_base_handle_t * ); - void ( *mapped_function_period )( struct hal_ll_tim_base_handle_t *, uint32_t ); - void ( *mapped_function_hw_init_control )( struct hal_ll_tim_base_handle_t * ); - void ( *mapped_function_hw_init_pwm_mode )( struct hal_ll_tim_base_handle_t * ); -} hal_ll_tim_functions; - -/*!< @brief TIM hw specific structure. */ -typedef struct { - hal_ll_base_addr_t base; - hal_ll_tim_t config; - uint32_t max_period; - uint32_t freq_hz; - hal_ll_pin_name_t module_index; - /* NOTE Added pointer function structure. - * Chips have two CCP's. - */ - hal_ll_tim_functions mapped_functions; +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; } hal_ll_tim_hw_specifics_map_t; -typedef struct { +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, -} hal_ll_tim_base_handle_t; + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; // ------------------------------------------------------------------ VARIABLES - /*!< @brief TIM specific info */ -static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[ TIM_MODULE_COUNT + 1 ] = { - #ifdef TIM_MODULE_0 - {HAL_LL_TIM0_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_0}, - #endif +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ #ifdef TIM_MODULE_1 - {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1}, + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, #endif #ifdef TIM_MODULE_2 - {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2}, + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, #endif #ifdef TIM_MODULE_3 - {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3}, + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, #endif #ifdef TIM_MODULE_4 - {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4}, + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, #endif #ifdef TIM_MODULE_5 - {HAL_LL_TIM5_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_5}, + {HAL_LL_TIM5_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_5 - 1}, #endif - #ifdef TIM_MODULE_6 - {HAL_LL_TIM6_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_6}, + #ifdef TIM_MODULE_8 + {HAL_LL_TIM8_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_8 - 1}, #endif - #ifdef TIM_MODULE_7 - {HAL_LL_TIM7_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_TIM_CCP_0, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_7}, + #ifdef TIM_MODULE_9 + {HAL_LL_TIM9_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_9 - 1}, + #endif + #ifdef TIM_MODULE_10 + {HAL_LL_TIM10_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_10 - 1}, + #endif + #ifdef TIM_MODULE_11 + {HAL_LL_TIM11_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_11 - 1}, + #endif + #ifdef TIM_MODULE_12 + {HAL_LL_TIM12_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_12 - 1}, + #endif + #ifdef TIM_MODULE_13 + {HAL_LL_TIM13_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_13 - 1}, + #endif + #ifdef TIM_MODULE_14 + {HAL_LL_TIM14_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_14 - 1}, + #endif + #ifdef TIM_MODULE_15 + {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, + #endif + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, #endif {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} }; -/*!< @brief Global handle variables used in functions. */ +/*!< @brief Global handle variables used in functions */ static volatile hal_ll_tim_handle_register_t *low_level_handle; static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; -// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS - -/** - * @brief Sets TIM pin alternate function state. - * - * Sets adequate value for alternate function settings. - * This function must be called if TIM is to work. - * Based on value of hal_ll_state, alternate functions can be - * set or cleared. - * - * @param[in] map - Object specific context handler. - * @param[in] hal_ll_state - Init/De-init. - * @return none - * - */ -static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); - -/** - * @brief Maps new-found module specific values. - * - * Maps pin names and alternate function values for - * TIM pin. - * - * @param[in] module_index - TIM HW module index -- 0,1,2... - * @param[in] index - Index from the TIM pin map. - * - * @return None - */ -static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); - -/** - * @brief Check if pin is adequate. - * - * Checks tim pin the user has passed with pre-defined - * pin in tim map. - * - * @param[in] pin - TIM pre-defined pin name. - * @param[out] index - Output parameter which is used to return pin index within the PIN map. - * @param[out] *handle_map - TIMER HAL low lever handle register. - * @return hal_ll_pin_name_t Module index based on pin. - * - * Returns pre-defined module index from pin maps, if pin - * is adequate. - */ -static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); - -/** - * @brief Get local hardware specific map. - * - * Checks handle value and returns address of adequate - * hal_ll_tim_hw_specifics_map array index. - * - * @param[in] handle - Object specific context handler. - * @return hal_ll_tim_hw_specifics_map_t Map address. - * - * Returns pre-defined map index address based on handle value, - * if handle is adequate. - */ -static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); - -/** - * @brief Full TIM module initialization procedure. - * - * Initializes TIM module on hardware level, based on beforehand - * set configuration and module handler. Sets adequate pin alternate functions. - * Initializes module clock. - * - * @param[in] *map - Object specific context handler. - * @return none - * - */ -static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); - -/** - * @brief Sets the TIM PWM period register and prescaler values. - * - * Using max_period from the map parameter it calculates values - * for the period and prescaler registers and modifies them. - * - * @param[in] *map - Object specific context handler. - * - * @return None - */ -static void _hal_ll_tim_set_period( hal_ll_tim_hw_specifics_map_t *map ); +static bool HAL_LL_TIM_IS_COMPLEMENTARY; +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS /** * @brief Enable TIM module gate clock. - * @param[in] *map - Object specific context handler. - * @param[in] hal_ll_state - True(enable clock)/False(disable clock). - * + * @param base - TIM module base + * address * @return None */ -static void _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_t* map, bool hal_ll_state ); - -/** - * @brief Enables or disables TIM module 0 clock. - * @param[in] hal_ll_state - True(enable clock)/False(disable clock). - * @return none - */ -static void _hal_ll_tim0_set_clock( bool hal_ll_state ); - -/** - * @brief Enables or disables TIM module 1 clock. - * @param[in] hal_ll_state - True(enable clock)/False(disable clock). - * @return none - */ -static void _hal_ll_tim1_set_clock( bool hal_ll_state ); - -/** - * @brief Enables or disables TIM module 2 clock. - * @param[in] hal_ll_state - True(enable clock)/False(disable clock). - * @return none - */ -static void _hal_ll_tim2_set_clock( bool hal_ll_state ); - -/** - * @brief Enables or disables TIM module 3 clock. - * @param[in] hal_ll_state - True(enable clock)/False(disable clock). - * @return none - */ -static void _hal_ll_tim3_set_clock( bool hal_ll_state ); - -/** - * @brief Enables or disables TIM module 4 clock. - * @param[in] hal_ll_state - True(enable clock)/False(disable clock). - * @return none - */ -static void _hal_ll_tim4_set_clock( bool hal_ll_state ); - -/** - * @brief Enables or disables TIM module 5 clock. - * @param[in] hal_ll_state - True(enable clock)/False(disable clock). - * @return none - */ -static void _hal_ll_tim5_set_clock( bool hal_ll_state ); +static void hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); /** - * @brief Enables or disables TIM module 6 clock. - * @param[in] hal_ll_state - True(enable clock)/False(disable clock). - * @return none + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source */ -static void _hal_ll_tim6_set_clock( bool hal_ll_state ); +static uint32_t hal_ll_tim_clock_source( uint8_t selector ); /** - * @brief Enables or disables TIM module 7 clock. - * @param[in] hal_ll_state - True(enable clock)/False(disable clock). - * @return none + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. */ -static void _hal_ll_tim7_set_clock( bool hal_ll_state ); +static uint32_t hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); /** * @brief Initialize TIM module on hardware level. @@ -299,202 +190,99 @@ static void _hal_ll_tim7_set_clock( bool hal_ll_state ); * Initializes TIM module on hardware level, based on beforehand * set configuration and module handler. * - * @param[in] *map - Object specific context handler. + * @param map - Object specific context handler. * @return none * */ -static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); +static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); /** - * @brief Map adequate function addresses. - * - * Function maps adequate function addresses based on] - * pin parity. - * - * @param[in] hal_ll_module_id - Module index. - * @param[in] pin_parity - CCP value (0/1). - * - * @return none - * - */ -static inline void map_pointer_functions( uint8_t hal_ll_module_id, uint8_t pin_parity ); - -/** - * @brief CCP0 duty function. - * - * Function sets duty value for CCP0 pins. - * - * @param[in] *hal_ll_hw_reg - Timer base structure. - * @param[in] duty_cycle_timeout - Duty cycle timeout value. - * @param[in] max_period - Maximum period value. - * - * @return none - * - */ -static inline void ptr_function_timer_a_duty( hal_ll_tim_base_handle_t *hal_ll_hw_reg, - uint32_t duty_cycle_timeout, - uint32_t max_period ); - -/** - * @brief CCP1 duty function. - * - * Function sets duty value for CCP1 pins. - * - * @param[in] *hal_ll_hw_reg - Timer base structure. - * @param[in] duty_cycle_timeout - Duty cycle timeout value. - * @param[in] max_period - Maximum period value. - * - * @return none - * - */ -static inline void ptr_function_timer_b_duty( hal_ll_tim_base_handle_t *hal_ll_hw_reg, - uint32_t duty_cycle_timeout, - uint32_t max_period ); - -/** - * @brief CCP0 start function. - * - * Function starts generating PWM signal on CCP0 pin. - * - * @param[in] *hal_ll_hw_reg - Timer base structure. - * - * @return none - * - */ -static inline void ptr_function_timer_a_start( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); - -/** - * @brief CCP1 start function. - * - * Function starts generating PWM signal on CCP1 pin. - * - * @param[in] *hal_ll_hw_reg - Timer base structure. - * - * @return none - * - */ -static inline void ptr_function_timer_b_start( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); - -/** - * @brief CCP0 stop function. - * - * Function stops PWM signal generation on CCP0 pin. - * - * @param[in] *hal_ll_hw_reg - Timer base structure. - * - * @return none - * - */ -static inline void ptr_function_timer_a_stop( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); - -/** - * @brief CCP1 stop function. - * - * Function stops PWM signal generation on CCP1 pin. - * - * @param[in] *hal_ll_hw_reg - Timer base structure. - * - * @return none - * - */ -static inline void ptr_function_timer_b_stop( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); - -/** - * @brief CCP0 period function. - * - * Function sets adequate period level on CCP0 pin. - * - * @param[in] *hal_ll_hw_reg - Timer base structure. - * @param[in] max_period - Maximum period value. - * - * @return none - * - */ -static inline void ptr_function_timer_a_period( hal_ll_tim_base_handle_t *hal_ll_hw_reg, - uint32_t max_period ); - -/** - * @brief CCP1 period function. - * - * Function sets adequate period level on CCP1 pin. + * @brief Full TIM module initialization procedure. * - * @param[in] *hal_ll_hw_reg - Timer base structure. - * @param[in] max_period - Maximum period value. + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. * + * @param map - Object specific context handler. * @return none * */ -static inline void ptr_function_timer_b_period( hal_ll_tim_base_handle_t *hal_ll_hw_reg, - uint32_t max_period ); +static void hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); /** - * @brief CCP0 control init function. - * - * Function sets adequate values in control registers - * for CCP0 pin. + * @brief Get local hardware specific map. * - * @param[in] *hal_ll_hw_reg - Timer base structure. + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. * - * @return none + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. */ -static inline void ptr_function_timer_a_hw_init_control( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); /** - * @brief CCP1 control init function. - * - * Function sets adequate values in control registers - * for CCP1 pin. + * @brief Check if pin is adequate. * - * @param[in] *hal_ll_hw_reg - Timer base structure. + * Checks tim pin the user has passed with pre-defined + * pin in tim map. * - * @return none + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. * + * Returns pre-defined module index from pin maps, if pin + * is adequate. */ -static inline void ptr_function_timer_b_hw_init_control( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); +static hal_ll_pin_name_t hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); /** - * @brief CCP0 timer init function. - * - * Function sets adequate values in timer registers - * for CCP0 pin. - * - * @param[in] *hal_ll_hw_reg - Timer base structure. - * - * @return none - * - */ -static inline void ptr_function_timer_a_pwm_mode_set( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); /** - * @brief CCP1 timer init function. + * @brief Sets TIM pin alternate function state. * - * Function sets adequate values in timer registers - * for CCP1 pin. + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. * - * @param[in] *hal_ll_hw_reg - Timer base structure. + * @param map - Object specific context handler. * + * @param hal_ll_state - Init/De-init * @return none * */ -static inline void ptr_function_timer_b_pwm_mode_set( hal_ll_tim_base_handle_t *hal_ll_hw_reg ); +static void hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, uint8_t *hal_module_id ) { + uint8_t index; uint16_t pin_check_result; - if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + if ( ( pin_check_result = hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { return HAL_LL_TIM_WRONG_PIN; } if ( hal_ll_tim_hw_specifics_map[ pin_check_result].config.pin != pin ) { - _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); - _hal_ll_tim_map_pin( pin_check_result, index ); + hal_ll_tim_map_pin( pin_check_result, index ); - _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); handle_map[ pin_check_result ].init_ll_state = false; @@ -515,7 +303,7 @@ hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; - _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; hal_ll_module_state[ pin_check_result ].init_ll_state = true; @@ -525,181 +313,199 @@ hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { } uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { - return 0; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_init(hal_ll_tim_hw_specifics_map_local); + + return HAL_LL_TIM_SUCCESS; } hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { - uint32_t duty_cycle_timeout; low_level_handle = hal_ll_tim_get_handle; hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); - if ( low_level_handle->init_ll_state == false ) { - hal_ll_tim_start( handle ); - low_level_handle->init_ll_state = true; - } - - duty_cycle_timeout = hal_ll_tim_hw_specifics_map_local->max_period * ( 1.0 - duty_ratio ); - - (hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_duty) - (hal_ll_tim_hw_specifics_map_local->base, duty_cycle_timeout, hal_ll_tim_hw_specifics_map_local->max_period); - return HAL_LL_TIM_SUCCESS; } hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + low_level_handle = hal_ll_tim_get_handle; hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); - (hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_signal_start) - (hal_ll_tim_hw_specifics_map_local->base); - return HAL_LL_TIM_SUCCESS; } hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + low_level_handle = hal_ll_tim_get_handle; hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); - (hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_signal_stop) - (hal_ll_tim_hw_specifics_map_local->base); - return HAL_LL_TIM_SUCCESS; } void hal_ll_tim_close( handle_t *handle ) { -} - -// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS - -static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { - -} - -static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { - return 0; -} - -static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { -} - -static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { - return 0; -} - -static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { - -} - -static void _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_t* map, bool hal_ll_state ) { - -} - -static void _hal_ll_tim0_set_clock( bool hal_ll_state ) { - -} - -static void _hal_ll_tim1_set_clock( bool hal_ll_state ) { - -} - -static void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); -} + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; -static void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + low_level_handle->init_ll_state = false; -} + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; -static void _hal_ll_tim4_set_clock( bool hal_ll_state ) { - -} - -static void _hal_ll_tim5_set_clock( bool hal_ll_state ) { + hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } } -static void _hal_ll_tim6_set_clock( bool hal_ll_state ) { +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, + hal_ll_tim_handle_register_t *handle_map ) { + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( hal_ll_tim_pin_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( hal_ll_tim_pin_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = hal_ll_tim_pin_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } } -static void _hal_ll_tim7_set_clock( bool hal_ll_state ) { +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { -} + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); -static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; } -static void _hal_ll_tim_set_period( hal_ll_tim_hw_specifics_map_t *map ) { +static void hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { } -// ---------------------------------------------------- STATIC POINTER FUNCTIONS - -static inline void map_pointer_functions( uint8_t hal_ll_module_id, uint8_t pin_parity ) { +static uint32_t hal_ll_tim_clock_source( uint8_t selector ) { + return 0; } -static inline void ptr_function_timer_a_duty( hal_ll_tim_base_handle_t *hal_ll_hw_reg, - uint32_t duty_cycle_timeout, - uint32_t max_period ) { +static uint32_t hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + return 0; } -static inline void ptr_function_timer_b_duty( hal_ll_tim_base_handle_t *hal_ll_hw_reg, - uint32_t duty_cycle_timeout, - uint32_t max_period ) { +static void hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { } -static inline void ptr_function_timer_a_start( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { +static void hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { } -static inline void ptr_function_timer_b_start( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { - -} +static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { +#define PCLK 60000000UL // Example Peripheral Clock +#define FREQ_HZ 1000.0f // Desired PWM frequency +#define DUTY 0.5f // 50% duty cycle -static inline void ptr_function_timer_a_stop( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { +#define PERIOD ((uint32_t)(PCLK / FREQ_HZ)) // e.g. 60000 +#define COMPARE ((uint32_t)(PERIOD * DUTY) - 1) // e.g. 29999 + // PSEL 3 + R_MSTP->MSTPCRD_b.MSTPD6 = 0; -} + R_GPT4->GTCR_b.CST = 0; // stop operation first + R_GPT4->GTCR_b.MD = 0x0; // PWM mode + R_GPT4->GTBER_b.PR = 1; // count up + R_GPT4->GTBER_b.PR = 1; // single buffer operation + // .... // freq settings + R_GPT4->GTCR = 0; // Clear control register (stop, reset config) -static inline void ptr_function_timer_b_stop( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { + R_GPT4->GTUDDTYC = 0x00; // Saw-wave PWM mode (count up) + R_GPT4->GTIOR = + (0b01 << 2) | // GTIOCA output when counting up and match A (initial output = 1) + (0b00 << 0) | // GTIOCA output when counting up and not matching (output = 0) + (1 << 14); // Enable GTIOCA output -} + R_GPT4->GTCCR[0] = COMPARE; // Set compare match A + R_GPT4->GTCCR[2] = COMPARE; // Buffered A -static inline void ptr_function_timer_a_period( hal_ll_tim_base_handle_t *hal_ll_hw_reg, - uint32_t max_period ) { + R_GPT4->GTPR = PERIOD - 1; // Set PWM period + R_GPT4->GTPBR = PERIOD - 1; // Buffered period -} + R_GPT4->GTCR = (0b000 << 1); // PCLK/1 as clock source (TPCS bits) -static inline void ptr_function_timer_b_period( hal_ll_tim_base_handle_t *hal_ll_hw_reg, - uint32_t max_period ) { + R_GPT4->GTCNT = 0; // Clear counter + R_GPT4->GTCR |= (1 << 0); // Start timer (CST = 1) + // .... // freq settings -} -static inline void ptr_function_timer_a_hw_init_control( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { + R_GPT4->GTCNT = 0; // initial counter value -} + // A + R_GPT4->GTIOR_b.GTIOA = 0x9; // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end) + R_GPT4->GTIOR_b.OAE = 1; // Enable GTIOC pin output + R_GPT4->GTBER_b.CCRA = 1; // Set buffer operation for the duty + // uint32_t duty = 0; // ???? + // R_GPT4->GTCCR[0] = duty? duty - 1 : duty; // Set compare match value + R_GPT4->GTCCR[2] = R_GPT4->GTCCR[0]; -static inline void ptr_function_timer_b_hw_init_control( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { + R_PFS->PORT[3].PIN[2].PmnPFS_b.PMR = 1; + R_PFS->PORT[3].PIN[2].PmnPFS_b.PMR = 1; + R_PFS->PORT[3].PIN[2].PmnPFS_b.PSEL = 3; + if (R_GPT4->GTPR && R_GPT4->GTCCR[0]) { + R_GPT4->GTCR_b.CST = 1; + } } -static inline void ptr_function_timer_a_pwm_mode_set( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { +static void hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { -} + hal_ll_tim_set_clock( map->base, true ); -static inline void ptr_function_timer_b_pwm_mode_set( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) { + hal_ll_tim_alternate_functions_set_state( map, true ); + hal_ll_tim_hw_init( map ); } - // ------------------------------------------------------------------------- END diff --git a/tests/pwm/default/main.c b/tests/pwm/default/main.c index 8f198aef62..17f52a1ba2 100644 --- a/tests/pwm/default/main.c +++ b/tests/pwm/default/main.c @@ -15,7 +15,7 @@ // -------------------------------------------------------------------- MACROS -#define TEST_PIN_PWM_TIM HAL_PIN_NC // TODO define pin used in test +#define TEST_PIN_PWM_TIM GPIO_P302 // TODO define pin used in test #define TEST_PWM_FREQUENCY 5000 // TODO define frequency used in last test @@ -124,6 +124,13 @@ static inline void run_test_3( void ) { wait_test_time; } } +#include "mcu.h" +#define PCLK 60000000UL // Example Peripheral Clock +#define FREQ_HZ 1000.0f // Desired PWM frequency +#define DUTY 0.5f // 50% duty cycle + +#define PERIOD ((uint32_t)(PCLK / FREQ_HZ)) // e.g. 60000 +#define COMPARE ((uint32_t)(PERIOD * DUTY) - 1) // e.g. 29999 int main( void ) { /* Do not remove this line or clock might not be set correctly. */ @@ -133,6 +140,79 @@ int main( void ) { int counter = 0; + // // PSEL 3 + // R_MSTP->MSTPCRD_b.MSTPD6 = 0; + + // R_GPT4->GTCR_b.CST = 0; // stop operation first + // R_GPT4->GTCR_b.MD = 0x0; // PWM mode + // R_GPT4->GTBER_b.PR = 1; // count up + // R_GPT4->GTBER_b.PR = 1; // single buffer operation + // // .... // freq settings + // R_GPT4->GTCR = 0; // Clear control register (stop, reset config) + + // R_GPT4->GTUDDTYC = 0x00; // Saw-wave PWM mode (count up) + // R_GPT4->GTIOR = + // (0b01 << 2) | // GTIOCA output when counting up and match A (initial output = 1) + // (0b00 << 0) | // GTIOCA output when counting up and not matching (output = 0) + // (1 << 14); // Enable GTIOCA output + + // R_GPT4->GTCCR[0] = COMPARE; // Set compare match A + // R_GPT4->GTCCR[2] = COMPARE; // Buffered A + + // R_GPT4->GTPR = PERIOD - 1; // Set PWM period + // R_GPT4->GTPBR = PERIOD - 1; // Buffered period + + // R_GPT4->GTCR = (0b000 << 1); // PCLK/1 as clock source (TPCS bits) + + // R_GPT4->GTCNT = 0; // Clear counter + // R_GPT4->GTCR |= (1 << 0); // Start timer (CST = 1) + // // .... // freq settings + + + // R_GPT4->GTCNT = 0; // initial counter value + + // // A + // R_GPT4->GTIOR_b.GTIOA = 0x9; // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end) + // R_GPT4->GTIOR_b.OAE = 1; // Enable GTIOC pin output + // R_GPT4->GTBER_b.CCRA = 1; // Set buffer operation for the duty + // // uint32_t duty = 0; // ???? + // // R_GPT4->GTCCR[0] = duty? duty - 1 : duty; // Set compare match value + // R_GPT4->GTCCR[2] = R_GPT4->GTCCR[0]; + + // R_PFS->PORT[3].PIN[2].PmnPFS_b.PMR = 1; + // R_PFS->PORT[3].PIN[2].PmnPFS_b.PMR = 1; + // R_PFS->PORT[3].PIN[2].PmnPFS_b.PSEL = 3; + + // if (R_GPT4->GTPR && R_GPT4->GTCCR[0]) { + // R_GPT4->GTCR_b.CST = 1; + // } + // float duty = 0.0f; + // float step = 0.01f; + // uint32_t compare; + + // while (1) { + // // Calculate compare value from duty + // compare = (uint32_t)(duty * PERIOD); + // if (compare > 0) compare--; // avoid overshoot + + // R_GPT4->GTCCR[0] = compare; + // R_GPT4->GTCCR[2] = compare; + + // // Update duty + // duty += step; + // if (duty >= 1.0f) { + // duty = 1.0f; + // step = -step; + // } else if (duty <= 0.0f) { + // duty = 0.0f; + // step = -step; + // } + + // // Delay to control speed of fading (adjust as needed) + // for (volatile int i = 0; i < 30000; i++); + // } + + // while(1); // Default config pwm_configure_default( &pwm_cfg ); @@ -148,21 +228,21 @@ int main( void ) { // Testing predefined cases for PWM // Test 1 - Change freq -> set duty -> start - for ( counter = 0; counter < (sizeof(freq_array) / sizeof(uint32_t)); counter++ ) { - // Check if pwm is stoped. - run_test_1( freq_array[ counter ] ); - wait_test_time; - } - - // Test 2 - Change freq -> start -> set duty - for ( counter = 0; counter < (sizeof(freq_array) / sizeof(uint32_t)); counter++ ) { - // Check if pwm is stoped. - run_test_2( freq_array[ counter ] ); - wait_test_time; - } - - // Test 3 - stop -> start and so on - simulate LED blinking - run_test_3(); + // for ( counter = 0; counter < (sizeof(freq_array) / sizeof(uint32_t)); counter++ ) { + // // Check if pwm is stoped. + // run_test_1( freq_array[ counter ] ); + // wait_test_time; + // } + + // // Test 2 - Change freq -> start -> set duty + // for ( counter = 0; counter < (sizeof(freq_array) / sizeof(uint32_t)); counter++ ) { + // // Check if pwm is stoped. + // run_test_2( freq_array[ counter ] ); + // wait_test_time; + // } + + // // Test 3 - stop -> start and so on - simulate LED blinking + // run_test_3(); // TODO Test different freq for PWM. // Using oscilloscope test all possible freq. @@ -185,6 +265,36 @@ int main( void ) { signal_error( TEST_PIN_4 ); } + // ADD begin + float duty = 0.0f; + float step = 0.01f; + uint32_t compare; + + while (1) { + // Calculate compare value from duty + compare = (uint32_t)(duty * PERIOD); + if (compare > 0) compare--; // avoid overshoot + + R_GPT4->GTCCR[0] = compare; + R_GPT4->GTCCR[2] = compare; + + // Update duty + duty += step; + if (duty >= 1.0f) { + duty = 1.0f; + step = -step; + } else if (duty <= 0.0f) { + duty = 0.0f; + step = -step; + } + + // Delay to control speed of fading (adjust as needed) + for (volatile int i = 0; i < 30000; i++); + } + + while(1); + // ADD end + wait_test_time; // Check if pwm is stoped. From 920e6e0c414a9724bbd5eb282f881856dba12d53 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Tue, 22 Jul 2025 14:25:22 +0200 Subject: [PATCH 23/62] PWM ongoing --- .../RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 4 + .../implementation_1/hal_ll_tim_pin_map.h | 27 ++- .../src/tim/implementation_1/hal_ll_tim.c | 217 ++++++++++++------ 3 files changed, 172 insertions(+), 76 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h index d77b696227..b51e97c1c1 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -81,6 +81,10 @@ //EOF SPI //TIM +#define TIM_MODULE_0 1 +#define TIM_MODULE_1 2 +#define TIM_MODULE_2 3 +#define TIM_MODULE_3 4 #define TIM_MODULE_4 5 #define TIM4_P302 diff --git a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h index 9d1725791a..51004b6e33 100644 --- a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h +++ b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h @@ -56,9 +56,29 @@ extern "C"{ #define hal_ll_tim_module_num(_module_num) (_module_num - 1) /*!< @brief TIMER module base addresses. */ +#ifdef TIM_MODULE_0 +static const hal_ll_base_addr_t HAL_LL_TIM0_BASE_ADDR = 0x40078400; +#endif +#ifdef TIM_MODULE_1 +static const hal_ll_base_addr_t HAL_LL_TIM1_BASE_ADDR = 0x40078400; +#endif +#ifdef TIM_MODULE_2 +static const hal_ll_base_addr_t HAL_LL_TIM2_BASE_ADDR = 0x40078400; +#endif +#ifdef TIM_MODULE_3 +static const hal_ll_base_addr_t HAL_LL_TIM3_BASE_ADDR = 0x40078400; +#endif #ifdef TIM_MODULE_4 static const hal_ll_base_addr_t HAL_LL_TIM4_BASE_ADDR = 0x40078400; #endif +#ifdef TIM_MODULE_5 +static const hal_ll_base_addr_t HAL_LL_TIM5_BASE_ADDR = 0x40078400; +#endif + +typedef enum { + HAL_LL_TIM_PIN_A = 0, + HAL_LL_TIM_PIN_B +} hal_ll_tim_pin_type; /*!< @brief TIM pin structure. */ typedef struct { @@ -66,16 +86,17 @@ typedef struct { hal_ll_base_addr_t base; uint8_t af; hal_ll_pin_name_t module_index; + hal_ll_tim_pin_type pin_type; } hal_ll_tim_pin_map_t; /*!< TIM pins. */ static const hal_ll_tim_pin_map_t hal_ll_tim_pin_map[] = { #ifdef TIM4_P302 - {GPIO_P302, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4)}, + {GPIO_P302, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_PIN_A}, #endif - - { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } + + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC } }; #ifdef __cplusplus diff --git a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c index c341054144..6fc61fb55e 100644 --- a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c @@ -44,13 +44,35 @@ #include "hal_ll_gpio.h" #include "hal_ll_tim.h" #include "hal_ll_tim_pin_map.h" +#include "hal_ll_mstpcr.h" #include "mcu.h" /*!< @brief Local handle list */ static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; // ------------------------------------------------------------- PRIVATE MACROS -/*!< CR1 constants. */ +/*!< Register defs. */ +#define HAL_LL_TIM_GTCR_CST (0) +#define HAL_LL_TIM_GTCR_MD_MASK (0x70000UL) + +#define HAL_LL_TIM_GTBER_PR_MASK (0x300000UL) +#define HAL_LL_TIM_GTBER_PR_SINGLE_BUFFER (0x100000UL) +#define HAL_LL_TIM_GTBER_CCRA_MASK (0x30000UL) +#define HAL_LL_TIM_GTBER_CCRA_SINGLE_BUFFER (0x10000UL) +#define HAL_LL_TIM_GTBER_CCRB_MASK (0xC0000UL) +#define HAL_LL_TIM_GTBER_CCRB_SINGLE_BUFFER (0x40000UL) + +#define HAL_LL_TIM_GTUDDTYC_UD (0) + +#define HAL_LL_TIM_GTIOR_GTIOA_MASK (0x1FUL) +#define HAL_LL_TIM_GTIOR_GTIOB_MASK (0x1FUL << 16) +#define HAL_LL_TIM_GTIOR_GTIOA_9 (0x9) +#define HAL_LL_TIM_GTIOR_GTIOB_9 (0x9 << 16) +#define HAL_LL_TIM_GTIOR_OAE (8) +#define HAL_LL_TIM_GTIOR_OBE (24) + + + /*!< @brief Helper macro for getting module specific control register structure */ #define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) @@ -69,14 +91,38 @@ static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COU /*!< @brief TIM register structure. */ typedef struct { - uint32_t todo; + uint32_t gtwp; + uint32_t gtstr; + uint32_t gtstp; + uint32_t gtclr; + uint32_t gtssr; + uint32_t gtpsr; + uint32_t gtcsr; + uint32_t gtupsr; + uint32_t gtdnsr; + uint32_t gticasr; + uint32_t gticbsr; + uint32_t gtcr; + uint32_t gtuddtyc; + uint32_t gtior; + uint32_t gtintad; + uint32_t gtst; + uint32_t gtber; + uint32_t gtcnt; + uint32_t gtccr[6]; + uint32_t gtpr; + uint32_t gtpbr; + uint32_t gtdtcr; + uint32_t gtdvu; + uint32_t opscr; } hal_ll_tim_base_handle_t; /*!< @brief TIM pin structure */ typedef struct { hal_ll_pin_name_t pin; - hal_ll_channel_t channel; + // hal_ll_channel_t channel; + hal_ll_tim_pin_type pin_type; uint32_t af; } hal_ll_tim_t; @@ -104,61 +150,29 @@ typedef enum /*!< @brief TIM specific info */ static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = { + #ifdef TIM_MODULE_0 + {HAL_LL_TIM0_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_0 - 1}, + #endif #ifdef TIM_MODULE_1 - {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, #endif #ifdef TIM_MODULE_2 - {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, #endif #ifdef TIM_MODULE_3 - {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, #endif #ifdef TIM_MODULE_4 - {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, - #endif - #ifdef TIM_MODULE_5 - {HAL_LL_TIM5_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_5 - 1}, - #endif - #ifdef TIM_MODULE_8 - {HAL_LL_TIM8_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_8 - 1}, - #endif - #ifdef TIM_MODULE_9 - {HAL_LL_TIM9_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_9 - 1}, - #endif - #ifdef TIM_MODULE_10 - {HAL_LL_TIM10_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_10 - 1}, - #endif - #ifdef TIM_MODULE_11 - {HAL_LL_TIM11_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_11 - 1}, - #endif - #ifdef TIM_MODULE_12 - {HAL_LL_TIM12_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_12 - 1}, - #endif - #ifdef TIM_MODULE_13 - {HAL_LL_TIM13_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_13 - 1}, - #endif - #ifdef TIM_MODULE_14 - {HAL_LL_TIM14_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_14 - 1}, - #endif - #ifdef TIM_MODULE_15 - {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, - #endif - #ifdef TIM_MODULE_16 - {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, - #endif - #ifdef TIM_MODULE_17 - {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, #endif - {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} }; /*!< @brief Global handle variables used in functions */ static volatile hal_ll_tim_handle_register_t *low_level_handle; static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; -static bool HAL_LL_TIM_IS_COMPLEMENTARY; - // ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS /** * @brief Enable TIM module gate clock. @@ -266,6 +280,9 @@ static void hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); */ static void hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); +// TODO +static void hal_ll_tim_set_freq_bare_metal( hal_ll_tim_hw_specifics_map_t *map ); + // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, uint8_t *hal_module_id ) { @@ -371,7 +388,7 @@ void hal_ll_tim_close( handle_t *handle ) { hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; - hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.pin_type = HAL_LL_PIN_NC; hal_ll_tim_hw_specifics_map_local->config.af = NULL; } } @@ -438,38 +455,50 @@ static uint32_t hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { } static void hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { - + // Map new pin. + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = hal_ll_tim_pin_map[ index ].pin; + hal_ll_tim_hw_specifics_map[ module_index ].config.pin_type = hal_ll_tim_pin_map[ index ].pin_type; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = hal_ll_tim_pin_map[ index ].af; } static void hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( ( map->config.pin != HAL_LL_PIN_NC ) && map->config.pin != HAL_LL_PIN_NC ) { + module.pins[0] = map->config.pin; + module.pins[1] = GPIO_MODULE_STRUCT_END; + module.configs[0] = map->config.af/* & HAL_LL_ALTERNATE_FUNCTION_MASK*/; + module.configs[1] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } } -static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { #define PCLK 60000000UL // Example Peripheral Clock #define FREQ_HZ 1000.0f // Desired PWM frequency #define DUTY 0.5f // 50% duty cycle #define PERIOD ((uint32_t)(PCLK / FREQ_HZ)) // e.g. 60000 #define COMPARE ((uint32_t)(PERIOD * DUTY) - 1) // e.g. 29999 - // PSEL 3 - R_MSTP->MSTPCRD_b.MSTPD6 = 0; +static void hal_ll_tim_set_freq_bare_metal( hal_ll_tim_hw_specifics_map_t *map ) { + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); - R_GPT4->GTCR_b.CST = 0; // stop operation first - R_GPT4->GTCR_b.MD = 0x0; // PWM mode - R_GPT4->GTBER_b.PR = 1; // count up - R_GPT4->GTBER_b.PR = 1; // single buffer operation - // .... // freq settings - R_GPT4->GTCR = 0; // Clear control register (stop, reset config) + // R_GPT4->GTCR = 0; // Clear control register (stop, reset config) + clear_reg( &hal_ll_hw_reg->gtcr ); // Clear control register (stop, reset config) - R_GPT4->GTUDDTYC = 0x00; // Saw-wave PWM mode (count up) - R_GPT4->GTIOR = - (0b01 << 2) | // GTIOCA output when counting up and match A (initial output = 1) - (0b00 << 0) | // GTIOCA output when counting up and not matching (output = 0) - (1 << 14); // Enable GTIOCA output + // R_GPT4->GTUDDTYC = 0x00; // Saw-wave PWM mode (count up) + set_reg_bit( &hal_ll_hw_reg->gtuddtyc, HAL_LL_TIM_GTUDDTYC_UD ); // Count up. - R_GPT4->GTCCR[0] = COMPARE; // Set compare match A - R_GPT4->GTCCR[2] = COMPARE; // Buffered A + if( HAL_LL_TIM_PIN_A == map->config.pin_type ) { + // R_GPT4->GTIOR = + // (0b01 << 2) | // GTIOCA output when counting up and match A (initial output = 1) + // (0b01 << 0) | // GTIOCA output when counting up and not matching (output = 0) + // (1 << 14); // Enable GTIOCA output + + R_GPT4->GTCCR[0] = COMPARE; // Set compare match A + R_GPT4->GTCCR[2] = COMPARE; // Buffered A + } R_GPT4->GTPR = PERIOD - 1; // Set PWM period R_GPT4->GTPBR = PERIOD - 1; // Buffered period @@ -478,22 +507,64 @@ static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { R_GPT4->GTCNT = 0; // Clear counter R_GPT4->GTCR |= (1 << 0); // Start timer (CST = 1) - // .... // freq settings +} +static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); - R_GPT4->GTCNT = 0; // initial counter value + // PSEL 3 + // R_MSTP->MSTPCRD_b.MSTPD6 = 0; + clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD6_POS ); + + // R_GPT4->GTCR_b.CST = 0; // stop operation first + clear_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST ); // Stop operation first. + // R_GPT4->GTCR_b.MD = 0x0; // PWM mode + clear_reg_bits( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_MD_MASK ); // PWM mode. + // R_GPT4->GTBER_b.PR = 1; // count up // ?????????? + // R_GPT4->GTBER_b.PR = 1; // single buffer operation + clear_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_PR_MASK ); + set_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_PR_SINGLE_BUFFER ); // Single buffer operation. - // A - R_GPT4->GTIOR_b.GTIOA = 0x9; // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end) - R_GPT4->GTIOR_b.OAE = 1; // Enable GTIOC pin output - R_GPT4->GTBER_b.CCRA = 1; // Set buffer operation for the duty - // uint32_t duty = 0; // ???? - // R_GPT4->GTCCR[0] = duty? duty - 1 : duty; // Set compare match value - R_GPT4->GTCCR[2] = R_GPT4->GTCCR[0]; + // .... // freq settings + hal_ll_tim_set_freq_bare_metal( map ); + // .... // freq settings + + // R_GPT4->GTCNT = 0; // initial counter value + clear_reg( &hal_ll_hw_reg->gtcnt ); + + if( HAL_LL_TIM_PIN_A == map->config.pin_type ) { + // A + // R_GPT4->GTIOR_b.GTIOA = 0x9; // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end) + // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end) + clear_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOA_MASK ); + set_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOA_9 ); + // R_GPT4->GTIOR_b.OAE = 1; // Enable GTIOC pin output + set_reg_bit( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_OAE ); // Enable GTIOC pin output + // R_GPT4->GTBER_b.CCRA = 1; // Set buffer operation for the duty + clear_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRA_MASK ); + set_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRA_SINGLE_BUFFER ); + // uint32_t duty = 0; // ???? + // R_GPT4->GTCCR[0] = duty? duty - 1 : duty; // Set compare match value + // R_GPT4->GTCCR[2] = R_GPT4->GTCCR[0]; + } else { + // A + // R_GPT4->GTIOR_b.GTIOB = 0x9; // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end) + // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end) + clear_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOB_MASK ); + set_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOB_9 ); + // R_GPT4->GTIOR_b.OBE = 1; // Enable GTIOC pin output + set_reg_bit( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_OBE ); // Enable GTIOC pin output + // R_GPT4->GTBER_b.CCRB = 1; // Set buffer operation for the duty + clear_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRB_MASK ); + set_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRB_SINGLE_BUFFER ); + // uint32_t duty = 0; // ???? + // R_GPT4->GTCCR[1] = duty? duty - 1 : duty; // Set compare match value + // R_GPT4->GTCCR[3] = R_GPT4->GTCCR[1]; + } - R_PFS->PORT[3].PIN[2].PmnPFS_b.PMR = 1; - R_PFS->PORT[3].PIN[2].PmnPFS_b.PMR = 1; - R_PFS->PORT[3].PIN[2].PmnPFS_b.PSEL = 3; + // R_PFS->PORT[3].PIN[2].PmnPFS_b.PMR = 1; + // R_PFS->PORT[3].PIN[2].PmnPFS_b.PMR = 1; + // R_PFS->PORT[3].PIN[2].PmnPFS_b.PSEL = 3; if (R_GPT4->GTPR && R_GPT4->GTCCR[0]) { R_GPT4->GTCR_b.CST = 1; From dddb26a3ea878dcd54c7a4202146dba576c2c44e Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Wed, 23 Jul 2025 09:16:47 +0200 Subject: [PATCH 24/62] WIP -> interrupts still don't work --- tests/renesas/src/main.c | 836 +++++++++++++++++++-------------------- 1 file changed, 410 insertions(+), 426 deletions(-) diff --git a/tests/renesas/src/main.c b/tests/renesas/src/main.c index f541961e45..5e319d4912 100644 --- a/tests/renesas/src/main.c +++ b/tests/renesas/src/main.c @@ -8,401 +8,355 @@ #endif #include "mcu.h" -#include "interrupts_mcu.h" +#include "interrupts.h" #define PWPR_REGISTER_BASE (* ( volatile uint8_t * )0x40040D03UL) -// Startup file should have this (from bsp_elc.h file) -// void NMI_Handler(void) WEAK_REF_ATTRIBUTE; -// void HardFault_Handler(void) WEAK_REF_ATTRIBUTE; -// void MemManage_Handler(void) WEAK_REF_ATTRIBUTE; -// void BusFault_Handler(void) WEAK_REF_ATTRIBUTE; -// void UsageFault_Handler(void) WEAK_REF_ATTRIBUTE; -// void SecureFault_Handler(void) WEAK_REF_ATTRIBUTE; -// void SVC_Handler(void) WEAK_REF_ATTRIBUTE; -// void DebugMon_Handler(void) WEAK_REF_ATTRIBUTE; -// void PendSV_Handler(void) WEAK_REF_ATTRIBUTE; -// void SysTick_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_IRQ0_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_IRQ1_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_IRQ2_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_IRQ3_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_IRQ4_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_IRQ5_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_IRQ6_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_IRQ7_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_IRQ8_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_IRQ9_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_IRQ10_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_IRQ11_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_IRQ12_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_IRQ14_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_IRQ15_Handler(void) WEAK_REF_ATTRIBUTE; -// void DMAC0_INT_Handler(void) WEAK_REF_ATTRIBUTE; -// void DMAC1_INT_Handler(void) WEAK_REF_ATTRIBUTE; -// void DMAC2_INT_Handler(void) WEAK_REF_ATTRIBUTE; -// void DMAC3_INT_Handler(void) WEAK_REF_ATTRIBUTE; -// void DTC_COMPLETE_Handler(void) WEAK_REF_ATTRIBUTE; -// void DTC_END_Handler(void) WEAK_REF_ATTRIBUTE; -// void ICU_SNOOZE_CANCEL_Handler(void) WEAK_REF_ATTRIBUTE; -// void FCU_FRDYI_Handler(void) WEAK_REF_ATTRIBUTE; -// void LVD_LVD1_Handler(void) WEAK_REF_ATTRIBUTE; -// void LVD_LVD2_Handler(void) WEAK_REF_ATTRIBUTE; -// void LVD_VBATT_Handler(void) WEAK_REF_ATTRIBUTE; -// void CGC_MOSC_STOP_Handler(void) WEAK_REF_ATTRIBUTE; -// void LPM_SNOOZE_REQUEST_Handler(void) WEAK_REF_ATTRIBUTE; -// void AGT0_INT_Handler(void) WEAK_REF_ATTRIBUTE; -// void AGT0_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; -// void AGT0_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; -// void AGT1_INT_Handler(void) WEAK_REF_ATTRIBUTE; -// void AGT1_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; -// void AGT1_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; -// void IWDT_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void WDT_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void RTC_ALARM_Handler(void) WEAK_REF_ATTRIBUTE; -// void RTC_PERIOD_Handler(void) WEAK_REF_ATTRIBUTE; -// void RTC_CARRY_Handler(void) WEAK_REF_ATTRIBUTE; -// void ADC0_SCAN_END_Handler(void) WEAK_REF_ATTRIBUTE; -// void ADC0_SCAN_END_B_Handler(void) WEAK_REF_ATTRIBUTE; -// void ADC0_WINDOW_A_Handler(void) WEAK_REF_ATTRIBUTE; -// void ADC0_WINDOW_B_Handler(void) WEAK_REF_ATTRIBUTE; -// void ADC0_COMPARE_MATCH_Handler(void) WEAK_REF_ATTRIBUTE; -// void ADC0_COMPARE_MISMATCH_Handler(void) WEAK_REF_ATTRIBUTE; -// void ACMPLP0_INT_Handler(void) WEAK_REF_ATTRIBUTE; -// void ACMPLP1_INT_Handler(void) WEAK_REF_ATTRIBUTE; -// void USBFS_FIFO_0_Handler(void) WEAK_REF_ATTRIBUTE; -// void USBFS_FIFO_1_Handler(void) WEAK_REF_ATTRIBUTE; -// void USBFS_INT_Handler(void) WEAK_REF_ATTRIBUTE; -// void USBFS_RESUME_Handler(void) WEAK_REF_ATTRIBUTE; -// void IIC0_RXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void IIC0_TXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void IIC0_TEI_Handler(void) WEAK_REF_ATTRIBUTE; -// void IIC0_ERI_Handler(void) WEAK_REF_ATTRIBUTE; -// void IIC0_WUI_Handler(void) WEAK_REF_ATTRIBUTE; -// void IIC1_RXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void IIC1_TXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void IIC1_TEI_Handler(void) WEAK_REF_ATTRIBUTE; -// void IIC1_ERI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SSI0_TXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SSI0_RXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SSI0_INT_Handler(void) WEAK_REF_ATTRIBUTE; -// void CTSU_WRITE_Handler(void) WEAK_REF_ATTRIBUTE; -// void CTSU_READ_Handler(void) WEAK_REF_ATTRIBUTE; -// void CTSU_END_Handler(void) WEAK_REF_ATTRIBUTE; -// void KEY_INT_Handler(void) WEAK_REF_ATTRIBUTE; -// void DOC_INT_Handler(void) WEAK_REF_ATTRIBUTE; -// void CAC_FREQUENCY_ERROR_Handler(void) WEAK_REF_ATTRIBUTE; -// void CAC_MEASUREMENT_END_Handler(void) WEAK_REF_ATTRIBUTE; -// void CAC_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void CAN0_ERROR_Handler(void) WEAK_REF_ATTRIBUTE; -// void CAN0_FIFO_RX_Handler(void) WEAK_REF_ATTRIBUTE; -// void CAN0_FIFO_TX_Handler(void) WEAK_REF_ATTRIBUTE; -// void CAN0_MAILBOX_RX_Handler(void) WEAK_REF_ATTRIBUTE; -// void CAN0_MAILBOX_TX_Handler(void) WEAK_REF_ATTRIBUTE; -// void IOPORT_EVENT_1_Handler(void) WEAK_REF_ATTRIBUTE; -// void IOPORT_EVENT_2_Handler(void) WEAK_REF_ATTRIBUTE; -// void IOPORT_EVENT_3_Handler(void) WEAK_REF_ATTRIBUTE; -// void IOPORT_EVENT_4_Handler(void) WEAK_REF_ATTRIBUTE; -// void ELC_SOFTWARE_EVENT_0_Handler(void) WEAK_REF_ATTRIBUTE; -// void ELC_SOFTWARE_EVENT_1_Handler(void) WEAK_REF_ATTRIBUTE; -// void POEG0_EVENT_Handler(void) WEAK_REF_ATTRIBUTE; -// void POEG1_EVENT_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT0_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT0_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT0_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT0_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT0_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT0_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT0_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT0_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT1_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT1_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT1_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT1_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT1_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT1_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT1_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT1_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT2_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT2_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT2_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT2_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT2_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT2_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT2_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT2_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT3_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT3_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT3_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT3_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT3_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT3_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT3_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT3_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT4_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT4_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT4_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT4_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT4_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT4_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT4_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT4_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT5_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT5_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT5_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT5_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT5_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT5_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT5_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT5_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT6_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT6_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT6_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT6_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT6_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT6_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT6_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT6_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT7_CAPTURE_COMPARE_A_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT7_CAPTURE_COMPARE_B_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT7_COMPARE_C_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT7_COMPARE_D_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT7_COMPARE_E_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT7_COMPARE_F_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT7_COUNTER_OVERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void GPT7_COUNTER_UNDERFLOW_Handler(void) WEAK_REF_ATTRIBUTE; -// void OPS_UVW_EDGE_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI0_RXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI0_TXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI0_TEI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI0_ERI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI0_AM_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI0_RXI_OR_ERI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI1_RXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI1_TXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI1_TEI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI1_ERI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI1_AM_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI2_RXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI2_TXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI2_TEI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI2_ERI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI2_AM_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI9_RXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI9_TXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI9_TEI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI9_ERI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SCI9_AM_Handler(void) WEAK_REF_ATTRIBUTE; -// void SPI0_RXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SPI0_TXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SPI0_IDLE_Handler(void) WEAK_REF_ATTRIBUTE; -// void SPI0_ERI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SPI0_TEI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SPI1_RXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SPI1_TXI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SPI1_IDLE_Handler(void) WEAK_REF_ATTRIBUTE; -// void SPI1_ERI_Handler(void) WEAK_REF_ATTRIBUTE; -// void SPI1_TEI_Handler(void) WEAK_REF_ATTRIBUTE; - -// BSP_DONT_REMOVE const exc_ptr_t __Vectors[196] BSP_PLACE_IN_SECTION( -// BSP_SECTION_FIXED_VECTORS) = -// { -// (exc_ptr_t) (&g_main_stack[0] + BSP_CFG_STACK_MAIN_BYTES), /* Initial Stack Pointer */ -// Reset_Handler, /* Reset Handler */ -// NMI_Handler, /* NMI Handler */ -// HardFault_Handler, /* Hard Fault Handler */ -// MemManage_Handler, /* MPU Fault Handler */ -// BusFault_Handler, /* Bus Fault Handler */ -// UsageFault_Handler, /* Usage Fault Handler */ -// SecureFault_Handler, /* Secure Fault Handler */ -// 0, /* Reserved */ -// 0, /* Reserved */ -// 0, /* Reserved */ -// SVC_Handler, /* SVCall Handler */ -// DebugMon_Handler, /* Debug Monitor Handler */ -// 0, /* Reserved */ -// PendSV_Handler, /* PendSV Handler */ -// SysTick_Handler, /* SysTick Handler */ -// ICU_IRQ0_Handler, /* External pin interrupt 0 */ -// ICU_IRQ1_Handler, /* External pin interrupt 1 */ -// ICU_IRQ2_Handler, /* External pin interrupt 2 */ -// ICU_IRQ3_Handler, /* External pin interrupt 3 */ -// ICU_IRQ4_Handler, /* External pin interrupt 4 */ -// ICU_IRQ5_Handler, /* External pin interrupt 5 */ -// ICU_IRQ6_Handler, /* External pin interrupt 6 */ -// ICU_IRQ7_Handler, /* External pin interrupt 7 */ -// ICU_IRQ8_Handler, /* External pin interrupt 8 */ -// ICU_IRQ9_Handler, /* External pin interrupt 9 */ -// ICU_IRQ10_Handler, /* External pin interrupt 10 */ -// ICU_IRQ11_Handler, /* External pin interrupt 11 */ -// ICU_IRQ12_Handler, /* External pin interrupt 12 */ -// ICU_IRQ14_Handler, /* External pin interrupt 14 */ -// ICU_IRQ15_Handler, /* External pin interrupt 15 */ -// DMAC0_INT_Handler, /* DMAC0 transfer end */ -// DMAC1_INT_Handler, /* DMAC1 transfer end */ -// DMAC2_INT_Handler, /* DMAC2 transfer end */ -// DMAC3_INT_Handler, /* DMAC3 transfer end */ -// DTC_COMPLETE_Handler, /* DTC transfer complete */ -// DTC_END_Handler, /* DTC transfer end */ -// ICU_SNOOZE_CANCEL_Handler, /* Canceling from Snooze mode */ -// FCU_FRDYI_Handler, /* Flash ready interrupt */ -// LVD_LVD1_Handler, /* Voltage monitor 1 interrupt */ -// LVD_LVD2_Handler, /* Voltage monitor 2 interrupt */ -// LVD_VBATT_Handler, /* VBATT low voltage detect */ -// CGC_MOSC_STOP_Handler, /* Main Clock oscillation stop */ -// LPM_SNOOZE_REQUEST_Handler, /* Snooze entry */ -// AGT0_INT_Handler, /* AGT interrupt */ -// AGT0_COMPARE_A_Handler, /* Compare match A */ -// AGT0_COMPARE_B_Handler, /* Compare match B */ -// AGT1_INT_Handler, /* AGT interrupt */ -// AGT1_COMPARE_A_Handler, /* Compare match A */ -// AGT1_COMPARE_B_Handler, /* Compare match B */ -// IWDT_UNDERFLOW_Handler, /* IWDT underflow */ -// WDT_UNDERFLOW_Handler, /* WDT underflow */ -// RTC_ALARM_Handler, /* Alarm interrupt */ -// RTC_PERIOD_Handler, /* Periodic interrupt */ -// RTC_CARRY_Handler, /* Carry interrupt */ -// ADC0_SCAN_END_Handler, /* End of A/D scanning operation */ -// ADC0_SCAN_END_B_Handler, /* A/D scan end interrupt for group B */ -// ADC0_WINDOW_A_Handler, /* Window A Compare match interrupt */ -// ADC0_WINDOW_B_Handler, /* Window B Compare match interrupt */ -// ADC0_COMPARE_MATCH_Handler, /* Compare match */ -// ADC0_COMPARE_MISMATCH_Handler, /* Compare mismatch */ -// ACMPLP0_INT_Handler, /* Low Power Comparator channel 0 interrupt */ -// ACMPLP1_INT_Handler, /* Low Power Comparator channel 1 interrupt */ -// USBFS_FIFO_0_Handler, /* DMA/DTC transfer request 0 */ -// USBFS_FIFO_1_Handler, /* DMA/DTC transfer request 1 */ -// USBFS_INT_Handler, /* USBFS interrupt */ -// USBFS_RESUME_Handler, /* USBFS resume interrupt */ -// IIC0_RXI_Handler, /* Receive data full */ -// IIC0_TXI_Handler, /* Transmit data empty */ -// IIC0_TEI_Handler, /* Transmit end */ -// IIC0_ERI_Handler, /* Transfer error */ -// IIC0_WUI_Handler, /* Wakeup interrupt */ -// IIC1_RXI_Handler, /* Receive data full */ -// IIC1_TXI_Handler, /* Transmit data empty */ -// IIC1_TEI_Handler, /* Transmit end */ -// IIC1_ERI_Handler, /* Transfer error */ -// SSI0_TXI_Handler, /* Transmit data empty */ -// SSI0_RXI_Handler, /* Receive data full */ -// SSI0_INT_Handler, /* Error interrupt */ -// CTSU_WRITE_Handler, /* Write request interrupt */ -// CTSU_READ_Handler, /* Measurement data transfer request interrupt */ -// CTSU_END_Handler, /* Measurement end interrupt */ -// KEY_INT_Handler, /* Key interrupt */ -// DOC_INT_Handler, /* Data operation circuit interrupt */ -// CAC_FREQUENCY_ERROR_Handler, /* Frequency error interrupt */ -// CAC_MEASUREMENT_END_Handler, /* Measurement end interrupt */ -// CAC_OVERFLOW_Handler, /* Overflow interrupt */ -// CAN0_ERROR_Handler, /* Error interrupt */ -// CAN0_FIFO_RX_Handler, /* Receive FIFO interrupt */ -// CAN0_FIFO_TX_Handler, /* Transmit FIFO interrupt */ -// CAN0_MAILBOX_RX_Handler, /* Reception complete interrupt */ -// CAN0_MAILBOX_TX_Handler, /* Transmission complete interrupt */ -// IOPORT_EVENT_1_Handler, /* Port 1 event */ -// IOPORT_EVENT_2_Handler, /* Port 2 event */ -// IOPORT_EVENT_3_Handler, /* Port 3 event */ -// IOPORT_EVENT_4_Handler, /* Port 4 event */ -// ELC_SOFTWARE_EVENT_0_Handler, /* Software event 0 */ -// ELC_SOFTWARE_EVENT_1_Handler, /* Software event 1 */ -// POEG0_EVENT_Handler, /* Port Output disable 0 interrupt */ -// POEG1_EVENT_Handler, /* Port Output disable 1 interrupt */ -// GPT0_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ -// GPT0_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ -// GPT0_COMPARE_C_Handler, /* Compare match C */ -// GPT0_COMPARE_D_Handler, /* Compare match D */ -// GPT0_COMPARE_E_Handler, /* Compare match E */ -// GPT0_COMPARE_F_Handler, /* Compare match F */ -// GPT0_COUNTER_OVERFLOW_Handler, /* Overflow */ -// GPT0_COUNTER_UNDERFLOW_Handler, /* Underflow */ -// GPT1_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ -// GPT1_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ -// GPT1_COMPARE_C_Handler, /* Compare match C */ -// GPT1_COMPARE_D_Handler, /* Compare match D */ -// GPT1_COMPARE_E_Handler, /* Compare match E */ -// GPT1_COMPARE_F_Handler, /* Compare match F */ -// GPT1_COUNTER_OVERFLOW_Handler, /* Overflow */ -// GPT1_COUNTER_UNDERFLOW_Handler, /* Underflow */ -// GPT2_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ -// GPT2_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ -// GPT2_COMPARE_C_Handler, /* Compare match C */ -// GPT2_COMPARE_D_Handler, /* Compare match D */ -// GPT2_COMPARE_E_Handler, /* Compare match E */ -// GPT2_COMPARE_F_Handler, /* Compare match F */ -// GPT2_COUNTER_OVERFLOW_Handler, /* Overflow */ -// GPT2_COUNTER_UNDERFLOW_Handler, /* Underflow */ -// GPT3_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ -// GPT3_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ -// GPT3_COMPARE_C_Handler, /* Compare match C */ -// GPT3_COMPARE_D_Handler, /* Compare match D */ -// GPT3_COMPARE_E_Handler, /* Compare match E */ -// GPT3_COMPARE_F_Handler, /* Compare match F */ -// GPT3_COUNTER_OVERFLOW_Handler, /* Overflow */ -// GPT3_COUNTER_UNDERFLOW_Handler, /* Underflow */ -// GPT4_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ -// GPT4_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ -// GPT4_COMPARE_C_Handler, /* Compare match C */ -// GPT4_COMPARE_D_Handler, /* Compare match D */ -// GPT4_COMPARE_E_Handler, /* Compare match E */ -// GPT4_COMPARE_F_Handler, /* Compare match F */ -// GPT4_COUNTER_OVERFLOW_Handler, /* Overflow */ -// GPT4_COUNTER_UNDERFLOW_Handler, /* Underflow */ -// GPT5_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ -// GPT5_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ -// GPT5_COMPARE_C_Handler, /* Compare match C */ -// GPT5_COMPARE_D_Handler, /* Compare match D */ -// GPT5_COMPARE_E_Handler, /* Compare match E */ -// GPT5_COMPARE_F_Handler, /* Compare match F */ -// GPT5_COUNTER_OVERFLOW_Handler, /* Overflow */ -// GPT5_COUNTER_UNDERFLOW_Handler, /* Underflow */ -// GPT6_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ -// GPT6_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ -// GPT6_COMPARE_C_Handler, /* Compare match C */ -// GPT6_COMPARE_D_Handler, /* Compare match D */ -// GPT6_COMPARE_E_Handler, /* Compare match E */ -// GPT6_COMPARE_F_Handler, /* Compare match F */ -// GPT6_COUNTER_OVERFLOW_Handler, /* Overflow */ -// GPT6_COUNTER_UNDERFLOW_Handler, /* Underflow */ -// GPT7_CAPTURE_COMPARE_A_Handler, /* Capture/Compare match A */ -// GPT7_CAPTURE_COMPARE_B_Handler, /* Capture/Compare match B */ -// GPT7_COMPARE_C_Handler, /* Compare match C */ -// GPT7_COMPARE_D_Handler, /* Compare match D */ -// GPT7_COMPARE_E_Handler, /* Compare match E */ -// GPT7_COMPARE_F_Handler, /* Compare match F */ -// GPT7_COUNTER_OVERFLOW_Handler, /* Overflow */ -// GPT7_COUNTER_UNDERFLOW_Handler, /* Underflow */ -// OPS_UVW_EDGE_Handler, /* UVW edge event */ -// SCI0_RXI_Handler, /* Receive data full */ -// SCI0_TXI_Handler, /* Transmit data empty */ -// SCI0_TEI_Handler, /* Transmit end */ -// SCI0_ERI_Handler, /* Receive error */ -// SCI0_AM_Handler, /* Address match event */ -// SCI0_RXI_OR_ERI_Handler, /* Receive data full/Receive error */ -// SCI1_RXI_Handler, /* Receive data full */ -// SCI1_TXI_Handler, /* Transmit data empty */ -// SCI1_TEI_Handler, /* Transmit end */ -// SCI1_ERI_Handler, /* Receive error */ -// SCI1_AM_Handler, /* Address match event */ -// SCI2_RXI_Handler, /* Receive data full */ -// SCI2_TXI_Handler, /* Transmit data empty */ -// SCI2_TEI_Handler, /* Transmit end */ -// SCI2_ERI_Handler, /* Receive error */ -// SCI2_AM_Handler, /* Address match event */ -// SCI9_RXI_Handler, /* Receive data full */ -// SCI9_TXI_Handler, /* Transmit data empty */ -// SCI9_TEI_Handler, /* Transmit end */ -// SCI9_ERI_Handler, /* Receive error */ -// SCI9_AM_Handler, /* Address match event */ -// SPI0_RXI_Handler, /* Receive buffer full */ -// SPI0_TXI_Handler, /* Transmit buffer empty */ -// SPI0_IDLE_Handler, /* Idle */ -// SPI0_ERI_Handler, /* Error */ -// SPI0_TEI_Handler, /* Transmission complete event */ -// SPI1_RXI_Handler, /* Receive buffer full */ -// SPI1_TXI_Handler, /* Transmit buffer empty */ -// SPI1_IDLE_Handler, /* Idle */ -// SPI1_ERI_Handler, /* Error */ -// SPI1_TEI_Handler /* Transmission complete event */ -// }; +// #define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ +// #define SCI0_RXI_IRQn ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ +// #define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ +// #define SCI0_TXI_IRQn ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ +// #define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ +// #define SCI0_TEI_IRQn ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ +// #define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ +// #define SCI0_ERI_IRQn ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ +// #define VECTOR_NUMBER_SCI1_RXI ((IRQn_Type)4) /* SCI1 RXI (Received data full) */ +// #define SCI1_RXI_IRQn ((IRQn_Type)4) /* SCI1 RXI (Received data full) */ +// #define VECTOR_NUMBER_SCI1_TXI ((IRQn_Type)5) /* SCI1 TXI (Transmit data empty) */ +// #define SCI1_TXI_IRQn ((IRQn_Type)5) /* SCI1 TXI (Transmit data empty) */ +// #define VECTOR_NUMBER_SCI1_TEI ((IRQn_Type)6) /* SCI1 TEI (Transmit end) */ +// #define SCI1_TEI_IRQn ((IRQn_Type)6) /* SCI1 TEI (Transmit end) */ +// #define VECTOR_NUMBER_SCI1_ERI ((IRQn_Type)7) /* SCI1 ERI (Receive error) */ +// #define SCI1_ERI_IRQn ((IRQn_Type)7) /* SCI1 ERI (Receive error) */ +// #define VECTOR_NUMBER_SCI2_RXI ((IRQn_Type)8) /* SCI2 RXI (Received data full) */ +// #define SCI2_RXI_IRQn ((IRQn_Type)8) /* SCI2 RXI (Received data full) */ +// #define VECTOR_NUMBER_SCI2_TXI ((IRQn_Type)9) /* SCI2 TXI (Transmit data empty) */ +// #define SCI2_TXI_IRQn ((IRQn_Type)9) /* SCI2 TXI (Transmit data empty) */ +// #define VECTOR_NUMBER_SCI2_TEI ((IRQn_Type)10) /* SCI2 TEI (Transmit end) */ +// #define SCI2_TEI_IRQn ((IRQn_Type)10) /* SCI2 TEI (Transmit end) */ +// #define VECTOR_NUMBER_SCI2_ERI ((IRQn_Type)11) /* SCI2 ERI (Receive error) */ +// #define SCI2_ERI_IRQn ((IRQn_Type)11) /* SCI2 ERI (Receive error) */ +// #define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ +// #define RTC_ALARM_IRQn ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ +// #define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ +// #define RTC_PERIOD_IRQn ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ +// #define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ +// #define RTC_CARRY_IRQn ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ +// #define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ +// #define AGT0_INT_IRQn ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ +// #define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */ +// #define ICU_IRQ0_IRQn ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */ +// #define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)17) /* SPI0 RXI (Receive buffer full) */ +// #define SPI0_RXI_IRQn ((IRQn_Type)17) /* SPI0 RXI (Receive buffer full) */ +// #define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)18) /* SPI0 TXI (Transmit buffer empty) */ +// #define SPI0_TXI_IRQn ((IRQn_Type)18) /* SPI0 TXI (Transmit buffer empty) */ +// #define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)19) /* SPI0 TEI (Transmission complete event) */ +// #define SPI0_TEI_IRQn ((IRQn_Type)19) /* SPI0 TEI (Transmission complete event) */ +// #define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)20) /* SPI0 ERI (Error) */ +// #define SPI0_ERI_IRQn ((IRQn_Type)20) /* SPI0 ERI (Error) */ + +typedef void (* fsp_vector_t)(void); +#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) + #define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" + + /* ISR prototypes */ +void ICU_IELSR0_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR1_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR2_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR3_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR4_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR5_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR6_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR7_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR8_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR9_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR10_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR11_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR12_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR13_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR14_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR15_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR16_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR17_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR18_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR19_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR20_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR21_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR22_Handler(void); +void ICU_IELSR23_Handler(void); +void ICU_IELSR24_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR25_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR26_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR27_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR28_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR29_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR30_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); +void ICU_IELSR31_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); + +const fsp_vector_t g_vector_table[32] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = +{ + ICU_IELSR0_Handler, + ICU_IELSR1_Handler, + ICU_IELSR2_Handler, + ICU_IELSR3_Handler, + ICU_IELSR4_Handler, + ICU_IELSR5_Handler, + ICU_IELSR6_Handler, + ICU_IELSR7_Handler, + ICU_IELSR8_Handler, + ICU_IELSR9_Handler, + ICU_IELSR10_Handler, + ICU_IELSR11_Handler, + ICU_IELSR12_Handler, + ICU_IELSR13_Handler, + ICU_IELSR14_Handler, + ICU_IELSR15_Handler, + ICU_IELSR16_Handler, + ICU_IELSR17_Handler, + ICU_IELSR18_Handler, + ICU_IELSR19_Handler, + ICU_IELSR20_Handler, + ICU_IELSR21_Handler, + ICU_IELSR22_Handler, + ICU_IELSR23_Handler, + ICU_IELSR24_Handler, + ICU_IELSR25_Handler, + ICU_IELSR26_Handler, + ICU_IELSR27_Handler, + ICU_IELSR28_Handler, + ICU_IELSR29_Handler, + ICU_IELSR30_Handler, + ICU_IELSR31_Handler +}; + +typedef enum e_elc_event_ra4m1 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (0x011), // DMAC0 transfer end + ELC_EVENT_DMAC1_INT = (0x012), // DMAC1 transfer end + ELC_EVENT_DMAC2_INT = (0x013), // DMAC2 transfer end + ELC_EVENT_DMAC3_INT = (0x014), // DMAC3 transfer end + ELC_EVENT_DTC_COMPLETE = (0x015), // DTC transfer complete + ELC_EVENT_DTC_END = (0x016), // DTC transfer end + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x017), // Canceling from Snooze mode + ELC_EVENT_FCU_FRDYI = (0x018), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x019), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x01A), // Voltage monitor 2 interrupt + ELC_EVENT_LVD_VBATT = (0x01B), // VBATT low voltage detect + ELC_EVENT_CGC_MOSC_STOP = (0x01C), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x01D), // Snooze entry + ELC_EVENT_AGT0_INT = (0x01E), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x01F), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x020), // Compare match B + ELC_EVENT_AGT1_INT = (0x021), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x022), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x023), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x024), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x025), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x026), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x027), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x028), // Carry interrupt + ELC_EVENT_ADC0_SCAN_END = (0x029), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x02A), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x02B), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x02C), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x02D), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x02E), // Compare mismatch + ELC_EVENT_ACMPLP0_INT = (0x02F), // Low Power Comparator channel 0 interrupt + ELC_EVENT_ACMPLP1_INT = (0x030), // Low Power Comparator channel 1 interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x031), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x032), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x033), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x034), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x035), // Receive data full + ELC_EVENT_IIC0_TXI = (0x036), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x037), // Transmit end + ELC_EVENT_IIC0_ERI = (0x038), // Transfer error + ELC_EVENT_IIC0_WUI = (0x039), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x03A), // Receive data full + ELC_EVENT_IIC1_TXI = (0x03B), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x03C), // Transmit end + ELC_EVENT_IIC1_ERI = (0x03D), // Transfer error + ELC_EVENT_SSI0_TXI = (0x03E), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x03F), // Receive data full + ELC_EVENT_SSI0_INT = (0x041), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x042), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x043), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x044), // Measurement end interrupt + ELC_EVENT_KEY_INT = (0x045), // Key interrupt + ELC_EVENT_DOC_INT = (0x046), // Data operation circuit interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x047), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x048), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x049), // Overflow interrupt + ELC_EVENT_CAN0_ERROR = (0x04A), // Error interrupt + ELC_EVENT_CAN0_FIFO_RX = (0x04B), // Receive FIFO interrupt + ELC_EVENT_CAN0_FIFO_TX = (0x04C), // Transmit FIFO interrupt + ELC_EVENT_CAN0_MAILBOX_RX = (0x04D), // Reception complete interrupt + ELC_EVENT_CAN0_MAILBOX_TX = (0x04E), // Transmission complete interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x04F), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x050), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x051), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x052), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x053), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x054), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x055), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x056), // Port Output disable 1 interrupt + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x057), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x058), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x059), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x05A), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x05B), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x05C), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x05D), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x05E), // Underflow + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x05F), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x060), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x061), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x062), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x063), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x064), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x065), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x066), // Underflow + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x067), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x068), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x069), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x06A), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x06B), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x06C), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x06D), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x06E), // Underflow + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x06F), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x070), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x071), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x072), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x073), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x074), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x075), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x076), // Underflow + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x077), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x078), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x079), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x07A), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x07B), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x07C), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x07D), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x07E), // Underflow + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x07F), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x080), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x081), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x082), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x083), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x084), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x085), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x086), // Underflow + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x087), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x088), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x089), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x08A), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x08B), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x08C), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x08D), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x08E), // Underflow + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x08F), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x090), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x091), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x092), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x093), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x094), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x095), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x096), // Underflow + ELC_EVENT_OPS_UVW_EDGE = (0x097), // UVW edge event + ELC_EVENT_SCI0_RXI = (0x098), // Receive data full + ELC_EVENT_SCI0_TXI = (0x099), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x09A), // Transmit end + ELC_EVENT_SCI0_ERI = (0x09B), // Receive error + ELC_EVENT_SCI0_AM = (0x09C), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x09D), // Receive data full/Receive error + ELC_EVENT_SCI1_RXI = (0x09E), // Receive data full + ELC_EVENT_SCI1_TXI = (0x09F), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x0A0), // Transmit end + ELC_EVENT_SCI1_ERI = (0x0A1), // Receive error + ELC_EVENT_SCI1_AM = (0x0A2), // Address match event + ELC_EVENT_SCI2_RXI = (0x0A3), // Receive data full + ELC_EVENT_SCI2_TXI = (0x0A4), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x0A5), // Transmit end + ELC_EVENT_SCI2_ERI = (0x0A6), // Receive error + ELC_EVENT_SCI2_AM = (0x0A7), // Address match event + ELC_EVENT_SCI9_RXI = (0x0A8), // Receive data full + ELC_EVENT_SCI9_TXI = (0x0A9), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x0AA), // Transmit end + ELC_EVENT_SCI9_ERI = (0x0AB), // Receive error + ELC_EVENT_SCI9_AM = (0x0AC), // Address match event + ELC_EVENT_SPI0_RXI = (0x0AD), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x0AE), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x0AF), // Idle + ELC_EVENT_SPI0_ERI = (0x0B0), // Error + ELC_EVENT_SPI0_TEI = (0x0B1), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x0B2), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x0B3), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x0B4), // Idle + ELC_EVENT_SPI1_ERI = (0x0B5), // Error + ELC_EVENT_SPI1_TEI = (0x0B6) // Transmission complete event +} elc_event_t; + +typedef elc_event_t bsp_interrupt_event_t; + +const bsp_interrupt_event_t g_interrupt_event_link_select[32] = +{ + [0] = ELC_EVENT_SCI0_RXI, /* SCI0 RXI (Receive data full) */ + [1] = ELC_EVENT_SCI0_TXI, /* SCI0 TXI (Transmit data empty) */ + [2] = ELC_EVENT_SCI0_TEI, /* SCI0 TEI (Transmit end) */ + [3] = ELC_EVENT_SCI0_ERI, /* SCI0 ERI (Receive error) */ + [4] = ELC_EVENT_SCI1_RXI, /* SCI1 RXI (Received data full) */ + [5] = ELC_EVENT_SCI1_TXI, /* SCI1 TXI (Transmit data empty) */ + [6] = ELC_EVENT_SCI1_TEI, /* SCI1 TEI (Transmit end) */ + [7] = ELC_EVENT_SCI1_ERI, /* SCI1 ERI (Receive error) */ + [8] = ELC_EVENT_SCI2_RXI, /* SCI2 RXI (Received data full) */ + [9] = ELC_EVENT_SCI2_TXI, /* SCI2 TXI (Transmit data empty) */ + [10] = ELC_EVENT_SCI2_TEI, /* SCI2 TEI (Transmit end) */ + [11] = ELC_EVENT_SCI2_ERI, /* SCI2 ERI (Receive error) */ + [12] = ELC_EVENT_RTC_ALARM, /* RTC ALARM (Alarm interrupt) */ + [13] = ELC_EVENT_RTC_PERIOD, /* RTC PERIOD (Periodic interrupt) */ + [14] = ELC_EVENT_RTC_CARRY, /* RTC CARRY (Carry interrupt) */ + [15] = ELC_EVENT_AGT0_INT, /* AGT0 INT (AGT interrupt) */ + [16] = ELC_EVENT_ICU_IRQ0, /* ICU IRQ0 (External pin interrupt 0) */ + [17] = ELC_EVENT_SPI0_RXI, /* SPI0 RXI (Receive buffer full) */ + [18] = ELC_EVENT_SPI0_TXI, /* SPI0 TXI (Transmit buffer empty) */ + [19] = ELC_EVENT_SPI0_TEI, /* SPI0 TEI (Transmission complete event) */ + [20] = ELC_EVENT_SPI0_ERI, /* SPI0 ERI (Error) */ +}; + +__attribute__((always_inline)) static inline void ra_enable_irq(__attribute__((unused)) uint32_t state) { + __asm__ volatile ("cpsie f" + : + : + : "memory"); +} + +__attribute__((always_inline)) static inline uint32_t ra_disable_irq(void) { + uint32_t state; + __asm__ volatile ("cpsid f" + : "=r" (state) + : + : "memory"); + return state; +} + +uint32_t check; void uart_init(void) { @@ -440,13 +394,15 @@ void uart_init(void) // 3. Initialize SCI1 registers + uint32_t state = ra_disable_irq(); + // Disable TE and RE R_SCI0->SCR = 0x00; while (R_SCI0->SCR != 0); - // R_SCI0->SMR = 0x00; - // R_SCI0->SCMR = 0xF3; - // R_SCI0->SEMR = 0xC0; + R_SCI0->SMR = 0x00; + R_SCI0->SCMR = 0xF3; + R_SCI0->SEMR = 0xC0; R_SCI0->FCR_b.FM = 1; R_SCI0->FCR_b.TFRST = 1; @@ -463,24 +419,33 @@ void uart_init(void) - R_SCI0->FCR_b.TFRST = 0; - R_SCI0->FCR_b.RFRST = 0; + // R_SCI0->FCR_b.TFRST = 0; + // R_SCI0->FCR_b.RFRST = 0; // Delay at least 1 bit time (~8.6 us at 115200 baud) // for (volatile int i = 0; i < 1000; ++i) { __asm__("nop"); } - // Enable transmit and receive - R_SCI0->SCR_b.RE = 0x01; - R_SCI0->SCR_b.TE = 0x01; - - R_SCI0->SCR_b.TIE = 1; // Transmit Interrupt Enable (TXI0) - R_SCI0->SCR_b.RIE = 1; // Receive Interrupt Enable (RXI0) - NVIC_EnableIRQ(INTERRUPTS_IELSR22); // Transmit interrupt - NVIC_EnableIRQ(INTERRUPTS_IELSR23); // Receive interrupt - __enable_irq(); + // Enable transmit and receive AND their interrupts + // NVIC_SetVector((IRQn_Type) INTERRUPTS_IELSR22, (uint32_t) sci_uart_rxi_isr); // SCI0_RXI_IRQn + // NVIC_SetVector((IRQn_Type) INTERRUPTS_IELSR23, (uint32_t) sci_uart_txi_isr); // SCI0_TXI_IRQn + R_ICU->IELSR[22] = (uint32_t) g_interrupt_event_link_select[0]; + R_ICU->IELSR[23] = (uint32_t) g_interrupt_event_link_select[1]; + NVIC_EnableIRQ(38); + NVIC_EnableIRQ(39); + interrupts_enable(); + R_SCI0->SSR_b.RDRF = 0; + R_SCI0->SSR_b.TDRE = 0; + R_SCI0->SCR = 0x30; // TE + RE + R_SCI0->SCR |= 0xC0; // TIE + RIE } +volatile char tx_buffer[128]; +volatile int tx_head = 0, tx_tail = 0; + +volatile char rx_buffer[128]; +volatile int rx_head = 0, rx_tail = 0; + void uart_send_char(char c) { // Wait until there is space in the transmit FIFO (TDFE = 1) @@ -503,54 +468,73 @@ char uart_receive_char(void) return c; } -void SCI0_RXI_Handler(void) -{ +static void ra_sci_isr_rx(uint32_t ch) { if (R_SCI0->SSR_b.RDRF) { - char received = R_SCI0->RDR; - R_SCI0->SSR_b.RDRF = 0; // Clear RDRF - // Echo back or process - uart_send_char(received); + char c = R_SCI0->RDR; + R_SCI0->SSR_b.RDRF = 0; // Clear flag + + int next = (rx_head + 1) % sizeof(rx_buffer); + if (next != rx_tail) + { + rx_buffer[rx_head] = c; + rx_head = next; + } } } -volatile const char *tx_buffer = "Hello World\r\n"; -volatile uint8_t tx_index = 0; - -void SCI0_TXI_Handler(void) -{ +static void ra_sci_isr_tx(uint32_t ch) { if (R_SCI0->SSR_b.TDRE) { - if (tx_buffer[tx_index] != '\0') + if (tx_head != tx_tail) { - R_SCI0->TDR = tx_buffer[tx_index++]; - R_SCI0->SSR_b.TDRE = 0; // Clear TDRE + R_SCI0->TDR = tx_buffer[tx_tail]; + tx_tail = (tx_tail + 1) % sizeof(tx_buffer); } else { - R_SCI0->SCR_b.TIE = 0; // Disable TX interrupt - tx_index = 0; + R_SCI0->SCR_b.TIE = 0; // Disable TX interrupt if nothing to send } + + R_SCI0->SSR_b.TDRE = 0; // Clear flag } } +/* rx-interrupt */ +void ICU_IELSR22_Handler(void) { + // IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint32_t ch = 0; + ra_sci_isr_rx(ch); +} + +/* tx-interrupt */ +void ICU_IELSR23_Handler(void) { + // IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint32_t ch = 1; + ra_sci_isr_tx(ch); +} + int main( void ) { /* Do not remove this line or clock might not be set correctly. */ #ifdef PREINIT_SUPPORTED preinit(); #endif + SCB->VTOR = (uint32_t)&g_vector_table; + uart_init(); + check = R_ICU->IELSR[23]; uart_send_char('H'); + check = R_ICU->IELSR[23]; uart_send_char('i'); - uart_send_char('!'); + uart_send_char('\r'); uart_send_char('\n'); while (1) { - char c = uart_receive_char(); - uart_send_char(c); // Echo received char + // char c = uart_receive_char(); + // uart_send_char(c); // Echo received char } return 0; From d804cd0ad9d15d800b53f5de14512c2eb2b0a0b0 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 23 Jul 2025 09:53:00 +0200 Subject: [PATCH 25/62] GPIO update --- .../RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 1 + .../include/gpio/hal_ll_gpio_constants.h | 42 +++++++++---------- .../implementation_1/hal_ll_tim_pin_map.h | 9 ++-- .../gpio/implementation_1/hal_ll_gpio_port.c | 38 +++++++++++++---- .../i2c/implementation_1/hal_ll_i2c_master.c | 3 +- .../src/tim/implementation_1/hal_ll_tim.c | 41 +++++++++++------- 6 files changed, 84 insertions(+), 50 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h index b51e97c1c1..3be04f9b3a 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -88,6 +88,7 @@ #define TIM_MODULE_4 5 #define TIM4_P302 +#define TIM0_P107 #define TIM_MODULE_COUNT 12 //EOF TIM diff --git a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_constants.h b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_constants.h index 402a14274a..ab4fe47a1f 100644 --- a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_constants.h +++ b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_constants.h @@ -48,30 +48,28 @@ extern "C"{ #endif -#define GPIO_CFG_PORT_DIRECTION_INPUT (0x00000000) // Sets the pin direction to input (default) -#define GPIO_CFG_PORT_DIRECTION_OUTPUT (0x00000004) // Sets the pin direction to output -#define GPIO_CFG_PORT_OUTPUT_LOW (0x00000000) // Sets the pin level to low -#define GPIO_CFG_PORT_OUTPUT_HIGH (0x00000001) // Sets the pin level to high -#define GPIO_CFG_PULLUP_ENABLE (0x00000010) // Enables the pin's internal pull-up -#define GPIO_CFG_PIM_TTL (0x00000020) // Enables the pin's input mode -#define GPIO_CFG_NMOS_ENABLE (0x00000040) // Enables the pin's NMOS open-drain output -#define GPIO_CFG_PMOS_ENABLE (0x00000080) // Enables the pin's PMOS open-drain ouput -#define GPIO_CFG_DRIVE_MID (0x00000400) // Sets pin drive output to medium -#define GPIO_CFG_DRIVE_HS_HIGH (0x00000800) // Sets pin drive output to high along with supporting high speed -#define GPIO_CFG_DRIVE_MID_IIC (0x00000800) // Sets pin to drive output needed for IIC on a 20mA port -#define GPIO_CFG_DRIVE_HIGH (0x00000C00) // Sets pin drive output to high -#define GPIO_CFG_EVENT_RISING_EDGE (0x00001000) // Sets pin event trigger to rising edge -#define GPIO_CFG_EVENT_FALLING_EDGE (0x00002000) // Sets pin event trigger to falling edge -#define GPIO_CFG_EVENT_BOTH_EDGES (0x00003000) // Sets pin event trigger to both edges -#define GPIO_CFG_IRQ_ENABLE (0x00004000) // Sets pin as an IRQ pin -#define GPIO_CFG_ANALOG_ENABLE (0x00008000) // Enables pin to operate as an analog pin -#define GPIO_CFG_PERIPHERAL_PIN (0x00010000) // Enables pin to operate as a peripheral pin +#define GPIO_CFG_PORT_OUTPUT_HIGH (0x00000001UL) // Sets the output level to HIGH (only valid for output pins) +#define GPIO_CFG_PORT_OUTPUT_LOW (0x00000000UL) // Sets the output level to LOW (only valid for output pins) +#define GPIO_CFG_PORT_DIRECTION_OUTPUT (0x00000004UL) // Configures the pin direction as OUTPUT +#define GPIO_CFG_PORT_DIRECTION_INPUT (0x00000000UL) // Configures the pin direction as INPUT +#define GPIO_CFG_PORT_PULL_UP_ENABLE (0x00000010UL) // Enables the internal pull-up resistor +#define GPIO_CFG_NMOS_OPEN_DRAIN_ENABLE (0x00000040UL) // Enables NMOS open-drain output (drives low or floats) +#define GPIO_CFG_PORT_LOW_DRIVE (0x00000000UL) // Sets the output drive strength to LOW +#define GPIO_CFG_PORT_MIDDLE_DRIVE (0x00000400UL) // Sets the output drive strength to MIDDLE +#define GPIO_CFG_PORT_MIDDLE_DRIVE_P408 (0x00000800UL) // Sets the output drive strength to MIDDLE for IIC Fast-mode +#define GPIO_CFG_EVENT_RISING_EDGE (0x00001000UL) // Configures the pin to trigger an event on rising edge +#define GPIO_CFG_EVENT_FALLING_EDGE (0x00002000UL) // Configures the pin to trigger an event on falling edge +#define GPIO_CFG_EVENT_BOTH_EDGES (0x00003000UL) // Configures the pin to trigger an event on both edges +#define GPIO_CFG_IRQ_ENABLE (0x00004000UL) // Enables interrupt generation for this pin +#define GPIO_CFG_ANALOG_ENABLE (0x00008000UL) // Configures the pin to operate in analog mode +#define GPIO_CFG_PERIPHERAL_PIN (0x00010000UL) // Configures the pin for peripheral function (not GPIO) -#define GPIO_PRV_PFS_PSEL_OFFSET (24) // Peripheral function selection offset +#define GPIO_PRV_PFS_PSEL_OFFSET (24) // Bit offset for Peripheral Function Selection (PSEL) +#define GPIO_PRV_PFS_PSEL_MASK (0x1F000000UL) // Bit mask for Peripheral Function Selection (PSEL) -#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_ANALOG_ENABLE | GPIO_CFG_PORT_DIRECTION_INPUT ) // TODO Esma -#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_PORT_DIRECTION_OUTPUT ) // TODO Esma -#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_PORT_DIRECTION_INPUT ) // TODO Esma +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_ANALOG_ENABLE | GPIO_CFG_PORT_DIRECTION_INPUT ) +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_PORT_DIRECTION_OUTPUT ) +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_PORT_DIRECTION_INPUT ) #ifdef __cplusplus } diff --git a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h index 51004b6e33..d2b974b7fd 100644 --- a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h +++ b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h @@ -57,7 +57,7 @@ extern "C"{ /*!< @brief TIMER module base addresses. */ #ifdef TIM_MODULE_0 -static const hal_ll_base_addr_t HAL_LL_TIM0_BASE_ADDR = 0x40078400; +static const hal_ll_base_addr_t HAL_LL_TIM0_BASE_ADDR = 0x40078000; #endif #ifdef TIM_MODULE_1 static const hal_ll_base_addr_t HAL_LL_TIM1_BASE_ADDR = 0x40078400; @@ -78,7 +78,7 @@ static const hal_ll_base_addr_t HAL_LL_TIM5_BASE_ADDR = 0x40078400; typedef enum { HAL_LL_TIM_PIN_A = 0, HAL_LL_TIM_PIN_B -} hal_ll_tim_pin_type; +} hal_ll_tim_pin_type_t; /*!< @brief TIM pin structure. */ typedef struct { @@ -86,7 +86,7 @@ typedef struct { hal_ll_base_addr_t base; uint8_t af; hal_ll_pin_name_t module_index; - hal_ll_tim_pin_type pin_type; + hal_ll_tim_pin_type_t pin_type; } hal_ll_tim_pin_map_t; /*!< TIM pins. */ @@ -94,6 +94,9 @@ static const hal_ll_tim_pin_map_t hal_ll_tim_pin_map[] = { #ifdef TIM4_P302 {GPIO_P302, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_PIN_A}, #endif + #ifdef TIM0_P107 + {GPIO_P107, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_PIN_A}, + #endif { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC } diff --git a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c index ff10d025d9..5c7179cf77 100644 --- a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c @@ -43,9 +43,9 @@ #include "hal_ll_gpio_port.h" -#define hal_ll_gpio_port_get_pin_index(__index) ( ( uint8_t )__index&0xF )//% PORT_SIZE ) +#define hal_ll_gpio_port_get_pin_index(__index) ( ( uint8_t )__index & 0xF ) -#define hal_ll_gpio_port_get_port_index(__index) ( ( uint8_t )(__index&0xF0) >> 4 ) +#define hal_ll_gpio_port_get_port_index(__index) ( ( uint8_t )( __index & 0xF0 ) >> 4 ) #ifdef GPIO_PORT_0 #define GPIO_PORT0_BASE (0x40040000UL) @@ -245,9 +245,9 @@ static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t conf PWPR_REGISTER_BASE |= 0x40; // Set PFSWE bit if ( pin_mask == 0xFFFF ) { - if ( GPIO_CFG_DIGITAL_OUTPUT == config ) + if ( config & GPIO_CFG_DIGITAL_OUTPUT ) port_ptr->pdr = pin_mask; - else if ( GPIO_CFG_DIGITAL_INPUT == config ) + else port_ptr->pdr = 0; } else { // Clear the Port Mode Control bit in the PMR for the target pin to select the general I/O port. @@ -255,18 +255,42 @@ static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t conf // Specify the input/output function for the pin through the PSEL[4:0] bit settings in the PmnPFS register. port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.psel = 0; - if( GPIO_CFG_ANALOG_INPUT == config ) { + if( config & GPIO_CFG_ANALOG_INPUT ) { port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pmr = 0; port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pdr = 0; port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.asel = 1; - } else if ( GPIO_CFG_DIGITAL_OUTPUT == config ) { + } else if ( config & GPIO_CFG_DIGITAL_OUTPUT ) { port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pdr = 1; port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.asel = 0; - } else if ( GPIO_CFG_DIGITAL_INPUT == config ) { + } else if ( config & GPIO_CFG_DIGITAL_INPUT ) { port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pdr = 0; port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.asel = 0; } + if( config & GPIO_CFG_PORT_PULL_UP_ENABLE ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pcr = 1; + + if( config & GPIO_CFG_NMOS_OPEN_DRAIN_ENABLE ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.ncodr = 1; + + if( config & GPIO_CFG_PORT_MIDDLE_DRIVE ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.dscr = 1; + + if( config & GPIO_CFG_EVENT_RISING_EDGE ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.eofr = 1; + + if( config & GPIO_CFG_EVENT_FALLING_EDGE ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.eofr = 2; + + if( config & GPIO_CFG_EVENT_BOTH_EDGES ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.eofr = 3; + + if( config & GPIO_CFG_IRQ_ENABLE ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.isel = 1; + + if( config & GPIO_CFG_PERIPHERAL_PIN ) + port_pfs_ptr->port[port_index].pin[pin_index].pmnpfs_b.pmr = 1; + // Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register. PWPR_REGISTER_BASE &= ~0x40; // Set PFSWE bit // Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register diff --git a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c index c9967f464d..480506b4b6 100644 --- a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c @@ -45,7 +45,6 @@ #include "hal_ll_i2c_pin_map.h" #include "hal_ll_mstpcr.h" #include "delays.h" -#include "mcu.h" // TODO Esma /*!< @brief Local handle list */ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; @@ -61,7 +60,7 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU #define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base -#define HAL_LL_I2C_AF_CONFIG 0xFF // TODO Esma +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_PORT_PULL_UP_ENABLE | GPIO_CFG_DIGITAL_OUTPUT | GPIO_CFG_NMOS_OPEN_DRAIN_ENABLE) // TODO Esma /*!< @brief Bit positions and masks */ #define HAL_LL_I2C_ICCR1_IICRST (6) diff --git a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c index 6fc61fb55e..b07e0d82a7 100644 --- a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c @@ -122,7 +122,7 @@ typedef struct { hal_ll_pin_name_t pin; // hal_ll_channel_t channel; - hal_ll_tim_pin_type pin_type; + hal_ll_tim_pin_type_t pin_type; uint32_t af; } hal_ll_tim_t; @@ -463,12 +463,19 @@ static void hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { static void hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { module_struct module; + uint32_t tim_config = 0; - if ( ( map->config.pin != HAL_LL_PIN_NC ) && map->config.pin != HAL_LL_PIN_NC ) { - module.pins[0] = map->config.pin; + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_DIGITAL_OUTPUT; // TODO Esma + } else { + tim_config = GPIO_CFG_DIGITAL_OUTPUT; // TODO Esma + } + + module.pins[0] = VALUE( map->config.pin, map->config.af ); module.pins[1] = GPIO_MODULE_STRUCT_END; - module.configs[0] = map->config.af/* & HAL_LL_ALTERNATE_FUNCTION_MASK*/; + module.configs[0] = tim_config; module.configs[1] = GPIO_MODULE_STRUCT_END; hal_ll_gpio_module_struct_init( &module, hal_ll_state ); @@ -496,25 +503,25 @@ static void hal_ll_tim_set_freq_bare_metal( hal_ll_tim_hw_specifics_map_t *map ) // (0b01 << 0) | // GTIOCA output when counting up and not matching (output = 0) // (1 << 14); // Enable GTIOCA output - R_GPT4->GTCCR[0] = COMPARE; // Set compare match A - R_GPT4->GTCCR[2] = COMPARE; // Buffered A + R_GPT0->GTCCR[0] = COMPARE; // Set compare match A + R_GPT0->GTCCR[2] = COMPARE; // Buffered A } - R_GPT4->GTPR = PERIOD - 1; // Set PWM period - R_GPT4->GTPBR = PERIOD - 1; // Buffered period + R_GPT0->GTPR = PERIOD - 1; // Set PWM period + R_GPT0->GTPBR = PERIOD - 1; // Buffered period - R_GPT4->GTCR = (0b000 << 1); // PCLK/1 as clock source (TPCS bits) + R_GPT0->GTCR = (0b000 << 1); // PCLK/1 as clock source (TPCS bits) - R_GPT4->GTCNT = 0; // Clear counter - R_GPT4->GTCR |= (1 << 0); // Start timer (CST = 1) + R_GPT0->GTCNT = 0; // Clear counter + R_GPT0->GTCR |= (1 << 0); // Start timer (CST = 1) } static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); - + hal_ll_tim_pin_type_t pin_type = map->config.pin_type; // PSEL 3 // R_MSTP->MSTPCRD_b.MSTPD6 = 0; - clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD6_POS ); + clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD5_POS ); // R_GPT4->GTCR_b.CST = 0; // stop operation first clear_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST ); // Stop operation first. @@ -566,9 +573,11 @@ static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { // R_PFS->PORT[3].PIN[2].PmnPFS_b.PMR = 1; // R_PFS->PORT[3].PIN[2].PmnPFS_b.PSEL = 3; - if (R_GPT4->GTPR && R_GPT4->GTCCR[0]) { - R_GPT4->GTCR_b.CST = 1; - } + // if (R_GPT4->GTPR && R_GPT4->GTCCR[0]) { + // R_GPT4->GTCR_b.CST = 1; + // } + if( read_reg( &hal_ll_hw_reg->gtpr ) && read_reg( &hal_ll_hw_reg->gtccr[(HAL_LL_TIM_PIN_A == pin_type) ? 0 : 1])) + set_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST ); // Start operation. } static void hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { From 8cad41da5b75eb31ebd18b5948974f4c855d5109 Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Wed, 23 Jul 2025 10:27:18 +0200 Subject: [PATCH 26/62] WIP update for SDK implementation --- .../RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 13 +++--- .../src/uart/implementation_1/hal_ll_uart.c | 45 ++++++++++++------- tests/CMakeLists.txt | 2 +- 3 files changed, 38 insertions(+), 22 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h index b51e97c1c1..99514588d4 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -67,13 +67,16 @@ //EOF I2C //UART +#define UART0_RX_P410 +#define UART0_TX_P411 -//EOF UART - -//USART +#define UART_MODULE_0 1 +#define UART_MODULE_1 2 +#define UART_MODULE_2 3 +#define UART_MODULE_9 10 -#define UART_MODULE_COUNT 8 -//EOF USART +#define UART_MODULE_COUNT 4 +//EOF UART //SPI diff --git a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c index 6ffc5c3aae..04edb2cc0a 100644 --- a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c @@ -82,7 +82,14 @@ static volatile hal_ll_uart_handle_register_t hal_ll_module_state[ UART_MODULE_C /*!< @brief UART HW register structure. */ typedef struct { - + uint8_t smr; // Serial Mode Register. + uint8_t brr; // Bit Rate Register. + uint8_t scr; // Serial Control Register. + uint8_t tdr; // Transmit Data Register. + uint8_t ssr; // Serial Status Register. + uint8_t rdr; // Receive Data Register. + uint8_t scmr; // Smart Card Mode Register. + uint8_t semr; // Serial Extended Mode Register. } hal_ll_uart_base_handle_t; /*!< @brief UART baud rate structure. */ @@ -127,28 +134,34 @@ typedef enum { /*!< @brief UART hardware specific info. */ static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[ UART_MODULE_COUNT + 1 ] = { #ifdef UART_MODULE_0 - {HAL_LL_UART0_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_0 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART0_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_0 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_1 - {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_1 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_1 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_2 - {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_2 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_2 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_3 - {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_3 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_3 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_4 - {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_4 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_4 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_5 - {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_5 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_5 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_6 - {HAL_LL_UART6_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_6 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART6_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_6 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_7 - {HAL_LL_UART7_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_7 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART7_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_7 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_8 + {HAL_LL_UART8_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_8 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_9 + {HAL_LL_UART9_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_9 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} @@ -553,37 +566,37 @@ void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { } switch ( hal_ll_uart_hw_specifics_map_local->module_index ) { - #if defined(UART_MODULE_0) && defined(UART0_NVIC) + #if defined( UART_MODULE_0 ) && defined( UART0_NVIC ) case hal_ll_uart_module_num( UART_MODULE_0 ): hal_ll_core_enable_irq( UART0_NVIC ); break; #endif - #if defined(UART_MODULE_1) && defined(UART1_NVIC) + #if defined( UART_MODULE_1 ) && defined( UART1_NVIC ) case hal_ll_uart_module_num( UART_MODULE_1 ): hal_ll_core_enable_irq( UART1_NVIC ); break; #endif - #if defined(UART_MODULE_2) && defined(UART2_NVIC) + #if defined( UART_MODULE_2 ) && defined( UART2_NVIC ) case hal_ll_uart_module_num( UART_MODULE_2 ): hal_ll_core_enable_irq( UART2_NVIC ); break; #endif - #if defined(UART_MODULE_3) && defined(UART3_NVIC) + #if defined( UART_MODULE_3 ) && defined( UART3_NVIC ) case hal_ll_uart_module_num( UART_MODULE_3 ): hal_ll_core_enable_irq( UART3_NVIC ); break; #endif - #if defined(UART_MODULE_4) && defined(UART4_NVIC) + #if defined( UART_MODULE_4 ) && defined( UART4_NVIC ) case hal_ll_uart_module_num( UART_MODULE_4 ): hal_ll_core_enable_irq( UART4_NVIC ); break; #endif - #if defined(UART_MODULE_5) && defined(UART5_NVIC) + #if defined( UART_MODULE_5 ) && defined( UART5_NVIC ) case hal_ll_uart_module_num( UART_MODULE_5 ): hal_ll_core_enable_irq( UART5_NVIC ); break; #endif - #if defined(UART_MODULE_6) && defined(UART6_NVIC) + #if defined( UART_MODULE_6 ) && defined( UART6_NVIC ) case hal_ll_uart_module_num( UART_MODULE_6 ): hal_ll_core_enable_irq( UART6_NVIC ); break; diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 8ae42e1322..99c7d316f8 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -60,7 +60,7 @@ endif() memory_sdk_test_check(memory_issue 8192 4096) if (${memory_issue} STREQUAL "FALSE") - # add_subdirectory(uart) + add_subdirectory(uart) else() message(INFO ": ${MCU_NAME} does not have enough memory for \"uart\" test.") endif() From b04579d5d643caf02919a636f41ceee70ed9ea99 Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Wed, 23 Jul 2025 12:52:24 +0200 Subject: [PATCH 27/62] WIP commit -> need to set baud rate dynamically --- platform/ring/lib/src/ring.c | 4 + .../mikroe/renesas/include/uart/hal_ll_uart.h | 1 + .../implementation_1/hal_ll_uart_pin_map.h | 192 +--------- .../src/uart/implementation_1/hal_ll_uart.c | 354 +++++++++++++----- 4 files changed, 279 insertions(+), 272 deletions(-) diff --git a/platform/ring/lib/src/ring.c b/platform/ring/lib/src/ring.c index b145eed239..501a3700f0 100644 --- a/platform/ring/lib/src/ring.c +++ b/platform/ring/lib/src/ring.c @@ -70,7 +70,11 @@ bool ring_buf8_push( ring_buf8_t *ring, uint8_t data_ ) uint8_t ring_buf8_pop( ring_buf8_t *ring ) { uint8_t result; + + // GCC & Clang compiler files for Renesas are not included into the project. + #if (vendor != renesas) assert( ring->size > 0 ); + #endif result = ring->buffer[ ring->tail ]; ring->tail = ( ring->tail + 1 ) % ring->capacity; diff --git a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h index 226d71a8eb..fb18eb9750 100644 --- a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h +++ b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h @@ -98,6 +98,7 @@ typedef enum HAL_LL_UART_DATA_BITS_6, HAL_LL_UART_DATA_BITS_7, HAL_LL_UART_DATA_BITS_8, + HAL_LL_UART_DATA_BITS_9, HAL_LL_UART_DATA_BITS_DEFAULT = HAL_LL_UART_DATA_BITS_8 } hal_ll_uart_data_bits_t; diff --git a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h index e5e17d758c..bc34f4700d 100644 --- a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h +++ b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h @@ -57,28 +57,34 @@ extern "C"{ /*!< @brief UART module base addresses */ #ifdef UART_MODULE_0 -static const hal_ll_base_addr_t HAL_LL_UART0_BASE_ADDRESS = 0x4000C000; +static const hal_ll_base_addr_t HAL_LL_UART0_BASE_ADDRESS = 0x40070000UL; #endif #ifdef UART_MODULE_1 -static const hal_ll_base_addr_t HAL_LL_UART1_BASE_ADDRESS = 0x4000D000; +static const hal_ll_base_addr_t HAL_LL_UART1_BASE_ADDRESS = 0x40070020UL; #endif #ifdef UART_MODULE_2 -static const hal_ll_base_addr_t HAL_LL_UART2_BASE_ADDRESS = 0x4000E000; +static const hal_ll_base_addr_t HAL_LL_UART2_BASE_ADDRESS = 0x40070040UL; #endif #ifdef UART_MODULE_3 -static const hal_ll_base_addr_t HAL_LL_UART3_BASE_ADDRESS = 0x4000F000; +static const hal_ll_base_addr_t HAL_LL_UART3_BASE_ADDRESS = 0x40070060UL; #endif #ifdef UART_MODULE_4 -static const hal_ll_base_addr_t HAL_LL_UART4_BASE_ADDRESS = 0x40010000; +static const hal_ll_base_addr_t HAL_LL_UART4_BASE_ADDRESS = 0x40070080UL; #endif #ifdef UART_MODULE_5 -static const hal_ll_base_addr_t HAL_LL_UART5_BASE_ADDRESS = 0x40011000; +static const hal_ll_base_addr_t HAL_LL_UART5_BASE_ADDRESS = 0x400700A0UL; #endif #ifdef UART_MODULE_6 -static const hal_ll_base_addr_t HAL_LL_UART6_BASE_ADDRESS = 0x40012000; +static const hal_ll_base_addr_t HAL_LL_UART6_BASE_ADDRESS = 0x400700C0UL; #endif #ifdef UART_MODULE_7 -static const hal_ll_base_addr_t HAL_LL_UART7_BASE_ADDRESS = 0x40013000; +static const hal_ll_base_addr_t HAL_LL_UART7_BASE_ADDRESS = 0x400700E0UL; +#endif +#ifdef UART_MODULE_8 +static const hal_ll_base_addr_t HAL_LL_UART8_BASE_ADDRESS = 0x40070100UL; +#endif +#ifdef UART_MODULE_9 +static const hal_ll_base_addr_t HAL_LL_UART9_BASE_ADDRESS = 0x40070120UL; #endif @@ -92,89 +98,8 @@ typedef struct { /*!< UART TX Pins. */ static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { - #ifdef UART0_TX_PA1_AF1 - {hal_ll_uart_module_num(UART_MODULE_0), GPIO_PA1, HAL_LL_UART0_BASE_ADDRESS, 1}, - #endif - #ifdef UART1_TX_PB1_AF1 - {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PB1, HAL_LL_UART1_BASE_ADDRESS, 1}, - #endif - #ifdef UART1_TX_PC5_AF2 - {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC5, HAL_LL_UART1_BASE_ADDRESS, 2}, - #endif - #ifdef UART2_TX_PD7_AF1 - {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PD7, HAL_LL_UART2_BASE_ADDRESS, 1}, - #endif - #ifdef UART2_TX_PG5_AF1 - {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PG5, HAL_LL_UART2_BASE_ADDRESS, 1}, - #endif - #ifdef UART3_TX_PC7_AF1 - {hal_ll_uart_module_num(UART_MODULE_3), GPIO_PC7, HAL_LL_UART3_BASE_ADDRESS, 1}, - #endif - #ifdef UART4_TX_PC5_AF1 - {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PC5, HAL_LL_UART4_BASE_ADDRESS, 1}, - #endif - #ifdef UART5_TX_PE5_AF1 - {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PE5, HAL_LL_UART5_BASE_ADDRESS, 1}, - #endif - #ifdef UART6_TX_PD5_AF1 - {hal_ll_uart_module_num(UART_MODULE_6), GPIO_PD5, HAL_LL_UART6_BASE_ADDRESS, 1}, - #endif - #ifdef UART7_TX_PE1_AF1 - {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PE1, HAL_LL_UART7_BASE_ADDRESS, 1}, - #endif - #ifdef UART4_TX_PJ1_AF1 - {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PJ1, HAL_LL_UART4_BASE_ADDRESS, 1}, - #endif - #ifdef UART5_TX_PJ3_AF1 - {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PJ3, HAL_LL_UART5_BASE_ADDRESS, 1}, - #endif - #ifdef UART6_TX_PJ5_AF1 - {hal_ll_uart_module_num(UART_MODULE_6), GPIO_PJ5, HAL_LL_UART6_BASE_ADDRESS, 1}, - #endif - #ifdef UART7_TX_PK5_AF1 - {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PK5, HAL_LL_UART7_BASE_ADDRESS, 1}, - #endif - #ifdef UART1_TX_PQ5_AF1 - {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PQ5, HAL_LL_UART1_BASE_ADDRESS, 1}, - #endif - #ifdef UART2_TX_PA7_AF1 - {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PA7, HAL_LL_UART2_BASE_ADDRESS, 1}, - #endif - #ifdef UART2_TX_PD5_AF1 - {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PD5, HAL_LL_UART2_BASE_ADDRESS, 1}, - #endif - #ifdef UART3_TX_PA5_AF1 - {hal_ll_uart_module_num(UART_MODULE_3), GPIO_PA5, HAL_LL_UART3_BASE_ADDRESS, 1}, - #endif - #ifdef UART3_TX_PJ1_AF1 - {hal_ll_uart_module_num(UART_MODULE_3), GPIO_PJ1, HAL_LL_UART3_BASE_ADDRESS, 1}, - #endif - #ifdef UART4_TX_PA3_AF1 - {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PA3, HAL_LL_UART4_BASE_ADDRESS, 1}, - #endif - #ifdef UART4_TX_PK1_AF1 - {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PK1, HAL_LL_UART4_BASE_ADDRESS, 1}, - #endif - #ifdef UART5_TX_PC7_AF1 - {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PC7, HAL_LL_UART5_BASE_ADDRESS, 1}, - #endif - #ifdef UART6_TX_PP1_AF1 - {hal_ll_uart_module_num(UART_MODULE_6), GPIO_PP1, HAL_LL_UART6_BASE_ADDRESS, 1}, - #endif - #ifdef UART7_TX_PC5_AF1 - {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PC5, HAL_LL_UART7_BASE_ADDRESS, 1}, - #endif - #ifdef UART1_TX_PR6_AF1 - {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PR6, HAL_LL_UART1_BASE_ADDRESS, 1}, - #endif - #ifdef UART4_TX_PR0_AF1 - {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PR0, HAL_LL_UART4_BASE_ADDRESS, 1}, - #endif - #ifdef UART5_TX_PH7_AF1 - {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PH7, HAL_LL_UART5_BASE_ADDRESS, 1}, - #endif - #ifdef UART7_TX_PH7_AF2 - {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PH7, HAL_LL_UART7_BASE_ADDRESS, 2}, + #ifdef UART0_TX_P411 + {hal_ll_uart_module_num(UART_MODULE_0), GPIO_P411, HAL_LL_UART0_BASE_ADDRESS, 4}, #endif {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} @@ -182,89 +107,8 @@ static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { /*!< UART RX Pins. */ static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = { - #ifdef UART0_RX_PA0_AF1 - {hal_ll_uart_module_num(UART_MODULE_0), GPIO_PA0, HAL_LL_UART0_BASE_ADDRESS, 1}, - #endif - #ifdef UART1_RX_PB0_AF1 - {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PB0, HAL_LL_UART1_BASE_ADDRESS, 1}, - #endif - #ifdef UART1_RX_PC4_AF2 - {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC4, HAL_LL_UART1_BASE_ADDRESS, 2}, - #endif - #ifdef UART2_RX_PD6_AF1 - {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PD6, HAL_LL_UART2_BASE_ADDRESS, 1}, - #endif - #ifdef UART2_RX_PG4_AF1 - {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PG4, HAL_LL_UART2_BASE_ADDRESS, 1}, - #endif - #ifdef UART3_RX_PC6_AF1 - {hal_ll_uart_module_num(UART_MODULE_3), GPIO_PC6, HAL_LL_UART3_BASE_ADDRESS, 1}, - #endif - #ifdef UART4_RX_PC4_AF1 - {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PC4, HAL_LL_UART4_BASE_ADDRESS, 1}, - #endif - #ifdef UART5_RX_PE4_AF1 - {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PE4, HAL_LL_UART5_BASE_ADDRESS, 1}, - #endif - #ifdef UART6_RX_PD4_AF1 - {hal_ll_uart_module_num(UART_MODULE_6), GPIO_PD4, HAL_LL_UART6_BASE_ADDRESS, 1}, - #endif - #ifdef UART7_RX_PE0_AF1 - {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PE0, HAL_LL_UART7_BASE_ADDRESS, 1}, - #endif - #ifdef UART4_RX_PJ0_AF1 - {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PJ0, HAL_LL_UART4_BASE_ADDRESS, 1}, - #endif - #ifdef UART5_RX_PJ2_AF1 - {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PJ2, HAL_LL_UART5_BASE_ADDRESS, 1}, - #endif - #ifdef UART6_RX_PJ4_AF1 - {hal_ll_uart_module_num(UART_MODULE_6), GPIO_PJ4, HAL_LL_UART6_BASE_ADDRESS, 1}, - #endif - #ifdef UART7_RX_PK4_AF1 - {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PK4, HAL_LL_UART7_BASE_ADDRESS, 1}, - #endif - #ifdef UART1_RX_PQ4_AF1 - {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PQ4, HAL_LL_UART1_BASE_ADDRESS, 1}, - #endif - #ifdef UART2_RX_PA6_AF1 - {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PA6, HAL_LL_UART2_BASE_ADDRESS, 1}, - #endif - #ifdef UART2_RX_PD4_AF1 - {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PD4, HAL_LL_UART2_BASE_ADDRESS, 1}, - #endif - #ifdef UART3_RX_PA4_AF1 - {hal_ll_uart_module_num(UART_MODULE_3), GPIO_PA4, HAL_LL_UART3_BASE_ADDRESS, 1}, - #endif - #ifdef UART3_RX_PJ0_AF1 - {hal_ll_uart_module_num(UART_MODULE_3), GPIO_PJ0, HAL_LL_UART3_BASE_ADDRESS, 1}, - #endif - #ifdef UART4_RX_PA2_AF1 - {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PA2, HAL_LL_UART4_BASE_ADDRESS, 1}, - #endif - #ifdef UART4_RX_PK0_AF1 - {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PK0, HAL_LL_UART4_BASE_ADDRESS, 1}, - #endif - #ifdef UART5_RX_PC6_AF1 - {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PC6, HAL_LL_UART5_BASE_ADDRESS, 1}, - #endif - #ifdef UART6_RX_PP0_AF1 - {hal_ll_uart_module_num(UART_MODULE_6), GPIO_PP0, HAL_LL_UART6_BASE_ADDRESS, 1}, - #endif - #ifdef UART7_RX_PC4_AF1 - {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PC4, HAL_LL_UART7_BASE_ADDRESS, 1}, - #endif - #ifdef UART1_RX_PR5_AF1 - {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PR5, HAL_LL_UART1_BASE_ADDRESS, 1}, - #endif - #ifdef UART4_RX_PR1_AF1 - {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PR1, HAL_LL_UART4_BASE_ADDRESS, 1}, - #endif - #ifdef UART5_RX_PH6_AF1 - {hal_ll_uart_module_num(UART_MODULE_5), GPIO_PH6, HAL_LL_UART5_BASE_ADDRESS, 1}, - #endif - #ifdef UART7_RX_PH6_AF2 - {hal_ll_uart_module_num(UART_MODULE_7), GPIO_PH6, HAL_LL_UART7_BASE_ADDRESS, 2}, + #ifdef UART0_RX_P410 + {hal_ll_uart_module_num(UART_MODULE_0), GPIO_P410, HAL_LL_UART0_BASE_ADDRESS, 4}, #endif {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} diff --git a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c index 04edb2cc0a..6a1d7c9a83 100644 --- a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c @@ -41,9 +41,11 @@ * @brief UART HAL LOW LEVEL layer implementation. */ +#include "mcu.h" #include "hal_ll_uart.h" #include "hal_ll_gpio.h" #include "hal_ll_core.h" +#include "hal_ll_mstpcr.h" #include "hal_ll_core_defines.h" #include "hal_ll_uart_pin_map.h" @@ -80,6 +82,21 @@ static volatile hal_ll_uart_handle_register_t hal_ll_module_state[ UART_MODULE_C */ #define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit(&(((hal_ll_uart_base_handle_t *)_handle)->icr), _flag)) +/*!< @brief Macros defining bit location */ +#define HAL_LL_SCI_SMR_STOP 3 +#define HAL_LL_SCI_SCMR_CHR1 4 +#define HAL_LL_SCI_SMR_PM 4 +#define HAL_LL_SCI_SCR_RE 4 +#define HAL_LL_SCI_SCR_TE 5 +#define HAL_LL_SCI_SMR_PE 5 +#define HAL_LL_SCI_SMR_CHR 6 +#define HAL_LL_SCI_SSR_RDRF 6 +#define HAL_LL_SCI_SSR_TDRE 7 + +/*!< @brief Macros defining register bit values */ +#define HAL_LL_SCI_CLOCK_INTERNAL 0x3 + + /*!< @brief UART HW register structure. */ typedef struct { uint8_t smr; // Serial Mode Register. @@ -432,13 +449,13 @@ hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_n } hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); - hal_ll_uart_handle_register_t *hal_handle = (hal_ll_uart_handle_register_t *)*handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + hal_ll_uart_handle_register_t *hal_handle = ( hal_ll_uart_handle_register_t * )*handle; uint8_t pin_check_result = hal_ll_uart_hw_specifics_map_local->module_index; hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); - hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = ( handle_t * )&hal_ll_uart_hw_specifics_map[pin_check_result].base; hal_ll_module_state[pin_check_result].init_ll_state = true; hal_handle->init_ll_state = true; @@ -447,13 +464,13 @@ hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { low_level_handle = hal_ll_uart_get_handle; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); low_level_handle->init_ll_state = false; hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; - hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); low_level_handle->init_ll_state = true; @@ -462,13 +479,13 @@ hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { low_level_handle = hal_ll_uart_get_handle; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); low_level_handle->init_ll_state = false; hal_ll_uart_hw_specifics_map_local->parity = parity; - hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); low_level_handle->init_ll_state = true; @@ -477,13 +494,13 @@ hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t pari hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { low_level_handle = hal_ll_uart_get_handle; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); low_level_handle->init_ll_state = false; hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; - hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); low_level_handle->init_ll_state = true; @@ -492,7 +509,7 @@ hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_ hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { low_level_handle = hal_ll_uart_get_handle; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); // Chips using this implementation do not support 7 bit data. if ( ( data_bit < HAL_LL_UART_DATA_BITS_5 ) || ( data_bit > HAL_LL_UART_DATA_BITS_8 ) ) { @@ -503,7 +520,7 @@ hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_ hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; - hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); low_level_handle->init_ll_state = true; @@ -512,17 +529,17 @@ hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_ void hal_ll_uart_close( handle_t *handle ) { low_level_handle = hal_ll_uart_get_handle; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); if( low_level_handle->hal_ll_uart_handle != NULL ) { - hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, true); + hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_local, true ); hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); - hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); - hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + hal_ll_uart_irq_disable( handle, HAL_LL_UART_IRQ_RX ); + hal_ll_uart_irq_disable( handle, HAL_LL_UART_IRQ_TX ); - hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); - hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + hal_ll_uart_clear_regs( hal_ll_uart_hw_specifics_map_local->base ); + hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_local, false ); hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; @@ -549,7 +566,7 @@ void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handl void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { low_level_handle = hal_ll_uart_get_handle; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; @@ -614,7 +631,7 @@ void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) { low_level_handle = hal_ll_uart_get_handle; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; @@ -642,42 +659,42 @@ void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) { ) { switch ( hal_ll_uart_hw_specifics_map_local->module_index ) { - #if defined(UART_MODULE_0) && defined(UART0_NVIC) + #if defined( UART_MODULE_0 ) && defined( UART0_NVIC ) case hal_ll_uart_module_num( UART_MODULE_0 ): hal_ll_core_disable_irq( UART0_NVIC ); break; #endif - #if defined(UART_MODULE_1) && defined(UART1_NVIC) + #if defined( UART_MODULE_1 ) && defined( UART1_NVIC ) case hal_ll_uart_module_num( UART_MODULE_1 ): hal_ll_core_disable_irq( UART1_NVIC ); break; #endif - #if defined(UART_MODULE_2) && defined(UART2_NVIC) + #if defined( UART_MODULE_2 ) && defined( UART2_NVIC ) case hal_ll_uart_module_num( UART_MODULE_2 ): hal_ll_core_disable_irq( UART2_NVIC ); break; #endif - #if defined(UART_MODULE_3) && defined(UART3_NVIC) + #if defined( UART_MODULE_3 ) && defined( UART3_NVIC ) case hal_ll_uart_module_num( UART_MODULE_3 ): hal_ll_core_disable_irq( UART3_NVIC ); break; #endif - #if defined(UART_MODULE_4) && defined(UART4_NVIC) + #if defined( UART_MODULE_4 ) && defined( UART4_NVIC ) case hal_ll_uart_module_num( UART_MODULE_4 ): hal_ll_core_disable_irq( UART4_NVIC ); break; #endif - #if defined(UART_MODULE_5) && defined(UART5_NVIC) + #if defined( UART_MODULE_5 ) && defined( UART5_NVIC ) case hal_ll_uart_module_num( UART_MODULE_5 ): hal_ll_core_disable_irq( UART5_NVIC ); break; #endif - #if defined(UART_MODULE_6) && defined(UART6_NVIC) + #if defined( UART_MODULE_6 ) && defined( UART6_NVIC ) case hal_ll_uart_module_num( UART_MODULE_6 ): hal_ll_core_disable_irq( UART6_NVIC ); break; #endif - #if defined(UART_MODULE_7) && defined(UART7_NVIC) + #if defined( UART_MODULE_7 ) && defined( UART7_NVIC ) case hal_ll_uart_module_num( UART_MODULE_7 ): hal_ll_core_disable_irq( UART7_NVIC ); break; @@ -689,142 +706,173 @@ void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) { } } -void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; - // TODO + + hal_ll_hw_reg->tdr = wr_data; } -void hal_ll_uart_write_polling( handle_t *handle, uint8_t wr_data) { - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); - hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; - // TODO +void hal_ll_uart_write_polling( handle_t *handle, uint8_t wr_data ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t * )hal_ll_uart_hw_specifics_map_local->base; + + // Wait until transmit data register is empty. + while ( !( check_reg_bit( &hal_ll_hw_reg->ssr, HAL_LL_SCI_SSR_TDRE ))); + hal_ll_hw_reg->tdr = wr_data; } uint8_t hal_ll_uart_read( handle_t *handle ) { - volatile uint16_t frame = 0; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); - hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t * )hal_ll_uart_hw_specifics_map_local->base; - return 0; // TODO + return hal_ll_hw_reg->rdr;; } uint8_t hal_ll_uart_read_polling( handle_t *handle ) { - volatile uint16_t frame = 0; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; - return 0; // TODO + // Wait until there is data in the receive data register. + while ( !( check_reg_bit( &hal_ll_hw_reg->ssr, HAL_LL_SCI_SSR_RDRF ))); + + return hal_ll_hw_reg->rdr; } // ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS -#if defined(UART_MODULE_0) && defined(UART0_NVIC) -void MARK_AS_IRQ_HANDLER UART0_IRQHandler(void) MIKROC_IV(UART0_NVIC) { - if ( hal_ll_uart_get_status_flags( HAL_LL_UART0_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { +#if defined( UART_MODULE_0 ) && defined( UART0_NVIC ) +void MARK_AS_IRQ_HANDLER UART0_IRQHandler( void ) MIKROC_IV( UART0_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART0_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART0_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_0 ) ], HAL_LL_UART_IRQ_RX ); } - if ( hal_ll_uart_get_status_flags( HAL_LL_UART0_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART0_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART0_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_0 ) ], HAL_LL_UART_IRQ_TX ); } } #endif -#if defined(UART_MODULE_1) && defined(UART1_NVIC) -void MARK_AS_IRQ_HANDLER UART1_IRQHandler(void) MIKROC_IV(UART1_NVIC) { - if ( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { +#if defined( UART_MODULE_1 ) && defined( UART1_NVIC ) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler( void ) MIKROC_IV( UART1_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_1 ) ], HAL_LL_UART_IRQ_RX ); } - if ( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_1 ) ], HAL_LL_UART_IRQ_TX ); } } #endif -#if defined(UART_MODULE_2) && defined(UART2_NVIC) -void MARK_AS_IRQ_HANDLER UART2_IRQHandler(void) MIKROC_IV(UART2_NVIC) { - if ( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { +#if defined( UART_MODULE_2 ) && defined( UART2_NVIC ) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler( void ) MIKROC_IV( UART2_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_2 ) ], HAL_LL_UART_IRQ_RX ); } - if ( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_2 ) ], HAL_LL_UART_IRQ_TX ); } } #endif -#if defined(UART_MODULE_3) && defined(UART3_NVIC) -void MARK_AS_IRQ_HANDLER UART3_IRQHandler(void) MIKROC_IV(UART3_NVIC) { - if ( hal_ll_uart_get_status_flags( HAL_LL_UART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { +#if defined( UART_MODULE_3 ) && defined( UART3_NVIC ) +void MARK_AS_IRQ_HANDLER UART3_IRQHandler( void ) MIKROC_IV( UART3_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_3 ) ], HAL_LL_UART_IRQ_RX ); } - if ( hal_ll_uart_get_status_flags( HAL_LL_UART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_3 ) ], HAL_LL_UART_IRQ_TX ); } } #endif -#if defined(UART_MODULE_4) && defined(UART4_NVIC) -void MARK_AS_IRQ_HANDLER UART4_IRQHandler(void) MIKROC_IV(UART4_NVIC) { - if ( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { +#if defined( UART_MODULE_4 ) && defined( UART4_NVIC ) +void MARK_AS_IRQ_HANDLER UART4_IRQHandler( void ) MIKROC_IV( UART4_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_4 ) ], HAL_LL_UART_IRQ_RX ); } - if ( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_4 ) ], HAL_LL_UART_IRQ_TX ); } } #endif -#if defined(UART_MODULE_5) && defined(UART5_NVIC) -void MARK_AS_IRQ_HANDLER UART5_IRQHandler(void) MIKROC_IV(UART5_NVIC) { - if ( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { +#if defined( UART_MODULE_5 ) && defined( UART5_NVIC ) +void MARK_AS_IRQ_HANDLER UART5_IRQHandler( void ) MIKROC_IV( UART5_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_5 ) ], HAL_LL_UART_IRQ_RX ); } - if ( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_5 )], HAL_LL_UART_IRQ_TX ); } } #endif -#if defined(UART_MODULE_6) && defined(UART6_NVIC) -void MARK_AS_IRQ_HANDLER UART6_IRQHandler(void) MIKROC_IV(UART6_NVIC) { - if ( hal_ll_uart_get_status_flags( HAL_LL_UART6_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { +#if defined( UART_MODULE_6 ) && defined( UART6_NVIC ) +void MARK_AS_IRQ_HANDLER UART6_IRQHandler( void ) MIKROC_IV( UART6_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART6_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART6_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_6 ) ], HAL_LL_UART_IRQ_RX ); } - if ( hal_ll_uart_get_status_flags( HAL_LL_UART6_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART6_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART6_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_6 ) ], HAL_LL_UART_IRQ_TX ); } } #endif -#if defined(UART_MODULE_7) && defined(UART7_NVIC) -void MARK_AS_IRQ_HANDLER UART7_IRQHandler(void) MIKROC_IV(UART7_NVIC) { - if ( hal_ll_uart_get_status_flags( HAL_LL_UART7_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG ) ) { +#if defined( UART_MODULE_7 ) && defined( UART7_NVIC ) +void MARK_AS_IRQ_HANDLER UART7_IRQHandler( void ) MIKROC_IV( UART7_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART7_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART7_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_7 ) ], HAL_LL_UART_IRQ_RX ); } - if ( hal_ll_uart_get_status_flags( HAL_LL_UART7_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG ) ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART7_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { hal_ll_uart_clear_status_flag( HAL_LL_UART7_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_7 ) ], HAL_LL_UART_IRQ_TX ); } } #endif +#if defined( UART_MODULE_8 ) && defined( UART8_NVIC ) +void MARK_AS_IRQ_HANDLER UART8_IRQHandler( void ) MIKROC_IV( UART8_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART8_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART8_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_8 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART8_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART8_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_8 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + +#if defined( UART_MODULE_9 ) && defined( UART9_NVIC ) +void MARK_AS_IRQ_HANDLER UART9_IRQHandler( void ) MIKROC_IV( UART9_NVIC ) { + if ( hal_ll_uart_get_status_flags( HAL_LL_UART9_BASE_ADDRESS , HAL_LL_UART_STATUS_RXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART9_BASE_ADDRESS, HAL_LL_UART_IT_RXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_9 ) ], HAL_LL_UART_IRQ_RX ); + } + if ( hal_ll_uart_get_status_flags( HAL_LL_UART9_BASE_ADDRESS , HAL_LL_UART_STATUS_TXMIS_FLAG )) { + hal_ll_uart_clear_status_flag( HAL_LL_UART9_BASE_ADDRESS, HAL_LL_UART_IT_TXIM_BIT ); + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_9 ) ], HAL_LL_UART_IRQ_TX ); + } +} +#endif + // ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS static uint8_t hal_ll_uart_find_index( handle_t *handle ) { - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { return hal_ll_uart_hw_specifics_map_local->module_index; @@ -841,7 +889,7 @@ static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_l uint16_t tx_index; uint16_t rx_index; - if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + if (( HAL_LL_PIN_NC == tx_pin ) || ( HAL_LL_PIN_NC == rx_pin )) { return HAL_LL_PIN_NC; } @@ -877,11 +925,11 @@ static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_l } static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { - uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); - static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_uart_handle_register_t )); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_uart_handle_register_t )); while( hal_ll_module_count-- ) { - if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + if ( hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base ) { return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; } } @@ -893,42 +941,52 @@ static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal switch ( map->module_index ) { #ifdef UART_MODULE_0 case ( hal_ll_uart_module_num( UART_MODULE_0 )): - ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART0EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART0EN ) ); + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB31_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB31_POS )); break; #endif #ifdef UART_MODULE_1 case ( hal_ll_uart_module_num( UART_MODULE_1 )): - ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART1EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART1EN ) ); + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB30_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB30_POS )); break; #endif #ifdef UART_MODULE_2 case ( hal_ll_uart_module_num( UART_MODULE_2 )): - ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART2EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART2EN ) ); + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB29_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB29_POS )); break; #endif #ifdef UART_MODULE_3 case ( hal_ll_uart_module_num( UART_MODULE_3 )): - ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART3EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART3EN ) ); + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB28_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB28_POS )); break; #endif #ifdef UART_MODULE_4 case ( hal_ll_uart_module_num( UART_MODULE_4 )): - ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART4EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART4EN ) ); + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB27_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB27_POS )); break; #endif #ifdef UART_MODULE_5 case ( hal_ll_uart_module_num( UART_MODULE_5 )): - ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART5EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART5EN ) ); + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB26_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB26_POS )); break; #endif #ifdef UART_MODULE_6 case ( hal_ll_uart_module_num( UART_MODULE_6 )): - ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART6EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART6EN ) ); + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB25_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB25_POS )); break; #endif #ifdef UART_MODULE_7 case ( hal_ll_uart_module_num( UART_MODULE_7 )): - ( hal_ll_state == true ) ? ( set_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART7EN ) ) : ( clear_reg_bit( _SYSCTL_RCGCUART, HAL_LL_UART7EN ) ); + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB24_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB24_POS )); + break; + #endif + #ifdef UART_MODULE_8 + case ( hal_ll_uart_module_num( UART_MODULE_8 )): + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB23_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB23_POS )); + break; + #endif + #ifdef UART_MODULE_9 + case ( hal_ll_uart_module_num( UART_MODULE_9 )): + ( hal_ll_state == false ) ? ( set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB22_POS )) : ( clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB22_POS )); break; #endif @@ -939,24 +997,20 @@ static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { // Map new pins. - hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; - hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[index_list[module_index].pin_tx].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[index_list[module_index].pin_rx].pin; // TX and RX could have different alternate function settings, hence save both AF values. - hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; - hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[index_list[module_index].pin_tx].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[index_list[module_index].pin_rx].af; } static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { module_struct module; uint32_t uart_config = 0; - if ( (map->pins.rx_pin.pin_name != HAL_LL_PIN_NC) && - (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) ) + if (( map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) && + ( map->pins.tx_pin.pin_name != HAL_LL_PIN_NC )) { - if( hal_ll_state != false ) { - // uart_config |= GPIO_CFG_ALT_FUNCTION | GPIO_CFG_DIGITAL_ENABLE | GPIO_CFG_DRIVE_8mA; - } - module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); module.pins[2] = GPIO_MODULE_STRUCT_END; @@ -970,7 +1024,7 @@ static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_ } static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { - + R_SCI0->BRR = 106; } static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { @@ -978,39 +1032,143 @@ static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { } static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base ); + + switch ( map->stop_bit ) { + case HAL_LL_UART_STOP_BITS_ONE: + clear_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_STOP ); + break; + case HAL_LL_UART_STOP_BITS_TWO: + set_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_STOP ); + break; + default: + break; + } } static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base ); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + set_reg_bit( &hal_ll_hw_reg->scmr, HAL_LL_SCI_SCMR_CHR1 ); + set_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_CHR ); + break; + case HAL_LL_UART_DATA_BITS_8: + set_reg_bit( &hal_ll_hw_reg->scmr, HAL_LL_SCI_SCMR_CHR1 ); + clear_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_CHR ); + break; + case HAL_LL_UART_DATA_BITS_9: + clear_reg_bit( &hal_ll_hw_reg->scmr, HAL_LL_SCI_SCMR_CHR1 ); + break; + default: + break; + } } static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base ); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + clear_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_PE ); + break; + case HAL_LL_UART_PARITY_EVEN: + set_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_PE ); + break; + case HAL_LL_UART_PARITY_ODD: + set_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_PE ); + set_reg_bit( &hal_ll_hw_reg->smr, HAL_LL_SCI_SMR_PM ); + break; + default: + break; + } } static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + set_reg_bits( &hal_ll_hw_reg->scr, HAL_LL_SCI_CLOCK_INTERNAL ); + break; + + case HAL_LL_UART_ENABLE: + clear_reg_bits( &hal_ll_hw_reg->scr, HAL_LL_SCI_CLOCK_INTERNAL ); + break; + default: + break; + } } static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &hal_ll_hw_reg->scr, HAL_LL_SCI_SCR_TE ); + break; + case HAL_LL_UART_ENABLE: + set_reg_bit( &hal_ll_hw_reg->scr, HAL_LL_SCI_SCR_TE ); + break; + + default: + break; + } } static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &hal_ll_hw_reg->scr, HAL_LL_SCI_SCR_RE ); + break; + case HAL_LL_UART_ENABLE: + set_reg_bit( &hal_ll_hw_reg->scr, HAL_LL_SCI_SCR_RE ); + break; + + default: + break; + } } static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { - + clear_reg( &hal_ll_hw_reg->scr ); + while ( read_reg( &hal_ll_hw_reg->scr )); + clear_reg( &hal_ll_hw_reg->smr ); + clear_reg( &hal_ll_hw_reg->ssr ); } static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); } static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + hal_ll_uart_hw_init( map ); } // ------------------------------------------------------------------------- END From f461d2fc10220ca0269c083f3a05bc7db148b458 Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Thu, 24 Jul 2025 11:39:51 +0200 Subject: [PATCH 28/62] Finished polling UART and tested all features --- .../RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 2 + .../mikroe/renesas/include/hal_ll_mstpcr.h | 10 + .../implementation_1/hal_ll_uart_pin_map.h | 6 + .../src/uart/implementation_1/hal_ll_uart.c | 192 ++++++++++++++---- 4 files changed, 174 insertions(+), 36 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h index 6fd8806e99..ed231ba7a5 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -69,6 +69,8 @@ //UART #define UART0_RX_P410 #define UART0_TX_P411 +#define UART1_TX_P401 +#define UART1_RX_P402 #define UART_MODULE_0 1 #define UART_MODULE_1 2 diff --git a/targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h b/targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h index fc76792c40..9203364bce 100644 --- a/targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h +++ b/targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h @@ -92,6 +92,16 @@ extern "C"{ #define MSTPCRD_MSTPD29_POS 29 // ACMPLP #define MSTPCRD_MSTPD31_POS 31 // OPAMP +typedef struct +{ + uint32_t iclk; // System clock frequency in Hz + uint32_t pclka; // PCLKA clock frequency in Hz + uint32_t pclkb; // PCLKB clock frequency in Hz + uint32_t pclkc; // PCLKC clock frequency in Hz + uint32_t pclkd; // PCLKD clock frequency in Hz + uint32_t fclk; // Flash interface clock frequency in Hz +} system_clocks_t; + #ifdef __cplusplus } #endif diff --git a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h index bc34f4700d..482773367e 100644 --- a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h +++ b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h @@ -101,6 +101,9 @@ static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { #ifdef UART0_TX_P411 {hal_ll_uart_module_num(UART_MODULE_0), GPIO_P411, HAL_LL_UART0_BASE_ADDRESS, 4}, #endif + #ifdef UART1_TX_P401 + {hal_ll_uart_module_num(UART_MODULE_1), GPIO_P401, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} }; @@ -110,6 +113,9 @@ static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = { #ifdef UART0_RX_P410 {hal_ll_uart_module_num(UART_MODULE_0), GPIO_P410, HAL_LL_UART0_BASE_ADDRESS, 4}, #endif + #ifdef UART1_RX_P402 + {hal_ll_uart_module_num(UART_MODULE_1), GPIO_P402, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} }; diff --git a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c index 6a1d7c9a83..c24a4b476b 100644 --- a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c @@ -41,7 +41,6 @@ * @brief UART HAL LOW LEVEL layer implementation. */ -#include "mcu.h" #include "hal_ll_uart.h" #include "hal_ll_gpio.h" #include "hal_ll_core.h" @@ -63,14 +62,8 @@ static volatile hal_ll_uart_handle_register_t hal_ll_module_state[ UART_MODULE_C #define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base -/*!< @brief Helper macro for UART module sync time */ -#define hal_ll_uart_wait_for_sync(_hal_sync_val) while( _hal_sync_val-- ) assembly(nop) - /*!< @brief Macros used for calculating actual baud rate value and error value. */ -#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 -#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)) -#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud))) -#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + /*!< @brief Macro used for status registed flag check. * Used in interrupt handlers. @@ -82,8 +75,39 @@ static volatile hal_ll_uart_handle_register_t hal_ll_module_state[ UART_MODULE_C */ #define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit(&(((hal_ll_uart_base_handle_t *)_handle)->icr), _flag)) -/*!< @brief Macros defining bit location */ +/*!< @brief Macro used for picking the divisors for the source clock. + * if is_base_16 == true: + * Skip this calculation for divisors that are not achievable with 16 base clk cycles per bit. + * if is_base_16 == false: + * Skip this calculation for divisors that are only achievable without 16 base clk cycles per bit. + */ +#define hal_ll_sci_brr_assert_divisors(is_base_16, i) \ + (is_base_16 ^ (g_async_baud[i].abcs | g_async_baud[i].abcse)) + +/*!< @brief Macro used for calculating BRR register value. + * BRR = (PCLKA / (div_coefficient * baud)) - 1 + */ +#define hal_ll_sci_brr_calculate(baud, pclka, i) (pclka / (g_div_coefficient[i] * baud)) + +/*!< @brief Macro used for calculating the baud rate error. + * error[%] = {(PCLKA / (baud * div_coefficient * (BRR + 1)) - 1} x 100 + * Promoting to 64 bits for calculation, but the final value can never be more than 32 bits, as + * described below, so this cast is safe. + * 1. Larger frequencies yield larger bit errors (absolute value). As the frequency grows, + * the current_error approaches -100000, so: + * 0 >= current_error >= -100000 + * 2. current_error is between -100000 and 0. This entire range fits in an int32_t type, so the cast + * to (int32_t) is safe. + */ +#define hal_ll_sci_brr_get_error(brr, pclka, baud, i) \ + (int32_t)(((((int64_t)pclka) * HAL_LL_SCI_BRR_ERROR_REFERENCE) / \ + (g_div_coefficient[i] * baud * (brr + 1))) - HAL_LL_SCI_BRR_ERROR_REFERENCE) + +/*!< @brief Macros defining bit location. */ +#define HAL_LL_SCI_SEMR_BRME 2 +#define HAL_LL_SCI_SEMR_ABCSE 3 #define HAL_LL_SCI_SMR_STOP 3 +#define HAL_LL_SCI_SEMR_ABCS 4 #define HAL_LL_SCI_SCMR_CHR1 4 #define HAL_LL_SCI_SMR_PM 4 #define HAL_LL_SCI_SCR_RE 4 @@ -91,11 +115,48 @@ static volatile hal_ll_uart_handle_register_t hal_ll_module_state[ UART_MODULE_C #define HAL_LL_SCI_SMR_PE 5 #define HAL_LL_SCI_SMR_CHR 6 #define HAL_LL_SCI_SSR_RDRF 6 +#define HAL_LL_SCI_SEMR_BGDM 6 #define HAL_LL_SCI_SSR_TDRE 7 -/*!< @brief Macros defining register bit values */ -#define HAL_LL_SCI_CLOCK_INTERNAL 0x3 +/*!< @brief Macros defining register bit values. */ +#define HAL_LL_SCI_CLOCK_EXTERNAL 0x3 +#define HAL_LL_SCI_SEMR_CONFIGURE(bgdm, abcs, abcse) \ + (bgdm << HAL_LL_SCI_SEMR_BGDM) | \ + (abcs << HAL_LL_SCI_SEMR_ABCS) | \ + (abcse << HAL_LL_SCI_SEMR_ABCSE) + +/*!< @brief Macros used for baudrate calculations. */ +#define HAL_LL_SCI_NUM_DIVISORS 7 +#define HAL_LL_SCI_BRR_MAX 255 +#define HAL_LL_SCI_BRR_ERROR_ACCEPTABLE 1000UL +#define HAL_LL_SCI_BRR_ERROR_REFERENCE 100000UL + +/*!< @brief Structures used for baudrate calculations. */ +typedef struct st_baud_setting_const_t +{ + uint8_t bgdm; /**< BGDM value to get divisor */ + uint8_t abcs; /**< ABCS value to get divisor */ + uint8_t abcse; /**< ABCSE value to get divisor */ + uint8_t cks; /**< CKS value to get divisor (CKS = N) */ +} baud_setting_const_t; + +/*!< @brief Baud rate bit divisor information structure. */ +static const baud_setting_const_t g_async_baud[ HAL_LL_SCI_NUM_DIVISORS ] = +{ + {0U, 0U, 1U, 0U}, /* BGDM, ABCS, ABCSE, n */ + {1U, 1U, 0U, 0U}, + {1U, 0U, 0U, 0U}, + {0U, 0U, 1U, 1U}, + {0U, 0U, 0U, 0U}, + {1U, 0U, 0U, 1U}, + {0U, 0U, 0U, 1U} +}; +/*!< @brief Baud rate divisor information structure. */ +static const uint8_t g_div_coefficient[ HAL_LL_SCI_NUM_DIVISORS ] = +{ + 6U, 8U, 16U, 24U, 32U, 64U, 128U +}; /*!< @brief UART HW register structure. */ typedef struct { @@ -154,31 +215,31 @@ static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[ UART_MODULE_ {HAL_LL_UART0_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_0 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_1 - {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_1 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_1 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_2 - {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_2 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_2 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_3 - {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_3 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_3 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_4 - {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_4 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_4 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_5 - {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_5 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_5 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_6 - {HAL_LL_UART6_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_6 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART6_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_6 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_7 - {HAL_LL_UART7_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_7 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART7_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_7 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_8 - {HAL_LL_UART8_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_8 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART8_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_8 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_9 - {HAL_LL_UART9_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_9 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART9_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_9 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} @@ -283,15 +344,11 @@ static uint8_t hal_ll_uart_find_index( handle_t *handle ); /** * @brief Get UART module clock speed. * - * Returns adequate clock speed based on - * UART module base address. - * - * @param[in] module_index - UART module index number. + * Returns adequate clock speed for UART module. * - * @return uint8_t Module number. - * Returns clock value. + * @return uint32_t UART source clock speed in Hz. */ -static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); +static uint32_t hal_ll_uart_get_clock_speed( void ); /** * @brief Clears UART registers. @@ -512,7 +569,7 @@ hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_ hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); // Chips using this implementation do not support 7 bit data. - if ( ( data_bit < HAL_LL_UART_DATA_BITS_5 ) || ( data_bit > HAL_LL_UART_DATA_BITS_8 ) ) { + if ( ( data_bit < HAL_LL_UART_DATA_BITS_7 ) || ( data_bit > HAL_LL_UART_DATA_BITS_9 ) ) { return HAL_LL_UART_MODULE_ERROR; } @@ -1024,11 +1081,74 @@ static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_ } static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { - R_SCI0->BRR = 106; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base ); + + /* Find the best BRR (bit rate register) value. + * In table g_async_baud, divisor values are stored for BGDM, ABCS, ABCSE and N values. Each set of divisors + * is tried, and the settings with the lowest bit rate error are stored. The formula to calculate BRR is as + * follows and it must be 255 or less: + * BRR = (PCLKA / (div_coefficient * baud)) - 1 + * Note: only values for internal baudrate generator are used as this implementation doesn't support use of + * external baudrate generator. + */ + uint32_t error = HAL_LL_SCI_BRR_ERROR_REFERENCE; + uint32_t temp_brr, divisor = 0U; + uint8_t abcse, abcs, bgdm, brr, cks; + int32_t err_divisor, current_error; + uint32_t source_clock = hal_ll_uart_get_clock_speed( ); + + for ( uint8_t select_16_base_clk_cycles = 0U; + (( 1 >= select_16_base_clk_cycles ) && ( HAL_LL_SCI_BRR_ERROR_ACCEPTABLE < error )); + select_16_base_clk_cycles++ ) + { + for ( uint8_t i = 0U; HAL_LL_SCI_NUM_DIVISORS > i ; i++ ) + { + if ( hal_ll_sci_brr_assert_divisors( select_16_base_clk_cycles, i )) + { + continue; + } + + temp_brr = hal_ll_sci_brr_calculate( map->baud_rate.baud, source_clock, i ); + + if (( HAL_LL_SCI_BRR_MAX + 1U ) >= temp_brr ) + { + while ( temp_brr-- > 0U ) + { + current_error = hal_ll_sci_brr_get_error( temp_brr, source_clock, map->baud_rate.baud, i ); + + /* Take the absolute value of the bit rate error. */ + if ( current_error < 0 ) + { + current_error = -current_error; + } + + /* If the absolute value of the bit rate error is less than the previous lowest absolute value of + * bit rate error, then store these settings as the best value. + */ + if ( current_error < error ) + { + bgdm = g_async_baud[i].bgdm; + abcs = g_async_baud[i].abcs; + abcse = g_async_baud[i].abcse; + cks = g_async_baud[i].cks; + brr = ( uint8_t ) temp_brr; + error = current_error; + } + } + } + } + } + + set_reg_bits( &hal_ll_hw_reg->semr, HAL_LL_SCI_SEMR_CONFIGURE( bgdm, abcs, abcse )); + set_reg_bits( &hal_ll_hw_reg->scr, cks ); + write_reg( &hal_ll_hw_reg->brr, brr ); } -static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { - return Get_Fosc_kHz() * 1000; +static uint32_t hal_ll_uart_get_clock_speed( void ) { + system_clocks_t system_clocks; + + SYSTEM_GetClocksFrequency( &system_clocks ); + return system_clocks.pclka; } static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { @@ -1093,12 +1213,12 @@ static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *m static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { switch ( pin_state ) { + /* SCI module doesn't have any specific bitfield for enabling it, but + * we disable UART work by switching source clock to external as this implementation + * doesn't support the use of external clock for SCI module. + */ case HAL_LL_UART_DISABLE: - set_reg_bits( &hal_ll_hw_reg->scr, HAL_LL_SCI_CLOCK_INTERNAL ); - break; - - case HAL_LL_UART_ENABLE: - clear_reg_bits( &hal_ll_hw_reg->scr, HAL_LL_SCI_CLOCK_INTERNAL ); + set_reg_bits( &hal_ll_hw_reg->scr, HAL_LL_SCI_CLOCK_EXTERNAL ); break; default: From 3b01f6db16329f6ab853e7a12a191da07d364889 Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Thu, 24 Jul 2025 11:40:50 +0200 Subject: [PATCH 29/62] Reverted CMake changes --- CMakeLists.txt | 2 +- .../lcd/lib/include/drivers/lcd_controllers.h | 2 +- .../arm/mikroe/common/include/flatten_me.h | 71 +++++++++++++++++++ tests/gpio/src/main.c | 6 +- tests/uart/test_example/main.c | 10 +-- .../ethernet/cyclonetcp/config/eth_driver.h | 57 +++++++++++++++ thirdparty/usb/tinyusb/config/tusb_config.h | 2 +- .../tinyusb/isr/include/usb_isr_routines.h | 4 +- .../usb/tinyusb/isr/src/usb_isr_routines.c | 6 +- 9 files changed, 144 insertions(+), 16 deletions(-) create mode 100644 targets/arm/mikroe/common/include/flatten_me.h create mode 100644 thirdparty/ethernet/cyclonetcp/config/eth_driver.h diff --git a/CMakeLists.txt b/CMakeLists.txt index 13ee6da2c5..6d64bb8250 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -56,8 +56,8 @@ if (NOT ${IS_BARE_METAL}) add_subdirectory(thirdparty) endif() - add_subdirectory(tests) if(${MSDK_TEST_EXAMPLES} MATCHES "true") + add_subdirectory(tests) endif() ## Deploy build is used for testing compiler specific issues. diff --git a/middleware/lcd/lib/include/drivers/lcd_controllers.h b/middleware/lcd/lib/include/drivers/lcd_controllers.h index 6b02056877..3f224978ce 100644 --- a/middleware/lcd/lib/include/drivers/lcd_controllers.h +++ b/middleware/lcd/lib/include/drivers/lcd_controllers.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Copyright (C) MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** Commercial License Usage diff --git a/targets/arm/mikroe/common/include/flatten_me.h b/targets/arm/mikroe/common/include/flatten_me.h new file mode 100644 index 0000000000..446641823e --- /dev/null +++ b/targets/arm/mikroe/common/include/flatten_me.h @@ -0,0 +1,71 @@ +/**************************************************************************** +** +** Copyright (C) MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file flatten_me.h + * @brief mikroSDK code flattener level selection. + */ + +#ifndef __FLATTEN_ME_H__ +#define __FLATTEN_ME_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Flattening levels. + * @ref FLATTEN_ME_LEVEL_NONE - no code flattening done. + * @ref FLATTEN_ME_LEVEL_LOW - flatten only HAL_LL APIs. + * @ref FLATTEN_ME_LEVEL_MID - flatten only HAL_LL and HAL APIs. + * @ref FLATTEN_ME_LEVEL_HIGH - flatten all layered APIs (HAL_LL, HAL and DRV). + */ +#define FLATTEN_ME_LEVEL_NONE (0) +#define FLATTEN_ME_LEVEL_LOW (1) +#define FLATTEN_ME_LEVEL_MID (2) +#define FLATTEN_ME_LEVEL_HIGH (3) + +// Flatten code or not? +#define FLATTEN_ME + +// Flatten level selection. +#define FLATTEN_ME_LEVEL FLATTEN_ME_LEVEL_HIGH + +#ifdef __cplusplus +} +#endif + +#endif // __FLATTEN_ME_H__ diff --git a/tests/gpio/src/main.c b/tests/gpio/src/main.c index b9a9c2d936..5997aa2691 100644 --- a/tests/gpio/src/main.c +++ b/tests/gpio/src/main.c @@ -61,14 +61,14 @@ // TODO // Define port used for testing. -#define PORT_NAME PORT_4 // Example: GPIO_PORT_B +#define PORT_NAME HAL_PORT_NC // Example: GPIO_PORT_B #define PORT_MASK (port_size_t)0xFFFFFFFF #define PORT_READ_VALUE 0xAA #define SINGLE_LED_DELAY 300 // Delay LED single shift test. // TODO // Define pins used for testing digital in/out. -#define LED GPIO_P409 // Example: GPIO_PA0 -#define BUTTON GPIO_P301 // Example: GPIO_PB0 +#define LED HAL_PIN_NC // Example: GPIO_PA0 +#define BUTTON HAL_PIN_NC // Example: GPIO_PB0 // ----------------------------------------------------------------- VARIABLES static port_t test_port; // PORT driver context structure. static digital_in_t input_pin; // Digital input driver context structure. diff --git a/tests/uart/test_example/main.c b/tests/uart/test_example/main.c index 5c325e755e..32c7f147a3 100644 --- a/tests/uart/test_example/main.c +++ b/tests/uart/test_example/main.c @@ -18,8 +18,8 @@ // TODO If set to 1, will work simultaneously with two objects #define TEST_TWO_MODULES 0 -#define TEST_PIN_UART_TX HAL_PIN_NC // TODO define UART TX pin -#define TEST_PIN_UART_RX HAL_PIN_NC // TODO define UART RX pin +#define TEST_PIN_UART_TX GPIO_P411 // TODO define UART TX pin +#define TEST_PIN_UART_RX GPIO_P410 // TODO define UART RX pin #if TEST_TWO_MODULES #define TEST_PIN_UART_TX2 HAL_PIN_NC // TODO define UART TX pin @@ -133,7 +133,7 @@ int main( void ) { // Set baud rate. // TODO Test different baud rate values. - if ( UART_SUCCESS != uart_set_baud( &uart, 115200 ) ) { + if ( UART_SUCCESS != uart_set_baud( &uart, 9600 ) ) { signal_error( TEST_PIN_2 ); } #if TEST_TWO_MODULES @@ -146,7 +146,7 @@ int main( void ) { // TODO Test different parity values. // This test can be performed by checking // register for adequate values. - if ( UART_SUCCESS != uart_set_parity( &uart, UART_PARITY_DEFAULT ) ) { + if ( UART_SUCCESS != uart_set_parity( &uart, UART_PARITY_NONE) ) { signal_error( TEST_PIN_3 ); }; #if TEST_TWO_MODULES @@ -172,7 +172,7 @@ int main( void ) { // TODO Test different bit per wr/rd values. // This test can be performed by checking // register for adequate values. - if ( UART_SUCCESS != uart_set_data_bits( &uart, UART_DATA_BITS_DEFAULT ) ) { + if ( UART_SUCCESS != uart_set_data_bits( &uart, UART_DATA_BITS_9 ) ) { signal_error( TEST_PIN_5 ); } #if TEST_TWO_MODULES diff --git a/thirdparty/ethernet/cyclonetcp/config/eth_driver.h b/thirdparty/ethernet/cyclonetcp/config/eth_driver.h new file mode 100644 index 0000000000..4a79296c1d --- /dev/null +++ b/thirdparty/ethernet/cyclonetcp/config/eth_driver.h @@ -0,0 +1,57 @@ +/**************************************************************************** +** +** Copyright (C) MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file eth_driver.h + * @brief mikroSDK CycloneTCP ETH driver. + */ + +#ifndef __ETH_DRIVER_H__ +#define __ETH_DRIVER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +// Currently active ETH driver. +#include "drivers/mac/stm32f4xx_eth_driver.h" +#define ETHERNET_DRIVER_HANDLER stm32f4xxEthDriver + +#ifdef __cplusplus +} +#endif + +#endif // __ETH_DRIVER_H__ diff --git a/thirdparty/usb/tinyusb/config/tusb_config.h b/thirdparty/usb/tinyusb/config/tusb_config.h index 575bb8757e..52abbb4b99 100644 --- a/thirdparty/usb/tinyusb/config/tusb_config.h +++ b/thirdparty/usb/tinyusb/config/tusb_config.h @@ -54,7 +54,7 @@ extern "C" { #endif -#define CFG_TUSB_MCU OPT_MCU_NONE +#define CFG_TUSB_MCU OPT_MCU_STM32F4 //--------------------------------------------------------------------+ diff --git a/thirdparty/usb/tinyusb/isr/include/usb_isr_routines.h b/thirdparty/usb/tinyusb/isr/include/usb_isr_routines.h index 126a538fb8..4297477e3b 100644 --- a/thirdparty/usb/tinyusb/isr/include/usb_isr_routines.h +++ b/thirdparty/usb/tinyusb/isr/include/usb_isr_routines.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Copyright (C) MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package @@ -84,7 +84,7 @@ extern "C"{ * @return None * @warning MUST be defined somewhere in code. */ - void define_usb_handler_here(void) __attribute__((interrupt)); + void OTG_FS_IRQHandler(void) __attribute__((interrupt ("IRQ"))); #pragma GCC pop_options #endif diff --git a/thirdparty/usb/tinyusb/isr/src/usb_isr_routines.c b/thirdparty/usb/tinyusb/isr/src/usb_isr_routines.c index 9fe1a13b2d..e236ccc2d7 100644 --- a/thirdparty/usb/tinyusb/isr/src/usb_isr_routines.c +++ b/thirdparty/usb/tinyusb/isr/src/usb_isr_routines.c @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Copyright (C) MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package @@ -45,13 +45,13 @@ #if defined(__PROJECT_MIKROSDK_MIKROE__) && (__USE_MIKROE_ISR__==1) // Clock value in Hz. -volatile uint32_t SystemCoreClock = (uint32_t)(1*1000000UL); +volatile uint32_t SystemCoreClock = (uint32_t)(168*1000000UL); void usb_isr_include(void) { asm volatile ("NOP"); } -void define_usb_handler_here(void) +void OTG_FS_IRQHandler(void) { #if CFG_TUH_ENABLED tuh_int_handler(BOARD_TUH_RHPORT); From d3450abc5967f075a1e401c2fcc4c4594860f6a0 Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Thu, 24 Jul 2025 12:35:47 +0200 Subject: [PATCH 30/62] Reverted all common files that were changed --- middleware/lcd/lib/include/drivers/lcd_controllers.h | 2 +- targets/arm/mikroe/common/include/flatten_me.h | 2 +- thirdparty/ethernet/cyclonetcp/config/eth_driver.h | 2 +- thirdparty/usb/tinyusb/config/tusb_config.h | 2 +- thirdparty/usb/tinyusb/isr/include/usb_isr_routines.h | 2 +- thirdparty/usb/tinyusb/isr/src/usb_isr_routines.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/middleware/lcd/lib/include/drivers/lcd_controllers.h b/middleware/lcd/lib/include/drivers/lcd_controllers.h index 3f224978ce..6b02056877 100644 --- a/middleware/lcd/lib/include/drivers/lcd_controllers.h +++ b/middleware/lcd/lib/include/drivers/lcd_controllers.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** Commercial License Usage diff --git a/targets/arm/mikroe/common/include/flatten_me.h b/targets/arm/mikroe/common/include/flatten_me.h index 446641823e..d897b290a5 100644 --- a/targets/arm/mikroe/common/include/flatten_me.h +++ b/targets/arm/mikroe/common/include/flatten_me.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** Commercial License Usage diff --git a/thirdparty/ethernet/cyclonetcp/config/eth_driver.h b/thirdparty/ethernet/cyclonetcp/config/eth_driver.h index 4a79296c1d..25254dba64 100644 --- a/thirdparty/ethernet/cyclonetcp/config/eth_driver.h +++ b/thirdparty/ethernet/cyclonetcp/config/eth_driver.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** Commercial License Usage diff --git a/thirdparty/usb/tinyusb/config/tusb_config.h b/thirdparty/usb/tinyusb/config/tusb_config.h index 52abbb4b99..575bb8757e 100644 --- a/thirdparty/usb/tinyusb/config/tusb_config.h +++ b/thirdparty/usb/tinyusb/config/tusb_config.h @@ -54,7 +54,7 @@ extern "C" { #endif -#define CFG_TUSB_MCU OPT_MCU_STM32F4 +#define CFG_TUSB_MCU OPT_MCU_NONE //--------------------------------------------------------------------+ diff --git a/thirdparty/usb/tinyusb/isr/include/usb_isr_routines.h b/thirdparty/usb/tinyusb/isr/include/usb_isr_routines.h index 4297477e3b..f507648fcf 100644 --- a/thirdparty/usb/tinyusb/isr/include/usb_isr_routines.h +++ b/thirdparty/usb/tinyusb/isr/include/usb_isr_routines.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/thirdparty/usb/tinyusb/isr/src/usb_isr_routines.c b/thirdparty/usb/tinyusb/isr/src/usb_isr_routines.c index e236ccc2d7..fa6c8878bb 100644 --- a/thirdparty/usb/tinyusb/isr/src/usb_isr_routines.c +++ b/thirdparty/usb/tinyusb/isr/src/usb_isr_routines.c @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package From 7edc7623ced7c88ca6273296435c018be0e2c806 Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Thu, 24 Jul 2025 12:39:57 +0200 Subject: [PATCH 31/62] Reverted all common files that were changed #2 --- .../arm/mikroe/common/include/flatten_me.h | 71 ------------------- tests/CMakeLists.txt | 40 +++++------ tests/uart/test_example/main.c | 10 +-- .../ethernet/cyclonetcp/config/eth_driver.h | 57 --------------- .../tinyusb/isr/include/usb_isr_routines.h | 2 +- .../usb/tinyusb/isr/src/usb_isr_routines.c | 4 +- 6 files changed, 28 insertions(+), 156 deletions(-) delete mode 100644 targets/arm/mikroe/common/include/flatten_me.h delete mode 100644 thirdparty/ethernet/cyclonetcp/config/eth_driver.h diff --git a/targets/arm/mikroe/common/include/flatten_me.h b/targets/arm/mikroe/common/include/flatten_me.h deleted file mode 100644 index d897b290a5..0000000000 --- a/targets/arm/mikroe/common/include/flatten_me.h +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** -** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. -** Contact: https://www.mikroe.com/contact -** -** Commercial License Usage -** -** Licensees holding valid commercial NECTO compilers AI licenses may use this -** file in accordance with the commercial license agreement provided with the -** Software or, alternatively, in accordance with the terms contained in -** a written agreement between you and The MikroElektronika Company. -** For licensing terms and conditions see -** https://www.mikroe.com/legal/software-license-agreement. -** For further information use the contact form at -** https://www.mikroe.com/contact. -** -** -** GNU Lesser General Public License Usage -** -** Alternatively, this file may be used for -** non-commercial projects under the terms of the GNU Lesser -** General Public License version 3 as published by the Free Software -** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. -** -** The above copyright notice and this permission notice shall be -** included in all copies or substantial portions of the Software. -** -** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT -** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE -** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -** -****************************************************************************/ -/*! - * @file flatten_me.h - * @brief mikroSDK code flattener level selection. - */ - -#ifndef __FLATTEN_ME_H__ -#define __FLATTEN_ME_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Flattening levels. - * @ref FLATTEN_ME_LEVEL_NONE - no code flattening done. - * @ref FLATTEN_ME_LEVEL_LOW - flatten only HAL_LL APIs. - * @ref FLATTEN_ME_LEVEL_MID - flatten only HAL_LL and HAL APIs. - * @ref FLATTEN_ME_LEVEL_HIGH - flatten all layered APIs (HAL_LL, HAL and DRV). - */ -#define FLATTEN_ME_LEVEL_NONE (0) -#define FLATTEN_ME_LEVEL_LOW (1) -#define FLATTEN_ME_LEVEL_MID (2) -#define FLATTEN_ME_LEVEL_HIGH (3) - -// Flatten code or not? -#define FLATTEN_ME - -// Flatten level selection. -#define FLATTEN_ME_LEVEL FLATTEN_ME_LEVEL_HIGH - -#ifdef __cplusplus -} -#endif - -#endif // __FLATTEN_ME_H__ diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 99c7d316f8..aa5a1ac302 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -17,14 +17,14 @@ if (${_MSDK_BOARD_NAME_} MATCHES "^MIKROMEDIA(.+)$") endif() add_subdirectory(gpio) -# add_subdirectory(button_simulation) +add_subdirectory(button_simulation) add_subdirectory(renesas) ## 8K Flash and 2K RAM minimum for this test. memory_sdk_test_check(memory_issue 8192 2048) if (${memory_issue} STREQUAL "FALSE") - # add_subdirectory(adc) + add_subdirectory(adc) else() message(INFO ": ${MCU_NAME} does not have enough memory for \"adc\" test.") endif() @@ -33,7 +33,7 @@ endif() memory_sdk_test_check(memory_issue 8192 2048) if (${memory_issue} STREQUAL "FALSE") - # add_subdirectory(i2c) + add_subdirectory(i2c) else() message(INFO ": ${MCU_NAME} does not have enough memory for \"i2c\" test.") endif() @@ -42,7 +42,7 @@ endif() memory_sdk_test_check(memory_issue 8192 4096) if (${memory_issue} STREQUAL "FALSE") - # add_subdirectory(pwm) + add_subdirectory(pwm) else() message(INFO ": ${MCU_NAME} does not have enough memory for \"pwm\" test.") endif() @@ -51,7 +51,7 @@ endif() memory_sdk_test_check(memory_issue 8192 2048) if (${memory_issue} STREQUAL "FALSE") - # add_subdirectory(spi) + add_subdirectory(spi) else() message(INFO ": ${MCU_NAME} does not have enough memory for \"spi\" test.") endif() @@ -68,13 +68,13 @@ endif() if (NOT _MSDK_DIP_SOCKET_TYPE_) if (_HAS_MIKROBUS_) if (${_HAS_MIKROBUS_} STREQUAL TRUE) - # add_subdirectory(mikrobus) + add_subdirectory(mikrobus) endif() endif() endif() if (${_MSDK_BOARD_NAME_} MATCHES "CLICKER") - # add_subdirectory(clicker_buttons) + add_subdirectory(clicker_buttons) endif() ## Initial mikroSDK 2.9.0 release shall only @@ -88,7 +88,7 @@ if(${TOOLCHAIN_LANGUAGE} STREQUAL "GNU") if((${has_usb} STREQUAL "true") AND (${has_usb_interrupts} STREQUAL "true")) check_usb_requirements(memory_requirements_passed) if(${memory_requirements_passed} STREQUAL "true") - # add_subdirectory(usb) + add_subdirectory(usb) endif() endif() endif() @@ -99,7 +99,7 @@ if(${TOOLCHAIN_ID} STREQUAL "gcc_arm_none_eabi" OR ${TOOLCHAIN_ID} STREQUAL "mch if(${has_eth} STREQUAL "true") check_eth_requirements(memory_requirements_passed) if(${memory_requirements_passed} STREQUAL "true") - # add_subdirectory(ethernet) + add_subdirectory(ethernet) endif() endif() endif() @@ -110,15 +110,15 @@ memory_sdk_test_check(memory_issue 12288 2048) find_package(MikroSDK.Driver.CAN) if(MikroSDK.Driver.CAN\_FOUND) if (${memory_issue} STREQUAL "FALSE") - # add_subdirectory(can) + add_subdirectory(can) else() message(INFO ": ${MCU_NAME} does not have enough memory for \"can\" test.") endif() endif() -# add_subdirectory(one_wire) +add_subdirectory(one_wire) -# add_subdirectory(lcd) +add_subdirectory(lcd) if (_MSDK_TFT_BOARD_) ## MikroE GL @@ -126,22 +126,22 @@ if (_MSDK_TFT_BOARD_) if (MikroSDK.GraphicLibrary\_FOUND) find_package(Components.TftBoard8) if (Components.TftBoard8\_FOUND) - # add_subdirectory(gl) + add_subdirectory(gl) endif() endif() ## LVGL if(${TOOLCHAIN_LANGUAGE} STREQUAL "GNU") - # add_subdirectory(lvgl) + add_subdirectory(lvgl) endif() endif() if (clickTests) - # add_subdirectory(clicks) + add_subdirectory(clicks) endif() if (tftTests) if(tftJigTest) - # add_subdirectory(tft_jig) + add_subdirectory(tft_jig) endif() endif() @@ -151,7 +151,7 @@ memory_sdk_test_check(memory_issue 12288 2048) find_package(MikroSDK.Driver.DMA) if(MikroSDK.Driver.DMA\_FOUND) if (${memory_issue} STREQUAL "FALSE") - # add_subdirectory(dma) + add_subdirectory(dma) else() message(INFO ": ${MCU_NAME} does not have enough memory for \"dma\" test.") endif() @@ -159,12 +159,12 @@ endif() check_rtc(has_rtc) if(${has_rtc} STREQUAL "true") - # add_subdirectory(rtc) + add_subdirectory(rtc) endif() memory_test_check(enough_memory) if(${enough_memory} STREQUAL "true") - # add_subdirectory(file_system) + add_subdirectory(file_system) endif() -# add_subdirectory(sprint) +add_subdirectory(sprint) diff --git a/tests/uart/test_example/main.c b/tests/uart/test_example/main.c index 32c7f147a3..6c88721b47 100644 --- a/tests/uart/test_example/main.c +++ b/tests/uart/test_example/main.c @@ -18,8 +18,8 @@ // TODO If set to 1, will work simultaneously with two objects #define TEST_TWO_MODULES 0 -#define TEST_PIN_UART_TX GPIO_P411 // TODO define UART TX pin -#define TEST_PIN_UART_RX GPIO_P410 // TODO define UART RX pin +#define TEST_PIN_UART_TX HAL_PIN_NC // TODO define UART TX pin +#define TEST_PIN_UART_RX HAL_PIN_NC // TODO define UART RX pin #if TEST_TWO_MODULES #define TEST_PIN_UART_TX2 HAL_PIN_NC // TODO define UART TX pin @@ -133,7 +133,7 @@ int main( void ) { // Set baud rate. // TODO Test different baud rate values. - if ( UART_SUCCESS != uart_set_baud( &uart, 9600 ) ) { + if ( UART_SUCCESS != uart_set_baud( &uart, 115200 ) ) { signal_error( TEST_PIN_2 ); } #if TEST_TWO_MODULES @@ -146,7 +146,7 @@ int main( void ) { // TODO Test different parity values. // This test can be performed by checking // register for adequate values. - if ( UART_SUCCESS != uart_set_parity( &uart, UART_PARITY_NONE) ) { + if ( UART_SUCCESS != uart_set_parity( &uart, UART_PARITY_DEFAULT) ) { signal_error( TEST_PIN_3 ); }; #if TEST_TWO_MODULES @@ -172,7 +172,7 @@ int main( void ) { // TODO Test different bit per wr/rd values. // This test can be performed by checking // register for adequate values. - if ( UART_SUCCESS != uart_set_data_bits( &uart, UART_DATA_BITS_9 ) ) { + if ( UART_SUCCESS != uart_set_data_bits( &uart, UART_DATA_BITS_DEFAULT ) ) { signal_error( TEST_PIN_5 ); } #if TEST_TWO_MODULES diff --git a/thirdparty/ethernet/cyclonetcp/config/eth_driver.h b/thirdparty/ethernet/cyclonetcp/config/eth_driver.h deleted file mode 100644 index 25254dba64..0000000000 --- a/thirdparty/ethernet/cyclonetcp/config/eth_driver.h +++ /dev/null @@ -1,57 +0,0 @@ -/**************************************************************************** -** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. -** Contact: https://www.mikroe.com/contact -** -** Commercial License Usage -** -** Licensees holding valid commercial NECTO compilers AI licenses may use this -** file in accordance with the commercial license agreement provided with the -** Software or, alternatively, in accordance with the terms contained in -** a written agreement between you and The MikroElektronika Company. -** For licensing terms and conditions see -** https://www.mikroe.com/legal/software-license-agreement. -** For further information use the contact form at -** https://www.mikroe.com/contact. -** -** -** GNU Lesser General Public License Usage -** -** Alternatively, this file may be used for -** non-commercial projects under the terms of the GNU Lesser -** General Public License version 3 as published by the Free Software -** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. -** -** The above copyright notice and this permission notice shall be -** included in all copies or substantial portions of the Software. -** -** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT -** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE -** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -** -****************************************************************************/ -/*! - * @file eth_driver.h - * @brief mikroSDK CycloneTCP ETH driver. - */ - -#ifndef __ETH_DRIVER_H__ -#define __ETH_DRIVER_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -// Currently active ETH driver. -#include "drivers/mac/stm32f4xx_eth_driver.h" -#define ETHERNET_DRIVER_HANDLER stm32f4xxEthDriver - -#ifdef __cplusplus -} -#endif - -#endif // __ETH_DRIVER_H__ diff --git a/thirdparty/usb/tinyusb/isr/include/usb_isr_routines.h b/thirdparty/usb/tinyusb/isr/include/usb_isr_routines.h index f507648fcf..126a538fb8 100644 --- a/thirdparty/usb/tinyusb/isr/include/usb_isr_routines.h +++ b/thirdparty/usb/tinyusb/isr/include/usb_isr_routines.h @@ -84,7 +84,7 @@ extern "C"{ * @return None * @warning MUST be defined somewhere in code. */ - void OTG_FS_IRQHandler(void) __attribute__((interrupt ("IRQ"))); + void define_usb_handler_here(void) __attribute__((interrupt)); #pragma GCC pop_options #endif diff --git a/thirdparty/usb/tinyusb/isr/src/usb_isr_routines.c b/thirdparty/usb/tinyusb/isr/src/usb_isr_routines.c index fa6c8878bb..9fe1a13b2d 100644 --- a/thirdparty/usb/tinyusb/isr/src/usb_isr_routines.c +++ b/thirdparty/usb/tinyusb/isr/src/usb_isr_routines.c @@ -45,13 +45,13 @@ #if defined(__PROJECT_MIKROSDK_MIKROE__) && (__USE_MIKROE_ISR__==1) // Clock value in Hz. -volatile uint32_t SystemCoreClock = (uint32_t)(168*1000000UL); +volatile uint32_t SystemCoreClock = (uint32_t)(1*1000000UL); void usb_isr_include(void) { asm volatile ("NOP"); } -void OTG_FS_IRQHandler(void) +void define_usb_handler_here(void) { #if CFG_TUH_ENABLED tuh_int_handler(BOARD_TUH_RHPORT); From 91c4a747b730504144b49b5b091e85746280e857 Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Thu, 24 Jul 2025 12:42:48 +0200 Subject: [PATCH 32/62] Last changes for UART --- platform/ring/lib/src/ring.c | 2 +- tests/uart/test_example/main.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/platform/ring/lib/src/ring.c b/platform/ring/lib/src/ring.c index 501a3700f0..a8f5821557 100644 --- a/platform/ring/lib/src/ring.c +++ b/platform/ring/lib/src/ring.c @@ -72,7 +72,7 @@ uint8_t ring_buf8_pop( ring_buf8_t *ring ) uint8_t result; // GCC & Clang compiler files for Renesas are not included into the project. - #if (vendor != renesas) + #if ( vendor != renesas ) assert( ring->size > 0 ); #endif diff --git a/tests/uart/test_example/main.c b/tests/uart/test_example/main.c index 6c88721b47..5c325e755e 100644 --- a/tests/uart/test_example/main.c +++ b/tests/uart/test_example/main.c @@ -146,7 +146,7 @@ int main( void ) { // TODO Test different parity values. // This test can be performed by checking // register for adequate values. - if ( UART_SUCCESS != uart_set_parity( &uart, UART_PARITY_DEFAULT) ) { + if ( UART_SUCCESS != uart_set_parity( &uart, UART_PARITY_DEFAULT ) ) { signal_error( TEST_PIN_3 ); }; #if TEST_TWO_MODULES From 565892a51b87eb3df23e3697492518bb43c48042 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Thu, 24 Jul 2025 13:53:14 +0200 Subject: [PATCH 33/62] Update targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c --- .../arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c index c24a4b476b..4b6906a20c 100644 --- a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c @@ -783,7 +783,7 @@ uint8_t hal_ll_uart_read( handle_t *handle ) { hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t * )hal_ll_uart_hw_specifics_map_local->base; - return hal_ll_hw_reg->rdr;; + return hal_ll_hw_reg->rdr; } uint8_t hal_ll_uart_read_polling( handle_t *handle ) { From 0e663440fe37b37c3d9d9134ef1b2b51ba74936b Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Thu, 24 Jul 2025 15:29:54 +0200 Subject: [PATCH 34/62] Functional PWM, more testing and prettifying needed --- .../src/tim/implementation_1/hal_ll_tim.c | 176 +++++++++--------- tests/pwm/default/main.c | 144 ++------------ 2 files changed, 103 insertions(+), 217 deletions(-) diff --git a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c index b07e0d82a7..6d603b0df7 100644 --- a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c @@ -54,6 +54,13 @@ static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COU /*!< Register defs. */ #define HAL_LL_TIM_GTCR_CST (0) #define HAL_LL_TIM_GTCR_MD_MASK (0x70000UL) +#define HAL_LL_TIM_GTCR_TPCS_MASK (0x7000000UL) +#define HAL_LL_TIM_GTCR_TPCS_DIV_1 (0x0000000UL) +#define HAL_LL_TIM_GTCR_TPCS_DIV_4 (0x1000000UL) +#define HAL_LL_TIM_GTCR_TPCS_DIV_16 (0x2000000UL) +#define HAL_LL_TIM_GTCR_TPCS_DIV_64 (0x3000000UL) +#define HAL_LL_TIM_GTCR_TPCS_DIV_256 (0x4000000UL) +#define HAL_LL_TIM_GTCR_TPCS_DIV_1024 (0x5000000UL) #define HAL_LL_TIM_GTBER_PR_MASK (0x300000UL) #define HAL_LL_TIM_GTBER_PR_SINGLE_BUFFER (0x100000UL) @@ -72,7 +79,7 @@ static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COU #define HAL_LL_TIM_GTIOR_OBE (24) - +#define HAL_LL_TIM_AF_CONFIG (GPIO_CFG_DIGITAL_OUTPUT | GPIO_CFG_PORT_PULL_UP_ENABLE) // TODO Esma /*!< @brief Helper macro for getting module specific control register structure */ #define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) @@ -91,30 +98,37 @@ static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COU /*!< @brief TIM register structure. */ typedef struct { - uint32_t gtwp; - uint32_t gtstr; - uint32_t gtstp; - uint32_t gtclr; - uint32_t gtssr; - uint32_t gtpsr; - uint32_t gtcsr; - uint32_t gtupsr; - uint32_t gtdnsr; - uint32_t gticasr; - uint32_t gticbsr; - uint32_t gtcr; - uint32_t gtuddtyc; - uint32_t gtior; - uint32_t gtintad; - uint32_t gtst; - uint32_t gtber; - uint32_t gtcnt; - uint32_t gtccr[6]; - uint32_t gtpr; - uint32_t gtpbr; - uint32_t gtdtcr; - uint32_t gtdvu; - uint32_t opscr; + uint32_t gtwp; //00 + uint32_t gtstr; //04 + uint32_t gtstp; //08 + uint32_t gtclr; //0c + uint32_t gtssr; //10 + uint32_t gtpsr; //14 + uint32_t gtcsr; //18 + uint32_t gtupsr; //1c + uint32_t gtdnsr; //20 + uint32_t gticasr; //24 + uint32_t gticbsr; //28 + uint32_t gtcr; //2c + uint32_t gtuddtyc; //30 + uint32_t gtior; //34 + uint32_t gtintad; //38 + uint32_t gtst; //3c + uint32_t gtber; //40 + uint32_t gtitc; //44 + uint32_t gtcnt; //48 + uint32_t gtccr[6]; //4c 50 54 58 5c 60 + uint32_t gtpr; // 64 + uint32_t gtpbr; //68 + uint32_t gtpdbr; //6c + uint32_t gtadtra; //70 + uint32_t gtadtbra; //74 + uint32_t gtadtdbra; //78 + uint32_t gtadtrb; //80 + uint32_t gtadtbrb; //84 + uint32_t gtdtcr; //88 + uint32_t gtdvu; //8c + // uint32_t opscr; etc } hal_ll_tim_base_handle_t; /*!< @brief TIM pin structure */ @@ -330,22 +344,48 @@ hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { } uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { - + uint16_t local_freq = 0; low_level_handle = hal_ll_tim_get_handle; hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; hal_ll_tim_init(hal_ll_tim_hw_specifics_map_local); - return HAL_LL_TIM_SUCCESS; + low_level_handle->init_ll_state = true; + + // Memorize information about the max period available (PWM duty cycle is dependant of this information). + return ( hal_ll_tim_hw_specifics_map_local->max_period = local_freq ); // TODO Esma } hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { - low_level_handle = hal_ll_tim_get_handle; hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); - hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + hal_ll_tim_pin_type_t pin_type = hal_ll_tim_hw_specifics_map_local->config.pin_type; + + system_clocks_t system_clocks; + + SYSTEM_GetClocksFrequency( &system_clocks ); + + if ( check_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST )) { + write_reg( &hal_ll_hw_reg->gtccr[(HAL_LL_TIM_PIN_A == pin_type) ? 2 : 3], + (( uint32_t )( system_clocks.pclkd / hal_ll_tim_hw_specifics_map_local->freq_hz ) * duty_ratio - 1) ); + } else { + write_reg( &hal_ll_hw_reg->gtccr[(HAL_LL_TIM_PIN_A == pin_type) ? 0 : 1], + (( uint32_t )( system_clocks.pclkd / hal_ll_tim_hw_specifics_map_local->freq_hz ) * duty_ratio - 1) ); + + if( HAL_LL_TIM_PIN_A == pin_type ) { + write_reg( &hal_ll_hw_reg->gtccr[2], read_reg( &hal_ll_hw_reg->gtccr[0] )); + } else { + write_reg( &hal_ll_hw_reg->gtccr[3], read_reg( &hal_ll_hw_reg->gtccr[1] )); + } + } + return HAL_LL_TIM_SUCCESS; } @@ -356,6 +396,11 @@ hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + hal_ll_tim_pin_type_t pin_type = hal_ll_tim_hw_specifics_map_local->config.pin_type; + + if( read_reg( &hal_ll_hw_reg->gtpr ) && read_reg( &hal_ll_hw_reg->gtccr[(HAL_LL_TIM_PIN_A == pin_type) ? 0 : 1])) + set_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST ); // Start operation. + return HAL_LL_TIM_SUCCESS; } @@ -366,6 +411,8 @@ hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + clear_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST ); + return HAL_LL_TIM_SUCCESS; } @@ -463,13 +510,13 @@ static void hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { static void hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { module_struct module; - uint32_t tim_config = 0; + uint32_t tim_config = 0; if( map->config.pin != HAL_LL_PIN_NC ) { if( hal_ll_state == false ) { - tim_config = GPIO_CFG_DIGITAL_OUTPUT; // TODO Esma + tim_config = 0; // TODO Esma } else { - tim_config = GPIO_CFG_DIGITAL_OUTPUT; // TODO Esma + tim_config = HAL_LL_TIM_AF_CONFIG; } module.pins[0] = VALUE( map->config.pin, map->config.af ); @@ -482,53 +529,26 @@ static void hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_ma } } -#define PCLK 60000000UL // Example Peripheral Clock -#define FREQ_HZ 1000.0f // Desired PWM frequency -#define DUTY 0.5f // 50% duty cycle - -#define PERIOD ((uint32_t)(PCLK / FREQ_HZ)) // e.g. 60000 -#define COMPARE ((uint32_t)(PERIOD * DUTY) - 1) // e.g. 29999 static void hal_ll_tim_set_freq_bare_metal( hal_ll_tim_hw_specifics_map_t *map ) { hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); - // R_GPT4->GTCR = 0; // Clear control register (stop, reset config) - clear_reg( &hal_ll_hw_reg->gtcr ); // Clear control register (stop, reset config) - - // R_GPT4->GTUDDTYC = 0x00; // Saw-wave PWM mode (count up) - set_reg_bit( &hal_ll_hw_reg->gtuddtyc, HAL_LL_TIM_GTUDDTYC_UD ); // Count up. - - if( HAL_LL_TIM_PIN_A == map->config.pin_type ) { - // R_GPT4->GTIOR = - // (0b01 << 2) | // GTIOCA output when counting up and match A (initial output = 1) - // (0b01 << 0) | // GTIOCA output when counting up and not matching (output = 0) - // (1 << 14); // Enable GTIOCA output - - R_GPT0->GTCCR[0] = COMPARE; // Set compare match A - R_GPT0->GTCCR[2] = COMPARE; // Buffered A - } + system_clocks_t system_clocks; - R_GPT0->GTPR = PERIOD - 1; // Set PWM period - R_GPT0->GTPBR = PERIOD - 1; // Buffered period + SYSTEM_GetClocksFrequency( &system_clocks ); - R_GPT0->GTCR = (0b000 << 1); // PCLK/1 as clock source (TPCS bits) - - R_GPT0->GTCNT = 0; // Clear counter - R_GPT0->GTCR |= (1 << 0); // Start timer (CST = 1) + write_reg( &hal_ll_hw_reg->gtpr, system_clocks.pclkd / map->freq_hz - 1 ); + write_reg( &hal_ll_hw_reg->gtpbr, system_clocks.pclkd / map->freq_hz - 1 ); } static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); hal_ll_tim_pin_type_t pin_type = map->config.pin_type; - // PSEL 3 - // R_MSTP->MSTPCRD_b.MSTPD6 = 0; + clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD5_POS ); - // R_GPT4->GTCR_b.CST = 0; // stop operation first clear_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST ); // Stop operation first. - // R_GPT4->GTCR_b.MD = 0x0; // PWM mode clear_reg_bits( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_MD_MASK ); // PWM mode. - // R_GPT4->GTBER_b.PR = 1; // count up // ?????????? - // R_GPT4->GTBER_b.PR = 1; // single buffer operation + set_reg_bit( &hal_ll_hw_reg->gtuddtyc, HAL_LL_TIM_GTUDDTYC_UD ); // Count up. clear_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_PR_MASK ); set_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_PR_SINGLE_BUFFER ); // Single buffer operation. @@ -536,48 +556,24 @@ static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { hal_ll_tim_set_freq_bare_metal( map ); // .... // freq settings - // R_GPT4->GTCNT = 0; // initial counter value clear_reg( &hal_ll_hw_reg->gtcnt ); if( HAL_LL_TIM_PIN_A == map->config.pin_type ) { // A - // R_GPT4->GTIOR_b.GTIOA = 0x9; // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end) // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end) clear_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOA_MASK ); set_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOA_9 ); - // R_GPT4->GTIOR_b.OAE = 1; // Enable GTIOC pin output set_reg_bit( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_OAE ); // Enable GTIOC pin output - // R_GPT4->GTBER_b.CCRA = 1; // Set buffer operation for the duty clear_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRA_MASK ); set_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRA_SINGLE_BUFFER ); - // uint32_t duty = 0; // ???? - // R_GPT4->GTCCR[0] = duty? duty - 1 : duty; // Set compare match value - // R_GPT4->GTCCR[2] = R_GPT4->GTCCR[0]; - } else { - // A - // R_GPT4->GTIOR_b.GTIOB = 0x9; // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end) + // B // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end) clear_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOB_MASK ); set_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOB_9 ); - // R_GPT4->GTIOR_b.OBE = 1; // Enable GTIOC pin output set_reg_bit( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_OBE ); // Enable GTIOC pin output - // R_GPT4->GTBER_b.CCRB = 1; // Set buffer operation for the duty clear_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRB_MASK ); set_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRB_SINGLE_BUFFER ); - // uint32_t duty = 0; // ???? - // R_GPT4->GTCCR[1] = duty? duty - 1 : duty; // Set compare match value - // R_GPT4->GTCCR[3] = R_GPT4->GTCCR[1]; } - - // R_PFS->PORT[3].PIN[2].PmnPFS_b.PMR = 1; - // R_PFS->PORT[3].PIN[2].PmnPFS_b.PMR = 1; - // R_PFS->PORT[3].PIN[2].PmnPFS_b.PSEL = 3; - - // if (R_GPT4->GTPR && R_GPT4->GTCCR[0]) { - // R_GPT4->GTCR_b.CST = 1; - // } - if( read_reg( &hal_ll_hw_reg->gtpr ) && read_reg( &hal_ll_hw_reg->gtccr[(HAL_LL_TIM_PIN_A == pin_type) ? 0 : 1])) - set_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST ); // Start operation. } static void hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { diff --git a/tests/pwm/default/main.c b/tests/pwm/default/main.c index 17f52a1ba2..246fefbdaa 100644 --- a/tests/pwm/default/main.c +++ b/tests/pwm/default/main.c @@ -15,7 +15,7 @@ // -------------------------------------------------------------------- MACROS -#define TEST_PIN_PWM_TIM GPIO_P302 // TODO define pin used in test +#define TEST_PIN_PWM_TIM GPIO_P107 // TODO define pin used in test #define TEST_PWM_FREQUENCY 5000 // TODO define frequency used in last test @@ -124,13 +124,6 @@ static inline void run_test_3( void ) { wait_test_time; } } -#include "mcu.h" -#define PCLK 60000000UL // Example Peripheral Clock -#define FREQ_HZ 1000.0f // Desired PWM frequency -#define DUTY 0.5f // 50% duty cycle - -#define PERIOD ((uint32_t)(PCLK / FREQ_HZ)) // e.g. 60000 -#define COMPARE ((uint32_t)(PERIOD * DUTY) - 1) // e.g. 29999 int main( void ) { /* Do not remove this line or clock might not be set correctly. */ @@ -140,79 +133,6 @@ int main( void ) { int counter = 0; - // // PSEL 3 - // R_MSTP->MSTPCRD_b.MSTPD6 = 0; - - // R_GPT4->GTCR_b.CST = 0; // stop operation first - // R_GPT4->GTCR_b.MD = 0x0; // PWM mode - // R_GPT4->GTBER_b.PR = 1; // count up - // R_GPT4->GTBER_b.PR = 1; // single buffer operation - // // .... // freq settings - // R_GPT4->GTCR = 0; // Clear control register (stop, reset config) - - // R_GPT4->GTUDDTYC = 0x00; // Saw-wave PWM mode (count up) - // R_GPT4->GTIOR = - // (0b01 << 2) | // GTIOCA output when counting up and match A (initial output = 1) - // (0b00 << 0) | // GTIOCA output when counting up and not matching (output = 0) - // (1 << 14); // Enable GTIOCA output - - // R_GPT4->GTCCR[0] = COMPARE; // Set compare match A - // R_GPT4->GTCCR[2] = COMPARE; // Buffered A - - // R_GPT4->GTPR = PERIOD - 1; // Set PWM period - // R_GPT4->GTPBR = PERIOD - 1; // Buffered period - - // R_GPT4->GTCR = (0b000 << 1); // PCLK/1 as clock source (TPCS bits) - - // R_GPT4->GTCNT = 0; // Clear counter - // R_GPT4->GTCR |= (1 << 0); // Start timer (CST = 1) - // // .... // freq settings - - - // R_GPT4->GTCNT = 0; // initial counter value - - // // A - // R_GPT4->GTIOR_b.GTIOA = 0x9; // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end) - // R_GPT4->GTIOR_b.OAE = 1; // Enable GTIOC pin output - // R_GPT4->GTBER_b.CCRA = 1; // Set buffer operation for the duty - // // uint32_t duty = 0; // ???? - // // R_GPT4->GTCCR[0] = duty? duty - 1 : duty; // Set compare match value - // R_GPT4->GTCCR[2] = R_GPT4->GTCCR[0]; - - // R_PFS->PORT[3].PIN[2].PmnPFS_b.PMR = 1; - // R_PFS->PORT[3].PIN[2].PmnPFS_b.PMR = 1; - // R_PFS->PORT[3].PIN[2].PmnPFS_b.PSEL = 3; - - // if (R_GPT4->GTPR && R_GPT4->GTCCR[0]) { - // R_GPT4->GTCR_b.CST = 1; - // } - // float duty = 0.0f; - // float step = 0.01f; - // uint32_t compare; - - // while (1) { - // // Calculate compare value from duty - // compare = (uint32_t)(duty * PERIOD); - // if (compare > 0) compare--; // avoid overshoot - - // R_GPT4->GTCCR[0] = compare; - // R_GPT4->GTCCR[2] = compare; - - // // Update duty - // duty += step; - // if (duty >= 1.0f) { - // duty = 1.0f; - // step = -step; - // } else if (duty <= 0.0f) { - // duty = 0.0f; - // step = -step; - // } - - // // Delay to control speed of fading (adjust as needed) - // for (volatile int i = 0; i < 30000; i++); - // } - - // while(1); // Default config pwm_configure_default( &pwm_cfg ); @@ -228,21 +148,21 @@ int main( void ) { // Testing predefined cases for PWM // Test 1 - Change freq -> set duty -> start - // for ( counter = 0; counter < (sizeof(freq_array) / sizeof(uint32_t)); counter++ ) { - // // Check if pwm is stoped. - // run_test_1( freq_array[ counter ] ); - // wait_test_time; - // } - - // // Test 2 - Change freq -> start -> set duty - // for ( counter = 0; counter < (sizeof(freq_array) / sizeof(uint32_t)); counter++ ) { - // // Check if pwm is stoped. - // run_test_2( freq_array[ counter ] ); - // wait_test_time; - // } - - // // Test 3 - stop -> start and so on - simulate LED blinking - // run_test_3(); + for ( counter = 0; counter < (sizeof(freq_array) / sizeof(uint32_t)); counter++ ) { + // Check if pwm is stoped. + run_test_1( freq_array[ counter ] ); + wait_test_time; + } + + // Test 2 - Change freq -> start -> set duty + for ( counter = 0; counter < (sizeof(freq_array) / sizeof(uint32_t)); counter++ ) { + // Check if pwm is stoped. + run_test_2( freq_array[ counter ] ); + wait_test_time; + } + + // Test 3 - stop -> start and so on - simulate LED blinking + run_test_3(); // TODO Test different freq for PWM. // Using oscilloscope test all possible freq. @@ -265,36 +185,6 @@ int main( void ) { signal_error( TEST_PIN_4 ); } - // ADD begin - float duty = 0.0f; - float step = 0.01f; - uint32_t compare; - - while (1) { - // Calculate compare value from duty - compare = (uint32_t)(duty * PERIOD); - if (compare > 0) compare--; // avoid overshoot - - R_GPT4->GTCCR[0] = compare; - R_GPT4->GTCCR[2] = compare; - - // Update duty - duty += step; - if (duty >= 1.0f) { - duty = 1.0f; - step = -step; - } else if (duty <= 0.0f) { - duty = 0.0f; - step = -step; - } - - // Delay to control speed of fading (adjust as needed) - for (volatile int i = 0; i < 30000; i++); - } - - while(1); - // ADD end - wait_test_time; // Check if pwm is stoped. @@ -311,4 +201,4 @@ int main( void ) { return 0; } -// ----------------------------------------------------------------------- END +// ----------------------------------------------------------------------- END \ No newline at end of file From ee6691d45467f45279429bb6e878ef6be7a57119 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Thu, 24 Jul 2025 16:21:58 +0200 Subject: [PATCH 35/62] PWMc ode clean up and B pin test --- .../RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 1 + .../implementation_1/hal_ll_tim_pin_map.h | 11 ++- .../src/tim/implementation_1/hal_ll_tim.c | 82 +++++++++++++------ 3 files changed, 63 insertions(+), 31 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h index ed231ba7a5..90d74a07d2 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -94,6 +94,7 @@ #define TIM4_P302 #define TIM0_P107 +#define TIM2_P102 #define TIM_MODULE_COUNT 12 //EOF TIM diff --git a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h index d2b974b7fd..11ba4dff8c 100644 --- a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h +++ b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h @@ -60,19 +60,19 @@ extern "C"{ static const hal_ll_base_addr_t HAL_LL_TIM0_BASE_ADDR = 0x40078000; #endif #ifdef TIM_MODULE_1 -static const hal_ll_base_addr_t HAL_LL_TIM1_BASE_ADDR = 0x40078400; +static const hal_ll_base_addr_t HAL_LL_TIM1_BASE_ADDR = 0x40078100; #endif #ifdef TIM_MODULE_2 -static const hal_ll_base_addr_t HAL_LL_TIM2_BASE_ADDR = 0x40078400; +static const hal_ll_base_addr_t HAL_LL_TIM2_BASE_ADDR = 0x40078200; #endif #ifdef TIM_MODULE_3 -static const hal_ll_base_addr_t HAL_LL_TIM3_BASE_ADDR = 0x40078400; +static const hal_ll_base_addr_t HAL_LL_TIM3_BASE_ADDR = 0x40078300; #endif #ifdef TIM_MODULE_4 static const hal_ll_base_addr_t HAL_LL_TIM4_BASE_ADDR = 0x40078400; #endif #ifdef TIM_MODULE_5 -static const hal_ll_base_addr_t HAL_LL_TIM5_BASE_ADDR = 0x40078400; +static const hal_ll_base_addr_t HAL_LL_TIM5_BASE_ADDR = 0x40078500; #endif typedef enum { @@ -97,6 +97,9 @@ static const hal_ll_tim_pin_map_t hal_ll_tim_pin_map[] = { #ifdef TIM0_P107 {GPIO_P107, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_PIN_A}, #endif + #ifdef TIM2_P102 + {GPIO_P102, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_PIN_B}, + #endif { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC } diff --git a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c index 6d603b0df7..5d1830e2d2 100644 --- a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c @@ -165,19 +165,19 @@ typedef enum static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = { #ifdef TIM_MODULE_0 - {HAL_LL_TIM0_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_0 - 1}, + {HAL_LL_TIM0_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_0)}, #endif #ifdef TIM_MODULE_1 - {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_1)}, #endif #ifdef TIM_MODULE_2 - {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_2)}, #endif #ifdef TIM_MODULE_3 - {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_3)}, #endif #ifdef TIM_MODULE_4 - {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_4)}, #endif {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} @@ -194,14 +194,13 @@ static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local * address * @return None */ -static void hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); +static void hal_ll_tim_module_enable( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); /** * @brief Select TIM clock source - * @param selector - clock source selector * @return uint32_t - clock source */ -static uint32_t hal_ll_tim_clock_source( uint8_t selector ); +static uint32_t hal_ll_tim_clock_source(); /** * @brief Based on selected TIM, @@ -360,7 +359,7 @@ uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { // Memorize information about the max period available (PWM duty cycle is dependant of this information). return ( hal_ll_tim_hw_specifics_map_local->max_period = local_freq ); // TODO Esma } - +uint32_t read; hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { low_level_handle = hal_ll_tim_get_handle; hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); @@ -368,16 +367,14 @@ hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { hal_ll_tim_pin_type_t pin_type = hal_ll_tim_hw_specifics_map_local->config.pin_type; - system_clocks_t system_clocks; - - SYSTEM_GetClocksFrequency( &system_clocks ); + uint32_t pclkd = hal_ll_tim_clock_source(); if ( check_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST )) { write_reg( &hal_ll_hw_reg->gtccr[(HAL_LL_TIM_PIN_A == pin_type) ? 2 : 3], - (( uint32_t )( system_clocks.pclkd / hal_ll_tim_hw_specifics_map_local->freq_hz ) * duty_ratio - 1) ); + (( uint32_t )( pclkd / hal_ll_tim_hw_specifics_map_local->freq_hz ) * duty_ratio - 1) ); } else { write_reg( &hal_ll_hw_reg->gtccr[(HAL_LL_TIM_PIN_A == pin_type) ? 0 : 1], - (( uint32_t )( system_clocks.pclkd / hal_ll_tim_hw_specifics_map_local->freq_hz ) * duty_ratio - 1) ); + (( uint32_t )( pclkd / hal_ll_tim_hw_specifics_map_local->freq_hz ) * duty_ratio - 1) ); if( HAL_LL_TIM_PIN_A == pin_type ) { write_reg( &hal_ll_hw_reg->gtccr[2], read_reg( &hal_ll_hw_reg->gtccr[0] )); @@ -430,9 +427,9 @@ void hal_ll_tim_close( handle_t *handle ) { hal_ll_tim_hw_specifics_map_local->max_period = 0; hal_ll_tim_hw_specifics_map_local->freq_hz = 0; - hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + hal_ll_tim_module_enable( hal_ll_tim_hw_specifics_map_local, true ); hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); - hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + hal_ll_tim_module_enable( hal_ll_tim_hw_specifics_map_local, false ); hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; hal_ll_tim_hw_specifics_map_local->config.pin_type = HAL_LL_PIN_NC; @@ -487,13 +484,47 @@ static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; } -static void hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { +static void hal_ll_tim_module_enable( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + if ( true == hal_ll_state) { + switch ( map->module_index ) { + case hal_ll_tim_module_num(TIM_MODULE_0): + case hal_ll_tim_module_num(TIM_MODULE_1): + clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD5_POS ); + break; + case hal_ll_tim_module_num(TIM_MODULE_2): + case hal_ll_tim_module_num(TIM_MODULE_3): + case hal_ll_tim_module_num(TIM_MODULE_4): + clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD6_POS ); + break; + + default: + break; + } + } else { + switch ( map->module_index ) { + case hal_ll_tim_module_num(TIM_MODULE_0): + case hal_ll_tim_module_num(TIM_MODULE_1): + set_reg_bit( _MSTPCRD, MSTPCRD_MSTPD5_POS ); + break; + case hal_ll_tim_module_num(TIM_MODULE_2): + case hal_ll_tim_module_num(TIM_MODULE_3): + case hal_ll_tim_module_num(TIM_MODULE_4): + set_reg_bit( _MSTPCRD, MSTPCRD_MSTPD6_POS ); + break; + + default: + break; + } + } } -static uint32_t hal_ll_tim_clock_source( uint8_t selector ) { +static uint32_t hal_ll_tim_clock_source() { + system_clocks_t system_clocks; - return 0; + SYSTEM_GetClocksFrequency( &system_clocks ); + + return system_clocks.pclkd; } static uint32_t hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { @@ -532,20 +563,16 @@ static void hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_ma static void hal_ll_tim_set_freq_bare_metal( hal_ll_tim_hw_specifics_map_t *map ) { hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); - system_clocks_t system_clocks; - - SYSTEM_GetClocksFrequency( &system_clocks ); + uint32_t pclkd = hal_ll_tim_clock_source(); - write_reg( &hal_ll_hw_reg->gtpr, system_clocks.pclkd / map->freq_hz - 1 ); - write_reg( &hal_ll_hw_reg->gtpbr, system_clocks.pclkd / map->freq_hz - 1 ); + write_reg( &hal_ll_hw_reg->gtpr, pclkd / map->freq_hz - 1 ); + write_reg( &hal_ll_hw_reg->gtpbr, pclkd / map->freq_hz - 1 ); } static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); hal_ll_tim_pin_type_t pin_type = map->config.pin_type; - clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD5_POS ); - clear_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST ); // Stop operation first. clear_reg_bits( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_MD_MASK ); // PWM mode. set_reg_bit( &hal_ll_hw_reg->gtuddtyc, HAL_LL_TIM_GTUDDTYC_UD ); // Count up. @@ -566,6 +593,7 @@ static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { set_reg_bit( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_OAE ); // Enable GTIOC pin output clear_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRA_MASK ); set_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRA_SINGLE_BUFFER ); + } else { // B // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end) clear_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOB_MASK ); @@ -578,7 +606,7 @@ static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { static void hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { - hal_ll_tim_set_clock( map->base, true ); + hal_ll_tim_module_enable( map, true ); hal_ll_tim_alternate_functions_set_state( map, true ); From 8480bbe2d4f2f3446201d2c337cd42532921848e Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Tue, 29 Jul 2025 10:27:41 +0200 Subject: [PATCH 36/62] Updated baud rate calculations for UART --- .../src/uart/implementation_1/hal_ll_uart.c | 34 +++++++++++++------ 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c index 4b6906a20c..35361aac39 100644 --- a/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/renesas/src/uart/implementation_1/hal_ll_uart.c @@ -103,6 +103,11 @@ static volatile hal_ll_uart_handle_register_t hal_ll_module_state[ UART_MODULE_C (int32_t)(((((int64_t)pclka) * HAL_LL_SCI_BRR_ERROR_REFERENCE) / \ (g_div_coefficient[i] * baud * (brr + 1))) - HAL_LL_SCI_BRR_ERROR_REFERENCE) +/*!< @brief Macro used for getting the real baudrate. + * baud = PCLKA / ((BRR + 1) * div_coefficient) + */ +#define hal_ll_sci_get_baud_rate(pclka, brr, i) (pclka / ((brr + 1) * g_div_coefficient[i])) + /*!< @brief Macros defining bit location. */ #define HAL_LL_SCI_SEMR_BRME 2 #define HAL_LL_SCI_SEMR_ABCSE 3 @@ -126,8 +131,8 @@ static volatile hal_ll_uart_handle_register_t hal_ll_module_state[ UART_MODULE_C (abcse << HAL_LL_SCI_SEMR_ABCSE) /*!< @brief Macros used for baudrate calculations. */ -#define HAL_LL_SCI_NUM_DIVISORS 7 -#define HAL_LL_SCI_BRR_MAX 255 +#define HAL_LL_SCI_NUM_DIVISORS 13 +#define HAL_LL_SCI_BRR_MAX 256 #define HAL_LL_SCI_BRR_ERROR_ACCEPTABLE 1000UL #define HAL_LL_SCI_BRR_ERROR_REFERENCE 100000UL @@ -143,19 +148,25 @@ typedef struct st_baud_setting_const_t /*!< @brief Baud rate bit divisor information structure. */ static const baud_setting_const_t g_async_baud[ HAL_LL_SCI_NUM_DIVISORS ] = { - {0U, 0U, 1U, 0U}, /* BGDM, ABCS, ABCSE, n */ + {0U, 0U, 1U, 0U}, /* BGDM, ABCS, ABCSE, n */ {1U, 1U, 0U, 0U}, {1U, 0U, 0U, 0U}, {0U, 0U, 1U, 1U}, {0U, 0U, 0U, 0U}, {1U, 0U, 0U, 1U}, - {0U, 0U, 0U, 1U} + {0U, 0U, 1U, 2U}, + {0U, 0U, 0U, 1U}, + {1U, 0U, 0U, 2U}, + {0U, 0U, 1U, 3U}, + {0U, 0U, 0U, 2U}, + {1U, 0U, 0U, 3U}, + {0U, 0U, 0U, 3U} }; /*!< @brief Baud rate divisor information structure. */ -static const uint8_t g_div_coefficient[ HAL_LL_SCI_NUM_DIVISORS ] = +static const uint16_t g_div_coefficient[ HAL_LL_SCI_NUM_DIVISORS ] = { - 6U, 8U, 16U, 24U, 32U, 64U, 128U + 6U, 8U, 16U, 24U, 32U, 64U, 96U, 128U, 256U, 384U, 512U, 1024U, 2048U, }; /*!< @brief UART HW register structure. */ @@ -1088,8 +1099,6 @@ static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map * is tried, and the settings with the lowest bit rate error are stored. The formula to calculate BRR is as * follows and it must be 255 or less: * BRR = (PCLKA / (div_coefficient * baud)) - 1 - * Note: only values for internal baudrate generator are used as this implementation doesn't support use of - * external baudrate generator. */ uint32_t error = HAL_LL_SCI_BRR_ERROR_REFERENCE; uint32_t temp_brr, divisor = 0U; @@ -1110,7 +1119,7 @@ static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map temp_brr = hal_ll_sci_brr_calculate( map->baud_rate.baud, source_clock, i ); - if (( HAL_LL_SCI_BRR_MAX + 1U ) >= temp_brr ) + if (( HAL_LL_SCI_BRR_MAX ) >= temp_brr ) { while ( temp_brr-- > 0U ) { @@ -1133,6 +1142,7 @@ static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map cks = g_async_baud[i].cks; brr = ( uint8_t ) temp_brr; error = current_error; + map->baud_rate.real_baud = hal_ll_sci_get_baud_rate( source_clock, brr ,i ); } } } @@ -1140,7 +1150,7 @@ static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map } set_reg_bits( &hal_ll_hw_reg->semr, HAL_LL_SCI_SEMR_CONFIGURE( bgdm, abcs, abcse )); - set_reg_bits( &hal_ll_hw_reg->scr, cks ); + set_reg_bits( &hal_ll_hw_reg->smr, cks ); write_reg( &hal_ll_hw_reg->brr, brr ); } @@ -1221,6 +1231,10 @@ static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, ha set_reg_bits( &hal_ll_hw_reg->scr, HAL_LL_SCI_CLOCK_EXTERNAL ); break; + case HAL_LL_UART_ENABLE: + clear_reg_bits( &hal_ll_hw_reg->scr, HAL_LL_SCI_CLOCK_EXTERNAL ); + break; + default: break; } From 2ba6232a42e828566825901ed81812fb1379771c Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Tue, 29 Jul 2025 15:49:13 +0200 Subject: [PATCH 37/62] SPI done --- .../RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 5 + .../include/spi_master/hal_ll_spi_master.h | 25 + .../hal_ll_spi_master_pin_map.h | 149 +---- .../implementation_1/hal_ll_spi_master.c | 542 +++++++++++++----- .../src/tim/implementation_1/hal_ll_tim.c | 84 ++- 5 files changed, 492 insertions(+), 313 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h index 90d74a07d2..60ceb2baac 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -81,6 +81,11 @@ //EOF UART //SPI +#define SPI0_SCK_P102_AF6 +#define SPI0_MISO_P100_AF6 +#define SPI0_MOSI_P101_AF6 + +#define SPI_MODULE_0 1 #define SPI_MODULE_COUNT 6 //EOF SPI diff --git a/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h index 24e926b0fc..ef8850fa70 100644 --- a/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h +++ b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h @@ -208,6 +208,31 @@ hal_ll_err_t hal_ll_spi_master_read( handle_t *handle, uint8_t *read_data_buffer */ hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data ); +/** + * @brief Performs simultaneous write and read on SPI bus. + * + * Executes a full-duplex SPI transfer. While writing `write_data_buffer`, + * the incoming bytes from the SPI slave are placed into `read_data_buffer`. + * This function is suitable for devices that require simultaneous + * transmission and reception. + * + * @param[in] handle HAL context object handle. + * @param[in] write_data_buffer Pointer to data to be written to the bus. + * @param[out] read_data_buffer Pointer to buffer where read data will be stored. + * @param[in] data_length Number of bytes to transfer. + * + * @return hal_ll_err_t Returns #HAL_LL_SPI_MASTER_SUCCESS on success, + * otherwise returns #HAL_LL_SPI_MASTER_MODULE_ERROR + * if handle is invalid or data_length is 0. + * + * @note This function assumes the SPI module is already initialized via + * #hal_ll_spi_master_register_handle and #hal_ll_module_configure_spi. + */ +hal_ll_err_t hal_ll_spi_master_transfer( handle_t *handle, + uint8_t *write_data_buffer, + uint8_t *read_data_buffer, + size_t data_length ); + /** * @brief Closes SPI Master HAL and HAL_LOW_LEVEL context object. * diff --git a/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h index feaa27b803..69afa2f297 100644 --- a/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h +++ b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h @@ -57,16 +57,7 @@ extern "C"{ /*!< SPI module base addresses. */ #ifdef SPI_MODULE_0 -static const hal_ll_base_addr_t HAL_LL_SPI0_MASTER_BASE_ADDR = 0X40008000; -#endif -#ifdef SPI_MODULE_1 -static const hal_ll_base_addr_t HAL_LL_SPI1_MASTER_BASE_ADDR = 0X40009000; -#endif -#ifdef SPI_MODULE_2 -static const hal_ll_base_addr_t HAL_LL_SPI2_MASTER_BASE_ADDR = 0X4000A000; -#endif -#ifdef SPI_MODULE_3 -static const hal_ll_base_addr_t HAL_LL_SPI3_MASTER_BASE_ADDR = 0X4000B000; +static const hal_ll_base_addr_t HAL_LL_SPI0_MASTER_BASE_ADDR = 0x40072000; #endif /*!< @brief SPI pin structure. */ @@ -78,147 +69,27 @@ typedef struct { } hal_ll_spi_master_pin_map_t; /*!< SPI SCK pins. */ -static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = { - #ifdef SPI0_SCK_PA2_AF2 - {GPIO_PA2, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 2}, - #endif - #ifdef SPI1_SCK_PD0_AF2 - {GPIO_PD0, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, - #endif - #ifdef SPI1_SCK_PF2_AF2 - {GPIO_PF2, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, - #endif - #ifdef SPI2_SCK_PB4_AF2 - {GPIO_PB4, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 2}, - #endif - #ifdef SPI3_SCK_PD0_AF1 - {GPIO_PD0, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 1}, - #endif - #ifdef SPI2_SCK_PH4_AF2 - {GPIO_PH4, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 2}, - #endif - #ifdef SPI3_SCK_PH0_AF2 - {GPIO_PH0, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 2}, - #endif - #ifdef SPI3_SCK_PK0_AF2 - {GPIO_PK0, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 2}, - #endif - #ifdef SPI0_SCK_PA2_AF15 - {GPIO_PA2, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 15}, - #endif - #ifdef SPI1_SCK_PB5_AF15 - {GPIO_PB5, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 15}, - #endif - #ifdef SPI2_SCK_PD3_AF15 - {GPIO_PD3, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 15}, - #endif - #ifdef SPI2_SCK_PG7_AF15 - {GPIO_PG7, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 15}, - #endif - #ifdef SPI3_SCK_PF2_AF14 - {GPIO_PF2, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 14}, - #endif - #ifdef SPI3_SCK_PF3_AF14 - {GPIO_PF3, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 14}, - #endif - #ifdef SPI3_SCK_PQ0_AF14 - {GPIO_PQ0, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 14}, +static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_sck_map[] = { + #ifdef SPI0_SCK_P102_AF6 + {GPIO_P102, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 6}, #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; /*!< SPI MISO pins. */ -static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = { - #ifdef SPI0_MISO_PA4_AF2 - {GPIO_PA4, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 2}, - #endif - #ifdef SPI1_MISO_PD2_AF2 - {GPIO_PD2, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, - #endif - #ifdef SPI1_MISO_PF0_AF2 - {GPIO_PF0, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, - #endif - #ifdef SPI2_MISO_PB6_AF2 - {GPIO_PB6, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 2}, - #endif - #ifdef SPI3_MISO_PD2_AF1 - {GPIO_PD2, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 1}, - #endif - #ifdef SPI2_MISO_PH6_AF2 - {GPIO_PH6, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 2}, - #endif - #ifdef SPI3_MISO_PH2_AF2 - {GPIO_PH2, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 2}, - #endif - #ifdef SPI3_MISO_PK2_AF2 - {GPIO_PK2, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 2}, - #endif - #ifdef SPI0_MISO_PA5_AF15 - {GPIO_PA5, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 15}, - #endif - #ifdef SPI1_MISO_PE5_AF15 - {GPIO_PE5, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 15}, - #endif - #ifdef SPI2_MISO_PD0_AF15 - {GPIO_PD0, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 15}, - #endif - #ifdef SPI2_MISO_PG4_AF15 - {GPIO_PG4, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 15}, - #endif - #ifdef SPI3_MISO_PF0_AF14 - {GPIO_PF0, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 14}, - #endif - #ifdef SPI3_MISO_PQ3_AF14 - {GPIO_PQ3, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 14}, +static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_miso_map[] = { + #ifdef SPI0_MISO_P100_AF6 + {GPIO_P100, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 6}, #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; /*!< SPI MOSI pins. */ -static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = { - #ifdef SPI0_MOSI_PA5_AF2 - {GPIO_PA5, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 2}, - #endif - #ifdef SPI1_MOSI_PD3_AF2 - {GPIO_PD3, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, - #endif - #ifdef SPI1_MOSI_PF1_AF2 - {GPIO_PF1, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, - #endif - #ifdef SPI2_MOSI_PB7_AF2 - {GPIO_PB7, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 2}, - #endif - #ifdef SPI3_MOSI_PD3_AF1 - {GPIO_PD3, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 1}, - #endif - #ifdef SPI2_MOSI_PH7_AF2 - {GPIO_PH7, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 2}, - #endif - #ifdef SPI3_MOSI_PH3_AF2 - {GPIO_PH3, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 2}, - #endif - #ifdef SPI3_MOSI_PK3_AF2 - {GPIO_PK3, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 2}, - #endif - #ifdef SPI0_MOSI_PA4_AF15 - {GPIO_PA4, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 15}, - #endif - #ifdef SPI1_MOSI_PE4_AF15 - {GPIO_PE4, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 15}, - #endif - #ifdef SPI2_MOSI_PD1_AF15 - {GPIO_PD1, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 15}, - #endif - #ifdef SPI2_MOSI_PG5_AF15 - {GPIO_PG5, HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), 15}, - #endif - #ifdef SPI3_MOSI_PF1_AF14 - {GPIO_PF1, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 14}, - #endif - #ifdef SPI3_MOSI_PQ2_AF14 - {GPIO_PQ2, HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), 14}, +static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_mosi_map[] = { + #ifdef SPI0_MOSI_P101_AF6 + {GPIO_P101, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 6}, #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} diff --git a/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c b/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c index b26175ddbe..033f91557e 100644 --- a/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c +++ b/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c @@ -43,6 +43,8 @@ #include "hal_ll_spi_master.h" #include "hal_ll_spi_master_pin_map.h" #include "hal_ll_gpio_port.h" +#include "hal_ll_mstpcr.h" +#include "mcu.h" /*!< @brief Local handle list */ static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[ SPI_MODULE_COUNT ] = { ( handle_t * )NULL, ( handle_t * )NULL, false }; @@ -61,6 +63,29 @@ static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[ SPI_MOD // -------------------------------------------------------------- PRIVATE TYPES +#define HAL_LL_SPI_SPSR_SPTEF (5) +#define HAL_LL_SPI_SPSR_SPRF (7) + +#define HAL_LL_SPI_SPDCR_SPBYT (6) + +#define HAL_LL_SPI_SPCR2_SCKASE (4) + +#define HAL_LL_SPI_SPCMD0_SPNDEN_MASK (1UL << 13) +#define HAL_LL_SPI_SPCMD0_SLNDEN_MASK (1UL << 14) +#define HAL_LL_SPI_SPCMD0_SCKDEN_MASK (1UL << 15) +#define HAL_LL_SPI_SPCMD0_SPB_8BIT_MASK (7UL << 8) +#define HAL_LL_SPI_SPCMD0_BRDV_MASK (3UL << 2) +#define HAL_LL_SPI_SPCMD0_BRDV (2) +#define HAL_LL_SPI_SPCMD0_CPHA (0) +#define HAL_LL_SPI_SPCMD0_CPOL (1) + +#define HAL_LL_SPI_SPCR_MSTR_MASK (1UL << 3) +#define HAL_LL_SPI_SPCR_SPE_MASK (1UL << 6) + + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + /*!< @brief SPI Master hw specific error values. */ typedef enum { HAL_LL_SPI_MASTER_SUCCESS = 0, @@ -72,7 +97,24 @@ typedef enum { /*!< @brief SPI register structure. */ typedef struct { - + uint8_t spcr; + uint8_t sslp; + uint8_t sppcr; + uint8_t spsr; + union { + uint32_t spdr; + uint16_t spdr_ha; + uint8_t spdr_by; + }; + uint8_t spscr; + uint8_t spssr; + uint8_t spbr; + uint8_t spdcr; + uint8_t spckd; + uint8_t sslnd; + uint8_t spnd; + uint8_t spcr2; + uint16_t spcmd0; } hal_ll_spi_master_base_handle_t; /*!< @brief SPI Master hardware specific module values. */ @@ -102,16 +144,9 @@ static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_speci /*!< @brief SPI Master hardware specific info. */ static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[ SPI_MODULE_COUNT + 1 ] = { #ifdef SPI_MODULE_0 - { HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT }, - #endif - #ifdef SPI_MODULE_1 - { HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT }, - #endif - #ifdef SPI_MODULE_2 - { HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT }, - #endif - #ifdef SPI_MODULE_3 - { HAL_LL_SPI3_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT }, + { HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), + { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, + HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT }, #endif { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, 0, 0, 0 } @@ -135,7 +170,11 @@ static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[ * Returns pre-defined module index from pin maps, if pins * are adequate. */ -static hal_ll_pin_name_t _hal_ll_spi_master_check_pins( hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); +static hal_ll_pin_name_t hal_ll_spi_master_check_pins( hal_ll_pin_name_t sck_pin, + hal_ll_pin_name_t miso_pin, + hal_ll_pin_name_t mosi_pin, + hal_ll_spi_pin_id *index_list, + hal_ll_spi_master_handle_register_t *handle_map ); /** * @brief Enable clock for SPI module on hardware level. @@ -147,7 +186,7 @@ static hal_ll_pin_name_t _hal_ll_spi_master_check_pins( hal_ll_pin_name_t sck_pi * @param[in] hal_ll_state - True(enable clock)/False(disable clock). * @return None */ -static void _hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ); +static void hal_ll_spi_master_module_enable( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ); /** * @brief Get local hardware specific map. @@ -161,7 +200,10 @@ static void _hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_t * * Returns pre-defined map index address based on handle value, * if handle is adequate. */ -static hal_ll_spi_master_hw_specifics_map_t *_hal_ll_get_specifics( handle_t handle ); +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +// TODO +static void hal_ll_spi_master_set_bit_rate( hal_ll_spi_master_hw_specifics_map_t *map ); /** * @brief Full SPI Master module initialization procedure. @@ -176,7 +218,7 @@ static hal_ll_spi_master_hw_specifics_map_t *_hal_ll_get_specifics( handle_t han * Returns one of pre-defined values. * Take into consideration that this is hardware specific. */ -static void _hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ); +static void hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ); /** * @brief Initialize hardware SPI module. @@ -187,20 +229,7 @@ static void _hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ) * Returns one of pre-defined error values. * Take into consideration that this is hardware specific. */ -static void _hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map ); - -/** - * @brief Transfer function used in read and write bare metal. - * - * Performs a dummy read/write, and then the real transfer for - * read and write. - * - * @param[in] *hal_ll_hw_register - Registers defined - * in the program. - * @param[in] data_buffer - Data which is going to be tranfered. - * @return - None - */ -uint8_t _hal_ll_spi_master_transfer( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer ); +static void hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map ); /** * @brief Perform a write on the SPI Master bus. @@ -216,7 +245,9 @@ uint8_t _hal_ll_spi_master_transfer( hal_ll_spi_master_base_handle_t *hal_ll_hw_ * Returns one of pre-defined error values. * Take into consideration that this is hardware specific. */ -static void _hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data, size_t write_data_size ); +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, + uint8_t *read_data, + size_t write_data_size ); /** * @brief Perform a read on the SPI Master bus. @@ -230,8 +261,33 @@ static void _hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t * @param[in] dummy_data - Data required for read procedure. * @return hal_ll_err_t Module specific error values. */ -static void _hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data ); +static void hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, + uint8_t *read_data_buffer, + size_t read_data_length, + uint8_t dummy_data ); +/** + * @brief Perform a simultaneous write and read on the SPI Master bus. + * + * Function performs a full-duplex SPI transfer. Each written byte results in + * a received byte which is optionally stored in the read buffer. + * If the write buffer is NULL, the configured dummy byte will be transmitted. + * If the read buffer is NULL, the received data will be discarded. + * + * @param[in] *map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to write data buffer. + * If NULL, dummy data will be used. + * @param[out] *read_data_buffer - Pointer to read data buffer. + * If NULL, received data will be discarded. + * @param[in] data_length - Number of bytes to be transferred. + * + * @note TX FIFO is flushed and re-enabled on each byte transfer to ensure proper behavior. + * This implementation uses polling and is blocking. + */ +static void hal_ll_spi_master_transfer_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, + uint8_t *write_data_buffer, + uint8_t *read_data_buffer, + size_t data_length ); /** * @brief Sets SPI Master pin alternate function state. * @@ -243,35 +299,8 @@ static void _hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t * @param[in] *map - Object specific context handler. * @param[in] hal_ll_state - Init/De-init */ -static void _hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ); - -/** - * @brief Enables or disables SPI module 0 clock. - * @param hal_ll_state - True(enable clock)/False(disable clock). - * @return none - */ -static inline void _hal_ll_spi_master0_set_clock ( bool hal_ll_state ); - -/** - * @brief Enables or disables SPI module 1 clock. - * @param hal_ll_state - True(enable clock)/False(disable clock). - * @return none - */ -static inline void _hal_ll_spi_master1_set_clock ( bool hal_ll_state ); - -/** - * @brief Enables or disables SPI module 2 clock. - * @param hal_ll_state - True(enable clock)/False(disable clock). - * @return none - */ -static inline void _hal_ll_spi_master2_set_clock ( bool hal_ll_state ); - -/** - * @brief Enables or disables SPI module 3 clock. - * @param hal_ll_state - True(enable clock)/False(disable clock). - * @return none - */ -static inline void _hal_ll_spi_master3_set_clock ( bool hal_ll_state ); +static void hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_t *map, + bool hal_ll_state ); /** * @brief Maps new-found module specific values. @@ -284,29 +313,17 @@ static inline void _hal_ll_spi_master3_set_clock ( bool hal_ll_state ); * * @return None */ -static void _hal_ll_spi_master_map_pins( uint8_t module_index, hal_ll_spi_pin_id *index_list ); - -/** - * @brief Configures SPI mode. - * - * Sets adequate Clock Polarity and Clock Phase settings - * based on @mode parameter. - * - * @param[in] *hal_ll_hw_register - Registers defined - * in the program. - * @param[in] mode - User-defined SPI mode property. - * - * @return None - */ -static void _hal_ll_spi_master_mode_selection( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, hal_ll_spi_master_mode_t mode ); +static void hal_ll_spi_master_map_pins( uint8_t module_index, hal_ll_spi_pin_id *index_list ); // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS -hal_ll_err_t hal_ll_spi_master_register_handle( hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { +hal_ll_err_t hal_ll_spi_master_register_handle( hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, + hal_ll_spi_master_handle_register_t *handle_map, + uint8_t *hal_module_id ) { hal_ll_spi_pin_id index_list[ SPI_MODULE_COUNT ] = { HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC }; uint16_t pin_check_result; // Check user-defined pins. - if ( ( pin_check_result = _hal_ll_spi_master_check_pins( sck, miso, mosi, &index_list, handle_map ) ) == HAL_LL_PIN_NC ) { + if ( ( pin_check_result = hal_ll_spi_master_check_pins( sck, miso, mosi, &index_list, handle_map ) ) == HAL_LL_PIN_NC ) { return HAL_LL_SPI_MASTER_WRONG_PINS; }; @@ -316,11 +333,11 @@ hal_ll_err_t hal_ll_spi_master_register_handle( hal_ll_pin_name_t sck, hal_ll_pi ( hal_ll_spi_master_hw_specifics_map[ pin_check_result ].pins.miso.pin_name != miso ) || ( hal_ll_spi_master_hw_specifics_map[ pin_check_result ].pins.mosi.pin_name != mosi ) ) { - _hal_ll_spi_master_alternate_functions_set_state( &hal_ll_spi_master_hw_specifics_map[ pin_check_result ], false ); + hal_ll_spi_master_alternate_functions_set_state( &hal_ll_spi_master_hw_specifics_map[ pin_check_result ], false ); - _hal_ll_spi_master_map_pins( pin_check_result, &index_list ); + hal_ll_spi_master_map_pins( pin_check_result, &index_list ); - _hal_ll_spi_master_alternate_functions_set_state( &hal_ll_spi_master_hw_specifics_map[ pin_check_result ], true ); + hal_ll_spi_master_alternate_functions_set_state( &hal_ll_spi_master_hw_specifics_map[ pin_check_result ], true ); handle_map[ pin_check_result ].init_ll_state = false; } @@ -329,22 +346,25 @@ hal_ll_err_t hal_ll_spi_master_register_handle( hal_ll_pin_name_t sck, hal_ll_pi *hal_module_id = pin_check_result; // Insert current module into hal_ll_module_state map. - hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle = ( handle_t * )&hal_ll_spi_master_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle = + ( handle_t * )&hal_ll_spi_master_hw_specifics_map[ pin_check_result ].base; // Return the same info about module one level up ( into the HAL level ). - handle_map[ pin_check_result ].hal_ll_spi_master_handle = ( handle_t* )&hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle; + handle_map[ pin_check_result ].hal_ll_spi_master_handle = + ( handle_t* )&hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle; return HAL_LL_SPI_MASTER_SUCCESS; } hal_ll_err_t hal_ll_module_configure_spi( handle_t *handle ) { - hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; - _hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local ); + hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local ); - hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle = ( handle_t * )&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle = + ( handle_t * )&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; hal_ll_module_state[ pin_check_result ].init_ll_state = true; hal_handle->init_ll_state = true; @@ -353,7 +373,7 @@ hal_ll_err_t hal_ll_module_configure_spi( handle_t *handle ) { void hal_ll_spi_master_set_default_write_data( handle_t *handle, uint8_t dummy_data ) { // Get appropriate hw specifics map. - hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); if( hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; @@ -365,9 +385,11 @@ hal_ll_err_t hal_ll_spi_master_write( handle_t *handle, uint8_t *write_data_buff low_level_handle = hal_ll_spi_master_get_handle; // Get appropriate hw specifics map. - hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); - _hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data ); + hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, + write_data_buffer, + length_data ); return HAL_LL_SPI_MASTER_SUCCESS; } @@ -377,22 +399,55 @@ hal_ll_err_t hal_ll_spi_master_read( handle_t *handle, uint8_t *read_data_buffer low_level_handle = hal_ll_spi_master_get_handle; // Get appropriate hw specifics map. - hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, + read_data_buffer, length_data, + hal_ll_spi_master_hw_specifics_map_local->dummy_data ); - _hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data ); return HAL_LL_SPI_MASTER_SUCCESS; } -hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data ) { +hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, + uint8_t *write_data_buffer, + size_t length_write_data, + uint8_t *read_data_buffer, + size_t length_read_data ) { // Get low level HAL handle. low_level_handle = hal_ll_spi_master_get_handle; // Get appropriate hw specifics map. - hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); - _hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data ); + hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, + write_data_buffer, + length_write_data ); - _hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data ); + hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, + read_data_buffer, + length_read_data, + hal_ll_spi_master_hw_specifics_map_local->dummy_data ); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_transfer(handle_t *handle, + uint8_t *write_data_buffer, + uint8_t *read_data_buffer, + size_t data_length) { + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if (NULL == low_level_handle->hal_ll_spi_master_handle) { + return HAL_LL_SPI_MASTER_MODULE_ERROR; + } + + hal_ll_spi_master_transfer_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, + write_data_buffer, read_data_buffer, data_length ); + + if (!hal_ll_spi_master_hw_specifics_map_local || !data_length) { + return HAL_LL_SPI_MASTER_MODULE_ERROR; + } return HAL_LL_SPI_MASTER_SUCCESS; } @@ -402,7 +457,8 @@ uint32_t hal_ll_spi_master_set_speed( handle_t *handle, uint32_t speed ) { low_level_handle = hal_ll_spi_master_get_handle; // Get appropriate hw specifics map. - hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + hal_ll_spi_master_hw_specifics_map_local = + hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); low_level_handle->init_ll_state = false; @@ -410,7 +466,7 @@ uint32_t hal_ll_spi_master_set_speed( handle_t *handle, uint32_t speed ) { hal_ll_spi_master_hw_specifics_map_local->speed = speed; // Init once again, but with updated SPI Master baud rate value. - _hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local ); + hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local ); low_level_handle->init_ll_state = true; @@ -419,11 +475,12 @@ uint32_t hal_ll_spi_master_set_speed( handle_t *handle, uint32_t speed ) { } hal_ll_err_t hal_ll_spi_master_set_mode( handle_t *handle, hal_ll_spi_master_mode_t mode ) { - // Get low level HAL handle. + // Get low level HAL handle. low_level_handle = hal_ll_spi_master_get_handle; // Get appropriate hw specifics map. - hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + hal_ll_spi_master_hw_specifics_map_local = + hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); low_level_handle->init_ll_state = false; @@ -431,7 +488,7 @@ hal_ll_err_t hal_ll_spi_master_set_mode( handle_t *handle, hal_ll_spi_master_mod hal_ll_spi_master_hw_specifics_map_local->mode = mode; // Init once again, but with updated SPI Master mode value. - _hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local ); + hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local ); low_level_handle->init_ll_state = true; @@ -440,7 +497,8 @@ hal_ll_err_t hal_ll_spi_master_set_mode( handle_t *handle, hal_ll_spi_master_mod void hal_ll_spi_master_close( handle_t* handle ) { low_level_handle = hal_ll_spi_master_get_handle; - hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + hal_ll_spi_master_hw_specifics_map_local = + hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); if( low_level_handle->hal_ll_spi_master_handle != NULL ) { low_level_handle->hal_ll_spi_master_handle = NULL; @@ -449,13 +507,13 @@ void hal_ll_spi_master_close( handle_t* handle ) { low_level_handle->init_ll_state = false; hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; - // hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; - _hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_local, true ); - _hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_local, false ); - _hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_local, false ); + hal_ll_spi_master_module_enable( hal_ll_spi_master_hw_specifics_map_local, true ); + hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_local, false ); + hal_ll_spi_master_module_enable( hal_ll_spi_master_hw_specifics_map_local, false ); hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; @@ -467,65 +525,293 @@ void hal_ll_spi_master_close( handle_t* handle ) { } // ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, + uint8_t *write_data_buffer, size_t write_data_length ) { + while ( 0 < write_data_length-- ) { + // Wait until transmit buffer is empty + while ( !check_reg_bit( &hal_ll_hw_reg->spsr, HAL_LL_SPI_SPSR_SPTEF )); -static hal_ll_pin_name_t _hal_ll_spi_master_check_pins( hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ) { - return 0; -} + // Send byte from write buffer + write_reg( &hal_ll_hw_reg->spdr_by, ( uint8_t )( *write_data_buffer++ ) ); -static hal_ll_spi_master_hw_specifics_map_t *_hal_ll_get_specifics( handle_t handle ) { - return 0; + // Wait until receive is complete + while ( !check_reg_bit( &hal_ll_hw_reg->spsr, HAL_LL_SPI_SPSR_SPRF )); + + // Dummy read + volatile uint8_t temp = read_reg( &hal_ll_hw_reg->spdr_by ); + } } -static void _hal_ll_spi_master_map_pins( uint8_t module_index, hal_ll_spi_pin_id *index_list ) { +static void hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, + uint8_t *read_data_buffer, size_t read_data_length, + uint8_t dummy_data ) { + while ( 0 < read_data_length-- ) { + // Wait until transmit buffer is empty + while ( !check_reg_bit( &hal_ll_hw_reg->spsr, HAL_LL_SPI_SPSR_SPTEF )); -} + // Send dummy data + write_reg( &hal_ll_hw_reg->spdr_by, (uint8_t)(dummy_data)); -static void _hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ) { + // Wait until receive is complete + while ( !check_reg_bit( &hal_ll_hw_reg->spsr, HAL_LL_SPI_SPSR_SPRF )); + // Read received byte and store if read buffer is provided + *read_data_buffer++ = (uint8_t)read_reg( &hal_ll_hw_reg->spdr_by ); + } } -static void _hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ) { - +static void hal_ll_spi_master_transfer_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, + uint8_t *write_data_buffer, + uint8_t *read_data_buffer, + size_t data_length ) { + while ( 0 < data_length-- ) { + // Wait until transmit buffer is empty + while ( !check_reg_bit( &hal_ll_hw_reg->spsr, HAL_LL_SPI_SPSR_SPTEF )); + + // Send byte from write buffer or dummy if NULL + uint8_t tx_data = ( write_data_buffer ) ? *write_data_buffer++ : 0xFF; + write_reg( &hal_ll_hw_reg->spdr_by, tx_data ); + + // Wait until receive is complete + while ( !check_reg_bit( &hal_ll_hw_reg->spsr, HAL_LL_SPI_SPSR_SPRF )); + + // Read received byte and store if read buffer is provided + uint8_t rx_data = (uint8_t)read_reg( &hal_ll_hw_reg->spdr_by ); + if ( read_data_buffer ) { + *read_data_buffer++ = rx_data; + } + } } -static inline void _hal_ll_spi_master0_set_clock ( bool hal_ll_state ) { +static hal_ll_pin_name_t hal_ll_spi_master_check_pins( hal_ll_pin_name_t sck_pin, + hal_ll_pin_name_t miso_pin, + hal_ll_pin_name_t mosi_pin, + hal_ll_spi_pin_id *index_list, + hal_ll_spi_master_handle_register_t *handle_map ) { + static const uint16_t sck_map_size = + ( sizeof( hal_ll_spi_master_sck_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) ); + static const uint16_t miso_map_size = + ( sizeof( hal_ll_spi_master_miso_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) ); + static const uint16_t mosi_map_size = + ( sizeof( hal_ll_spi_master_mosi_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( ( HAL_LL_PIN_NC == sck_pin ) || ( HAL_LL_PIN_NC == miso_pin ) || ( HAL_LL_PIN_NC == mosi_pin ) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for ( sck_index = 0; sck_index < sck_map_size; sck_index++ ) { + if (hal_ll_spi_master_sck_map[ sck_index ].pin == sck_pin ) { + for ( miso_index = 0; miso_index < miso_map_size; miso_index++ ) { + if (hal_ll_spi_master_miso_map[ miso_index ].pin == miso_pin ) { + if (hal_ll_spi_master_sck_map[ sck_index ].module_index == + hal_ll_spi_master_miso_map[ miso_index ].module_index ) { + for ( mosi_index = 0; mosi_index < mosi_map_size; mosi_index++ ) { + if (hal_ll_spi_master_mosi_map[mosi_index ].pin == mosi_pin ) { + if (hal_ll_spi_master_sck_map[sck_index].module_index == + hal_ll_spi_master_mosi_map[ mosi_index ].module_index ) { + // Get module number + hal_ll_module_id =hal_ll_spi_master_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[ hal_ll_module_id ].pin_sck = sck_index; + index_list[ hal_ll_module_id ].pin_miso = miso_index; + index_list[ hal_ll_module_id ].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } } -static inline void _hal_ll_spi_master1_set_clock( bool hal_ll_state ) { +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_spi_master_handle_register_t ) ); -} + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_spi_master_handle_register_t ) ); -static inline void _hal_ll_spi_master2_set_clock( bool hal_ll_state ) { + while ( hal_ll_module_count-- ) { + if ( hal_ll_spi_master_get_base_from_hal_handle == + hal_ll_spi_master_hw_specifics_map[ hal_ll_module_count ].base ) { + return &hal_ll_spi_master_hw_specifics_map[ hal_ll_module_count ]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} +static void hal_ll_spi_master_map_pins( uint8_t module_index, hal_ll_spi_pin_id *index_list ) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.sck.pin_name = + hal_ll_spi_master_sck_map[ index_list[ module_index ].pin_sck ].pin; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.miso.pin_name = + hal_ll_spi_master_miso_map[ index_list[ module_index ].pin_miso ].pin; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.mosi.pin_name = + hal_ll_spi_master_mosi_map[ index_list[ module_index ].pin_mosi ].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.sck.pin_af = + hal_ll_spi_master_sck_map[ index_list[ module_index ].pin_sck ].af; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.miso.pin_af = + hal_ll_spi_master_miso_map[ index_list[ module_index ].pin_miso ].af; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.mosi.pin_af = + hal_ll_spi_master_mosi_map[ index_list[ module_index ].pin_mosi ].af; } -static inline void _hal_ll_spi_master3_set_clock( bool hal_ll_state ) { +static void hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_t *map, + bool hal_ll_state ) { + module_struct module; + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && + (map->pins.miso.pin_name != HAL_LL_PIN_NC) && + (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = GPIO_CFG_PORT_PULL_UP_ENABLE | GPIO_CFG_DIGITAL_OUTPUT | GPIO_CFG_PERIPHERAL_PIN; + module.configs[1] = GPIO_CFG_DIGITAL_INPUT | GPIO_CFG_PERIPHERAL_PIN; + module.configs[2] = GPIO_CFG_PORT_PULL_UP_ENABLE | GPIO_CFG_DIGITAL_OUTPUT | GPIO_CFG_PERIPHERAL_PIN; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } } -uint8_t _hal_ll_spi_master_transfer( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer ) { - return 0; +static void hal_ll_spi_master_module_enable( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ) { + if ( true == hal_ll_state ) { + switch ( map->module_index ) { + #ifdef SPI_MODULE_0 + case hal_ll_spi_master_module_num(SPI_MODULE_0): + clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB19_POS ); + break; + #endif + #ifdef SPI_MODULE_1 + case hal_ll_spi_master_module_num(SPI_MODULE_1): + clear_reg_bit( _MSTPCRB, MSTPCRB_MSTPB18_POS ); + break; + #endif + + default: + break; + } + } else { + switch ( map->module_index ) { + #ifdef SPI_MODULE_0 + case hal_ll_spi_master_module_num(SPI_MODULE_0): + set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB19_POS ); + break; + #endif + #ifdef SPI_MODULE_1 + case hal_ll_spi_master_module_num(SPI_MODULE_1): + set_reg_bit( _MSTPCRB, MSTPCRB_MSTPB18_POS ); + break; + #endif + + default: + break; + } + } } -static void _hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { +static void hal_ll_spi_master_set_bit_rate( hal_ll_spi_master_hw_specifics_map_t *map ) { + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + static const int mul_table[] = { 2, 4, 8, 16 }; + uint8_t spbr, mul; -} + system_clocks_t system_clocks; + SYSTEM_GetClocksFrequency( &system_clocks ); -static void _hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data ) { + uint8_t brdv = ( read_reg( &hal_ll_hw_reg->spcmd0 ) & HAL_LL_SPI_SPCMD0_BRDV_MASK ) >> HAL_LL_SPI_SPCMD0_BRDV; -} + mul = mul_table[brdv]; + + spbr = system_clocks.pclka / ( map->speed * mul ) - 1; -static void _hal_ll_spi_master_mode_selection( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, hal_ll_spi_master_mode_t mode ) { + write_reg( &hal_ll_hw_reg->spbr, spbr ); + // TODO: Add support for highest and lowest possible bit rates, as well as deviation calculation. } -static void _hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map ) { +static void hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map ) { + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Disable loopback mode; set MOSI output value. + clear_reg( &hal_ll_hw_reg->sppcr ); + + // Set the desired bit rate. + hal_ll_spi_master_set_bit_rate( map ); + + // Byte access is used for SPDR. + set_reg_bit( &hal_ll_hw_reg->spdcr, HAL_LL_SPI_SPDCR_SPBYT ); + clear_reg( &hal_ll_hw_reg->spckd ); // 1RSPCK delay + clear_reg( &hal_ll_hw_reg->sslnd ); // 1RSPCK delay + clear_reg( &hal_ll_hw_reg->spnd ); // 1RSPCK + 2PCLKA delay + + // Enable RSPCK auto-stop function. + set_reg_bit( &hal_ll_hw_reg->spcr2, HAL_LL_SPI_SPCR2_SCKASE ); + + // Use delays as defined in SPND, SSLND and SPCKD. + write_reg( &hal_ll_hw_reg->spcmd0, HAL_LL_SPI_SPCMD0_SPNDEN_MASK | + HAL_LL_SPI_SPCMD0_SLNDEN_MASK | + HAL_LL_SPI_SPCMD0_SCKDEN_MASK ); + + // 8 bit data length. + write_reg( &hal_ll_hw_reg->spcmd0, HAL_LL_SPI_SPCMD0_SPB_8BIT_MASK ); + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (HAL_LL_SPI_MASTER_MODE_1 >= map->mode ) { + clear_reg_bit( &hal_ll_hw_reg->spcmd0, HAL_LL_SPI_SPCMD0_CPOL ); + } else { + set_reg_bit(&( hal_ll_hw_reg->spcmd0), HAL_LL_SPI_SPCMD0_CPOL ); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if ( HAL_LL_SPI_MASTER_MODE_0 == map->mode || HAL_LL_SPI_MASTER_MODE_2 == map->mode ) { + clear_reg_bit( &hal_ll_hw_reg->spcmd0, HAL_LL_SPI_SPCMD0_CPHA ); + } else { + set_reg_bit( &hal_ll_hw_reg->spcmd0, HAL_LL_SPI_SPCMD0_CPHA ); + } + + // Enable SPI; Master mode + write_reg( &hal_ll_hw_reg->spcr, HAL_LL_SPI_SPCR_MSTR_MASK | HAL_LL_SPI_SPCR_SPE_MASK ); + + volatile uint8_t temp = read_reg( &hal_ll_hw_reg->spcr ); } -static void _hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ) { +static void hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ) { + + hal_ll_spi_master_module_enable( map, true ); + + hal_ll_spi_master_alternate_functions_set_state( map, true ); + hal_ll_spi_master_hw_init( map ); } // ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c index 5d1830e2d2..56fc3fb9ca 100644 --- a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c @@ -54,13 +54,6 @@ static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COU /*!< Register defs. */ #define HAL_LL_TIM_GTCR_CST (0) #define HAL_LL_TIM_GTCR_MD_MASK (0x70000UL) -#define HAL_LL_TIM_GTCR_TPCS_MASK (0x7000000UL) -#define HAL_LL_TIM_GTCR_TPCS_DIV_1 (0x0000000UL) -#define HAL_LL_TIM_GTCR_TPCS_DIV_4 (0x1000000UL) -#define HAL_LL_TIM_GTCR_TPCS_DIV_16 (0x2000000UL) -#define HAL_LL_TIM_GTCR_TPCS_DIV_64 (0x3000000UL) -#define HAL_LL_TIM_GTCR_TPCS_DIV_256 (0x4000000UL) -#define HAL_LL_TIM_GTCR_TPCS_DIV_1024 (0x5000000UL) #define HAL_LL_TIM_GTBER_PR_MASK (0x300000UL) #define HAL_LL_TIM_GTBER_PR_SINGLE_BUFFER (0x100000UL) @@ -78,8 +71,7 @@ static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COU #define HAL_LL_TIM_GTIOR_OAE (8) #define HAL_LL_TIM_GTIOR_OBE (24) - -#define HAL_LL_TIM_AF_CONFIG (GPIO_CFG_DIGITAL_OUTPUT | GPIO_CFG_PORT_PULL_UP_ENABLE) // TODO Esma +#define HAL_LL_TIM_AF_CONFIG (GPIO_CFG_DIGITAL_OUTPUT | GPIO_CFG_PORT_PULL_UP_ENABLE) /*!< @brief Helper macro for getting module specific control register structure */ #define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) @@ -98,44 +90,42 @@ static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COU /*!< @brief TIM register structure. */ typedef struct { - uint32_t gtwp; //00 - uint32_t gtstr; //04 - uint32_t gtstp; //08 - uint32_t gtclr; //0c - uint32_t gtssr; //10 - uint32_t gtpsr; //14 - uint32_t gtcsr; //18 - uint32_t gtupsr; //1c - uint32_t gtdnsr; //20 - uint32_t gticasr; //24 - uint32_t gticbsr; //28 - uint32_t gtcr; //2c - uint32_t gtuddtyc; //30 - uint32_t gtior; //34 - uint32_t gtintad; //38 - uint32_t gtst; //3c - uint32_t gtber; //40 - uint32_t gtitc; //44 - uint32_t gtcnt; //48 - uint32_t gtccr[6]; //4c 50 54 58 5c 60 - uint32_t gtpr; // 64 - uint32_t gtpbr; //68 - uint32_t gtpdbr; //6c - uint32_t gtadtra; //70 - uint32_t gtadtbra; //74 - uint32_t gtadtdbra; //78 - uint32_t gtadtrb; //80 - uint32_t gtadtbrb; //84 - uint32_t gtdtcr; //88 - uint32_t gtdvu; //8c - // uint32_t opscr; etc + uint32_t gtwp; + uint32_t gtstr; + uint32_t gtstp; + uint32_t gtclr; + uint32_t gtssr; + uint32_t gtpsr; + uint32_t gtcsr; + uint32_t gtupsr; + uint32_t gtdnsr; + uint32_t gticasr; + uint32_t gticbsr; + uint32_t gtcr; + uint32_t gtuddtyc; + uint32_t gtior; + uint32_t gtintad; + uint32_t gtst; + uint32_t gtber; + uint32_t gtitc; + uint32_t gtcnt; + uint32_t gtccr[6]; + uint32_t gtpr; + uint32_t gtpbr; + uint32_t gtpdbr; + uint32_t gtadtra; + uint32_t gtadtbra; + uint32_t gtadtdbra; + uint32_t gtadtrb; + uint32_t gtadtbrb; + uint32_t gtdtcr; + uint32_t gtdvu; } hal_ll_tim_base_handle_t; /*!< @brief TIM pin structure */ typedef struct { hal_ll_pin_name_t pin; - // hal_ll_channel_t channel; hal_ll_tim_pin_type_t pin_type; uint32_t af; } hal_ll_tim_t; @@ -262,7 +252,8 @@ static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); * Returns pre-defined module index from pin maps, if pin * is adequate. */ -static hal_ll_pin_name_t hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); +static hal_ll_pin_name_t hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, + hal_ll_tim_handle_register_t *handle_map ); /** * @brief Maps new-found module specific values. @@ -485,7 +476,7 @@ static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { } static void hal_ll_tim_module_enable( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { - if ( true == hal_ll_state) { + if ( true == hal_ll_state ) { switch ( map->module_index ) { case hal_ll_tim_module_num(TIM_MODULE_0): case hal_ll_tim_module_num(TIM_MODULE_1): @@ -573,15 +564,16 @@ static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); hal_ll_tim_pin_type_t pin_type = map->config.pin_type; + hal_ll_tim_module_enable( map, true ); + clear_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST ); // Stop operation first. clear_reg_bits( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_MD_MASK ); // PWM mode. set_reg_bit( &hal_ll_hw_reg->gtuddtyc, HAL_LL_TIM_GTUDDTYC_UD ); // Count up. clear_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_PR_MASK ); set_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_PR_SINGLE_BUFFER ); // Single buffer operation. - // .... // freq settings + // Frequency settings hal_ll_tim_set_freq_bare_metal( map ); - // .... // freq settings clear_reg( &hal_ll_hw_reg->gtcnt ); @@ -606,7 +598,7 @@ static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { static void hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { - hal_ll_tim_module_enable( map, true ); + hal_ll_tim_module_enable( map->base, true ); hal_ll_tim_alternate_functions_set_state( map, true ); From 27130683462ddd4d196b85a4fa3ada089a227309 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 30 Jul 2025 10:50:36 +0200 Subject: [PATCH 38/62] I2C updated, ready for review --- .../i2c/implementation_1/hal_ll_i2c_master.c | 277 ++++++++++++------ 1 file changed, 195 insertions(+), 82 deletions(-) diff --git a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c index 480506b4b6..27688f47c8 100644 --- a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c @@ -60,7 +60,10 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU #define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base -#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_PORT_PULL_UP_ENABLE | GPIO_CFG_DIGITAL_OUTPUT | GPIO_CFG_NMOS_OPEN_DRAIN_ENABLE) // TODO Esma +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_PORT_PULL_UP_ENABLE |\ + GPIO_CFG_DIGITAL_OUTPUT |\ + GPIO_CFG_NMOS_OPEN_DRAIN_ENABLE |\ + GPIO_CFG_PERIPHERAL_PIN) /*!< @brief Bit positions and masks */ #define HAL_LL_I2C_ICCR1_IICRST (6) @@ -78,6 +81,15 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU #define HAL_LL_I2C_ICMR3_ACKWP (4) #define HAL_LL_I2C_ICFER_SCLE (6) #define HAL_LL_I2C_ICFER_NFE (5) +#define HAL_LL_I2C_ICMR1_CKS (4) +#define HAL_LL_I2C_ICMR1_CKS_DIV_1 (0) +#define HAL_LL_I2C_ICMR1_CKS_DIV_2 (1) +#define HAL_LL_I2C_ICMR1_CKS_DIV_4 (2) +#define HAL_LL_I2C_ICMR1_CKS_DIV_8 (3) +#define HAL_LL_I2C_ICMR1_CKS_DIV_16 (4) +#define HAL_LL_I2C_ICMR1_CKS_DIV_32 (5) +#define HAL_LL_I2C_ICMR1_CKS_DIV_64 (6) +#define HAL_LL_I2C_ICMR1_CKS_DIV_128 (7) /*!< @brief Default I2C bit-rate if no speed is set */ #define HAL_LL_I2C_MASTER_SPEED_100K (100000UL) @@ -89,26 +101,25 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU /*!< @brief I2C register structure */ typedef struct { - uint8_t iccr1; // IIC0.ICCR1 4005 3000h, IIC1.ICCR1 4005 3100h - uint8_t iccr2; // IIC0.ICCR2 4005 3001h, IIC1.ICCR2 4005 3101h - uint8_t icmr1; // IIC0.ICCR2 4005 3002h, IIC1.ICCR2 4005 3102h - uint8_t icmr2; // IIC0.ICCR2 4005 3003h, IIC1.ICCR2 4005 3103h - uint8_t icmr3; // IIC0.ICCR2 4005 3004h, IIC1.ICCR2 4005 3104h - uint8_t icfer; // IIC0.ICCR2 4005 3005h, IIC1.ICCR2 4005 3105h - uint8_t icser; // IIC0.ICCR2 4005 3006h, IIC1.ICCR2 4005 3106h - uint8_t icier; // IIC0.ICCR2 4005 3007h, IIC1.ICCR2 4005 3107h - uint8_t icsr1; // IIC0.ICCR2 4005 3008h, IIC1.ICCR2 4005 3108h - uint8_t icsr2; // IIC0.ICCR2 4005 3009h, IIC1.ICCR2 4005 3109h - uint8_t sarl[3]; // ? - uint8_t saru[3]; // ? - uint8_t icbrl; // IIC0.ICCR2 4005 3010h, IIC1.ICCR2 4005 3110h - uint8_t icbrh; // IIC0.ICCR2 4005 3011h, IIC1.ICCR2 4005 3111h - uint8_t icdrt; // IIC0.ICCR2 4005 3012h, IIC1.ICCR2 4005 3112h - uint8_t icdrr; // IIC0.ICCR2 4005 3013h, IIC1.ICCR2 4005 3113h - // uint8_t icdrs; // ? + uint8_t iccr1; + uint8_t iccr2; + uint8_t icmr1; + uint8_t icmr2; + uint8_t icmr3; + uint8_t icfer; + uint8_t icser; + uint8_t icier; + uint8_t icsr1; + uint8_t icsr2; + uint8_t sarl[3]; + uint8_t saru[3]; + uint8_t icbrl; + uint8_t icbrh; + uint8_t icdrt; + uint8_t icdrr; uint8_t reserved[2]; - uint8_t icwur; // IIC0.ICCR2 4005 3016h // ? , IIC1.ICCR2 4005 3109h - uint8_t icwur2; // IIC0.ICCR2 4005 3017h // ? , IIC1.ICCR2 4005 3109h + uint8_t icwur; + uint8_t icwur2; } hal_ll_i2c_base_handle_t; /*!< @brief I2C hw specific structure */ @@ -164,34 +175,12 @@ typedef enum { // ------------------------------------------------------------------ VARIABLES static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[ I2C_MODULE_COUNT + 1 ] = { #ifdef I2C_MODULE_0 - {0x40053000UL, hal_ll_i2c_module_num( I2C_MODULE_0 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + {0x40053000UL, hal_ll_i2c_module_num( I2C_MODULE_0 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, + HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, #endif #ifdef I2C_MODULE_1 - {0x40053100UL, hal_ll_i2c_module_num( I2C_MODULE_1 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, - #endif - #ifdef I2C_MODULE_2 - {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_2 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, - #endif - #ifdef I2C_MODULE_3 - {HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_3 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, - #endif - #ifdef I2C_MODULE_4 - {HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_4 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, - #endif - #ifdef I2C_MODULE_5 - {HAL_LL_I2C5_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_5 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, - #endif - #ifdef I2C_MODULE_6 - {HAL_LL_I2C6_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_6 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, - #endif - #ifdef I2C_MODULE_7 - {HAL_LL_I2C7_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_7 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, - #endif - #ifdef I2C_MODULE_8 - {HAL_LL_I2C8_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_8 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, - #endif - #ifdef I2C_MODULE_9 - {HAL_LL_I2C9_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_9 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + {0x40053100UL, hal_ll_i2c_module_num( I2C_MODULE_1 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, + HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, #endif {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} @@ -217,9 +206,6 @@ static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local */ static void hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); -// TODO Esma -static void hal_ll_i2c_calculate_speed( hal_ll_i2c_hw_specifics_map_t *map, uint32_t clock_value ); - /** * @brief Full I2C module initialization procedure. * @@ -329,6 +315,18 @@ static hal_ll_err_t hal_ll_i2c_master_wait_for_idle( hal_ll_i2c_hw_specifics_map */ static uint32_t hal_ll_i2c_get_speed( uint32_t bit_rate ); +/** + * @brief Set I2C speed registers based on clock and bit rate. + * + * Sets ICMR1, ICBRL, and ICBRH values based on the PCLKB clock + * and desired I2C speed (100kHz, 400kHz, or 1MHz). + * + * @param[in] *map - I2C hardware context. + * + * @note Supports only 24MHz and 32MHz PCLKB. + */ +static void hal_ll_i2c_calculate_speed( hal_ll_i2c_hw_specifics_map_t *map ); + /** * @brief Perform a read on the I2C bus. * @@ -345,7 +343,8 @@ static uint32_t hal_ll_i2c_get_speed( uint32_t bit_rate ); */ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, - size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + size_t len_read_data, + hal_ll_i2c_master_end_mode_t mode ); /** * @brief Perform a write on the I2C bus. @@ -363,7 +362,8 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m */ static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, - size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + size_t len_write_data, + hal_ll_i2c_master_end_mode_t mode ); // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, @@ -532,31 +532,60 @@ static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_ set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_ST ); - while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )); + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } write_reg( &hal_ll_hw_reg->icdrt, map->address << 1 ); - while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )); + time_counter = map->timeout; + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } if( check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_NACKF )) set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_SP ); + time_counter = map->timeout; for( uint8_t i = 0; i < len_write_data; i++ ) { - while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )); + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } write_reg( &hal_ll_hw_reg->icdrt, write_data_buf[i] ); } - while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TEND )); + time_counter = map->timeout; + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TEND )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_SP ); - while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP )); + time_counter = map->timeout; + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } set_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_NACKF ); clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); - return HAL_LL_I2C_MASTER_SUCCESS; // TODO ESMA: add timeout and returning errors + return HAL_LL_I2C_MASTER_SUCCESS; } static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, @@ -571,12 +600,24 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_ST ); - while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )); + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_TDRE )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } write_reg( &hal_ll_hw_reg->icdrt, ( map->address << 1 ) | 1 ); - while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )); + time_counter = map->timeout; + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + time_counter = map->timeout; if( check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_NACKF )) { // Error clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); @@ -587,7 +628,12 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m if( 1 != len_read_data ) { for( uint8_t i = 0; i < len_read_data - 2; i++ ) { read_data_buf[i] = read_reg( &hal_ll_hw_reg->icdrr ); - while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )); + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } } } @@ -597,7 +643,13 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m read_data_buf[len_read_data - 2] = read_reg( &hal_ll_hw_reg->icdrr ); - while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )); + time_counter = map->timeout; + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_SP ); @@ -606,7 +658,13 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m clear_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_WAIT ); } - while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP )); + time_counter = map->timeout; + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_NACKF ); clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); @@ -614,7 +672,8 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m return HAL_LL_I2C_MASTER_SUCCESS; } -static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, + bool hal_ll_state ) { module_struct module; if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { @@ -622,8 +681,8 @@ static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_speci module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); module.pins[2] = GPIO_MODULE_STRUCT_END; - module.configs[0] = HAL_LL_I2C_AF_CONFIG; // TODO - module.configs[1] = HAL_LL_I2C_AF_CONFIG; // TODO + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; module.configs[2] = GPIO_MODULE_STRUCT_END; hal_ll_gpio_module_struct_init( &module, hal_ll_state ); @@ -669,11 +728,14 @@ static uint32_t hal_ll_i2c_get_speed( uint32_t bit_rate ) { } static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { - uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / (sizeof( hal_ll_i2c_master_handle_register_t )); - static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_i2c_master_handle_register_t)); + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / + (sizeof( hal_ll_i2c_master_handle_register_t )); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / + (sizeof( hal_ll_i2c_master_handle_register_t)); while( hal_ll_module_count-- ) { - if ( hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[ hal_ll_module_count ].base ) { + if ( hal_ll_i2c_get_base_from_hal_handle == + hal_ll_i2c_hw_specifics_map[ hal_ll_module_count ].base ) { return &hal_ll_i2c_hw_specifics_map[ hal_ll_module_count ]; } } @@ -685,8 +747,10 @@ static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { - static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); - static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t scl_map_size = + ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = + ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); uint8_t hal_ll_module_id = 0; uint8_t index_counter = 0; uint16_t scl_index; @@ -700,7 +764,8 @@ static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { - if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == + hal_ll_i2c_sda_map[ sda_index ].module_index ) { // Get module number hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; // Map pin names @@ -728,21 +793,72 @@ static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, static hal_ll_err_t hal_ll_i2c_master_wait_for_idle( hal_ll_i2c_hw_specifics_map_t *map ) { hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + uint16_t time_counter = map->timeout; - while( check_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_BBSY )); + while( check_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_BBSY )) { + if( map->timeout ) { + if( !time_counter-- ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE; + } + } + } - return 0; + return HAL_LL_I2C_MASTER_SUCCESS; } -static void hal_ll_i2c_calculate_speed( hal_ll_i2c_hw_specifics_map_t *map, uint32_t clock_value ) { +static void hal_ll_i2c_calculate_speed( hal_ll_i2c_hw_specifics_map_t *map ) { hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); - // 32MHz on PCLKB, 100kbps I2C - write_reg( &hal_ll_hw_reg->icmr1, 0x3 << 4 ); + system_clocks_t system_clocks; + SYSTEM_GetClocksFrequency( &system_clocks ); + + uint32_t i2c_source_clock = system_clocks.pclkb; + set_reg_bit( &hal_ll_hw_reg->icfer, HAL_LL_I2C_ICFER_SCLE ); set_reg_bit( &hal_ll_hw_reg->icfer, HAL_LL_I2C_ICFER_NFE ); - write_reg( &hal_ll_hw_reg->icbrl, 0xF2 ); - write_reg( &hal_ll_hw_reg->icbrh, 0xF0 ); + + // TODO: Add bit rate calculation based on the formulas. + if ( 32000000 == i2c_source_clock ) { + if ( HAL_LL_I2C_MASTER_SPEED_1M == map->speed ) { + // 32MHz on PCLKB, 1Mbps I2C + write_reg( &hal_ll_hw_reg->icmr1, + ( HAL_LL_I2C_ICMR1_CKS_DIV_2 << HAL_LL_I2C_ICMR1_CKS )); + write_reg( &hal_ll_hw_reg->icbrl, 0xE3 ); + write_reg( &hal_ll_hw_reg->icbrh, 0xE4 ); + } else if ( HAL_LL_I2C_MASTER_SPEED_400K == map->speed ) { + // 32MHz on PCLKB, 400kbps I2C + write_reg( &hal_ll_hw_reg->icmr1, + ( HAL_LL_I2C_ICMR1_CKS_DIV_2 << HAL_LL_I2C_ICMR1_CKS )); + write_reg( &hal_ll_hw_reg->icbrl, 0xF0 ); + write_reg( &hal_ll_hw_reg->icbrh, 0xEF ); + } else { + // 32MHz on PCLKB, 100kbps I2C + write_reg( &hal_ll_hw_reg->icmr1, + ( HAL_LL_I2C_ICMR1_CKS_DIV_8 << HAL_LL_I2C_ICMR1_CKS )); + write_reg( &hal_ll_hw_reg->icbrl, 0xF2 ); + write_reg( &hal_ll_hw_reg->icbrh, 0xF0 ); + } + } else if ( 24000000 == i2c_source_clock ) { + if ( HAL_LL_I2C_MASTER_SPEED_1M == map->speed ) { + // 24MHz on PCLKB, 1Mbps I2C + write_reg( &hal_ll_hw_reg->icmr1, + ( HAL_LL_I2C_ICMR1_CKS_DIV_2 << HAL_LL_I2C_ICMR1_CKS )); + write_reg( &hal_ll_hw_reg->icbrl, 0xE2 ); + write_reg( &hal_ll_hw_reg->icbrh, 0xE2 ); + } else if ( HAL_LL_I2C_MASTER_SPEED_400K == map->speed ) { + // 24MHz on PCLKB, 400kbps I2C + write_reg( &hal_ll_hw_reg->icmr1, + ( HAL_LL_I2C_ICMR1_CKS_DIV_2 << HAL_LL_I2C_ICMR1_CKS )); + write_reg( &hal_ll_hw_reg->icbrl, 0xEA ); + write_reg( &hal_ll_hw_reg->icbrh, 0xEB ); + } else { + // 24MHz on PCLKB, 100kbps I2C + write_reg( &hal_ll_hw_reg->icmr1, + ( HAL_LL_I2C_ICMR1_CKS_DIV_4 << HAL_LL_I2C_ICMR1_CKS )); + write_reg( &hal_ll_hw_reg->icbrl, 0xFA ); + write_reg( &hal_ll_hw_reg->icbrh, 0xFB ); + } + } } static void hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { @@ -761,7 +877,6 @@ static void hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { static void hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); - uint32_t clock_value; // TODO Esma get source clock value // Enable IIC peripheral if( hal_ll_i2c_module_num( I2C_MODULE_0 ) == map->module_index ) @@ -771,13 +886,11 @@ static void hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { hal_ll_i2c_hw_init( map ); - hal_ll_i2c_calculate_speed( map, clock_value ); + hal_ll_i2c_calculate_speed( map ); // When the required register settings are complete, // set the ICCR1.IICRST bit to 0 to release the IIC reset. clear_reg_bit( &hal_ll_hw_reg->iccr1, HAL_LL_I2C_ICCR1_IICRST ); - - return; } // ------------------------------------------------------------------------- END From 39f935f65c1922c4a2c3cc2505eb3e9457f2db93 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 30 Jul 2025 10:51:18 +0200 Subject: [PATCH 39/62] comment fix --- .../mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c index 27688f47c8..7ee437d008 100644 --- a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c @@ -867,7 +867,7 @@ static void hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { // I2C initialization // Set the ICCR1.ICE bit set to 0 to set the SCLn and SDAn pins to the inactive state. clear_reg_bit( &hal_ll_hw_reg->iccr1, HAL_LL_I2C_ICCR1_ICE ); - // Set the ICCR1.IICRST bit to 1 to initiate IIC reset + // Set the ICCR1.IICRST bit to 1 to initiate IIC reset. set_reg_bit( &hal_ll_hw_reg->iccr1, HAL_LL_I2C_ICCR1_IICRST ); // Set the ICCR1.ICE bit to 1 to initiate internal reset. set_reg_bit( &hal_ll_hw_reg->iccr1, HAL_LL_I2C_ICCR1_ICE ); From 20ec401e6b552ae7e1d36c381357989a6a36f592 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 30 Jul 2025 11:52:00 +0200 Subject: [PATCH 40/62] PWM implementation improved, ready for review --- .../src/tim/implementation_1/hal_ll_tim.c | 149 +++++++++--------- 1 file changed, 71 insertions(+), 78 deletions(-) diff --git a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c index 56fc3fb9ca..57bf1e952e 100644 --- a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c @@ -45,7 +45,6 @@ #include "hal_ll_tim.h" #include "hal_ll_tim_pin_map.h" #include "hal_ll_mstpcr.h" -#include "mcu.h" /*!< @brief Local handle list */ static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; @@ -169,6 +168,15 @@ static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = #ifdef TIM_MODULE_4 {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_4)}, #endif + #ifdef TIM_MODULE_5 + {HAL_LL_TIM5_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM_MODULE_6 + {HAL_LL_TIM6_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_6)}, + #endif + #ifdef TIM_MODULE_7 + {HAL_LL_TIM7_BASE_ADDR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_7)}, + #endif {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} }; @@ -192,15 +200,6 @@ static void hal_ll_tim_module_enable( hal_ll_tim_hw_specifics_map_t *map, bool h */ static uint32_t hal_ll_tim_clock_source(); -/** - * @brief Based on selected TIM, - * return clock speed. - * @param base - TIM module base - * address - * @return uint32_t clock source. - */ -static uint32_t hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); - /** * @brief Initialize TIM module on hardware level. * @@ -208,10 +207,10 @@ static uint32_t hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); * set configuration and module handler. * * @param map - Object specific context handler. - * @return none + * @return uint32_t - Set period. * */ -static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); +static uint32_t hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); /** * @brief Full TIM module initialization procedure. @@ -221,10 +220,10 @@ static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); * Initializes module clock. * * @param map - Object specific context handler. - * @return none + * @return uint32_t - Set period. * */ -static void hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); +static uint32_t hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); /** * @brief Get local hardware specific map. @@ -282,10 +281,20 @@ static void hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); * @return none * */ -static void hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); +static void hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, + bool hal_ll_state ); -// TODO -static void hal_ll_tim_set_freq_bare_metal( hal_ll_tim_hw_specifics_map_t *map ); +/** + * @brief Set TIM frequency register values. + * + * Calculates and writes values to the period registers + * based on the peripheral clock and desired frequency. + * + * @param[in] map - Object specific context handler. + * @return uint32_t - Set period + * + */ +static uint32_t hal_ll_tim_set_freq_bare_metal( hal_ll_tim_hw_specifics_map_t *map ); // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, @@ -312,9 +321,11 @@ hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handl *hal_module_id = pin_check_result; - hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = + ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; - handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + handle_map[ pin_check_result ].hal_ll_tim_handle = + ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; return HAL_LL_TIM_SUCCESS; } @@ -326,7 +337,8 @@ hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); - hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = + (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; hal_ll_module_state[ pin_check_result ].init_ll_state = true; hal_handle->init_ll_state = true; @@ -338,19 +350,20 @@ uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { low_level_handle = hal_ll_tim_get_handle; hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + uint32_t period; low_level_handle->init_ll_state = false; hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; - hal_ll_tim_init(hal_ll_tim_hw_specifics_map_local); + period = hal_ll_tim_init(hal_ll_tim_hw_specifics_map_local); low_level_handle->init_ll_state = true; // Memorize information about the max period available (PWM duty cycle is dependant of this information). - return ( hal_ll_tim_hw_specifics_map_local->max_period = local_freq ); // TODO Esma + return ( hal_ll_tim_hw_specifics_map_local->max_period = period ); } -uint32_t read; + hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { low_level_handle = hal_ll_tim_get_handle; hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); @@ -362,10 +375,10 @@ hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { if ( check_reg_bit( &hal_ll_hw_reg->gtcr, HAL_LL_TIM_GTCR_CST )) { write_reg( &hal_ll_hw_reg->gtccr[(HAL_LL_TIM_PIN_A == pin_type) ? 2 : 3], - (( uint32_t )( pclkd / hal_ll_tim_hw_specifics_map_local->freq_hz ) * duty_ratio - 1) ); + (( uint32_t )( hal_ll_tim_hw_specifics_map_local->max_period + 1 ) * duty_ratio - 1 ) ); } else { write_reg( &hal_ll_hw_reg->gtccr[(HAL_LL_TIM_PIN_A == pin_type) ? 0 : 1], - (( uint32_t )( pclkd / hal_ll_tim_hw_specifics_map_local->freq_hz ) * duty_ratio - 1) ); + (( uint32_t )( hal_ll_tim_hw_specifics_map_local->max_period + 1 ) * duty_ratio - 1 ) ); if( HAL_LL_TIM_PIN_A == pin_type ) { write_reg( &hal_ll_hw_reg->gtccr[2], read_reg( &hal_ll_hw_reg->gtccr[0] )); @@ -477,37 +490,16 @@ static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { static void hal_ll_tim_module_enable( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { if ( true == hal_ll_state ) { - switch ( map->module_index ) { - case hal_ll_tim_module_num(TIM_MODULE_0): - case hal_ll_tim_module_num(TIM_MODULE_1): - clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD5_POS ); - break; - case hal_ll_tim_module_num(TIM_MODULE_2): - case hal_ll_tim_module_num(TIM_MODULE_3): - case hal_ll_tim_module_num(TIM_MODULE_4): - clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD6_POS ); - break; - - default: - break; - } + if ( 1 >= map->module_index ) + clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD5_POS ); + else if ( 7 >= map->module_index ) + clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD6_POS ); } else { - switch ( map->module_index ) { - case hal_ll_tim_module_num(TIM_MODULE_0): - case hal_ll_tim_module_num(TIM_MODULE_1): - set_reg_bit( _MSTPCRD, MSTPCRD_MSTPD5_POS ); - break; - case hal_ll_tim_module_num(TIM_MODULE_2): - case hal_ll_tim_module_num(TIM_MODULE_3): - case hal_ll_tim_module_num(TIM_MODULE_4): - set_reg_bit( _MSTPCRD, MSTPCRD_MSTPD6_POS ); - break; - - default: - break; - } + if ( 1 >= map->module_index ) + set_reg_bit( _MSTPCRD, MSTPCRD_MSTPD5_POS ); + else if ( 7 >= map->module_index ) + set_reg_bit( _MSTPCRD, MSTPCRD_MSTPD6_POS ); } - } static uint32_t hal_ll_tim_clock_source() { @@ -518,11 +510,6 @@ static uint32_t hal_ll_tim_clock_source() { return system_clocks.pclkd; } -static uint32_t hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { - - return 0; -} - static void hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { // Map new pin. hal_ll_tim_hw_specifics_map[ module_index ].config.pin = hal_ll_tim_pin_map[ index ].pin; @@ -532,37 +519,41 @@ static void hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { static void hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { module_struct module; - uint32_t tim_config = 0; if( map->config.pin != HAL_LL_PIN_NC ) { - if( hal_ll_state == false ) { - tim_config = 0; // TODO Esma - } else { - tim_config = HAL_LL_TIM_AF_CONFIG; - } - module.pins[0] = VALUE( map->config.pin, map->config.af ); module.pins[1] = GPIO_MODULE_STRUCT_END; - module.configs[0] = tim_config; + module.configs[0] = HAL_LL_TIM_AF_CONFIG; module.configs[1] = GPIO_MODULE_STRUCT_END; hal_ll_gpio_module_struct_init( &module, hal_ll_state ); } } -static void hal_ll_tim_set_freq_bare_metal( hal_ll_tim_hw_specifics_map_t *map ) { +static uint32_t hal_ll_tim_set_freq_bare_metal( hal_ll_tim_hw_specifics_map_t *map ) { hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + uint32_t period; uint32_t pclkd = hal_ll_tim_clock_source(); - write_reg( &hal_ll_hw_reg->gtpr, pclkd / map->freq_hz - 1 ); - write_reg( &hal_ll_hw_reg->gtpbr, pclkd / map->freq_hz - 1 ); + period = pclkd / map->freq_hz - 1; + + // When using modules GPT2 - GPT7, the minimum possible frequency with PCKLD = 48MHz is ~732Hz. + if ( 7 >= map->module_index && 1 < map->module_index ) + if ( 0xFFFF < period ) + period = 0xFFFF; + + write_reg( &hal_ll_hw_reg->gtpr, ( uint32_t ) period ); + write_reg( &hal_ll_hw_reg->gtpbr, ( uint32_t ) period ); + + return period; } -static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { +static uint32_t hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); hal_ll_tim_pin_type_t pin_type = map->config.pin_type; + uint32_t period; hal_ll_tim_module_enable( map, true ); @@ -573,35 +564,37 @@ static void hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { set_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_PR_SINGLE_BUFFER ); // Single buffer operation. // Frequency settings - hal_ll_tim_set_freq_bare_metal( map ); + period = hal_ll_tim_set_freq_bare_metal( map ); clear_reg( &hal_ll_hw_reg->gtcnt ); if( HAL_LL_TIM_PIN_A == map->config.pin_type ) { // A - // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end) + // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end). clear_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOA_MASK ); set_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOA_9 ); - set_reg_bit( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_OAE ); // Enable GTIOC pin output + set_reg_bit( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_OAE ); // Enable GTIOC pin output. clear_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRA_MASK ); set_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRA_SINGLE_BUFFER ); } else { // B - // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end) + // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end). clear_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOB_MASK ); set_reg_bits( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_GTIOB_9 ); - set_reg_bit( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_OBE ); // Enable GTIOC pin output + set_reg_bit( &hal_ll_hw_reg->gtior, HAL_LL_TIM_GTIOR_OBE ); // Enable GTIOC pin output. clear_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRB_MASK ); set_reg_bits( &hal_ll_hw_reg->gtber, HAL_LL_TIM_GTBER_CCRB_SINGLE_BUFFER ); } + + return period; } -static void hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { +static uint32_t hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { hal_ll_tim_module_enable( map->base, true ); hal_ll_tim_alternate_functions_set_state( map, true ); - hal_ll_tim_hw_init( map ); + return hal_ll_tim_hw_init( map ); } // ------------------------------------------------------------------------- END From 763395bdfd623ab7e321b53c6b39f046f4ffd6ed Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 30 Jul 2025 12:05:21 +0200 Subject: [PATCH 41/62] Initial changelog added --- changelog/v2.15.0/changelog.md | 65 ++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 changelog/v2.15.0/changelog.md diff --git a/changelog/v2.15.0/changelog.md b/changelog/v2.15.0/changelog.md new file mode 100644 index 0000000000..4a058cda45 --- /dev/null +++ b/changelog/v2.15.0/changelog.md @@ -0,0 +1,65 @@ +

+ MikroElektronika +

+ +--- + +**[BACK TO MAIN FILE](../../changelog.md)** + +--- + +# `v2.15.0` + ++ released: 2025-08-07 + +## Changes + +- [`v2.15.0`](#v2150) + - [Changes](#changes) + - [RENESAS](#renesas) + - [Fixes](#fixes) + - [mikroSDK](#mikrosdk) + - [NEW HARDWARE](#new-hardware) + +### RENESAS + +**RA4M1 MCUs supported!** + +| MCU | +| :------------: | +| R7FA4M1AB3CFP | +| R7FA4M1AB2CLJ | +| R7FA4M1AB3CFM | +| R7FA4M1AB3CNB | +| R7FA4M1AB3CFL | +| R7FA4M1AB3CNE | +| R7FA4M1AB3CNF | + +**Supported modules:** + ++ ADC (Full module support) ++ SPI (Full module support) ++ UART (Full module support) ++ I2C (Full module support) ++ PWM (Full module support) ++ GPIO (Full module support) ++ OW (Full module support) + +### Fixes + +#### mikroSDK + ++ TODO + +### NEW HARDWARE + +> NOTE: +>> If any new hardware was added to current version, it will be listed here. + +Support added for following hardware: + +--- + +**[BACK TO MAIN FILE](../../changelog.md)** + +--- From cba99aa19beec9e5e29b9ef77086337f07fbab22 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 30 Jul 2025 14:12:40 +0200 Subject: [PATCH 42/62] ADC improved --- .../src/adc/implementation_1/hal_ll_adc.c | 57 ++++++++++--------- 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c index 51d754136a..7e38a05a2c 100644 --- a/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c +++ b/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c @@ -45,7 +45,6 @@ #include "hal_ll_gpio.h" #include "hal_ll_adc_pin_map.h" #include "hal_ll_mstpcr.h" -#include "mcu.h" // ------------------------------------------------------------- PRIVATE MACROS @@ -72,7 +71,7 @@ #define HAL_LL_ADC0_ADHVREFCNT_HVSEL_VREFH0 (0x1UL) #define HAL_LL_ADC0_ADHVREFCNT_HVSEL_INTERNAL (0x2UL) -#define HAL_LL_ADC0_ADHVREFCNT_REG_ADDR ( uint8_t * )0x4005C08AUL +#define HAL_LL_ADC0_ADHVREFCNT_REG_ADDR ((uint8_t *)0x4005C08AUL) // -------------------------------------------------------------- PRIVATE TYPES /*!< @brief Local handle list. */ @@ -80,23 +79,23 @@ static hal_ll_adc_handle_register_t hal_ll_module_state[ ADC_MODULE_COUNT ] = { /*!< @brief ADC register structure. */ typedef struct { - volatile uint16_t adcsr; // 0 - volatile uint8_t adref; // 2 - volatile uint8_t adexref; //3 - volatile uint16_t adansa[2]; // 4 - volatile uint16_t adads[2]; // 8 - volatile uint8_t adadc; // c - volatile uint8_t reserved; // d - volatile uint16_t adcer; // e - volatile uint16_t adstrgr; // 10 - volatile uint16_t adexicr; // 12 - volatile uint16_t adansb[2]; // 14 - volatile uint16_t addbldr; // 18 - volatile uint16_t adtsdr; // 1a - volatile uint16_t adocdr; // 1c - volatile uint16_t adrd; // 1e - volatile uint16_t addr[29]; // 20 - // TODO ako zatreba jos registara + volatile uint16_t adcsr; + volatile uint8_t adref; + volatile uint8_t adexref; + volatile uint16_t adansa[2]; + volatile uint16_t adads[2]; + volatile uint8_t adadc; + volatile uint8_t reserved; + volatile uint16_t adcer; + volatile uint16_t adstrgr; + volatile uint16_t adexicr; + volatile uint16_t adansb[2]; + volatile uint16_t addbldr; + volatile uint16_t adtsdr; + volatile uint16_t adocdr; + volatile uint16_t adrd; + volatile uint16_t addr[29]; + // Other registers may be present, but are not used in this implementation. } hal_ll_adc_base_handle_t; /** @@ -266,11 +265,11 @@ hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) { return HAL_LL_ADC_SUCCESS; } -hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution){ +hal_ll_err_t hal_ll_adc_set_resolution( handle_t *handle, hal_ll_adc_resolution_t resolution ) { low_level_handle = hal_ll_adc_get_handle; hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); - if( low_level_handle->hal_ll_adc_handle == NULL ) { + if( NULL == low_level_handle->hal_ll_adc_handle ) { return HAL_LL_MODULE_ERROR; } @@ -294,7 +293,7 @@ hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t return HAL_LL_ADC_SUCCESS; } -hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) { +hal_ll_err_t hal_ll_adc_set_vref_input( handle_t *handle, hal_ll_adc_voltage_reference_t vref_input ) { hal_ll_adc_handle_register_t *low_level_handle = hal_ll_adc_get_handle; hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); @@ -322,7 +321,7 @@ hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_refe return HAL_LL_ADC_SUCCESS; } -void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value){ +void hal_ll_adc_set_vref_value( handle_t *handle, float vref_value ) { low_level_handle = hal_ll_adc_get_handle; hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); @@ -331,12 +330,12 @@ void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value){ } } -hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ){ +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) { hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); low_level_handle = hal_ll_adc_get_handle; hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base; - if( low_level_handle->hal_ll_adc_handle == NULL ) { + if( NULL == low_level_handle->hal_ll_adc_handle ) { return HAL_LL_MODULE_ERROR; } @@ -352,7 +351,7 @@ hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ){ return HAL_LL_ADC_SUCCESS; } -void hal_ll_adc_close( handle_t *handle ){ +void hal_ll_adc_close( handle_t *handle ) { hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); low_level_handle = hal_ll_adc_get_handle; @@ -421,8 +420,10 @@ static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) } static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { - uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_adc_handle_register_t )); - static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_adc_handle_register_t )); + uint8_t hal_ll_module_count = + sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_adc_handle_register_t )); + static uint8_t hal_ll_module_error = + sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_adc_handle_register_t )); while( hal_ll_module_count-- ) { if ( hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[ hal_ll_module_count ].base ) { From f33e558e141d5ad899475c519328dfe3847a0908 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Thu, 31 Jul 2025 12:40:38 +0200 Subject: [PATCH 43/62] 1-Wire implementation added --- .../include/one_wire/hal_ll_one_wire.h | 4 +- .../renesas/src/one_wire/hal_ll_one_wire.c | 381 +++++++++++++++++- 2 files changed, 375 insertions(+), 10 deletions(-) diff --git a/targets/arm/mikroe/renesas/include/one_wire/hal_ll_one_wire.h b/targets/arm/mikroe/renesas/include/one_wire/hal_ll_one_wire.h index b68688316c..274f6c1f7e 100644 --- a/targets/arm/mikroe/renesas/include/one_wire/hal_ll_one_wire.h +++ b/targets/arm/mikroe/renesas/include/one_wire/hal_ll_one_wire.h @@ -67,7 +67,9 @@ typedef struct { typedef struct { hal_ll_pin_name_t data_pin; // One Wire data pin. volatile uint32_t direction; // Register for altering GPIO pin direction. - volatile uint32_t input_output; // Register for GPIO port bit set/reset and for reading current GPIO pin state. + volatile uint32_t output_set; // Register for GPIO port bit set. + volatile uint32_t output_clear; // Register for GPIO port bit reset. + volatile uint32_t input; // Register for reading current GPIO pin state. } hal_ll_one_wire_local_t; /** diff --git a/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c b/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c index cb1a2177da..a7a4c8d7e8 100644 --- a/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c +++ b/targets/arm/mikroe/renesas/src/one_wire/hal_ll_one_wire.c @@ -140,56 +140,419 @@ static hal_ll_err_t hal_ll_one_wire_search( hal_ll_one_wire_t *obj, hal_ll_one_w // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS void hal_ll_one_wire_open( hal_ll_one_wire_t *obj ) { + // Local instance of One Wire pin. + hal_ll_gpio_pin_t one_wire_pin; + // Enable appropriate PORT clock, set pin to be digital output. + hal_ll_gpio_configure_pin( &one_wire_pin, obj->data_pin, HAL_LL_GPIO_DIGITAL_OUTPUT ); + + /* Enables appropriate PORT clock, configures pin to have digital output functionality, + * makes sure that HIGH voltage state is applied on pin before any One Wire actions. */ + hal_ll_one_wire_reconfigure( obj ); } hal_ll_err_t hal_ll_one_wire_reset( hal_ll_one_wire_t *obj ) { - return 0; + /* Variable for checking whether there are device(s) on + * One Wire data pin (0) or there aren't any devices at all (1). */ + uint16_t device_response = 1; + + // One Wire data pin mask. + uint16_t bit_location = 1ul << one_wire_handle.data_pin; + + // Make sure that pin has output capability. + *(uint16_t *)one_wire_handle.direction |= bit_location; + + // Set pin to LOW voltage level. + *(uint16_t *)one_wire_handle.output_clear |= bit_location; + + // Timing value for reset of One Wire bus - LOW voltage level. + one_wire_timing_value_h(); + + // Release pin ( pull-up resistor will do the rest (pull the data line up) ). + *(uint16_t *)one_wire_handle.direction &= ~(bit_location); + + // Timing value for reset of One Wire bus - Master sample pulse. + one_wire_timing_value_i(); + + // Check whether there are devices on One Wire data pin. + device_response = *(uint16_t *)one_wire_handle.input & bit_location; + + // Provide enough time for power injection into internal power logic of devices that are present. + one_wire_timing_value_j(); + + // Return final result of device response. + return device_response; } hal_ll_err_t hal_ll_one_wire_read_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ) { - return 0; + // Initiate Reset sequence. + if ( hal_ll_one_wire_reset( obj ) ) { + return HAL_LL_ONE_WIRE_ERROR; + } + + // Initiate "Read ROM" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_read_rom_command, 1 ); + + // Read ROM address. + hal_ll_one_wire_read_byte( &device_rom_address->address[0], 8 ); + + return HAL_LL_ONE_WIRE_SUCCESS; } hal_ll_err_t hal_ll_one_wire_skip_rom( hal_ll_one_wire_t *obj ) { - return 0; + // Initiate Reset sequence. + if ( hal_ll_one_wire_reset( obj ) ) { + return HAL_LL_ONE_WIRE_ERROR; + } + + // Initiate "Skip ROM" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_skip_rom_command, 1 ); + + return HAL_LL_ONE_WIRE_SUCCESS; } hal_ll_err_t hal_ll_one_wire_match_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ) { - return 0; + // Initiate Reset sequence. + if ( hal_ll_one_wire_reset( obj ) ) { + return HAL_LL_ONE_WIRE_ERROR; + } + + // Initiate "Match" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_match_rom_command, 1 ); + + // Send ROM address. + hal_ll_one_wire_write_byte( (uint32_t)device_rom_address, 8 ); + + return HAL_LL_ONE_WIRE_SUCCESS; } static hal_ll_err_t hal_ll_one_wire_search( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) { - return 0; + // Final search result variable. + uint8_t search_result = 0; + + // Initialize variables for search method. + uint8_t rom_byte_number = 0; + uint8_t rom_byte_mask = 1; + uint8_t id_bit_number = 1; + uint8_t last_zero = 0; + + // The first bit read in a bit search sequence. + // ( logical AND of all of the id_bit_number bits of the devices that are still participating in the search ). + uint8_t id_bit = 0; + + // The complement of id_bit. + // ( logical AND of the complement of all id_bit_number bits of the devices that are still participating in the search ). + uint8_t cmp_id_bit = 0; + + // Search direction ( bit-per-bit search ). + uint8_t search_direction = 0; + + // If the last call was not the last one... + if ( !last_device_flag ) { + + // If there were no any device while executing One Wire reset sequence... + if ( hal_ll_one_wire_reset( obj ) ) { + + // Reset all the important variables. + last_device_flag = 0; + last_discrepancy = 0; + last_family_discrepancy = 0; + + // Stop searching because there are no any One Wire capable devices. + return HAL_LL_ONE_WIRE_ERROR; + } + + // If device(s) has(have) been found, initiate "Search" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_search_rom_command, 1 ); + + // Iterate until all 64 bits (8 bytes) of unique ROM 'registration' numbers have not been found. + do { + // Read a bit. + hal_ll_one_wire_read_bit( &id_bit ); + + // Then, read its complement. + hal_ll_one_wire_read_bit( &cmp_id_bit ); + + // Check whether no devices participating in current search. + if ( ( id_bit == 1 ) && ( cmp_id_bit == 1 ) ) { + break; + // Proceed, because we have found some device(s). + } else { + // We are going to check once again whether read bit and + // its complement of all the devices on the One Wire grid are not the same. + // If they are not the same, we are going to start our search with non-complement bit. + if ( id_bit != cmp_id_bit ) { + search_direction = id_bit; // Bit write value for search. + + // Otherwise, there are both binary zeros and ones in the current + // bit position of the participating ROM numbers. This is a discrepancy. + } else { + if ( id_bit_number < last_discrepancy ) { + search_direction = ( ( one_wire_device_list->address[ rom_byte_number ] & rom_byte_mask ) > 0 ); + } else { + search_direction = ( id_bit_number == last_discrepancy ); + } + + // If 0 is picked, save its position. + if ( search_direction == 0) { + last_zero = id_bit_number; + + // Check for last discrepancy in family. + if ( last_zero < 9 ) { + last_family_discrepancy = last_zero; + } + } + } + + // Set or clear bit in the ROM byte rom_byte_number with mask rom_byte_mask. + if ( search_direction == 1 ) { + one_wire_device_list->address[ rom_byte_number ] |= rom_byte_mask; + } else { + one_wire_device_list->address[ rom_byte_number ] &= ~rom_byte_mask; + } + + // Search number search direction write bit. + hal_ll_one_wire_write_bit( search_direction ); + + // Increment the byte counter "id_bit_number", and shift the mask "rom_byte_mask". + id_bit_number++; + rom_byte_mask <<= 1; + + // If the mask is zero, then go to new "serial_num" byte, "rom_byte_number" and "reset_mask". + if ( rom_byte_mask == 0 ) { + rom_byte_number++; + rom_byte_mask = 1; + } + } + } while ( rom_byte_number < HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ); + + // If the search was successful then... + if ( !( id_bit_number < 65 ) ) { + + last_discrepancy = last_zero; + + // Check for last device. + if ( last_discrepancy == 0 ) { + last_device_flag = 1; + } + search_result = 1; + } + } + // If no device found then reset counters so next "search" will be like a first. + if ( !search_result || !one_wire_device_list->address[0] ) { + last_discrepancy = 0; + last_family_discrepancy = 0; + last_device_flag = 0; + search_result = 0; + } + + // Return info whether we have found some device ID or not. + return search_result; } hal_ll_err_t hal_ll_one_wire_search_first_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) { - return 0; + // Reset the search state. + last_discrepancy = 0; + last_device_flag = 0; + last_family_discrepancy = 0; + + // Initiate search algorithm, in order to get first device on One Wire grid. + hal_ll_one_wire_search( obj, one_wire_device_list ); + + return HAL_LL_ONE_WIRE_SUCCESS; } hal_ll_err_t hal_ll_one_wire_search_next_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) { - return 0; + // Initiate search algorithm, in order to get first device on One Wire grid. + hal_ll_one_wire_search( obj, one_wire_device_list ); + + return HAL_LL_ONE_WIRE_SUCCESS; } void hal_ll_one_wire_write_byte( uint8_t *write_data_buffer, size_t write_data_length ) { - + // Local instance of One Wire pin. + hal_ll_gpio_pin_t one_wire_pin; + uint32_t bit_location = 1ul << one_wire_handle.data_pin; + + size_t local_byte_checker = 0; + uint8_t local_bit_checker = 0; + + // For every byte to be sent... + while ( local_byte_checker != write_data_length ) { + + // ...restart bit checker... + local_bit_checker = 0; + + // For every bit in byte to be sent... + while ( local_bit_checker != HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ) { + // Set pin to be digital output. + *(uint16_t *)one_wire_handle.direction |= bit_location; + + // Set pin to LOW voltage level. + *(uint16_t *)one_wire_handle.output_clear |= bit_location; + + // Check whether a bit is binary one. + if ( write_data_buffer[ local_byte_checker ] & hal_ll_one_wire_selected_bit[ local_bit_checker ] ) { + // Timing value "a" for writing logical '1' - LOW voltage level. + one_wire_timing_value_a(); + // Else, bit is binary zero. + } else { + // Timing value "c" for writing logical '0' - LOW voltage level. + one_wire_timing_value_c(); + } + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint16_t *)one_wire_handle.direction &= ~bit_location; + + // Recommended timing after writing 1's or 0's. + if ( write_data_buffer[ local_byte_checker ] & hal_ll_one_wire_selected_bit[ local_bit_checker ] ) { + // Timing value "b" for writing logical '1' - LOW voltage level. + one_wire_timing_value_b(); + } else { + // Timing value "d" for writing logical '0' - HIGH voltage level. + one_wire_timing_value_d(); + } + // Increment so we could send another bit. + ++local_bit_checker; + } + // Increment so we could send another byte. + ++local_byte_checker; + } } void hal_ll_one_wire_read_byte( uint8_t *read_data_buffer, size_t read_data_length ) { + size_t local_byte_checker = 0; + uint8_t local_bit_checker = 0; + uint32_t bit_location = 1ul << one_wire_handle.data_pin; + uint8_t local_buffer = 0; + + // For every byte to be read... + while ( local_byte_checker != read_data_length ) { + // ...restart bit checker and buffer... + local_bit_checker = 0; + local_buffer = 0; + + // For every bit in byte to be read... + while ( local_bit_checker != HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ) { + // Set pin to be digital output. + *(uint16_t*)one_wire_handle.direction |= bit_location; + + // Set pin to LOW voltage level. + *(uint16_t*)one_wire_handle.output_clear |= bit_location; + + // Timing value "a" for bit reading - LOW voltage level. + one_wire_timing_value_a(); + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint16_t*)one_wire_handle.direction &= ~bit_location; + + // Timing value "e" for sampling read information. + one_wire_timing_value_e(); + + // Read bit. + local_buffer += ( (*(uint32_t*)one_wire_handle.input & bit_location)?(1):(0) ) << local_bit_checker; + + // Timing value "f" for the rest of the read operation. + one_wire_timing_value_f(); + + // Increment so we could send another bit. + ++local_bit_checker; + } + // Send back one logical level up a byte of data that has been just read. + read_data_buffer[local_byte_checker++] = local_buffer; + } } // ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS static void hal_ll_one_wire_write_bit( uint8_t write_data_buffer ) { - + uint32_t bit_location = 1ul << one_wire_handle.data_pin; + + // Set pin to be digital output. + *(uint16_t *)one_wire_handle.direction |= bit_location; + + // Set pin to LOW voltage level. + *(uint16_t *)one_wire_handle.output_clear |= bit_location; + + // Check whether a bit is binary one. + if ( write_data_buffer & 1 ) { + // Timing value "a" for writing logical '1' - LOW voltage level. + one_wire_timing_value_a(); + // Else, bit is binary zero. + } else { + // Timing value "c" for writing logical '0' - LOW voltage level. + one_wire_timing_value_c(); + } + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint16_t *)one_wire_handle.direction &= ~bit_location; + + // Recommended timing after writing 1's or 0's. + if ( write_data_buffer & 1 ) { + // Timing value "b" for writing logical '1' - LOW voltage level. + one_wire_timing_value_b(); + } else { + // Timing value "d" for writing logical '0' - HIGH voltage level. + one_wire_timing_value_d(); + } } static void hal_ll_one_wire_read_bit( uint8_t *read_data_buffer ) { + uint16_t bit_location = 1ul << one_wire_handle.data_pin; + + // Set pin to be digital output. + *(uint16_t *)one_wire_handle.direction |= bit_location; + + // Set pin to LOW voltage level. + *(uint16_t *)one_wire_handle.output_clear |= bit_location; + // Timing value "a" for bit reading - LOW voltage level. + one_wire_timing_value_a(); + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint16_t *)one_wire_handle.direction &= ~bit_location; + + // Timing value "e" for sampling read information. + one_wire_timing_value_e(); + + // Read bit. + read_data_buffer[ 0 ] = ( *(uint32_t *)one_wire_handle.input & bit_location ) ? 0x01 : 0x00; + + // Timing value "f" for the rest of the read operation. + one_wire_timing_value_f(); } void hal_ll_one_wire_reconfigure( hal_ll_one_wire_t *obj ) { + // Local instance of One Wire pin. + hal_ll_gpio_pin_t one_wire_pin; + + one_wire_pin.base = (hal_ll_gpio_base_t)hal_ll_gpio_port_base(hal_ll_gpio_port_index(obj->data_pin)); + one_wire_pin.mask = hal_ll_gpio_pin_mask(obj->data_pin); + + // The idle state for the One Wire bus is HIGH. + do { + // Make sure that we have HIGH voltage state before any actions. + hal_ll_gpio_write_pin_output( &one_wire_pin, 1 ); + + // Make sure that pin is at HIGH voltage state. + } while ( !hal_ll_gpio_read_pin_output( &one_wire_pin ) ); + + // Memorize info about pin number (for future use). + one_wire_handle.data_pin = obj->data_pin % PORT_SIZE; + + // Memorize info about register whose main task is to alter GPIO pin direction. + hal_ll_gpio_base_handle_t *gpio_ptr = (hal_ll_gpio_base_handle_t *)one_wire_pin.base; + + // Pin direction registers. + one_wire_handle.direction = (uint32_t)&gpio_ptr->pdr; + one_wire_handle.input = (uint32_t)&gpio_ptr->pidr; + + // GPIO pin set/reset registers. + one_wire_handle.output_clear = (uint32_t)&gpio_ptr->porr; + one_wire_handle.output_set = (uint32_t)&gpio_ptr->posr; + // Set object state to true. + obj->state = true; } // ------------------------------------------------------------------------- END From 1d540222ccd9eb19cd302c6e7e7fec6a94c960e4 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Mon, 4 Aug 2025 14:55:11 +0200 Subject: [PATCH 44/62] removed rtc, can, dma --- .../mikroe/renesas/include/can/hal_ll_can.h | 426 ------------------ .../hal_ll_can_pin_map/hal_ll_can_pin_map.h | 151 ------- .../mikroe/renesas/include/dma/hal_ll_dma.h | 311 ------------- .../mikroe/renesas/include/rtc/hal_ll_rtc.h | 152 ------- .../arm/mikroe/renesas/src/rtc/CMakeLists.txt | 39 -- .../src/rtc/implementation_1/hal_ll_rtc.c | 276 ------------ .../src/rtc/implementation_2/hal_ll_rtc.c | 265 ----------- 7 files changed, 1620 deletions(-) delete mode 100644 targets/arm/mikroe/renesas/include/can/hal_ll_can.h delete mode 100644 targets/arm/mikroe/renesas/include/can/hal_ll_can_pin_map/hal_ll_can_pin_map.h delete mode 100644 targets/arm/mikroe/renesas/include/dma/hal_ll_dma.h delete mode 100644 targets/arm/mikroe/renesas/include/rtc/hal_ll_rtc.h delete mode 100644 targets/arm/mikroe/renesas/src/rtc/CMakeLists.txt delete mode 100644 targets/arm/mikroe/renesas/src/rtc/implementation_1/hal_ll_rtc.c delete mode 100644 targets/arm/mikroe/renesas/src/rtc/implementation_2/hal_ll_rtc.c diff --git a/targets/arm/mikroe/renesas/include/can/hal_ll_can.h b/targets/arm/mikroe/renesas/include/can/hal_ll_can.h deleted file mode 100644 index 0d87e37119..0000000000 --- a/targets/arm/mikroe/renesas/include/can/hal_ll_can.h +++ /dev/null @@ -1,426 +0,0 @@ -/**************************************************************************** -** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. -** Contact: https://www.mikroe.com/contact -** -** This file is part of the mikroSDK package -** -** Commercial License Usage -** -** Licensees holding valid commercial NECTO compilers AI licenses may use this -** file in accordance with the commercial license agreement provided with the -** Software or, alternatively, in accordance with the terms contained in -** a written agreement between you and The MikroElektronika Company. -** For licensing terms and conditions see -** https://www.mikroe.com/legal/software-license-agreement. -** For further information use the contact form at -** https://www.mikroe.com/contact. -** -** -** GNU Lesser General Public License Usage -** -** Alternatively, this file may be used for -** non-commercial projects under the terms of the GNU Lesser -** General Public License version 3 as published by the Free Software -** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. -** -** The above copyright notice and this permission notice shall be -** included in all copies or substantial portions of the Software. -** -** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT -** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE -** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -** -****************************************************************************/ -/*! - * @file hal_ll_can.h - * @brief API for CAN HAL LOW LEVEL layer. - */ - -#ifndef _HAL_LL_CAN_H_ -#define _HAL_LL_CAN_H_ - -#include "hal_ll_target.h" - -#ifdef __cplusplus -extern "C"{ -#endif - -/** - * @brief CAN low level pins config structure. - * - * The context structure for storing low level pin configuration - * for both TX and RX pins. - * - */ -typedef struct -{ - hal_ll_pin_af_t tx_pin; - hal_ll_pin_af_t rx_pin; -} hal_ll_can_pins_t; - -/** - * @details CAN modes. - */ -typedef enum -{ - /* Universal Modes. */ - HAL_LL_CAN_MODE_NORMAL = 0, /*!< Mode for normal operation. */ - HAL_LL_CAN_MODE_LOOPBACK, /*!< Mode for testing communication internally with sending TX data frames to other nodes. */ - HAL_LL_CAN_MODE_DISABLE, /*!< Mode for ignoring TX and RX data frames. */ - /* STM32 and RISC-V Modes. */ - HAL_LL_CAN_MODE_SILENT, /*!< Mode for only receiving messages. */ - HAL_LL_CAN_MODE_LOOPBACK_SILENT, /*!< Mode for testing communication internally without sending TX data frames to other nodes. */ - /* NXP Modes. */ - HAL_LL_CAN_MODE_LISTENONLY, /*!< Mode for only receiving messages. */ - HAL_LL_CAN_MODE_DOZE, /*!< Mode for acknowledging system low-power mode. */ - HAL_LL_CAN_MODE_STOP, /*!< Mode for acknowledging system clock stop. */ - HAL_LL_CAN_MODE_FREEZE, /*!< Mode for ignoring TX and RX data frames. */ - /* dsPIC Modes. */ - HAL_LL_CAN_MODE_LISTENALL, /*!< Mode for receiving data frames without filter configs. */ - /* PIC/PIC32 Modes. */ - HAL_LL_CAN_MODE_CONFIGURATION /*!< Mode for configuring CAN module. */ -} hal_ll_can_mode_t; - -/** - * @details CAN data frame formats. - */ -typedef enum -{ - HAL_LL_CAN_FRAME_FORMAT_STANDARD_11BITS = 0, /*!< Standard format identifier. */ - HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS /*!< Extended format identifier. */ -} hal_ll_can_frame_format_t; - -/** - * @details CAN data frame types. - */ -typedef enum -{ - HAL_LL_CAN_FRAME_TYPE_DATA = 0, /*!< Data frame. */ - HAL_LL_CAN_FRAME_TYPE_RTR /*!< Remote frame. */ -} hal_ll_can_frame_type_t; - -/** - * @details CAN filter mode. - */ -typedef enum -{ - HAL_LL_CAN_FILTER_MODE_IDMASK = 0, /*!< Identifier mask mode. */ - HAL_LL_CAN_FILTER_MODE_IDLIST /*!< Identifier list mode. */ -} hal_ll_can_filter_mode_t; - -/** - * @details CAN filter scale. - */ -typedef enum -{ - HAL_LL_CAN_FILTER_SCALE_16BIT = 0, /*!< Two 16-bit filters. */ - HAL_LL_CAN_FILTER_SCALE_32BIT /*!< One 32-bit filter. */ -} hal_ll_can_filter_scale_t; - -/** - * @details CAN filter FIFO. - */ -typedef enum -{ - HAL_LL_CAN_FILTER_FIFO0 = 0, /*!< Filter mapped to FIFO0. */ - HAL_LL_CAN_FILTER_FIFO1, /*!< Filter mapped to FIFO1. */ - HAL_LL_CAN_FILTER_FIFO2, /*!< Filter mapped to FIFO2. */ - HAL_LL_CAN_FILTER_FIFO3, /*!< Filter mapped to FIFO3. */ - HAL_LL_CAN_FILTER_FIFO4, /*!< Filter mapped to FIFO4. */ - HAL_LL_CAN_FILTER_FIFO5, /*!< Filter mapped to FIFO5. */ - HAL_LL_CAN_FILTER_FIFO6, /*!< Filter mapped to FIFO6. */ - HAL_LL_CAN_FILTER_FIFO7, /*!< Filter mapped to FIFO7. */ - HAL_LL_CAN_FILTER_FIFO8, /*!< Filter mapped to FIFO8. */ - HAL_LL_CAN_FILTER_FIFO9, /*!< Filter mapped to FIFO9. */ - HAL_LL_CAN_FILTER_FIFO10, /*!< Filter mapped to FIFO10. */ - HAL_LL_CAN_FILTER_FIFO11, /*!< Filter mapped to FIFO11. */ - HAL_LL_CAN_FILTER_FIFO12, /*!< Filter mapped to FIFO12. */ - HAL_LL_CAN_FILTER_FIFO13, /*!< Filter mapped to FIFO13. */ - HAL_LL_CAN_FILTER_FIFO14, /*!< Filter mapped to FIFO14. */ - HAL_LL_CAN_FILTER_FIFO15, /*!< Filter mapped to FIFO15. */ - HAL_LL_CAN_FILTER_FIFO16, /*!< Filter mapped to FIFO16. */ - HAL_LL_CAN_FILTER_FIFO17, /*!< Filter mapped to FIFO17. */ - HAL_LL_CAN_FILTER_FIFO18, /*!< Filter mapped to FIFO18. */ - HAL_LL_CAN_FILTER_FIFO19, /*!< Filter mapped to FIFO19. */ - HAL_LL_CAN_FILTER_FIFO20, /*!< Filter mapped to FIFO20. */ - HAL_LL_CAN_FILTER_FIFO21, /*!< Filter mapped to FIFO21. */ - HAL_LL_CAN_FILTER_FIFO22, /*!< Filter mapped to FIFO22. */ - HAL_LL_CAN_FILTER_FIFO23, /*!< Filter mapped to FIFO23. */ - HAL_LL_CAN_FILTER_FIFO24, /*!< Filter mapped to FIFO24. */ - HAL_LL_CAN_FILTER_FIFO25, /*!< Filter mapped to FIFO25. */ - HAL_LL_CAN_FILTER_FIFO26, /*!< Filter mapped to FIFO26. */ - HAL_LL_CAN_FILTER_FIFO27, /*!< Filter mapped to FIFO27. */ - HAL_LL_CAN_FILTER_FIFO28, /*!< Filter mapped to FIFO28. */ - HAL_LL_CAN_FILTER_FIFO29, /*!< Filter mapped to FIFO29. */ - HAL_LL_CAN_FILTER_FIFO30, /*!< Filter mapped to FIFO30. */ - HAL_LL_CAN_FILTER_FIFO31 /*!< Filter mapped to FIFO31. */ -} hal_ll_can_filter_fifo_t; - -/*< @brief Default FIFO number and filter bank used for CAN implementation */ -#define HAL_LL_CAN_FILTER_FIFO_DEFAULT HAL_LL_CAN_FILTER_FIFO2 -#define HAL_LL_CAN_FILTER_BANK_DEFAULT (0) - -/** - * @details CAN filter activation. - */ -typedef enum -{ - HAL_LL_CAN_FILTER_DISABLE = 0, /*!< CAN filter disable. */ - HAL_LL_CAN_FILTER_ENABLE /*!< CAN filter enable. */ -} hal_ll_can_filter_activation_t; - -/** - * @details CAN filter config structure. - */ -typedef struct -{ - union { - struct { - uint16_t can_filter_id_low; /*!< 16-bit Filter ID. */ - uint16_t can_filter_id_high; /*!< 16-bit Filter ID. */ - }; - uint32_t can_filter_id; /*!< 32-bit Filter ID. */ - }; - union { - struct { - uint16_t can_filter_mask_id_low; /*!< 16-bit Filter ID or Filter Mask. */ - uint16_t can_filter_mask_id_high; /*!< 16-bit Filter ID or Filter Mask. */ - }; - uint32_t can_filter_mask_id; /*!< 32-bit Filter ID or Filter Mask. */ - }; - uint8_t can_filter_bank; /*!< Filter bank. */ - hal_ll_can_frame_type_t can_filter_frame_type[4]; /*!< Type of frame, data or remote. */ - hal_ll_can_filter_activation_t can_filter_enable; /*!< Filter activation status. */ - hal_ll_can_filter_mode_t can_filter_mode; /*!< Filter mode. */ - hal_ll_can_filter_scale_t can_filter_scale; /*!< Filter scale. */ - hal_ll_can_filter_fifo_t can_filter_fifo; /*!< Filter-to-FIFO mapping. */ -} hal_ll_can_filter_config_t; - -/** - * @details CAN module config structure. - */ -typedef struct -{ - hal_ll_pin_name_t tx_pin; /*!< Tx pin. */ - hal_ll_pin_name_t rx_pin; /*!< Rx pin. */ - hal_ll_can_mode_t mode; /*!< CAN mode. */ - uint32_t frequency; /*!< CAN frequency. */ -} hal_ll_can_config_t; - -/** - * @details Message structure. - */ -typedef struct -{ - union { - struct { - uint16_t std_id; /*!< Standard format frame identifier. */ - uint16_t ext_id; /*!< Extended format frame identifier. */ - }; - uint32_t message_id; - }; - hal_ll_can_frame_format_t frame_format; /*!< Format of frame, standard or extended format. */ - hal_ll_can_frame_type_t frame_type; /*!< Type of frame, data or remote. */ - uint8_t data_len; /*!< Data length. */ - uint8_t message_data[8]; /*!< Data. */ -} hal_ll_can_message_t; - -/** - * @details CAN HAL low level transmit message structure. - */ -typedef struct -{ - hal_ll_can_message_t message; /* CAN message structure. */ -} hal_ll_can_transmit_message_struct; - -/** - * @details CAN HAL low level receive message structure. - */ -typedef struct -{ - hal_ll_can_message_t message; /* CAN message structure. */ - uint8_t rx_fifo_number; /* Receive FIFO number. */ -} hal_ll_can_receive_message_struct; - -/** - * @brief CAN low level handle. - * - * The context for storing low level object handler. - * User is not to change these values or unexpected behaviour - * may occur. - */ -typedef struct -{ - handle_t *hal_ll_can_handle; /*!< CAN HAL low level handle */ - handle_t *hal_drv_can_handle; /*!< CAN DRV level handle */ - bool init_ll_state; /*!< CAN HAL low level object init state */ -} hal_ll_can_handle_register_t; - -/** - * @brief Registers handler for future use. - * - * Registers low level and hal level handlers - * for use with appropriate functions. - * - * @param[in] tx_pin CAN TX pin. - * @param[in] rx_pin CAN RX pin. - * @param[in] *handle_map HAL layer local handle map. - * @param[in] *hal_module_id HAL layer module number. - - * @return hal_ll_err_t Module specific error. - * - * Returns one of pre-defined values. - * Take into consideration that this is hardware specific. - */ -hal_ll_err_t hal_ll_can_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, - hal_ll_can_handle_register_t *handle_map, uint8_t *hal_module_id ); - -/** - * @brief Initializes specified module. - * - * Performs module configuration on the hardware - * level. Enables module specific clock gate and - * sets adequate alternate function values. - * - * @param[in] handle HAL context object handle. - * @param[in] config HAL low level config structure. - * @param[in] filter_config HAL low level filter config structure. - * - * @return hal_ll_err_t Module specific error. - * - * Returns one of pre-defined values. - * Take into consideration that this is hardware specific. - */ -hal_ll_err_t hal_ll_can_init( handle_t *handle, hal_ll_can_config_t *config, - hal_ll_can_filter_config_t *filter_config ); - -/** - * @brief Sets filter parameters. - * - * Initializes module with specified filter parameters. - * - * @param[in] handle HAL context object handle. - * @param[in] config HAL low level config structure. - * @param[in] filter_config HAL low level filter config structure. - * - * Returns one of pre-defined values. - * Take into consideration that this is hardware specific. - */ -hal_ll_err_t hal_ll_can_set_filter( handle_t *handle, hal_ll_can_config_t *config, - hal_ll_can_filter_config_t *filter_config ); - -/** - * @brief Sets adequate bit timing parameters for desired frequency. - * - * @note: Setting parameters that result in a baud rate that - * differs from the desired value is not acceptable. - * If two devices communicate over CAN, their baud - * rates need to be exactly the same. - * - * @param[in] handle HAL context object handle. - * @param[in] config HAL low level config structure. - * @param[in] filter_config HAL low level filter config structure. - * - * Returns one of pre-defined values. - * Take into consideration that this is hardware specific. - */ -hal_ll_err_t hal_ll_can_set_frequency( handle_t *handle, hal_ll_can_config_t *config, - hal_ll_can_filter_config_t *filter_config ); - -/** - * @brief Gets CAN frequency. - * - * Gets the currently configured CAN frequency. - * - * @param[in] handle HAL context object handle. - * - * Returns CAN frequency. - */ -hal_ll_err_t hal_ll_can_get_frequency( handle_t *handle ); - -/** - * @brief Sets desired CAN operating mode. - * - * Initializes module with specified CAN mode. - * - * @param[in] handle HAL context object handle. - * @param[in] config HAL low level config structure. - * @param[in] filter_config HAL low level filter config structure. - * - * Returns one of pre-defined values. - * Take into consideration that this is hardware specific. - */ -hal_ll_err_t hal_ll_can_set_mode( handle_t *handle, hal_ll_can_config_t *config, - hal_ll_can_filter_config_t *filter_config ); - -/** - * @brief Gets CAN mode. - * - * Gets the currently configured CAN mode. - * - * @param[in] handle HAL context object handle. - * - * Returns CAN mode. - */ -hal_ll_err_t hal_ll_can_get_mode( handle_t *handle ); - -/** - * @brief Performs transmit operation. - * - * Accesses hardware transmit registers and - * writes parameters and data directly to them. - * - * @param[in] handle HAL context object handle. - * @param[in] transmit_message Transmit message structure. - * - * Returns one of pre-defined values. - */ -hal_ll_err_t hal_ll_can_transmit( handle_t *handle, hal_ll_can_transmit_message_struct *transmit_message ); - -/** - * @brief Stops transmit operation. - * - * Accesses hardware transmit registers and stops data transmission. - * - * @param[in] handle HAL context object handle. - * - * @return void None. - */ -void hal_ll_can_transmission_stop( handle_t *handle ); - -/** - * @brief Performs receive operation. - * - * Accesses hardware receive registers and - * reads parameters and data directly from them. - * - * @param[in] handle HAL context object handle. - * @param[in] receive_message Receive message structure. - * - * Returns one of pre-defined values. - */ -hal_ll_err_t hal_ll_can_receive( handle_t *handle, hal_ll_can_receive_message_struct *receive_message ); - -/** - * @brief Closes CAN HAL and HAL_LOW_LEVEL context object. - * - * De-allocates hardware resources for specific driver object and - * de-initializes the module on a hardware level. - * - * @param[in] *handle HAL context object handle. - * - * Returns one of pre-defined values. - */ -hal_ll_err_t hal_ll_can_close( handle_t *handle ); - -#ifdef __cplusplus -} -#endif - -#endif // _HAL_LL_CAN_H_ -// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/can/hal_ll_can_pin_map/hal_ll_can_pin_map.h b/targets/arm/mikroe/renesas/include/can/hal_ll_can_pin_map/hal_ll_can_pin_map.h deleted file mode 100644 index 1253ba173b..0000000000 --- a/targets/arm/mikroe/renesas/include/can/hal_ll_can_pin_map/hal_ll_can_pin_map.h +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** -** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. -** Contact: https://www.mikroe.com/contact -** -** This file is part of the mikroSDK package -** -** Commercial License Usage -** -** Licensees holding valid commercial NECTO compilers AI licenses may use this -** file in accordance with the commercial license agreement provided with the -** Software or, alternatively, in accordance with the terms contained in -** a written agreement between you and The MikroElektronika Company. -** For licensing terms and conditions see -** https://www.mikroe.com/legal/software-license-agreement. -** For further information use the contact form at -** https://www.mikroe.com/contact. -** -** -** GNU Lesser General Public License Usage -** -** Alternatively, this file may be used for -** non-commercial projects under the terms of the GNU Lesser -** General Public License version 3 as published by the Free Software -** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. -** -** The above copyright notice and this permission notice shall be -** included in all copies or substantial portions of the Software. -** -** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT -** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE -** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -** -****************************************************************************/ -/*! - * @file hal_ll_can_pin_map.h - * @brief CAN HAL LOW LEVEL PIN MAPS. - */ - -#ifndef _HAL_LL_CAN_PIN_MAP_H_ -#define _HAL_LL_CAN_PIN_MAP_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -#include "hal_ll_pin_names.h" - -/*!< @brief Helper macro for getting adequate module index number */ -#define hal_ll_can_module_num(_module_num) (_module_num - 1) - -/*!< @brief Macro defining `weak` attribute */ -#define __weak __attribute__((weak)) - -/*!< @brief Pin structure */ -typedef struct -{ - uint8_t module_index; - hal_ll_pin_name_t pin; - hal_ll_base_addr_t base; - uint32_t af; -} hal_ll_can_pin_map_t; - -/*!< @brief CAN RX pins */ -static const hal_ll_can_pin_map_t hal_ll_can_rx_map[] = -{ - //------------ BEGIN RX - #ifdef CAN0_RX_PF0_AF3 - {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PF0, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF3}, - #endif - #ifdef CAN0_RX_PE4_AF8 - {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PE4, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF8}, - #endif - #ifdef CAN0_RX_PB4_AF8 - {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PB4, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF8}, - #endif - #ifdef CAN0_RX_PN0_AF1 - {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PN0, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF1}, - #endif - #ifdef CAN1_RX_PA0_AF8 - {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PA0, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF8}, - #endif - #ifdef CAN1_RX_PE6_AF8 - {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PE6, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF8}, - #endif - #ifdef CAN0_RX_PA0_AF7 - {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PA0, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF7}, - #endif - #ifdef CAN1_RX_PB0_AF7 - {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PB0, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF7}, - #endif - #ifdef CAN1_RX_PT2_AF7 - {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PT2, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF7}, - #endif - #ifdef CAN0_RX_PT0_AF7 - {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PT0, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF7}, - #endif - - {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} - //------------ END RX -}; - -/*!< @brief CAN TX pins */ -static const hal_ll_can_pin_map_t hal_ll_can_tx_map[] = -{ - //------------ BEGIN TX - #ifdef CAN0_TX_PE5_AF8 - {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PE5, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF8}, - #endif - #ifdef CAN0_TX_PB5_AF8 - {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PB5, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF8}, - #endif - #ifdef CAN0_TX_PF3_AF3 - {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PF3, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF3}, - #endif - #ifdef CAN0_TX_PN1_AF1 - {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PN1, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF1}, - #endif - #ifdef CAN1_TX_PA1_AF8 - {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PA1, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF8}, - #endif - #ifdef CAN1_TX_PE7_AF8 - {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PE7, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF8}, - #endif - #ifdef CAN1_TX_PB1_AF7 - {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PB1, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF7}, - #endif - #ifdef CAN0_TX_PA1_AF7 - {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PA1, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF7}, - #endif - #ifdef CAN1_TX_PT3_AF7 - {hal_ll_can_module_num(CAN_MODULE_1), GPIO_PT3, HAL_LL_CAN1_BASE_ADDRESS, HAL_LL_CAN1_GPIO_AF7}, - #endif - #ifdef CAN0_TX_PT1_AF7 - {hal_ll_can_module_num(CAN_MODULE_0), GPIO_PT1, HAL_LL_CAN0_BASE_ADDRESS, HAL_LL_CAN0_GPIO_AF7}, - #endif - - {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} - //------------ END TX -}; - -#ifdef __cplusplus -} -#endif - -#endif // _HAL_LL_CAN_PIN_MAP_H_ -// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/dma/hal_ll_dma.h b/targets/arm/mikroe/renesas/include/dma/hal_ll_dma.h deleted file mode 100644 index 40767116ad..0000000000 --- a/targets/arm/mikroe/renesas/include/dma/hal_ll_dma.h +++ /dev/null @@ -1,311 +0,0 @@ -/**************************************************************************** -** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. -** Contact: https://www.mikroe.com/contact -** -** This file is part of the mikroSDK package -** -** Commercial License Usage -** -** Licensees holding valid commercial NECTO compilers AI licenses may use this -** file in accordance with the commercial license agreement provided with the -** Software or, alternatively, in accordance with the terms contained in -** a written agreement between you and The MikroElektronika Company. -** For licensing terms and conditions see -** https://www.mikroe.com/legal/software-license-agreement. -** For further information use the contact form at -** https://www.mikroe.com/contact. -** -** -** GNU Lesser General Public License Usage -** -** Alternatively, this file may be used for -** non-commercial projects under the terms of the GNU Lesser -** General Public License version 3 as published by the Free Software -** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. -** -** The above copyright notice and this permission notice shall be -** included in all copies or substantial portions of the Software. -** -** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT -** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE -** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -** -****************************************************************************/ -/*! - * @file hal_ll_dma.h - * @brief API for DMA HAL LOW LEVEL layer. - */ - -#ifndef _HAL_LL_DMA_H_ -#define _HAL_LL_DMA_H_ - -#include "hal_ll_target.h" - -#ifdef __cplusplus -extern "C"{ -#endif - -/** - * @details Return values. - */ -typedef enum -{ - HAL_LL_DMA_SUCCESS = 0, /*!< Success. */ - HAL_LL_DMA_ERROR = (-1) /*!< Error. */ -} hal_ll_dma_err_t; - -/** - * @details Module state values. - */ -typedef enum -{ - HAL_LL_DMA_STATE_FREE = 0, /*!< DMA object is free for use. */ - HAL_LL_DMA_STATE_ALLOCATED /*!< DMA object has been allocated - not free for use. */ -} hal_ll_dma_state_t; - -/** - * @details Source address memory region. - */ -typedef enum -{ - HAL_LL_DMA_SOURCE_MEMORY_REGION_RAM = 0, /*!< DMA source address is in RAM section. */ - HAL_LL_DMA_SOURCE_MEMORY_REGION_PFM = 1, /*!< DMA source address is in Program Flash Memory section. */ - HAL_LL_DMA_SOURCE_MEMORY_REGION_DEEPROM = 2 /*!< DMA source address is in Data EEPROM section. */ -} hal_ll_dma_source_memory_region_t; - -/** - * @details Module direction values. - */ -typedef enum -{ - HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY = 0, /*!< M2M */ - HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH, /*!< M2P */ - HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY, /*!< P2M */ - HAL_LL_DMA_DIRECTION_PERIPH_TO_PERIPH, /*!< P2P */ - - HAL_LL_DMA_DIRECTION_DEFAULT = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Default value is M2M. */ -} hal_ll_dma_direction_t; - -/** - * @details Module data alignment values. - */ -typedef enum -{ - HAL_LL_DMA_DATA_ALIGN_BYTES_1 = 0, /*!< Align data to byte (uint8_t). */ - HAL_LL_DMA_DATA_ALIGN_BYTES_2, /*!< Align data to half word (uint16_t). */ - HAL_LL_DMA_DATA_ALIGN_BYTES_3, /*!< Align data to 3 bytes (uint24_t). */ - HAL_LL_DMA_DATA_ALIGN_BYTES_4, /*!< Align data to word (uint32_t). */ - - HAL_LL_DMA_DATA_ALIGN_DEFAULT = HAL_LL_DMA_DATA_ALIGN_BYTES_1 /*!< Default data alignment of byte (uint8_t). */ -} hal_ll_dma_data_align_t; - -/** - * @details Module mode values. - */ -typedef enum -{ - HAL_LL_DMA_MODE_NORMAL = 0, /*!< Normal mode. */ - HAL_LL_DMA_MODE_CIRCULAR, /*!< Circular mode. */ - - HAL_LL_DMA_MODE_DEFAULT = HAL_LL_DMA_MODE_NORMAL /*!< Default mode set to normal. */ -} hal_ll_dma_mode_t; - -/** - * @details Module priority levels. - */ -typedef enum -{ - HAL_LL_DMA_PRIORITY_LOW = 0, /*!< Sets priority level to low. */ - HAL_LL_DMA_PRIORITY_MEDIUM, /*!< Sets priority level to medium. */ - HAL_LL_DMA_PRIORITY_HIGH, /*!< Sets priority level to high. */ - HAL_LL_DMA_PRIORITY_VERY_HIGH, /*!< Sets priority level to very high. */ - - HAL_LL_DMA_PRIORITY_DEFAULT = HAL_LL_DMA_PRIORITY_MEDIUM /*!< Default priority level set to medium. */ -} hal_ll_dma_priority_t; - -/** - * @details Module burst increment size. - */ -typedef enum -{ - HAL_LL_DMA_BURST_SIZE_INCREMENT_1 = 0, /*!< Dma module burst increment size set to 1 byte. */ - HAL_LL_DMA_BURST_SIZE_INCREMENT_2, /*!< Dma module burst increment size set to 2 bytes. */ - HAL_LL_DMA_BURST_SIZE_INCREMENT_4, /*!< Dma module burst increment size set to 4 bytes. */ - HAL_LL_DMA_BURST_SIZE_INCREMENT_8, /*!< Dma module burst increment size set to 8 bytes. */ - HAL_LL_DMA_BURST_SIZE_INCREMENT_16, /*!< Dma module burst increment size set to 16 bytes. */ - HAL_LL_DMA_BURST_SIZE_INCREMENT_32, /*!< Dma module burst increment size set to 32 bytes. */ - - HAL_LL_DMA_BURST_SIZE_INCREMENT_DEFAULT = HAL_LL_DMA_BURST_SIZE_INCREMENT_1 /*!< Default burst increment size set to 1 byte. */ -} hal_ll_dma_burst_size_t; - -/** - * @brief HAL LL DMA Configuration Structure prototype. - */ -typedef struct -{ - uint8_t module; /*!< Specifies the module. */ - uint8_t stream; /*!< Specifies the stream. */ - uint8_t channel; /*!< Specifies the channel used for the specified stream. */ - hal_ll_dma_direction_t direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory, from peripheral to memory, or from - peripheral to peripheral. - This parameter can be a value of @ref hal_ll_dma_direction_t */ - hal_ll_dma_mode_t mode; /*!< Specifies the operation mode of the DMA Stream. - This parameter can be a value of @ref hal_ll_dma_mode_t */ - bool src_inc; /*!< Specifies whether the Source address register should be incremented or not. */ - hal_ll_dma_data_align_t data_align_source; /*!< Specifies the Source data width. - This parameter can be a value of @ref hal_ll_dma_data_align_t */ - hal_ll_dma_burst_size_t burst_size_source; /*!< Specifies the Burst transfer configuration for the source transfers. - It specifies the amount of data to be transferred in a single non interruptable - transaction. - This parameter can be a value of @ref hal_ll_dma_burst_size_t - @note The burst mode is possible only if the address increment mode is enabled. */ - bool dst_inc; /*!< Specifies whether the Destination address register should be incremented or not. */ - hal_ll_dma_data_align_t data_align_destination; /*!< Specifies the Destination data width. - This parameter can be a value of @ref hal_ll_dma_data_align_t */ - hal_ll_dma_burst_size_t burst_size_destination; /*!< Specifies the Burst transfer configuration for the destination transfers. - It specifies the amount of data to be transferred in a single non interruptable - transaction. - This parameter can be a value of @ref hal_ll_dma_burst_size_t - @note The burst mode is possible only if the address increment mode is enabled. */ - hal_ll_dma_priority_t priority; /*!< Specifies the software priority for the DMA Stream. - This parameter can be a value of @ref hal_ll_dma_priority_t */ - uint32_t addr_src; /*!< Address to transfer from. */ - uint32_t addr_dst; /*!< Address to transfer to. */ - size_t transfer_length; /*!< Number of bytes to transfer. */ -} hal_ll_dma_config_t; - -/** - * @brief HAL DMA Handle prototype. - * @details DMA hal context structure, used by every other function later on. - */ -typedef struct -{ - handle_t handle; /*!< DMA HAL LL handle. */ - hal_ll_dma_config_t config; /*!< DMA HAL LL configuration structure. */ - uint8_t module; /*!< Specifies the module. */ - uint8_t stream; /*!< Specifies the stream. */ - uint8_t channel; /*!< Specifies the channel used for the specified stream. */ - hal_ll_dma_state_t allocated; /*!< Is the object allocated or not? */ - bool initialized; /*!< Is the object initialized or not? */ -} hal_ll_dma_t; - -/** - * @brief Initializes the DMA module. - * @details Enables module clock and initializes to values set in - * @b hal_ll_dma_t->hal_ll_dma_config_t - * @param[in,out] obj DMA HAL LL object. - * See #hal_ll_dma_t structure definition for detailed explanation. - * @return The function can return one of the values defined by - * hal_ll_err_t, which is dependant on the architecture and ported low level layer. - * @note It is recommended to check return value for error. - */ -hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ); - -/** - * @brief Set the DMA mode. - * @details Sets DMA mode to be used by the DMA HAL LL. - * @param[in,out] obj DMA HAL LL object. - * See #hal_ll_dma_t structure definition for detailed explanation. - * @param[in] mode DMA mode. - * See #hal_ll_dma_mode_t for valid values. - * @return The function can return one of the values defined by - * hal_ll_err_t, which is dependant on the architecture and ported low level layer. - * @note It is recommended to check return value for error. - */ -hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ); - -/** - * @brief Set the DMA direction. - * @details Sets DMA direction to be used by the DMA HAL LL. - * @param[in,out] obj DMA HAL LL object. - * See #hal_ll_dma_t structure definition for detailed explanation. - * @param[in] direction DMA direction. - * See #hal_ll_dma_direction_t for valid values. - * @return The function can return one of the values defined by - * hal_ll_err_t, which is dependant on the architecture and ported low level layer. - * @note It is recommended to check return value for error. - */ -hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ); - -/** - * @brief Set the DMA priority. - * @details Sets DMA priority level to be used by the DMA HAL LL. - * @param[in,out] obj DMA HAL LL object. - * See #hal_ll_dma_t structure definition for detailed explanation. - * @param[in] priority DMA priority level. - * See #hal_ll_dma_priority_t for valid values. - * @return The function can return one of the values defined by - * hal_ll_err_t, which is dependant on the architecture and ported low level layer. - * @note It is recommended to check return value for error. - */ -hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ); - -/** - * @brief Configure the DMA transfer. - * @details Configures initialized DMA stream for transfer. - * @param[in,out] obj DMA HAL LL object. - * See #hal_dma_t structure definition for detailed explanation. - * @param[in] addr_src Source address for transfer. - * @param[in] addr_dst Destination address for transfer. - * @param[in] transfer_size Number of bytes to transfer. - * @param[in] src_mem_type Source address memory region. - * @return Nothing. - */ -hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ); - -/** - * @brief Initializes the DMA transfer. - * @details Starts previously configured DMA transfer by enabling stream. - * @param[in,out] obj DMA HAL LL object. - * See #hal_ll_dma_t structure definition for detailed explanation. - * @return The function can return one of the values defined by - * hal_ll_err_t, which is dependant on the architecture and ported low level layer. - * @note It is recommended to check return value for error. - */ -hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ); - -/** - * @brief Stops the DMA transfer. - * @details Stops an active DMA transfer by disabling stream. - * @param[in,out] obj DMA HAL LL object. - * See #hal_ll_dma_t structure definition for detailed explanation. - * @return The function can return one of the values defined by - * hal_ll_err_t, which is dependant on the architecture and ported low level layer. - * @note It is recommended to check return value for error. - */ -hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ); - -/** - * @brief Aborts a DMA transfer. - * @details Aborts any ongoing DMA transfers and disables stream. - * @param[in,out] obj DMA HAL LL object. - * See #hal_ll_dma_t structure definition for detailed explanation. - * @return The function can return one of the values defined by - * hal_ll_err_t, which is dependant on the architecture and ported low level layer. - * @note It is recommended to check return value for error. - */ -hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ); - -/** - * @brief De-initializes the DMA module. - * @details Disables module clock and de-initializes module. - * @param[in,out] obj DMA HAL LL object. - * See #hal_ll_dma_t structure definition for detailed explanation. - * @return The function can return one of the values defined by - * hal_ll_err_t, which is dependant on the architecture and ported low level layer. - * @note It is recommended to check return value for error. - */ -hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *dma_obj ); - -#ifdef __cplusplus -} -#endif - -#endif // _HAL_LL_DMA_H_ -// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/renesas/include/rtc/hal_ll_rtc.h b/targets/arm/mikroe/renesas/include/rtc/hal_ll_rtc.h deleted file mode 100644 index 95ca553b1d..0000000000 --- a/targets/arm/mikroe/renesas/include/rtc/hal_ll_rtc.h +++ /dev/null @@ -1,152 +0,0 @@ -/**************************************************************************** -** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. -** Contact: https://www.mikroe.com/contact -** -** This file is part of the mikroSDK package -** -** Commercial License Usage -** -** Licensees holding valid commercial NECTO compilers AI licenses may use this -** file in accordance with the commercial license agreement provided with the -** Software or, alternatively, in accordance with the terms contained in -** a written agreement between you and The MikroElektronika Company. -** For licensing terms and conditions see -** https://www.mikroe.com/legal/software-license-agreement. -** For further information use the contact form at -** https://www.mikroe.com/contact. -** -** -** GNU Lesser General Public License Usage -** -** Alternatively, this file may be used for -** non-commercial projects under the terms of the GNU Lesser -** General Public License version 3 as published by the Free Software -** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. -** -** The above copyright notice and this permission notice shall be -** included in all copies or substantial portions of the Software. -** -** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT -** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE -** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -** -****************************************************************************/ -/*! - * @file hal_ll_rtc.h - * @brief API for RTC HAL LOW level layer. - */ - -#ifndef _HAL_LL_RTC_H -#define _HAL_LL_RTC_H - -#ifdef __cplusplus -extern "C"{ -#endif - -#ifdef __GNUC__ -#include "mcu.h" -#endif - -#include "hal_target.h" -#include "hal_ll_bit_control.h" - -/** - * @brief Structure representing the RTC time. - * @details This structure is used to hold the real-time clock information, including - * hour, minute, second and it follows a 24-hour format. - * @note Take into consideration that any value can be changed explicitly by the user. - */ -typedef struct -{ - uint8_t hour; // 2-digit format - supports values from 00 to 23 - uint8_t minute; // 2-digit format - supports values from 00 to 59 - uint8_t second; // 2-digit format - supports values from 00 to 59 -} hal_ll_rtc_time_t; - -/** - * @brief Initialize the RTC module. - * @details Initialize the RTC module. - * @param None. - */ -void hal_ll_rtc_init(); - -/** - * @brief Start the RTC module. - * @details Continue the RTC module count from the stored value in the count register. - * @param None. - * @return The function can return one of the values defined by - * hal_ll_rtc_err_t structure, which is size dependant on the architecture. - * @note It is recommended to check return value for error. - * @pre Before calling this function, the user is expected - * to have initialized RTC by using hal_ll_rtc_init() and have the RTC not counting. - */ -err_t hal_ll_rtc_start(); - -/** - * @brief Stop the RTC module. - * @details Stop the RTC module count. - * @param None. - * @return The function can return one of the values defined by - * hal_ll_rtc_err_t structure, which is size dependant on the architecture. - * @note It is recommended to check return value for error. - * @pre Before calling this function, the user is expected - * to have the RTC started. - */ -err_t hal_ll_rtc_stop(); - -/** - * @brief Reset the RTC module. - * @details Reset the RTC counter to the default values of 0h:0m:0s. - * @param None. - * @return The function can return one of the values defined by - * hal_ll_rtc_err_t structure, which is size dependant on the architecture. - * @note It is recommended to check return value for error. - * @pre Before calling this function, the user is expected - * to have the RTC started. - */ -err_t hal_ll_rtc_reset(); - -/** - * @brief Configure time of RTC module. - * @details Configure time registers with the values from hal_ll_rtc_time_t structure. - * @param time hal_ll_rtc_time_t structure. - * @return The function can return one of the values defined by - * hal_ll_rtc_err_t structure, which is size dependant on the architecture. - * @note It is recommended to check return value for error. - * @pre Before calling this function, the user is expected - * to have the RTC enabled. - */ -err_t hal_ll_rtc_set_time( hal_ll_rtc_time_t *time ); - -/** - * @brief Get time from RTC module. - * @details Configure hal_ll_rtc_time_t structure with the values from time registers. - * @param time hal_ll_rtc_time_t structure. - * @return The function can return one of the values defined by - * hal_ll_rtc_err_t structure, which is size dependant on the architecture. - * @note It is recommended to check return value for error. - * @pre Before calling this function, the user is expected - * to have the RTC enabled. - */ -err_t hal_ll_rtc_get_time( hal_ll_rtc_time_t *time ); - -/** - * @brief Preforms system reset. - * @details Resets the core and all on-chip peripherals except the Debug - * interface. - * @param None. - * @warning System reset affects core and periferals, - * depending on the architecture you will need to reconfigure opened modules. - */ -void hal_ll_rtc_system_reset(); - -#ifdef __cplusplus -} -#endif - -#endif // HAL_LL_RTC_H diff --git a/targets/arm/mikroe/renesas/src/rtc/CMakeLists.txt b/targets/arm/mikroe/renesas/src/rtc/CMakeLists.txt deleted file mode 100644 index 06a7e7ca95..0000000000 --- a/targets/arm/mikroe/renesas/src/rtc/CMakeLists.txt +++ /dev/null @@ -1,39 +0,0 @@ -## ./targets/arm/mikroe/tiva/src/rtc/CMakeLists.txt -set(hal_ll_def_list "") - -## BEGIN RTC -list(APPEND hal_ll_def_list "MACRO_USAGE_RTC") - -if(${MCU_NAME} MATCHES "TM4C129.+") - set(rtc_subimplementation "implementation_1/hal_ll_rtc.c") -elseif(${MCU_NAME} MATCHES "TM4C123[137BG].+") - set(rtc_subimplementation "implementation_2/hal_ll_rtc.c") -endif() -## END RTC - -mikrosdk_add_library(lib_hal_ll_rtc MikroSDK.HalLowLevel.RTC - ${rtc_subimplementation} - - ../../include/rtc/hal_ll_rtc.h) - -target_compile_definitions(lib_hal_ll_rtc PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_rtc PUBLIC - MikroC.Core - MikroSDK.HalInterface - MikroSDK.HalLowLevelCommon -) - -target_include_directories(lib_hal_ll_rtc - PRIVATE - ../../include/rtc - INTERFACE - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.RTC) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.RTC ../../include/rtc/hal_ll_rtc.h) diff --git a/targets/arm/mikroe/renesas/src/rtc/implementation_1/hal_ll_rtc.c b/targets/arm/mikroe/renesas/src/rtc/implementation_1/hal_ll_rtc.c deleted file mode 100644 index f0f9279d59..0000000000 --- a/targets/arm/mikroe/renesas/src/rtc/implementation_1/hal_ll_rtc.c +++ /dev/null @@ -1,276 +0,0 @@ -/**************************************************************************** -** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. -** Contact: https://www.mikroe.com/contact -** -** This file is part of the mikroSDK package -** -** Commercial License Usage -** -** Licensees holding valid commercial NECTO compilers AI licenses may use this -** file in accordance with the commercial license agreement provided with the -** Software or, alternatively, in accordance with the terms contained in -** a written agreement between you and The MikroElektronika Company. -** For licensing terms and conditions see -** https://www.mikroe.com/legal/software-license-agreement. -** For further information use the contact form at -** https://www.mikroe.com/contact. -** -** -** GNU Lesser General Public License Usage -** -** Alternatively, this file may be used for -** non-commercial projects under the terms of the GNU Lesser -** General Public License version 3 as published by the Free Software -** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. -** -** The above copyright notice and this permission notice shall be -** included in all copies or substantial portions of the Software. -** -** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT -** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE -** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -** -****************************************************************************/ -/*! - * @file hal_ll_rtc.c - * @brief Rtc HAL LOW LEVEL layer implementation. - */ - -#include "hal_ll_rtc.h" - -/** - * Return values - */ -typedef enum -{ - HAL_LL_RTC_SUCCESS = 0, - HAL_LL_RTC_ERROR = (-1) -} hal_ll_rtc_err_t; - -#define SYSCTL_RCGCHIB_R0_BIT 0 -#define HIB_IM_WC_BIT 4 -#define HIB_CTL_RTCEN_BIT 0 -#define HIB_CTL_CLK32EN_BIT 6 -#define HIB_CTL_WRC_BIT 31 -#define HIB_MIS_WC_BIT 4 -#define HIB_CALCTL_CALEN_BIT 0 -#define HIB_CALCTL_CAL24_BIT 2 - -#define WRC !check_reg_bit( registers.hib_ctl, HIB_CTL_WRC_BIT ) -#define WC !check_reg_bit( registers.hib_mis, HIB_MIS_WC_BIT ) - -#define MASK_SECOND 0x0000003F -#define MASK_MINUTE 0x00003F00 -#define MASK_HOUR 0x001f0000 -#define MASK_DAY_MONTH 0x0000001F -#define MASK_MONTH 0x00000F00 -#define MASK_YEAR 0x007f0000 - -#define GET_SECOND time_second % 60 -#define GET_HOUR time_second / 3600 -#define GET_MINUTE time_second / 60 - GET_HOUR * 60 - -#define SET_TIME (uint32_t)time->hour * 3600 + (uint32_t)time->minute * 60 + (uint32_t)time->second - -#define SECOND_IN_ONE_DAY 86400 - -#define RESET 0x00000000 -#define LOCK_KEY 0xA3359554 -#define SOFTWARE_RESET_KEY 0x05FA0004 - -/** - * @brief Writes specified value to - * specified register. - * - * @param[in] reg - register address. - * @param[in] _val - Value to be written. - */ -#define write_reg(reg,_val) (selected_reg(reg) = (_val)) - -/** - * @brief Returns value stored - * in a register. - * - * @param[in] reg - register address. - * - * @return Register(reg) value. - */ -#define read_reg(reg) (selected_reg(reg)) - -typedef struct -{ - hal_ll_base_addr_t* sysctl_rcgchib; - hal_ll_base_addr_t* hib_mis; - hal_ll_base_addr_t* hib_ctl; - hal_ll_base_addr_t* hib_im; - hal_ll_base_addr_t* hib_rtcld; - hal_ll_base_addr_t* nvic_apint; - hal_ll_base_addr_t* hib_rtcc; - hal_ll_base_addr_t* hib_lock; -} reg_t; - -reg_t registers = { SYSCTL_RCGCHIB_REG_ADDRESS, HIB_MIS_REG_ADDRESS, HIB_CTL_REG_ADDRESS, HIB_IM_REG_ADDRESS, HIB_RTCLD_REG_ADDRESS, NVIC_AP_REG_ADDRESS, HIB_RTCC_REG_ADDRESS, HIB_LOCK_REG_ADDRESS }; - -#ifdef __GNUC__ - -/** - * @brief Initialize the RTC module. - * @details Initialize the RTC module. - * @param None. - */ -void __attribute__ ((weak)) hal_ll_rtc_init(); - -/** - * @brief Start the RTC module. - * @details Continue the RTC module count from the stored value in the counter register. - * @param None. - * @return The function can return one of the values defined by - * hal_ll_rtc_err_t structure, which is size dependant on the architecture. - */ -err_t __attribute__ ((weak)) hal_ll_rtc_start(); - -/** - * @brief Stop the RTC module. - * @details Stop the RTC module count. - * @param None. - * @return The function can return one of the values defined by - * hal_ll_rtc_err_t structure, which is size dependant on the architecture. - */ -err_t __attribute__ ((weak)) hal_ll_rtc_stop(); - -/** - * @brief Reset the RTC module. - * @details Reset the RTC counter to the default values of 0h:0m:0s. - * @param None. - * @return The function can return one of the values defined by - * hal_ll_rtc_err_t structure, which is size dependant on the architecture. - */ -err_t __attribute__ ((weak)) hal_ll_rtc_reset(); - -/** - * @brief Configure time of RTC module. - * @details Configure time registers with the values from hal_ll_rtc_time_t structure. - * @param time hal_ll_rtc_time_t structure. - * @return The function can return one of the values defined by - * hal_ll_rtc_err_t structure, which is size dependant on the architecture. - */ -err_t __attribute__ ((weak)) hal_ll_rtc_set_time( hal_ll_rtc_time_t *time ); - -/** - * @brief Get time and date. - * @details Configure hal_ll_rtc_time_t structure with the values from time registers. - * @param time hal_ll_rtc_time_t structure. - * @return The function can return one of the values defined by - * hal_ll_rtc_err_t structure, which is size dependant on the architecture. - */ -err_t __attribute__((weak)) hal_ll_rtc_get_time( hal_ll_rtc_time_t *rtc ); - -/** - * @brief Preforms system reset. - * @details Resets the core and all on-chip peripherals except the Debug - * interface. - * @param None. - * @warning System reset affects core and periferals, - * depending on the architecture you will need to reconfigure opened modules. - */ -void __attribute__ ((weak)) hal_ll_rtc_system_reset(); - -#endif - -void hal_ll_rtc_init() { - set_reg_bit( registers.sysctl_rcgchib, SYSCTL_RCGCHIB_R0_BIT ); - if ( !check_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN ) ) { - set_reg_bit( registers.hib_im, HIB_IM_WC_BIT ); - while ( WRC ); - set_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN_BIT ); - while ( WC ); - } -} - -err_t hal_ll_rtc_start() { - while ( WRC ); - set_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ); - while ( WRC ); - if ( check_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ) ) { - return HAL_LL_RTC_SUCCESS; - } - return HAL_LL_RTC_ERROR; -} - -err_t hal_ll_rtc_stop() { - while ( WRC ); - clear_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ); - while ( WRC ); - if ( check_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ) ) { - return HAL_LL_RTC_ERROR; - } - return HAL_LL_RTC_SUCCESS; -} - -err_t hal_ll_rtc_reset() { - if ( !check_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN_BIT ) ) { - return HAL_LL_RTC_ERROR; - } - if ( HAL_LL_RTC_ERROR == hal_ll_rtc_stop() ) { - return HAL_LL_RTC_ERROR; - } - if ( registers.hib_lock ) { - write_reg( registers.hib_lock, LOCK_KEY ); - } - while ( WRC ); - write_reg( registers.hib_rtcld, RESET ); - if ( HAL_LL_RTC_ERROR == hal_ll_rtc_start() ) { - return HAL_LL_RTC_ERROR; - } - return HAL_LL_RTC_SUCCESS; -} - -err_t hal_ll_rtc_set_time( hal_ll_rtc_time_t *time ) { - uint32_t value; - if ( !check_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN_BIT ) ) { - return HAL_LL_RTC_ERROR; - } - if ( HAL_LL_RTC_ERROR == hal_ll_rtc_stop() ) { - return HAL_LL_RTC_ERROR; - } - if ( registers.hib_lock ) { - write_reg( registers.hib_lock, LOCK_KEY ); - } - value = SET_TIME; - while ( WRC ); - write_reg( registers.hib_rtcld, value ); - while ( WRC ); - if ( read_reg( registers.hib_rtcc ) != value ) { - return HAL_LL_RTC_ERROR; - } - if ( HAL_LL_RTC_ERROR == hal_ll_rtc_start() ) { - return HAL_LL_RTC_ERROR; - } - return HAL_LL_RTC_SUCCESS; -} - -err_t hal_ll_rtc_get_time( hal_ll_rtc_time_t *time ) { - uint32_t time_second = read_reg( registers.hib_rtcc ); - if ( registers.hib_lock ) { - write_reg( registers.hib_lock, LOCK_KEY ); - } - while ( time_second >= SECOND_IN_ONE_DAY ) { - while ( WRC ); - write_reg( registers.hib_rtcld, time_second - SECOND_IN_ONE_DAY ); - while ( WRC ); - time_second = read_reg( registers.hib_rtcc ); - } - time->second = GET_SECOND; - time->minute = GET_MINUTE; - time->hour = GET_HOUR; - return HAL_LL_RTC_SUCCESS; -} - -void hal_ll_rtc_system_reset() { - write_reg( registers.nvic_apint, SOFTWARE_RESET_KEY ); -} diff --git a/targets/arm/mikroe/renesas/src/rtc/implementation_2/hal_ll_rtc.c b/targets/arm/mikroe/renesas/src/rtc/implementation_2/hal_ll_rtc.c deleted file mode 100644 index 54b8c57b39..0000000000 --- a/targets/arm/mikroe/renesas/src/rtc/implementation_2/hal_ll_rtc.c +++ /dev/null @@ -1,265 +0,0 @@ -/**************************************************************************** -** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. -** Contact: https://www.mikroe.com/contact -** -** This file is part of the mikroSDK package -** -** Commercial License Usage -** -** Licensees holding valid commercial NECTO compilers AI licenses may use this -** file in accordance with the commercial license agreement provided with the -** Software or, alternatively, in accordance with the terms contained in -** a written agreement between you and The MikroElektronika Company. -** For licensing terms and conditions see -** https://www.mikroe.com/legal/software-license-agreement. -** For further information use the contact form at -** https://www.mikroe.com/contact. -** -** -** GNU Lesser General Public License Usage -** -** Alternatively, this file may be used for -** non-commercial projects under the terms of the GNU Lesser -** General Public License version 3 as published by the Free Software -** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. -** -** The above copyright notice and this permission notice shall be -** included in all copies or substantial portions of the Software. -** -** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT -** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE -** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -** -****************************************************************************/ -/*! - * @file hal_ll_rtc.c - * @brief Rtc HAL LOW LEVEL layer implementation. - */ - -#include "hal_ll_rtc.h" - -/** - * Return values - */ -typedef enum -{ - HAL_LL_RTC_SUCCESS = 0, - HAL_LL_RTC_ERROR = (-1) -} hal_ll_rtc_err_t; - -#define SYSCTL_RCGCHIB_R0_BIT 0 -#define HIB_IM_WC_BIT 4 -#define HIB_CTL_RTCEN_BIT 0 -#define HIB_CTL_CLK32EN_BIT 6 -#define HIB_CTL_WRC_BIT 31 -#define HIB_MIS_WC_BIT 4 -#define HIB_CALCTL_CALEN_BIT 0 -#define HIB_CALCTL_CAL24_BIT 2 - -#define WRC !check_reg_bit( registers.hib_ctl, HIB_CTL_WRC_BIT ) -#define WC !check_reg_bit( registers.hib_mis, HIB_MIS_WC_BIT ) - -#define MASK_SECOND 0x0000003F -#define MASK_MINUTE 0x00003F00 -#define MASK_HOUR 0x001f0000 -#define MASK_DAY_MONTH 0x0000001F -#define MASK_MONTH 0x00000F00 -#define MASK_YEAR 0x007f0000 - -#define GET_SECOND time_second % 60 -#define GET_MINUTE time_second / 60 - GET_HOUR * 60 -#define GET_HOUR time_second / 3600 - -#define SET_TIME (uint32_t)time->hour * 3600 + (uint32_t)time->minute * 60 + (uint32_t)time->second - -#define SECOND_IN_ONE_DAY 86400 - -#define RESET 0x00000000 -#define SOFTWARE_RESET_KEY 0x05FA0004 - -/** - * @brief Writes specified value to - * specified register. - * - * @param[in] reg - register address. - * @param[in] _val - Value to be written. - */ -#define write_reg(reg,_val) (selected_reg(reg) = (_val)) - -/** - * @brief Returns value stored - * in a register. - * - * @param[in] reg - register address. - * - * @return Register(reg) value. - */ -#define read_reg(reg) (selected_reg(reg)) - -typedef struct -{ - hal_ll_base_addr_t* sysctl_rcgchib; - hal_ll_base_addr_t* hib_mis; - hal_ll_base_addr_t* hib_ctl; - hal_ll_base_addr_t* hib_im; - hal_ll_base_addr_t* hib_rtcld; - hal_ll_base_addr_t* nvic_apint; - hal_ll_base_addr_t* hib_rtcc; -} reg_t; - -reg_t registers = { SYSCTL_RCGCHIB_REG_ADDRESS, HIB_MIS_REG_ADDRESS, HIB_CTL_REG_ADDRESS, HIB_IM_REG_ADDRESS, HIB_RTCLD_REG_ADDRESS, NVIC_AP_REG_ADDRESS, HIB_RTCC_REG_ADDRESS }; - -#ifdef __GNUC__ - -/** - * @brief Initialize the RTC module. - * @details Initialize the RTC module. - * @param None. - */ -void __attribute__ ((weak)) hal_ll_rtc_init(); - -/** - * @brief Start the RTC module. - * @details Continue the RTC module count from the stored value in the counter register. - * @param None. - * @return The function can return one of the values defined by - * hal_ll_rtc_err_t structure, which is size dependant on the architecture. - */ -err_t __attribute__ ((weak)) hal_ll_rtc_start(); - -/** - * @brief Stop the RTC module. - * @details Stop the RTC module count. - * @param None. - * @return The function can return one of the values defined by - * hal_ll_rtc_err_t structure, which is size dependant on the architecture. - */ -err_t __attribute__ ((weak)) hal_ll_rtc_stop(); - -/** - * @brief Reset the RTC module. - * @details Reset the RTC counter to the default values of 0h:0m:0s. - * @param None. - * @return The function can return one of the values defined by - * hal_ll_rtc_err_t structure, which is size dependant on the architecture. - */ -err_t __attribute__ ((weak)) hal_ll_rtc_reset(); - -/** - * @brief Configure time of RTC module. - * @details Configure time registers with the values from hal_ll_rtc_time_t structure. - * @param time hal_ll_rtc_time_t structure. - * @return The function can return one of the values defined by - * hal_ll_rtc_err_t structure, which is size dependant on the architecture. - */ -err_t __attribute__ ((weak)) hal_ll_rtc_set_time( hal_ll_rtc_time_t *time ); - -/** - * @brief Get time and date. - * @details Configure hal_ll_rtc_time_t structure with the values from time registers. - * @param time hal_ll_rtc_time_t structure. - * @return The function can return one of the values defined by - * hal_ll_rtc_err_t structure, which is size dependant on the architecture. - */ -err_t __attribute__((weak)) hal_ll_rtc_get_time( hal_ll_rtc_time_t *rtc ); - -/** - * @brief Preforms system reset. - * @details Resets the core and all on-chip peripherals except the Debug - * interface. - * @param None. - * @warning System reset affects core and periferals, - * depending on the architecture you will need to reconfigure opened modules. - */ -void __attribute__ ((weak)) hal_ll_rtc_system_reset(); - -#endif - -void hal_ll_rtc_init() { - set_reg_bit( registers.sysctl_rcgchib, SYSCTL_RCGCHIB_R0_BIT ); - if ( !check_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN ) ) { - set_reg_bit( registers.hib_im, HIB_IM_WC_BIT ); - while ( WRC ); - set_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN_BIT ); - while ( WC ); - } -} - -err_t hal_ll_rtc_start() { - while ( WRC ); - set_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ); - while ( WRC ); - if ( check_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ) ) { - return HAL_LL_RTC_SUCCESS; - } - return HAL_LL_RTC_ERROR; -} - -err_t hal_ll_rtc_stop() { - while ( WRC ); - clear_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ); - while ( WRC ); - if ( check_reg_bit( registers.hib_ctl, HIB_CTL_RTCEN_BIT ) ) { - return HAL_LL_RTC_ERROR; - } - return HAL_LL_RTC_SUCCESS; -} - -err_t hal_ll_rtc_reset() { - if ( !check_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN_BIT ) ) { - return HAL_LL_RTC_ERROR; - } - if ( HAL_LL_RTC_ERROR == hal_ll_rtc_stop() ) { - return HAL_LL_RTC_ERROR; - } - while ( WRC ); - write_reg( registers.hib_rtcld, RESET ); - if ( HAL_LL_RTC_ERROR == hal_ll_rtc_start() ) { - return HAL_LL_RTC_ERROR; - } - return HAL_LL_RTC_SUCCESS; -} - -err_t hal_ll_rtc_set_time( hal_ll_rtc_time_t *time ) { - uint32_t value; - if ( !check_reg_bit( registers.hib_ctl, HIB_CTL_CLK32EN_BIT ) ) { - return HAL_LL_RTC_ERROR; - } - if ( HAL_LL_RTC_ERROR == hal_ll_rtc_stop() ) { - return HAL_LL_RTC_ERROR; - } - value = SET_TIME; - while ( WRC ); - write_reg( registers.hib_rtcld, value ); - while ( WRC ); - if ( read_reg( registers.hib_rtcc ) != value ) { - return HAL_LL_RTC_ERROR; - } - if ( HAL_LL_RTC_ERROR == hal_ll_rtc_start() ) { - return HAL_LL_RTC_ERROR; - } - return HAL_LL_RTC_SUCCESS; -} - -err_t hal_ll_rtc_get_time( hal_ll_rtc_time_t *time ) { - uint32_t time_second = read_reg( registers.hib_rtcc ); - while ( time_second >= SECOND_IN_ONE_DAY ) { - while ( WRC ); - write_reg( registers.hib_rtcld, time_second - SECOND_IN_ONE_DAY ); - while ( WRC ); - time_second = read_reg( registers.hib_rtcc ); - } - time->second = GET_SECOND; - time->minute = GET_MINUTE; - time->hour = GET_HOUR; - return HAL_LL_RTC_SUCCESS; -} - -void hal_ll_rtc_system_reset() { - write_reg( registers.nvic_apint, SOFTWARE_RESET_KEY ); -} From 901807628ba4d8522fa361477db3811da85e9652 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Mon, 4 Aug 2025 15:11:13 +0200 Subject: [PATCH 45/62] mcu defs added --- .../RENESAS/R7FA4M1AB2CLJ/mcu_definitions.h | 339 ++++++++++++++++++ .../RENESAS/R7FA4M1AB3CFL/mcu_definitions.h | 225 ++++++++++++ .../RENESAS/R7FA4M1AB3CFM/mcu_definitions.h | 250 ++++++------- .../RENESAS/R7FA4M1AB3CFP/mcu_definitions.h | 339 ++++++++++++++++++ .../RENESAS/R7FA4M1AB3CNB/mcu_definitions.h | 272 ++++++++++++++ .../RENESAS/R7FA4M1AB3CNE/mcu_definitions.h | 225 ++++++++++++ .../RENESAS/R7FA4M1AB3CNF/mcu_definitions.h | 200 +++++++++++ 7 files changed, 1716 insertions(+), 134 deletions(-) create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB2CLJ/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFL/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFP/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNB/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNE/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNF/mcu_definitions.h diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB2CLJ/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB2CLJ/mcu_definitions.h new file mode 100644 index 0000000000..d88846319b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB2CLJ/mcu_definitions.h @@ -0,0 +1,339 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#include "mcu_reg_addresses.h" + +//ADC +#define ADC0_P000_AN000 +#define ADC0_P001_AN001 +#define ADC0_P002_AN002 +#define ADC0_P003_AN003 +#define ADC0_P004_AN004 +#define ADC0_P005_AN011 +#define ADC0_P006_AN012 +#define ADC0_P007_AN013 +#define ADC0_P008_AN014 +#define ADC0_P010_AN005 +#define ADC0_P011_AN006 +#define ADC0_P012_AN007 +#define ADC0_P013_AN008 +#define ADC0_P014_AN009 +#define ADC0_P015_AN010 +#define ADC0_P100_AN022 +#define ADC0_P101_AN021 +#define ADC0_P102_AN020 +#define ADC0_P103_AN019 +#define ADC0_P500_AN016 +#define ADC0_P501_AN017 +#define ADC0_P502_AN018 +#define ADC0_P503_AN023 +#define ADC0_P504_AN024 +#define ADC0_P505_AN025 + +#define ADC_MODULE_0 1 + +#define ADC_MODULE_COUNT 1 +//EOF ADC + +//I2C +#define I2C0_SCL_P204_AF7 +#define I2C0_SCL_P400_AF7 +#define I2C0_SCL_P408_AF7 +#define I2C0_SDA_P401_AF7 +#define I2C0_SDA_P407_AF7 +#define I2C1_SCL_P100_AF7 +#define I2C1_SCL_P205_AF7 +#define I2C1_SDA_P101_AF7 +#define I2C1_SDA_P206_AF7 + +#define I2C_MODULE_0 1 +#define I2C_MODULE_1 2 + +#define I2C_MODULE_COUNT 2 +//EOF I2C + +//UART +#define UART0_RX_P100_AF4 +#define UART0_RX_P104_AF4 +#define UART0_RX_P206_AF4 +#define UART0_RX_P410_AF4 +#define UART0_TX_P101_AF4 +#define UART0_TX_P205_AF4 +#define UART0_TX_P411_AF4 +#define UART1_RX_P212_AF5 +#define UART1_RX_P402_AF5 +#define UART1_RX_P502_AF5 +#define UART1_RX_P708_AF5 +#define UART1_TX_P213_AF5 +#define UART1_TX_P401_AF5 +#define UART1_TX_P501_AF5 +#define UART2_RX_P301_AF4 +#define UART2_TX_P102_AF4 +#define UART2_TX_P112_AF4 +#define UART2_TX_P302_AF4 +#define UART9_RX_P110_AF5 +#define UART9_RX_P202_AF5 +#define UART9_RX_P408_AF5 +#define UART9_RX_P601_AF5 +#define UART9_TX_P109_AF5 +#define UART9_TX_P203_AF5 +#define UART9_TX_P409_AF5 +#define UART9_TX_P602_AF5 + +#define UART_MODULE_0 1 +#define UART_MODULE_1 2 +#define UART_MODULE_2 3 +#define UART_MODULE_9 10 + +#define UART_MODULE_COUNT 4 +//EOF UART + +//SPI +#define SPI0_MISO_P100_AF6 +#define SPI0_MISO_P410_AF6 +#define SPI0_MOSI_P101_AF6 +#define SPI0_MOSI_P411_AF6 +#define SPI0_SCK_P102_AF6 +#define SPI0_SCK_P412_AF6 +#define SPI1_MISO_P110_AF6 +#define SPI1_MISO_P202_AF6 +#define SPI1_MOSI_P109_AF6 +#define SPI1_MOSI_P203_AF6 +#define SPI1_SCK_P111_AF6 +#define SPI1_SCK_P204_AF6 + +#define SPI_MODULE_0 1 +#define SPI_MODULE_1 2 + +#define SPI_MODULE_COUNT 2 +//EOF SPI + +//TIM +#define TIM0_P106_CHB_AF3 +#define TIM0_P107_CHA_AF3 +#define TIM0_P108_CHB_AF3 +#define TIM0_P212_CHB_AF3 +#define TIM0_P213_CHA_AF3 +#define TIM0_P300_CHA_AF3 +#define TIM0_P414_CHB_AF3 +#define TIM0_P415_CHA_AF3 +#define TIM1_P104_CHB_AF3 +#define TIM1_P105_CHA_AF3 +#define TIM1_P109_CHA_AF3 +#define TIM1_P110_CHB_AF3 +#define TIM1_P405_CHA_AF3 +#define TIM1_P406_CHB_AF3 +#define TIM2_P102_CHB_AF3 +#define TIM2_P103_CHA_AF3 +#define TIM2_P113_CHA_AF3 +#define TIM2_P114_CHB_AF3 +#define TIM2_P500_CHA_AF3 +#define TIM2_P501_CHB_AF3 +#define TIM3_P111_CHA_AF3 +#define TIM3_P112_CHB_AF3 +#define TIM3_P403_CHA_AF3 +#define TIM3_P404_CHB_AF3 +#define TIM3_P502_CHB_AF3 +#define TIM4_P115_CHA_AF3 +#define TIM4_P204_CHB_AF3 +#define TIM4_P205_CHA_AF3 +#define TIM4_P301_CHB_AF3 +#define TIM4_P302_CHA_AF3 +#define TIM4_P608_CHB_AF3 +#define TIM5_P100_CHB_AF3 +#define TIM5_P101_CHA_AF3 +#define TIM5_P202_CHB_AF3 +#define TIM5_P203_CHA_AF3 +#define TIM5_P408_CHB_AF3 +#define TIM5_P409_CHA_AF3 +#define TIM5_P609_CHA_AF3 +#define TIM5_P610_CHB_AF3 +#define TIM6_P400_CHA_AF3 +#define TIM6_P401_CHB_AF3 +#define TIM6_P410_CHB_AF3 +#define TIM6_P411_CHA_AF3 +#define TIM6_P600_CHB_AF3 +#define TIM6_P601_CHA_AF3 +#define TIM7_P303_CHB_AF3 +#define TIM7_P304_CHA_AF3 +#define TIM7_P602_CHB_AF3 +#define TIM7_P603_CHA_AF3 + +#define TIM_MODULE_0 1 +#define TIM_MODULE_1 2 +#define TIM_MODULE_2 3 +#define TIM_MODULE_3 4 +#define TIM_MODULE_4 5 +#define TIM_MODULE_5 6 +#define TIM_MODULE_6 7 +#define TIM_MODULE_7 8 + +#define TIM_MODULE_COUNT 8 +//EOF TIM + +//GPIO +#define __P000_CN +#define __P001_CN +#define __P002_CN +#define __P003_CN +#define __P004_CN +#define __P005_CN +#define __P006_CN +#define __P007_CN +#define __P008_CN +#define __P010_CN +#define __P011_CN +#define __P012_CN +#define __P013_CN +#define __P014_CN +#define __P015_CN +#define __P100_CN +#define __P101_CN +#define __P102_CN +#define __P103_CN +#define __P104_CN +#define __P105_CN +#define __P106_CN +#define __P107_CN +#define __P108_CN +#define __P109_CN +#define __P110_CN +#define __P111_CN +#define __P112_CN +#define __P113_CN +#define __P114_CN +#define __P115_CN +#define __P200_CN +#define __P201_CN +#define __P202_CN +#define __P203_CN +#define __P204_CN +#define __P205_CN +#define __P206_CN +#define __P212_CN +#define __P213_CN +#define __P214_CN +#define __P215_CN +#define __P300_CN +#define __P301_CN +#define __P302_CN +#define __P303_CN +#define __P304_CN +#define __P305_CN +#define __P306_CN +#define __P307_CN +#define __P400_CN +#define __P401_CN +#define __P402_CN +#define __P403_CN +#define __P404_CN +#define __P405_CN +#define __P406_CN +#define __P407_CN +#define __P408_CN +#define __P409_CN +#define __P410_CN +#define __P411_CN +#define __P412_CN +#define __P413_CN +#define __P414_CN +#define __P415_CN +#define __P500_CN +#define __P501_CN +#define __P502_CN +#define __P503_CN +#define __P504_CN +#define __P505_CN +#define __P600_CN +#define __P601_CN +#define __P602_CN +#define __P603_CN +#define __P608_CN +#define __P609_CN +#define __P610_CN +#define __P708_CN +#define __P808_CN +#define __P809_CN +#define __P914_CN +#define __P915_CN + +#define __PORT_0_CN +#define __PORT_1_CN +#define __PORT_2_CN +#define __PORT_3_CN +#define __PORT_4_CN +#define __PORT_5_CN +#define __PORT_6_CN +#define __PORT_7_CN +#define __PORT_8_CN +#define __PORT_9_CN + +#define PORT_SIZE (16) +#define PORT_COUNT (10) +//EOF GPIO + +//IVT_TABLE +#define UART0_TXI_NVIC 0 +#define UART0_TXI_EVENT 0x99 +#define UART0_RXI_NVIC 1 +#define UART0_RXI_EVENT 0x98 +#define UART1_TXI_NVIC 2 +#define UART1_TXI_EVENT 0x9F +#define UART1_RXI_NVIC 3 +#define UART1_RXI_EVENT 0x9E +#define UART2_TXI_NVIC 4 +#define UART2_TXI_EVENT 0xA4 +#define UART2_RXI_NVIC 5 +#define UART2_RXI_EVENT 0xA3 +#define UART9_TXI_NVIC 18 +#define UART9_TXI_EVENT 0xA9 +#define UART9_RXI_NVIC 19 +#define UART9_RXI_EVENT 0xA8 +//EOF IVT_TABLE + + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFL/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFL/mcu_definitions.h new file mode 100644 index 0000000000..197ec8a89f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFL/mcu_definitions.h @@ -0,0 +1,225 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#include "mcu_reg_addresses.h" + +//ADC +#define ADC0_P000_AN000 +#define ADC0_P001_AN001 +#define ADC0_P002_AN002 +#define ADC0_P010_AN005 +#define ADC0_P011_AN006 +#define ADC0_P012_AN007 +#define ADC0_P013_AN008 +#define ADC0_P014_AN009 +#define ADC0_P015_AN010 +#define ADC0_P100_AN022 +#define ADC0_P101_AN021 +#define ADC0_P102_AN020 +#define ADC0_P103_AN019 +#define ADC0_P500_AN016 + +#define ADC_MODULE_0 1 + +#define ADC_MODULE_COUNT 1 +//EOF ADC + +//I2C +#define I2C0_SCL_P400_AF7 +#define I2C0_SCL_P408_AF7 +#define I2C0_SDA_P407_AF7 +#define I2C1_SCL_P100_AF7 +#define I2C1_SDA_P101_AF7 +#define I2C1_SDA_P206_AF7 + +#define I2C_MODULE_0 1 +#define I2C_MODULE_1 2 + +#define I2C_MODULE_COUNT 2 +//EOF I2C + +//UART +#define UART0_RX_P100_AF4 +#define UART0_RX_P104_AF4 +#define UART0_RX_P206_AF4 +#define UART0_TX_P101_AF4 +#define UART1_RX_P212_AF5 +#define UART1_TX_P213_AF5 +#define UART2_RX_P301_AF4 +#define UART2_TX_P102_AF4 +#define UART2_TX_P112_AF4 +#define UART2_TX_P302_AF4 +#define UART9_RX_P110_AF5 +#define UART9_RX_P408_AF5 +#define UART9_TX_P109_AF5 +#define UART9_TX_P409_AF5 + +#define UART_MODULE_0 1 +#define UART_MODULE_1 2 +#define UART_MODULE_2 3 +#define UART_MODULE_9 10 + +#define UART_MODULE_COUNT 4 +//EOF UART + +//SPI +#define SPI0_MISO_P100_AF6 +#define SPI0_MOSI_P101_AF6 +#define SPI0_SCK_P102_AF6 +#define SPI1_MISO_P110_AF6 +#define SPI1_MOSI_P109_AF6 +#define SPI1_SCK_P111_AF6 + +#define SPI_MODULE_0 1 +#define SPI_MODULE_1 2 + +#define SPI_MODULE_COUNT 2 +//EOF SPI + +//TIM +#define TIM0_P108_CHB_AF3 +#define TIM0_P212_CHB_AF3 +#define TIM0_P213_CHA_AF3 +#define TIM0_P300_CHA_AF3 +#define TIM1_P104_CHB_AF3 +#define TIM1_P109_CHA_AF3 +#define TIM1_P110_CHB_AF3 +#define TIM2_P102_CHB_AF3 +#define TIM2_P103_CHA_AF3 +#define TIM2_P500_CHA_AF3 +#define TIM3_P111_CHA_AF3 +#define TIM3_P112_CHB_AF3 +#define TIM4_P301_CHB_AF3 +#define TIM4_P302_CHA_AF3 +#define TIM5_P100_CHB_AF3 +#define TIM5_P101_CHA_AF3 +#define TIM5_P408_CHB_AF3 +#define TIM5_P409_CHA_AF3 +#define TIM6_P400_CHA_AF3 + +#define TIM_MODULE_0 1 +#define TIM_MODULE_1 2 +#define TIM_MODULE_2 3 +#define TIM_MODULE_3 4 +#define TIM_MODULE_4 5 +#define TIM_MODULE_5 6 +#define TIM_MODULE_6 7 + +#define TIM_MODULE_COUNT 7 +//EOF TIM + +//GPIO +#define __P000_CN +#define __P001_CN +#define __P002_CN +#define __P010_CN +#define __P011_CN +#define __P012_CN +#define __P013_CN +#define __P014_CN +#define __P015_CN +#define __P100_CN +#define __P101_CN +#define __P102_CN +#define __P103_CN +#define __P104_CN +#define __P108_CN +#define __P109_CN +#define __P110_CN +#define __P111_CN +#define __P112_CN +#define __P200_CN +#define __P201_CN +#define __P206_CN +#define __P212_CN +#define __P213_CN +#define __P214_CN +#define __P215_CN +#define __P300_CN +#define __P301_CN +#define __P302_CN +#define __P400_CN +#define __P407_CN +#define __P408_CN +#define __P409_CN +#define __P500_CN +#define __P914_CN +#define __P915_CN + +#define __PORT_0_CN +#define __PORT_1_CN +#define __PORT_2_CN +#define __PORT_3_CN +#define __PORT_4_CN +#define __PORT_5_CN +#define __PORT_9_CN + +#define PORT_SIZE (16) +#define PORT_COUNT (7) +//EOF GPIO + +//IVT_TABLE +#define UART0_TXI_NVIC 0 +#define UART0_TXI_EVENT 0x99 +#define UART0_RXI_NVIC 1 +#define UART0_RXI_EVENT 0x98 +#define UART1_TXI_NVIC 2 +#define UART1_TXI_EVENT 0x9F +#define UART1_RXI_NVIC 3 +#define UART1_RXI_EVENT 0x9E +#define UART2_TXI_NVIC 4 +#define UART2_TXI_EVENT 0xA4 +#define UART2_RXI_NVIC 5 +#define UART2_RXI_EVENT 0xA3 +#define UART9_TXI_NVIC 18 +#define UART9_TXI_EVENT 0xA9 +#define UART9_RXI_NVIC 19 +#define UART9_RXI_EVENT 0xA8 +//EOF IVT_TABLE + + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h index 60ceb2baac..d116e5cab2 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFM/mcu_definitions.h @@ -44,33 +44,72 @@ #ifndef _MCU_DEFINITIONS_H_ #define _MCU_DEFINITIONS_H_ +#include "mcu_reg_addresses.h" //ADC -#define ADC_MODULE_0 (1) - -#define ADC_AN000_P000 -#define ADC_AN007_P012 -#define ADC_AN018_P502 +#define ADC0_P000_AN000 +#define ADC0_P001_AN001 +#define ADC0_P002_AN002 +#define ADC0_P003_AN003 +#define ADC0_P004_AN004 +#define ADC0_P010_AN005 +#define ADC0_P011_AN006 +#define ADC0_P012_AN007 +#define ADC0_P013_AN008 +#define ADC0_P014_AN009 +#define ADC0_P015_AN010 +#define ADC0_P100_AN022 +#define ADC0_P101_AN021 +#define ADC0_P102_AN020 +#define ADC0_P103_AN019 +#define ADC0_P500_AN016 +#define ADC0_P501_AN017 +#define ADC0_P502_AN018 +#define ADC_MODULE_0 1 #define ADC_MODULE_COUNT 1 //EOF ADC //I2C -#define I2C_MODULE_0 (1) -#define I2C_MODULE_1 (2) +#define I2C0_SCL_P204_AF7 +#define I2C0_SCL_P400_AF7 +#define I2C0_SCL_P408_AF7 +#define I2C0_SDA_P401_AF7 +#define I2C0_SDA_P407_AF7 +#define I2C1_SCL_P100_AF7 +#define I2C1_SCL_P205_AF7 +#define I2C1_SDA_P101_AF7 +#define I2C1_SDA_P206_AF7 -#define I2C0_SCL_P205 -#define I2C0_SDA_P206 +#define I2C_MODULE_0 1 +#define I2C_MODULE_1 2 -#define I2C_MODULE_COUNT (2) +#define I2C_MODULE_COUNT 2 //EOF I2C //UART -#define UART0_RX_P410 -#define UART0_TX_P411 -#define UART1_TX_P401 -#define UART1_RX_P402 +#define UART0_RX_P100_AF4 +#define UART0_RX_P104_AF4 +#define UART0_RX_P206_AF4 +#define UART0_RX_P410_AF4 +#define UART0_TX_P101_AF4 +#define UART0_TX_P205_AF4 +#define UART0_TX_P411_AF4 +#define UART1_RX_P212_AF5 +#define UART1_RX_P402_AF5 +#define UART1_RX_P502_AF5 +#define UART1_TX_P213_AF5 +#define UART1_TX_P401_AF5 +#define UART1_TX_P501_AF5 +#define UART2_RX_P301_AF4 +#define UART2_TX_P102_AF4 +#define UART2_TX_P112_AF4 +#define UART2_TX_P302_AF4 +#define UART9_RX_P110_AF5 +#define UART9_RX_P408_AF5 +#define UART9_TX_P109_AF5 +#define UART9_TX_P409_AF5 #define UART_MODULE_0 1 #define UART_MODULE_1 2 @@ -81,27 +120,66 @@ //EOF UART //SPI -#define SPI0_SCK_P102_AF6 #define SPI0_MISO_P100_AF6 +#define SPI0_MISO_P410_AF6 #define SPI0_MOSI_P101_AF6 +#define SPI0_MOSI_P411_AF6 +#define SPI0_SCK_P102_AF6 +#define SPI1_MISO_P110_AF6 +#define SPI1_MOSI_P109_AF6 +#define SPI1_SCK_P111_AF6 +#define SPI1_SCK_P204_AF6 #define SPI_MODULE_0 1 +#define SPI_MODULE_1 2 -#define SPI_MODULE_COUNT 6 +#define SPI_MODULE_COUNT 2 //EOF SPI //TIM +#define TIM0_P106_CHB_AF3 +#define TIM0_P107_CHA_AF3 +#define TIM0_P108_CHB_AF3 +#define TIM0_P212_CHB_AF3 +#define TIM0_P213_CHA_AF3 +#define TIM0_P300_CHA_AF3 +#define TIM1_P104_CHB_AF3 +#define TIM1_P105_CHA_AF3 +#define TIM1_P109_CHA_AF3 +#define TIM1_P110_CHB_AF3 +#define TIM2_P102_CHB_AF3 +#define TIM2_P103_CHA_AF3 +#define TIM2_P113_CHA_AF3 +#define TIM2_P500_CHA_AF3 +#define TIM2_P501_CHB_AF3 +#define TIM3_P111_CHA_AF3 +#define TIM3_P112_CHB_AF3 +#define TIM3_P502_CHB_AF3 +#define TIM4_P204_CHB_AF3 +#define TIM4_P205_CHA_AF3 +#define TIM4_P301_CHB_AF3 +#define TIM4_P302_CHA_AF3 +#define TIM5_P100_CHB_AF3 +#define TIM5_P101_CHA_AF3 +#define TIM5_P408_CHB_AF3 +#define TIM5_P409_CHA_AF3 +#define TIM6_P400_CHA_AF3 +#define TIM6_P401_CHB_AF3 +#define TIM6_P410_CHB_AF3 +#define TIM6_P411_CHA_AF3 +#define TIM7_P303_CHB_AF3 +#define TIM7_P304_CHA_AF3 + #define TIM_MODULE_0 1 #define TIM_MODULE_1 2 #define TIM_MODULE_2 3 #define TIM_MODULE_3 4 #define TIM_MODULE_4 5 +#define TIM_MODULE_5 6 +#define TIM_MODULE_6 7 +#define TIM_MODULE_7 8 -#define TIM4_P302 -#define TIM0_P107 -#define TIM2_P102 - -#define TIM_MODULE_COUNT 12 +#define TIM_MODULE_COUNT 8 //EOF TIM //GPIO @@ -110,11 +188,6 @@ #define __P002_CN #define __P003_CN #define __P004_CN -#define __P005_CN -#define __P006_CN -#define __P007_CN -#define __P008_CN -#define __P009_CN #define __P010_CN #define __P011_CN #define __P012_CN @@ -135,20 +208,11 @@ #define __P111_CN #define __P112_CN #define __P113_CN -#define __P114_CN -#define __P115_CN #define __P200_CN #define __P201_CN -#define __P202_CN -#define __P203_CN #define __P204_CN #define __P205_CN #define __P206_CN -#define __P207_CN -#define __P208_CN -#define __P209_CN -#define __P210_CN -#define __P211_CN #define __P212_CN #define __P213_CN #define __P214_CN @@ -158,111 +222,17 @@ #define __P302_CN #define __P303_CN #define __P304_CN -#define __P305_CN -#define __P306_CN -#define __P307_CN -#define __P308_CN -#define __P309_CN -#define __P310_CN -#define __P311_CN -#define __P312_CN -#define __P313_CN -#define __P314_CN -#define __P315_CN #define __P400_CN #define __P401_CN #define __P402_CN -#define __P403_CN -#define __P404_CN -#define __P405_CN -#define __P406_CN #define __P407_CN #define __P408_CN #define __P409_CN #define __P410_CN #define __P411_CN -#define __P412_CN -#define __P413_CN -#define __P414_CN -#define __P415_CN #define __P500_CN #define __P501_CN #define __P502_CN -#define __P503_CN -#define __P504_CN -#define __P505_CN -#define __P506_CN -#define __P507_CN -#define __P508_CN -#define __P509_CN -#define __P510_CN -#define __P511_CN -#define __P512_CN -#define __P513_CN -#define __P514_CN -#define __P515_CN -#define __P600_CN -#define __P601_CN -#define __P602_CN -#define __P603_CN -#define __P604_CN -#define __P605_CN -#define __P606_CN -#define __P607_CN -#define __P608_CN -#define __P609_CN -#define __P610_CN -#define __P611_CN -#define __P612_CN -#define __P613_CN -#define __P614_CN -#define __P615_CN -#define __P700_CN -#define __P701_CN -#define __P702_CN -#define __P703_CN -#define __P704_CN -#define __P705_CN -#define __P706_CN -#define __P707_CN -#define __P708_CN -#define __P709_CN -#define __P710_CN -#define __P711_CN -#define __P712_CN -#define __P713_CN -#define __P714_CN -#define __P715_CN -#define __P800_CN -#define __P801_CN -#define __P802_CN -#define __P803_CN -#define __P804_CN -#define __P805_CN -#define __P806_CN -#define __P807_CN -#define __P808_CN -#define __P809_CN -#define __P810_CN -#define __P811_CN -#define __P812_CN -#define __P813_CN -#define __P814_CN -#define __P815_CN -#define __P900_CN -#define __P901_CN -#define __P902_CN -#define __P903_CN -#define __P904_CN -#define __P905_CN -#define __P906_CN -#define __P907_CN -#define __P908_CN -#define __P909_CN -#define __P910_CN -#define __P911_CN -#define __P912_CN -#define __P913_CN #define __P914_CN #define __P915_CN @@ -272,17 +242,29 @@ #define __PORT_3_CN #define __PORT_4_CN #define __PORT_5_CN -#define __PORT_6_CN -#define __PORT_7_CN -#define __PORT_8_CN #define __PORT_9_CN #define PORT_SIZE (16) -#define PORT_COUNT (10) +#define PORT_COUNT (7) //EOF GPIO //IVT_TABLE - +#define UART0_TXI_NVIC 0 +#define UART0_TXI_EVENT 0x99 +#define UART0_RXI_NVIC 1 +#define UART0_RXI_EVENT 0x98 +#define UART1_TXI_NVIC 2 +#define UART1_TXI_EVENT 0x9F +#define UART1_RXI_NVIC 3 +#define UART1_RXI_EVENT 0x9E +#define UART2_TXI_NVIC 4 +#define UART2_TXI_EVENT 0xA4 +#define UART2_RXI_NVIC 5 +#define UART2_RXI_EVENT 0xA3 +#define UART9_TXI_NVIC 18 +#define UART9_TXI_EVENT 0xA9 +#define UART9_RXI_NVIC 19 +#define UART9_RXI_EVENT 0xA8 //EOF IVT_TABLE diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFP/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFP/mcu_definitions.h new file mode 100644 index 0000000000..d88846319b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CFP/mcu_definitions.h @@ -0,0 +1,339 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#include "mcu_reg_addresses.h" + +//ADC +#define ADC0_P000_AN000 +#define ADC0_P001_AN001 +#define ADC0_P002_AN002 +#define ADC0_P003_AN003 +#define ADC0_P004_AN004 +#define ADC0_P005_AN011 +#define ADC0_P006_AN012 +#define ADC0_P007_AN013 +#define ADC0_P008_AN014 +#define ADC0_P010_AN005 +#define ADC0_P011_AN006 +#define ADC0_P012_AN007 +#define ADC0_P013_AN008 +#define ADC0_P014_AN009 +#define ADC0_P015_AN010 +#define ADC0_P100_AN022 +#define ADC0_P101_AN021 +#define ADC0_P102_AN020 +#define ADC0_P103_AN019 +#define ADC0_P500_AN016 +#define ADC0_P501_AN017 +#define ADC0_P502_AN018 +#define ADC0_P503_AN023 +#define ADC0_P504_AN024 +#define ADC0_P505_AN025 + +#define ADC_MODULE_0 1 + +#define ADC_MODULE_COUNT 1 +//EOF ADC + +//I2C +#define I2C0_SCL_P204_AF7 +#define I2C0_SCL_P400_AF7 +#define I2C0_SCL_P408_AF7 +#define I2C0_SDA_P401_AF7 +#define I2C0_SDA_P407_AF7 +#define I2C1_SCL_P100_AF7 +#define I2C1_SCL_P205_AF7 +#define I2C1_SDA_P101_AF7 +#define I2C1_SDA_P206_AF7 + +#define I2C_MODULE_0 1 +#define I2C_MODULE_1 2 + +#define I2C_MODULE_COUNT 2 +//EOF I2C + +//UART +#define UART0_RX_P100_AF4 +#define UART0_RX_P104_AF4 +#define UART0_RX_P206_AF4 +#define UART0_RX_P410_AF4 +#define UART0_TX_P101_AF4 +#define UART0_TX_P205_AF4 +#define UART0_TX_P411_AF4 +#define UART1_RX_P212_AF5 +#define UART1_RX_P402_AF5 +#define UART1_RX_P502_AF5 +#define UART1_RX_P708_AF5 +#define UART1_TX_P213_AF5 +#define UART1_TX_P401_AF5 +#define UART1_TX_P501_AF5 +#define UART2_RX_P301_AF4 +#define UART2_TX_P102_AF4 +#define UART2_TX_P112_AF4 +#define UART2_TX_P302_AF4 +#define UART9_RX_P110_AF5 +#define UART9_RX_P202_AF5 +#define UART9_RX_P408_AF5 +#define UART9_RX_P601_AF5 +#define UART9_TX_P109_AF5 +#define UART9_TX_P203_AF5 +#define UART9_TX_P409_AF5 +#define UART9_TX_P602_AF5 + +#define UART_MODULE_0 1 +#define UART_MODULE_1 2 +#define UART_MODULE_2 3 +#define UART_MODULE_9 10 + +#define UART_MODULE_COUNT 4 +//EOF UART + +//SPI +#define SPI0_MISO_P100_AF6 +#define SPI0_MISO_P410_AF6 +#define SPI0_MOSI_P101_AF6 +#define SPI0_MOSI_P411_AF6 +#define SPI0_SCK_P102_AF6 +#define SPI0_SCK_P412_AF6 +#define SPI1_MISO_P110_AF6 +#define SPI1_MISO_P202_AF6 +#define SPI1_MOSI_P109_AF6 +#define SPI1_MOSI_P203_AF6 +#define SPI1_SCK_P111_AF6 +#define SPI1_SCK_P204_AF6 + +#define SPI_MODULE_0 1 +#define SPI_MODULE_1 2 + +#define SPI_MODULE_COUNT 2 +//EOF SPI + +//TIM +#define TIM0_P106_CHB_AF3 +#define TIM0_P107_CHA_AF3 +#define TIM0_P108_CHB_AF3 +#define TIM0_P212_CHB_AF3 +#define TIM0_P213_CHA_AF3 +#define TIM0_P300_CHA_AF3 +#define TIM0_P414_CHB_AF3 +#define TIM0_P415_CHA_AF3 +#define TIM1_P104_CHB_AF3 +#define TIM1_P105_CHA_AF3 +#define TIM1_P109_CHA_AF3 +#define TIM1_P110_CHB_AF3 +#define TIM1_P405_CHA_AF3 +#define TIM1_P406_CHB_AF3 +#define TIM2_P102_CHB_AF3 +#define TIM2_P103_CHA_AF3 +#define TIM2_P113_CHA_AF3 +#define TIM2_P114_CHB_AF3 +#define TIM2_P500_CHA_AF3 +#define TIM2_P501_CHB_AF3 +#define TIM3_P111_CHA_AF3 +#define TIM3_P112_CHB_AF3 +#define TIM3_P403_CHA_AF3 +#define TIM3_P404_CHB_AF3 +#define TIM3_P502_CHB_AF3 +#define TIM4_P115_CHA_AF3 +#define TIM4_P204_CHB_AF3 +#define TIM4_P205_CHA_AF3 +#define TIM4_P301_CHB_AF3 +#define TIM4_P302_CHA_AF3 +#define TIM4_P608_CHB_AF3 +#define TIM5_P100_CHB_AF3 +#define TIM5_P101_CHA_AF3 +#define TIM5_P202_CHB_AF3 +#define TIM5_P203_CHA_AF3 +#define TIM5_P408_CHB_AF3 +#define TIM5_P409_CHA_AF3 +#define TIM5_P609_CHA_AF3 +#define TIM5_P610_CHB_AF3 +#define TIM6_P400_CHA_AF3 +#define TIM6_P401_CHB_AF3 +#define TIM6_P410_CHB_AF3 +#define TIM6_P411_CHA_AF3 +#define TIM6_P600_CHB_AF3 +#define TIM6_P601_CHA_AF3 +#define TIM7_P303_CHB_AF3 +#define TIM7_P304_CHA_AF3 +#define TIM7_P602_CHB_AF3 +#define TIM7_P603_CHA_AF3 + +#define TIM_MODULE_0 1 +#define TIM_MODULE_1 2 +#define TIM_MODULE_2 3 +#define TIM_MODULE_3 4 +#define TIM_MODULE_4 5 +#define TIM_MODULE_5 6 +#define TIM_MODULE_6 7 +#define TIM_MODULE_7 8 + +#define TIM_MODULE_COUNT 8 +//EOF TIM + +//GPIO +#define __P000_CN +#define __P001_CN +#define __P002_CN +#define __P003_CN +#define __P004_CN +#define __P005_CN +#define __P006_CN +#define __P007_CN +#define __P008_CN +#define __P010_CN +#define __P011_CN +#define __P012_CN +#define __P013_CN +#define __P014_CN +#define __P015_CN +#define __P100_CN +#define __P101_CN +#define __P102_CN +#define __P103_CN +#define __P104_CN +#define __P105_CN +#define __P106_CN +#define __P107_CN +#define __P108_CN +#define __P109_CN +#define __P110_CN +#define __P111_CN +#define __P112_CN +#define __P113_CN +#define __P114_CN +#define __P115_CN +#define __P200_CN +#define __P201_CN +#define __P202_CN +#define __P203_CN +#define __P204_CN +#define __P205_CN +#define __P206_CN +#define __P212_CN +#define __P213_CN +#define __P214_CN +#define __P215_CN +#define __P300_CN +#define __P301_CN +#define __P302_CN +#define __P303_CN +#define __P304_CN +#define __P305_CN +#define __P306_CN +#define __P307_CN +#define __P400_CN +#define __P401_CN +#define __P402_CN +#define __P403_CN +#define __P404_CN +#define __P405_CN +#define __P406_CN +#define __P407_CN +#define __P408_CN +#define __P409_CN +#define __P410_CN +#define __P411_CN +#define __P412_CN +#define __P413_CN +#define __P414_CN +#define __P415_CN +#define __P500_CN +#define __P501_CN +#define __P502_CN +#define __P503_CN +#define __P504_CN +#define __P505_CN +#define __P600_CN +#define __P601_CN +#define __P602_CN +#define __P603_CN +#define __P608_CN +#define __P609_CN +#define __P610_CN +#define __P708_CN +#define __P808_CN +#define __P809_CN +#define __P914_CN +#define __P915_CN + +#define __PORT_0_CN +#define __PORT_1_CN +#define __PORT_2_CN +#define __PORT_3_CN +#define __PORT_4_CN +#define __PORT_5_CN +#define __PORT_6_CN +#define __PORT_7_CN +#define __PORT_8_CN +#define __PORT_9_CN + +#define PORT_SIZE (16) +#define PORT_COUNT (10) +//EOF GPIO + +//IVT_TABLE +#define UART0_TXI_NVIC 0 +#define UART0_TXI_EVENT 0x99 +#define UART0_RXI_NVIC 1 +#define UART0_RXI_EVENT 0x98 +#define UART1_TXI_NVIC 2 +#define UART1_TXI_EVENT 0x9F +#define UART1_RXI_NVIC 3 +#define UART1_RXI_EVENT 0x9E +#define UART2_TXI_NVIC 4 +#define UART2_TXI_EVENT 0xA4 +#define UART2_RXI_NVIC 5 +#define UART2_RXI_EVENT 0xA3 +#define UART9_TXI_NVIC 18 +#define UART9_TXI_EVENT 0xA9 +#define UART9_RXI_NVIC 19 +#define UART9_RXI_EVENT 0xA8 +//EOF IVT_TABLE + + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNB/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNB/mcu_definitions.h new file mode 100644 index 0000000000..d116e5cab2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNB/mcu_definitions.h @@ -0,0 +1,272 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#include "mcu_reg_addresses.h" + +//ADC +#define ADC0_P000_AN000 +#define ADC0_P001_AN001 +#define ADC0_P002_AN002 +#define ADC0_P003_AN003 +#define ADC0_P004_AN004 +#define ADC0_P010_AN005 +#define ADC0_P011_AN006 +#define ADC0_P012_AN007 +#define ADC0_P013_AN008 +#define ADC0_P014_AN009 +#define ADC0_P015_AN010 +#define ADC0_P100_AN022 +#define ADC0_P101_AN021 +#define ADC0_P102_AN020 +#define ADC0_P103_AN019 +#define ADC0_P500_AN016 +#define ADC0_P501_AN017 +#define ADC0_P502_AN018 + +#define ADC_MODULE_0 1 + +#define ADC_MODULE_COUNT 1 +//EOF ADC + +//I2C +#define I2C0_SCL_P204_AF7 +#define I2C0_SCL_P400_AF7 +#define I2C0_SCL_P408_AF7 +#define I2C0_SDA_P401_AF7 +#define I2C0_SDA_P407_AF7 +#define I2C1_SCL_P100_AF7 +#define I2C1_SCL_P205_AF7 +#define I2C1_SDA_P101_AF7 +#define I2C1_SDA_P206_AF7 + +#define I2C_MODULE_0 1 +#define I2C_MODULE_1 2 + +#define I2C_MODULE_COUNT 2 +//EOF I2C + +//UART +#define UART0_RX_P100_AF4 +#define UART0_RX_P104_AF4 +#define UART0_RX_P206_AF4 +#define UART0_RX_P410_AF4 +#define UART0_TX_P101_AF4 +#define UART0_TX_P205_AF4 +#define UART0_TX_P411_AF4 +#define UART1_RX_P212_AF5 +#define UART1_RX_P402_AF5 +#define UART1_RX_P502_AF5 +#define UART1_TX_P213_AF5 +#define UART1_TX_P401_AF5 +#define UART1_TX_P501_AF5 +#define UART2_RX_P301_AF4 +#define UART2_TX_P102_AF4 +#define UART2_TX_P112_AF4 +#define UART2_TX_P302_AF4 +#define UART9_RX_P110_AF5 +#define UART9_RX_P408_AF5 +#define UART9_TX_P109_AF5 +#define UART9_TX_P409_AF5 + +#define UART_MODULE_0 1 +#define UART_MODULE_1 2 +#define UART_MODULE_2 3 +#define UART_MODULE_9 10 + +#define UART_MODULE_COUNT 4 +//EOF UART + +//SPI +#define SPI0_MISO_P100_AF6 +#define SPI0_MISO_P410_AF6 +#define SPI0_MOSI_P101_AF6 +#define SPI0_MOSI_P411_AF6 +#define SPI0_SCK_P102_AF6 +#define SPI1_MISO_P110_AF6 +#define SPI1_MOSI_P109_AF6 +#define SPI1_SCK_P111_AF6 +#define SPI1_SCK_P204_AF6 + +#define SPI_MODULE_0 1 +#define SPI_MODULE_1 2 + +#define SPI_MODULE_COUNT 2 +//EOF SPI + +//TIM +#define TIM0_P106_CHB_AF3 +#define TIM0_P107_CHA_AF3 +#define TIM0_P108_CHB_AF3 +#define TIM0_P212_CHB_AF3 +#define TIM0_P213_CHA_AF3 +#define TIM0_P300_CHA_AF3 +#define TIM1_P104_CHB_AF3 +#define TIM1_P105_CHA_AF3 +#define TIM1_P109_CHA_AF3 +#define TIM1_P110_CHB_AF3 +#define TIM2_P102_CHB_AF3 +#define TIM2_P103_CHA_AF3 +#define TIM2_P113_CHA_AF3 +#define TIM2_P500_CHA_AF3 +#define TIM2_P501_CHB_AF3 +#define TIM3_P111_CHA_AF3 +#define TIM3_P112_CHB_AF3 +#define TIM3_P502_CHB_AF3 +#define TIM4_P204_CHB_AF3 +#define TIM4_P205_CHA_AF3 +#define TIM4_P301_CHB_AF3 +#define TIM4_P302_CHA_AF3 +#define TIM5_P100_CHB_AF3 +#define TIM5_P101_CHA_AF3 +#define TIM5_P408_CHB_AF3 +#define TIM5_P409_CHA_AF3 +#define TIM6_P400_CHA_AF3 +#define TIM6_P401_CHB_AF3 +#define TIM6_P410_CHB_AF3 +#define TIM6_P411_CHA_AF3 +#define TIM7_P303_CHB_AF3 +#define TIM7_P304_CHA_AF3 + +#define TIM_MODULE_0 1 +#define TIM_MODULE_1 2 +#define TIM_MODULE_2 3 +#define TIM_MODULE_3 4 +#define TIM_MODULE_4 5 +#define TIM_MODULE_5 6 +#define TIM_MODULE_6 7 +#define TIM_MODULE_7 8 + +#define TIM_MODULE_COUNT 8 +//EOF TIM + +//GPIO +#define __P000_CN +#define __P001_CN +#define __P002_CN +#define __P003_CN +#define __P004_CN +#define __P010_CN +#define __P011_CN +#define __P012_CN +#define __P013_CN +#define __P014_CN +#define __P015_CN +#define __P100_CN +#define __P101_CN +#define __P102_CN +#define __P103_CN +#define __P104_CN +#define __P105_CN +#define __P106_CN +#define __P107_CN +#define __P108_CN +#define __P109_CN +#define __P110_CN +#define __P111_CN +#define __P112_CN +#define __P113_CN +#define __P200_CN +#define __P201_CN +#define __P204_CN +#define __P205_CN +#define __P206_CN +#define __P212_CN +#define __P213_CN +#define __P214_CN +#define __P215_CN +#define __P300_CN +#define __P301_CN +#define __P302_CN +#define __P303_CN +#define __P304_CN +#define __P400_CN +#define __P401_CN +#define __P402_CN +#define __P407_CN +#define __P408_CN +#define __P409_CN +#define __P410_CN +#define __P411_CN +#define __P500_CN +#define __P501_CN +#define __P502_CN +#define __P914_CN +#define __P915_CN + +#define __PORT_0_CN +#define __PORT_1_CN +#define __PORT_2_CN +#define __PORT_3_CN +#define __PORT_4_CN +#define __PORT_5_CN +#define __PORT_9_CN + +#define PORT_SIZE (16) +#define PORT_COUNT (7) +//EOF GPIO + +//IVT_TABLE +#define UART0_TXI_NVIC 0 +#define UART0_TXI_EVENT 0x99 +#define UART0_RXI_NVIC 1 +#define UART0_RXI_EVENT 0x98 +#define UART1_TXI_NVIC 2 +#define UART1_TXI_EVENT 0x9F +#define UART1_RXI_NVIC 3 +#define UART1_RXI_EVENT 0x9E +#define UART2_TXI_NVIC 4 +#define UART2_TXI_EVENT 0xA4 +#define UART2_RXI_NVIC 5 +#define UART2_RXI_EVENT 0xA3 +#define UART9_TXI_NVIC 18 +#define UART9_TXI_EVENT 0xA9 +#define UART9_RXI_NVIC 19 +#define UART9_RXI_EVENT 0xA8 +//EOF IVT_TABLE + + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNE/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNE/mcu_definitions.h new file mode 100644 index 0000000000..197ec8a89f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNE/mcu_definitions.h @@ -0,0 +1,225 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#include "mcu_reg_addresses.h" + +//ADC +#define ADC0_P000_AN000 +#define ADC0_P001_AN001 +#define ADC0_P002_AN002 +#define ADC0_P010_AN005 +#define ADC0_P011_AN006 +#define ADC0_P012_AN007 +#define ADC0_P013_AN008 +#define ADC0_P014_AN009 +#define ADC0_P015_AN010 +#define ADC0_P100_AN022 +#define ADC0_P101_AN021 +#define ADC0_P102_AN020 +#define ADC0_P103_AN019 +#define ADC0_P500_AN016 + +#define ADC_MODULE_0 1 + +#define ADC_MODULE_COUNT 1 +//EOF ADC + +//I2C +#define I2C0_SCL_P400_AF7 +#define I2C0_SCL_P408_AF7 +#define I2C0_SDA_P407_AF7 +#define I2C1_SCL_P100_AF7 +#define I2C1_SDA_P101_AF7 +#define I2C1_SDA_P206_AF7 + +#define I2C_MODULE_0 1 +#define I2C_MODULE_1 2 + +#define I2C_MODULE_COUNT 2 +//EOF I2C + +//UART +#define UART0_RX_P100_AF4 +#define UART0_RX_P104_AF4 +#define UART0_RX_P206_AF4 +#define UART0_TX_P101_AF4 +#define UART1_RX_P212_AF5 +#define UART1_TX_P213_AF5 +#define UART2_RX_P301_AF4 +#define UART2_TX_P102_AF4 +#define UART2_TX_P112_AF4 +#define UART2_TX_P302_AF4 +#define UART9_RX_P110_AF5 +#define UART9_RX_P408_AF5 +#define UART9_TX_P109_AF5 +#define UART9_TX_P409_AF5 + +#define UART_MODULE_0 1 +#define UART_MODULE_1 2 +#define UART_MODULE_2 3 +#define UART_MODULE_9 10 + +#define UART_MODULE_COUNT 4 +//EOF UART + +//SPI +#define SPI0_MISO_P100_AF6 +#define SPI0_MOSI_P101_AF6 +#define SPI0_SCK_P102_AF6 +#define SPI1_MISO_P110_AF6 +#define SPI1_MOSI_P109_AF6 +#define SPI1_SCK_P111_AF6 + +#define SPI_MODULE_0 1 +#define SPI_MODULE_1 2 + +#define SPI_MODULE_COUNT 2 +//EOF SPI + +//TIM +#define TIM0_P108_CHB_AF3 +#define TIM0_P212_CHB_AF3 +#define TIM0_P213_CHA_AF3 +#define TIM0_P300_CHA_AF3 +#define TIM1_P104_CHB_AF3 +#define TIM1_P109_CHA_AF3 +#define TIM1_P110_CHB_AF3 +#define TIM2_P102_CHB_AF3 +#define TIM2_P103_CHA_AF3 +#define TIM2_P500_CHA_AF3 +#define TIM3_P111_CHA_AF3 +#define TIM3_P112_CHB_AF3 +#define TIM4_P301_CHB_AF3 +#define TIM4_P302_CHA_AF3 +#define TIM5_P100_CHB_AF3 +#define TIM5_P101_CHA_AF3 +#define TIM5_P408_CHB_AF3 +#define TIM5_P409_CHA_AF3 +#define TIM6_P400_CHA_AF3 + +#define TIM_MODULE_0 1 +#define TIM_MODULE_1 2 +#define TIM_MODULE_2 3 +#define TIM_MODULE_3 4 +#define TIM_MODULE_4 5 +#define TIM_MODULE_5 6 +#define TIM_MODULE_6 7 + +#define TIM_MODULE_COUNT 7 +//EOF TIM + +//GPIO +#define __P000_CN +#define __P001_CN +#define __P002_CN +#define __P010_CN +#define __P011_CN +#define __P012_CN +#define __P013_CN +#define __P014_CN +#define __P015_CN +#define __P100_CN +#define __P101_CN +#define __P102_CN +#define __P103_CN +#define __P104_CN +#define __P108_CN +#define __P109_CN +#define __P110_CN +#define __P111_CN +#define __P112_CN +#define __P200_CN +#define __P201_CN +#define __P206_CN +#define __P212_CN +#define __P213_CN +#define __P214_CN +#define __P215_CN +#define __P300_CN +#define __P301_CN +#define __P302_CN +#define __P400_CN +#define __P407_CN +#define __P408_CN +#define __P409_CN +#define __P500_CN +#define __P914_CN +#define __P915_CN + +#define __PORT_0_CN +#define __PORT_1_CN +#define __PORT_2_CN +#define __PORT_3_CN +#define __PORT_4_CN +#define __PORT_5_CN +#define __PORT_9_CN + +#define PORT_SIZE (16) +#define PORT_COUNT (7) +//EOF GPIO + +//IVT_TABLE +#define UART0_TXI_NVIC 0 +#define UART0_TXI_EVENT 0x99 +#define UART0_RXI_NVIC 1 +#define UART0_RXI_EVENT 0x98 +#define UART1_TXI_NVIC 2 +#define UART1_TXI_EVENT 0x9F +#define UART1_RXI_NVIC 3 +#define UART1_RXI_EVENT 0x9E +#define UART2_TXI_NVIC 4 +#define UART2_TXI_EVENT 0xA4 +#define UART2_RXI_NVIC 5 +#define UART2_RXI_EVENT 0xA3 +#define UART9_TXI_NVIC 18 +#define UART9_TXI_EVENT 0xA9 +#define UART9_RXI_NVIC 19 +#define UART9_RXI_EVENT 0xA8 +//EOF IVT_TABLE + + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNF/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNF/mcu_definitions.h new file mode 100644 index 0000000000..1cecb5eb30 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/RENESAS/R7FA4M1AB3CNF/mcu_definitions.h @@ -0,0 +1,200 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#include "mcu_reg_addresses.h" + +//ADC +#define ADC0_P000_AN000 +#define ADC0_P001_AN001 +#define ADC0_P010_AN005 +#define ADC0_P011_AN006 +#define ADC0_P012_AN007 +#define ADC0_P013_AN008 +#define ADC0_P014_AN009 +#define ADC0_P015_AN010 +#define ADC0_P100_AN022 +#define ADC0_P101_AN021 +#define ADC0_P102_AN020 + +#define ADC_MODULE_0 1 + +#define ADC_MODULE_COUNT 1 +//EOF ADC + +//I2C +#define I2C0_SCL_P408_AF7 +#define I2C0_SDA_P407_AF7 +#define I2C1_SCL_P100_AF7 +#define I2C1_SDA_P101_AF7 + +#define I2C_MODULE_0 1 +#define I2C_MODULE_1 2 + +#define I2C_MODULE_COUNT 2 +//EOF I2C + +//UART +#define UART0_RX_P100_AF4 +#define UART0_TX_P101_AF4 +#define UART1_RX_P212_AF5 +#define UART1_TX_P213_AF5 +#define UART2_RX_P301_AF4 +#define UART2_TX_P102_AF4 +#define UART2_TX_P112_AF4 +#define UART9_RX_P110_AF5 +#define UART9_RX_P408_AF5 +#define UART9_TX_P109_AF5 + +#define UART_MODULE_0 1 +#define UART_MODULE_1 2 +#define UART_MODULE_2 3 +#define UART_MODULE_9 10 + +#define UART_MODULE_COUNT 4 +//EOF UART + +//SPI +#define SPI0_MISO_P100_AF6 +#define SPI0_MOSI_P101_AF6 +#define SPI0_SCK_P102_AF6 +#define SPI1_MISO_P110_AF6 +#define SPI1_MOSI_P109_AF6 +#define SPI1_SCK_P111_AF6 + +#define SPI_MODULE_0 1 +#define SPI_MODULE_1 2 + +#define SPI_MODULE_COUNT 2 +//EOF SPI + +//TIM +#define TIM0_P108_CHB_AF3 +#define TIM0_P212_CHB_AF3 +#define TIM0_P213_CHA_AF3 +#define TIM0_P300_CHA_AF3 +#define TIM1_P109_CHA_AF3 +#define TIM1_P110_CHB_AF3 +#define TIM2_P102_CHB_AF3 +#define TIM3_P111_CHA_AF3 +#define TIM3_P112_CHB_AF3 +#define TIM4_P301_CHB_AF3 +#define TIM5_P100_CHB_AF3 +#define TIM5_P101_CHA_AF3 +#define TIM5_P408_CHB_AF3 + +#define TIM_MODULE_0 1 +#define TIM_MODULE_1 2 +#define TIM_MODULE_2 3 +#define TIM_MODULE_3 4 +#define TIM_MODULE_4 5 +#define TIM_MODULE_5 6 + +#define TIM_MODULE_COUNT 6 +//EOF TIM + +//GPIO +#define __P000_CN +#define __P001_CN +#define __P010_CN +#define __P011_CN +#define __P012_CN +#define __P013_CN +#define __P014_CN +#define __P015_CN +#define __P100_CN +#define __P101_CN +#define __P102_CN +#define __P108_CN +#define __P109_CN +#define __P110_CN +#define __P111_CN +#define __P112_CN +#define __P200_CN +#define __P201_CN +#define __P212_CN +#define __P213_CN +#define __P214_CN +#define __P215_CN +#define __P300_CN +#define __P301_CN +#define __P407_CN +#define __P408_CN +#define __P914_CN +#define __P915_CN + +#define __PORT_0_CN +#define __PORT_1_CN +#define __PORT_2_CN +#define __PORT_3_CN +#define __PORT_4_CN +#define __PORT_9_CN + +#define PORT_SIZE (16) +#define PORT_COUNT (6) +//EOF GPIO + +//IVT_TABLE +#define UART0_TXI_NVIC 0 +#define UART0_TXI_EVENT 0x99 +#define UART0_RXI_NVIC 1 +#define UART0_RXI_EVENT 0x98 +#define UART1_TXI_NVIC 2 +#define UART1_TXI_EVENT 0x9F +#define UART1_RXI_NVIC 3 +#define UART1_RXI_EVENT 0x9E +#define UART2_TXI_NVIC 4 +#define UART2_TXI_EVENT 0xA4 +#define UART2_RXI_NVIC 5 +#define UART2_RXI_EVENT 0xA3 +#define UART9_TXI_NVIC 18 +#define UART9_TXI_EVENT 0xA9 +#define UART9_RXI_NVIC 19 +#define UART9_RXI_EVENT 0xA8 +//EOF IVT_TABLE + + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END From bdac955df5e178d61a9d3e08b718bb6838df4167 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Mon, 4 Aug 2025 16:45:26 +0200 Subject: [PATCH 46/62] RA4M1 update --- .../arm/mikroe/renesas/include/hal_ll_mstpcr.h | 10 ++++------ .../implementation_1/hal_ll_tim_pin_map.h | 6 ++++++ .../arm/mikroe/renesas/src/adc/CMakeLists.txt | 2 +- .../src/adc/implementation_1/hal_ll_adc.c | 8 ++------ .../arm/mikroe/renesas/src/gpio/CMakeLists.txt | 2 +- .../gpio/implementation_1/hal_ll_gpio_port.c | 6 +++--- .../mikroe/renesas/src/hal_ll/CMakeLists.txt | 2 +- .../arm/mikroe/renesas/src/i2c/CMakeLists.txt | 2 +- .../i2c/implementation_1/hal_ll_i2c_master.c | 18 +++++++++++------- .../mikroe/renesas/src/one_wire/CMakeLists.txt | 2 +- .../renesas/src/spi_master/CMakeLists.txt | 2 +- .../implementation_1/hal_ll_spi_master.c | 13 ++++++++++--- .../arm/mikroe/renesas/src/tim/CMakeLists.txt | 2 +- .../src/tim/implementation_1/hal_ll_tim.c | 2 +- .../arm/mikroe/renesas/src/uart/CMakeLists.txt | 2 +- 15 files changed, 45 insertions(+), 34 deletions(-) diff --git a/targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h b/targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h index 9203364bce..1fdc2f3dea 100644 --- a/targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h +++ b/targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h @@ -53,12 +53,10 @@ extern "C"{ /** * Core register addresses used in source */ -#if defined(R7FA4M1AB3CFM) // || TODO - #define _MSTPCRA ( uint32_t * )0x4001E01C - #define _MSTPCRB ( uint32_t * )0x40047000 - #define _MSTPCRC ( uint32_t * )0x40047004 - #define _MSTPCRD ( uint32_t * )0x40047008 -#endif +#define _MSTPCRA ( uint32_t * )0x4001E01C +#define _MSTPCRB ( uint32_t * )0x40047000 +#define _MSTPCRC ( uint32_t * )0x40047004 +#define _MSTPCRD ( uint32_t * )0x40047008 #define MSTPCRA_MSTPA0_POS 0 // SRAM0 #define MSTPCRA_MSTPA6_POS 6 // ECCSRAM diff --git a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h index 11ba4dff8c..494d9a61a5 100644 --- a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h +++ b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h @@ -74,6 +74,12 @@ static const hal_ll_base_addr_t HAL_LL_TIM4_BASE_ADDR = 0x40078400; #ifdef TIM_MODULE_5 static const hal_ll_base_addr_t HAL_LL_TIM5_BASE_ADDR = 0x40078500; #endif +#ifdef TIM_MODULE_6 +static const hal_ll_base_addr_t HAL_LL_TIM6_BASE_ADDR = 0x40078500; +#endif +#ifdef TIM_MODULE_7 +static const hal_ll_base_addr_t HAL_LL_TIM7_BASE_ADDR = 0x40078500; +#endif typedef enum { HAL_LL_TIM_PIN_A = 0, diff --git a/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt b/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt index 31b7bc2909..7ce0824264 100644 --- a/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/adc/CMakeLists.txt @@ -1,4 +1,4 @@ -## ./targets/arm/mikroe/tiva/src/adc/CMakeLists.txt +## ./targets/arm/mikroe/renesas/src/adc/CMakeLists.txt set(hal_ll_def_list "") set(mcu_header_path ${MCU_NAME}) diff --git a/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c index 7e38a05a2c..d33d03225d 100644 --- a/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c +++ b/targets/arm/mikroe/renesas/src/adc/implementation_1/hal_ll_adc.c @@ -122,11 +122,7 @@ typedef struct { */ static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[ADC_MODULE_COUNT + 1] = { #ifdef ADC_MODULE_0 - {ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_PIN_NC, - HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, - #endif - #ifdef ADC_MODULE_1 - {ADC1_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_1 ), HAL_LL_PIN_NC, + {HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, #endif @@ -179,7 +175,7 @@ static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); /** * @brief Initialize hardware ADC module. - * @details Hardware initialization of Tiva. + * @details ADC hardware initialization. * @param *map - ADC module local map, pointer to a * member in hal_ll_adc_hw_specifics_map global array. * @return None diff --git a/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt b/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt index 03e3b173e0..c82627ab60 100644 --- a/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt @@ -1,4 +1,4 @@ -## ./targets/arm/mikroe/tiva/src/gpio/CMakeLists.txt +## ./targets/arm/mikroe/renesas/src/gpio/CMakeLists.txt set(hal_ll_def_list "") set(MCU_NAME_FIRST_7 "") set(mcu_header_path ${MCU_NAME}) diff --git a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c index 5c7179cf77..064143f082 100644 --- a/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/renesas/src/gpio/implementation_1/hal_ll_gpio_port.c @@ -226,14 +226,14 @@ static uint32_t hal_ll_gpio_get_port_number(uint32_t base_addr) { for (int i = 0; i < sizeof(hal_ll_gpio_port_base_arr) / sizeof(hal_ll_gpio_port_base_arr[0]); i++) { if (hal_ll_gpio_port_base_arr[i] == base_addr) { - return i; // port number + return i; // Port number. } } - return -1; // not found + return -1; // Not found. } static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) { - uint32_t pin_index = ( pin_mask == 0xFFFF ) ? 0xFFFF : __builtin_ctz(pin_mask); // TODO Esma + uint32_t pin_index = ( pin_mask == 0xFFFF ) ? 0xFFFF : __builtin_ctz(pin_mask); hal_ll_port_name_t port_index; port_index = hal_ll_gpio_get_port_number( *port ); hal_ll_gpio_pfs_t *port_pfs_ptr = PFS_REGISTER_ADDR; diff --git a/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt b/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt index 381c7fdfd4..79a55e1dfd 100644 --- a/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt @@ -1,4 +1,4 @@ -## ./targets/arm/mikroe/tiva/src/hal_ll/CMakeLists.txt +## ./targets/arm/mikroe/renesas/src/hal_ll/CMakeLists.txt add_library(lib_hal_ll INTERFACE) add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) diff --git a/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt b/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt index 5dfac15560..1e0c7de59c 100644 --- a/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt @@ -1,4 +1,4 @@ -## ./targets/arm/mikroe/tiva/src/i2c/CMakeLists.txt +## ./targets/arm/mikroe/renesas/src/i2c/CMakeLists.txt set(mcu_header_path ${MCU_NAME}) find_cortex(hal_ll_def_list) diff --git a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c index 7ee437d008..d99abb6134 100644 --- a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c @@ -175,11 +175,11 @@ typedef enum { // ------------------------------------------------------------------ VARIABLES static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[ I2C_MODULE_COUNT + 1 ] = { #ifdef I2C_MODULE_0 - {0x40053000UL, hal_ll_i2c_module_num( I2C_MODULE_0 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, + {HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, #endif #ifdef I2C_MODULE_1 - {0x40053100UL, hal_ll_i2c_module_num( I2C_MODULE_1 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, #endif @@ -528,7 +528,9 @@ static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_ hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); uint16_t time_counter = map->timeout; - hal_ll_i2c_master_wait_for_idle( map ); + if( HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE == hal_ll_i2c_master_wait_for_idle( map )) { + return HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE; + } set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_ST ); @@ -596,7 +598,9 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m uint16_t time_counter = map->timeout; uint8_t dummy_read; - hal_ll_i2c_master_wait_for_idle( map ); + if( HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE == hal_ll_i2c_master_wait_for_idle( map )) { + return HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE; + } set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_ST ); @@ -626,7 +630,7 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m } else { set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_WAIT ); if( 1 != len_read_data ) { - for( uint8_t i = 0; i < len_read_data - 2; i++ ) { + for( uint8_t i = 0; i < len_read_data - 1; i++ ) { read_data_buf[i] = read_reg( &hal_ll_hw_reg->icdrr ); while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )) { if( map->timeout ) { @@ -641,7 +645,7 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_ACKBT ); clear_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_ACKWP ); - read_data_buf[len_read_data - 2] = read_reg( &hal_ll_hw_reg->icdrr ); + read_data_buf[len_read_data - 1] = read_reg( &hal_ll_hw_reg->icdrr ); time_counter = map->timeout; while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )) { @@ -654,7 +658,7 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_SP ); - read_data_buf[len_read_data - 1] = read_reg( &hal_ll_hw_reg->icdrr ); + read_data_buf[len_read_data] = read_reg( &hal_ll_hw_reg->icdrr ); clear_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_WAIT ); } diff --git a/targets/arm/mikroe/renesas/src/one_wire/CMakeLists.txt b/targets/arm/mikroe/renesas/src/one_wire/CMakeLists.txt index 8e2be839d5..0b7820f611 100644 --- a/targets/arm/mikroe/renesas/src/one_wire/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/one_wire/CMakeLists.txt @@ -1,4 +1,4 @@ -## ./targets/arm/mikroe/tiva/src/one_wire/CMakeLists.txt +## ./targets/arm/mikroe/renesas/src/one_wire/CMakeLists.txt set(hal_ll_def_list "") list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") diff --git a/targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt b/targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt index 1dd1af53dd..e4bc45ed41 100644 --- a/targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt @@ -1,4 +1,4 @@ -## ./targets/arm/mikroe/tiva/src/spi_master/CMakeLists.txt +## ./targets/arm/mikroe/renesas/src/spi_master/CMakeLists.txt set(hal_ll_def_list "") set(MCU_NAME_FIRST_7 "") set(mcu_header_path ${MCU_NAME}) diff --git a/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c b/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c index 033f91557e..cff46c96fb 100644 --- a/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c +++ b/targets/arm/mikroe/renesas/src/spi_master/implementation_1/hal_ll_spi_master.c @@ -202,7 +202,16 @@ static void hal_ll_spi_master_module_enable( hal_ll_spi_master_hw_specifics_map_ */ static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); -// TODO +/** + * @brief Set SPI Master bit rate. + * + * Calculates and sets the SPI bit rate by configuring the SPBR register, + * based on the system clock, desired speed, and BRDV setting. + * + * @param[in] *map Object-specific context handler. + * @return None + * + */ static void hal_ll_spi_master_set_bit_rate( hal_ll_spi_master_hw_specifics_map_t *map ); /** @@ -226,8 +235,6 @@ static void hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ); * @param[in] *map - Object specific context handler. * @return None * - * Returns one of pre-defined error values. - * Take into consideration that this is hardware specific. */ static void hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map ); diff --git a/targets/arm/mikroe/renesas/src/tim/CMakeLists.txt b/targets/arm/mikroe/renesas/src/tim/CMakeLists.txt index 3d8bddbff7..1bcd6323b1 100644 --- a/targets/arm/mikroe/renesas/src/tim/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/tim/CMakeLists.txt @@ -1,4 +1,4 @@ -## ./targets/arm/mikroe/tiva/src/tim/CMakeLists.txt +## ./targets/arm/mikroe/renesas/src/tim/CMakeLists.txt set(hal_ll_def_list "") set(MCU_NAME_FIRST_7 "") set(mcu_header_path ${MCU_NAME}) diff --git a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c index 57bf1e952e..b6681ac296 100644 --- a/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c @@ -66,7 +66,7 @@ static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COU #define HAL_LL_TIM_GTIOR_GTIOA_MASK (0x1FUL) #define HAL_LL_TIM_GTIOR_GTIOB_MASK (0x1FUL << 16) #define HAL_LL_TIM_GTIOR_GTIOA_9 (0x9) -#define HAL_LL_TIM_GTIOR_GTIOB_9 (0x9 << 16) +#define HAL_LL_TIM_GTIOR_GTIOB_9 (0x9UL << 16) #define HAL_LL_TIM_GTIOR_OAE (8) #define HAL_LL_TIM_GTIOR_OBE (24) diff --git a/targets/arm/mikroe/renesas/src/uart/CMakeLists.txt b/targets/arm/mikroe/renesas/src/uart/CMakeLists.txt index a6a543a6f8..cbfd69b57d 100644 --- a/targets/arm/mikroe/renesas/src/uart/CMakeLists.txt +++ b/targets/arm/mikroe/renesas/src/uart/CMakeLists.txt @@ -1,4 +1,4 @@ -## ./targets/arm/mikroe/tiva/src/uart/CMakeLists.txt +## ./targets/arm/mikroe/renesas/src/uart/CMakeLists.txt set(hal_ll_def_list "") set(mcu_header_path ${MCU_NAME}) From b2f5c5de96e94c4f5500bee55dfb28a5d73e2b5a Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Tue, 5 Aug 2025 10:35:35 +0200 Subject: [PATCH 47/62] I2C read issue resolved --- .../implementation_1/hal_ll_adc_pin_map.h | 2 +- .../implementation_1/hal_ll_i2c_pin_map.h | 34 ++++++++++++---- .../i2c/implementation_1/hal_ll_i2c_master.c | 39 ++++++++++++------- 3 files changed, 54 insertions(+), 21 deletions(-) diff --git a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h index 80fa0d3f97..96f8c7bb88 100644 --- a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h +++ b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h @@ -58,7 +58,7 @@ extern "C"{ /*!< ADC module base addresses. */ #ifdef ADC_MODULE_0 -static const hal_ll_base_addr_t ADC0_BASE_ADDR = ( hal_ll_base_addr_t ) 0x4005C000; +static const hal_ll_base_addr_t HAL_LL_ADC0_BASE_ADDR = ( hal_ll_base_addr_t ) 0x4005C000; #endif /** diff --git a/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h index 05eca3c89b..026a06ec68 100644 --- a/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h +++ b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h @@ -72,19 +72,39 @@ typedef struct { /*!< I2C SCL Pins. */ static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = { - #ifdef I2C0_SCL_P205 - {GPIO_P205, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 7}, - #endif - + #ifdef I2C0_SCL_P408_AF7 + {GPIO_P408, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, + #endif + #ifdef I2C1_SCL_P100_AF7 + {GPIO_P100, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, + #endif + #ifdef I2C0_SCL_P204_AF7 + {GPIO_P204, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, + #endif + #ifdef I2C0_SCL_P400_AF7 + {GPIO_P400, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, + #endif + #ifdef I2C1_SCL_P205_AF7 + {GPIO_P205, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, + #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; /*!< I2C SDA Pins. */ static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = { - #ifdef I2C0_SDA_P206 - {GPIO_P206, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), 7}, - #endif + #ifdef I2C0_SDA_P407_AF7 + {GPIO_P407, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, + #endif + #ifdef I2C1_SDA_P101_AF7 + {GPIO_P101, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, + #endif + #ifdef I2C0_SDA_P401_AF7 + {GPIO_P401, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, + #endif + #ifdef I2C1_SDA_P206_AF7 + {GPIO_P206, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, + #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; diff --git a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c index d99abb6134..c216d60a43 100644 --- a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c @@ -175,15 +175,18 @@ typedef enum { // ------------------------------------------------------------------ VARIABLES static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[ I2C_MODULE_COUNT + 1 ] = { #ifdef I2C_MODULE_0 - {HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, + {HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), + {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 10000}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, #endif #ifdef I2C_MODULE_1 - {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), + {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 10000}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, #endif - {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, + {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} }; /*!< @brief Global handle variables used in functions */ @@ -621,31 +624,41 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m } } - time_counter = map->timeout; if( check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_NACKF )) { // Error clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_SP ); dummy_read = read_reg( &hal_ll_hw_reg->icdrr ); } else { - set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_WAIT ); + dummy_read = read_reg( &hal_ll_hw_reg->icdrr ); + // set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_WAIT ); if( 1 != len_read_data ) { - for( uint8_t i = 0; i < len_read_data - 1; i++ ) { - read_data_buf[i] = read_reg( &hal_ll_hw_reg->icdrr ); + for( uint8_t i = 0; i < len_read_data - 2; i++ ) { + time_counter = map->timeout; while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )) { if( map->timeout ) { if( !time_counter-- ) return HAL_LL_I2C_MASTER_TIMEOUT_READ; } } + read_data_buf[i] = read_reg( &hal_ll_hw_reg->icdrr ); } - } - set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_ACKWP ); - set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_ACKBT ); - clear_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_ACKWP ); + time_counter = map->timeout; + while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )) { + if( map->timeout ) { + if( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } - read_data_buf[len_read_data - 1] = read_reg( &hal_ll_hw_reg->icdrr ); + set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_ACKWP ); + set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_ACKBT ); + clear_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_ACKWP ); + set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_WAIT ); + + read_data_buf[len_read_data - 2] = read_reg( &hal_ll_hw_reg->icdrr ); + } time_counter = map->timeout; while( !check_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_RDRF )) { @@ -658,7 +671,7 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m clear_reg_bit( &hal_ll_hw_reg->icsr2, HAL_LL_I2C_ICSR2_STOP ); set_reg_bit( &hal_ll_hw_reg->iccr2, HAL_LL_I2C_ICCR2_SP ); - read_data_buf[len_read_data] = read_reg( &hal_ll_hw_reg->icdrr ); + read_data_buf[len_read_data - 1] = read_reg( &hal_ll_hw_reg->icdrr ); clear_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_WAIT ); } From b9ca1440364baae5e48a7e95984ac973d732a0e6 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Tue, 5 Aug 2025 10:41:27 +0200 Subject: [PATCH 48/62] Pin maps update --- .../implementation_1/hal_ll_adc_pin_map.h | 86 +++++++- .../implementation_1/hal_ll_tim_pin_map.h | 191 ++++++++++++++++-- .../implementation_1/hal_ll_uart_pin_map.h | 90 +++++++-- 3 files changed, 327 insertions(+), 40 deletions(-) diff --git a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h index 96f8c7bb88..f116f83d5b 100644 --- a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h +++ b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h @@ -107,17 +107,83 @@ typedef struct static const hal_ll_pin_channel_list_t hal_ll_analog_in_register_list[] = { - #ifdef ADC_AN000_P000 - {GPIO_P000, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_0}, - #endif - #ifdef ADC_AN007_P012 - {GPIO_P012, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7}, - #endif - #ifdef ADC_AN018_P502 - {GPIO_P502, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_18}, - #endif + #ifdef ADC0_P000_AN000 + {GPIO_P000, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_00}, + #endif + #ifdef ADC0_P001_AN001 + {GPIO_P001, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_01}, + #endif + #ifdef ADC0_P010_AN005 + {GPIO_P010, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_05}, + #endif + #ifdef ADC0_P011_AN006 + {GPIO_P011, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_06}, + #endif + #ifdef ADC0_P012_AN007 + {GPIO_P012, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_07}, + #endif + #ifdef ADC0_P013_AN008 + {GPIO_P013, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_08}, + #endif + #ifdef ADC0_P014_AN009 + {GPIO_P014, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_09}, + #endif + #ifdef ADC0_P015_AN010 + {GPIO_P015, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC0_P100_AN022 + {GPIO_P100, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_22}, + #endif + #ifdef ADC0_P101_AN021 + {GPIO_P101, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_21}, + #endif + #ifdef ADC0_P102_AN020 + {GPIO_P102, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_20}, + #endif + #ifdef ADC0_P002_AN002 + {GPIO_P002, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_02}, + #endif + #ifdef ADC0_P003_AN003 + {GPIO_P003, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_03}, + #endif + #ifdef ADC0_P004_AN004 + {GPIO_P004, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_04}, + #endif + #ifdef ADC0_P103_AN019 + {GPIO_P103, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_19}, + #endif + #ifdef ADC0_P500_AN016 + {GPIO_P500, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC0_P501_AN017 + {GPIO_P501, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC0_P502_AN018 + {GPIO_P502, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_18}, + #endif + #ifdef ADC0_P005_AN011 + {GPIO_P005, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC0_P006_AN012 + {GPIO_P006, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC0_P007_AN013 + {GPIO_P007, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC0_P008_AN014 + {GPIO_P008, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC0_P503_AN023 + {GPIO_P503, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_23}, + #endif + #ifdef ADC0_P504_AN024 + {GPIO_P504, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_24}, + #endif + #ifdef ADC0_P505_AN025 + {GPIO_P505, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_25}, + #endif - { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR } + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} //------------ END }; diff --git a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h index 494d9a61a5..7e75e0e64f 100644 --- a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h +++ b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h @@ -57,28 +57,46 @@ extern "C"{ /*!< @brief TIMER module base addresses. */ #ifdef TIM_MODULE_0 -static const hal_ll_base_addr_t HAL_LL_TIM0_BASE_ADDR = 0x40078000; +static const hal_ll_base_addr_t HAL_LL_TIM0_BASE_ADDR = 0x40078000UL; #endif #ifdef TIM_MODULE_1 -static const hal_ll_base_addr_t HAL_LL_TIM1_BASE_ADDR = 0x40078100; +static const hal_ll_base_addr_t HAL_LL_TIM1_BASE_ADDR = 0x40078100UL; #endif #ifdef TIM_MODULE_2 -static const hal_ll_base_addr_t HAL_LL_TIM2_BASE_ADDR = 0x40078200; +static const hal_ll_base_addr_t HAL_LL_TIM2_BASE_ADDR = 0x40078200UL; #endif #ifdef TIM_MODULE_3 -static const hal_ll_base_addr_t HAL_LL_TIM3_BASE_ADDR = 0x40078300; +static const hal_ll_base_addr_t HAL_LL_TIM3_BASE_ADDR = 0x40078300UL; #endif #ifdef TIM_MODULE_4 -static const hal_ll_base_addr_t HAL_LL_TIM4_BASE_ADDR = 0x40078400; +static const hal_ll_base_addr_t HAL_LL_TIM4_BASE_ADDR = 0x40078400UL; #endif #ifdef TIM_MODULE_5 -static const hal_ll_base_addr_t HAL_LL_TIM5_BASE_ADDR = 0x40078500; +static const hal_ll_base_addr_t HAL_LL_TIM5_BASE_ADDR = 0x40078500UL; #endif #ifdef TIM_MODULE_6 -static const hal_ll_base_addr_t HAL_LL_TIM6_BASE_ADDR = 0x40078500; +static const hal_ll_base_addr_t HAL_LL_TIM6_BASE_ADDR = 0x40078600UL; #endif #ifdef TIM_MODULE_7 -static const hal_ll_base_addr_t HAL_LL_TIM7_BASE_ADDR = 0x40078500; +static const hal_ll_base_addr_t HAL_LL_TIM7_BASE_ADDR = 0x40078700UL; +#endif +#ifdef TIM_MODULE_8 +static const hal_ll_base_addr_t HAL_LL_TIM8_BASE_ADDR = 0x40078800UL; +#endif +#ifdef TIM_MODULE_9 +static const hal_ll_base_addr_t HAL_LL_TIM9_BASE_ADDR = 0x40078900UL; +#endif +#ifdef TIM_MODULE_10 +static const hal_ll_base_addr_t HAL_LL_TIM10_BASE_ADDR = 0x40078A00UL; +#endif +#ifdef TIM_MODULE_11 +static const hal_ll_base_addr_t HAL_LL_TIM11_BASE_ADDR = 0x40078B00UL; +#endif +#ifdef TIM_MODULE_12 +static const hal_ll_base_addr_t HAL_LL_TIM12_BASE_ADDR = 0x40078C00UL; +#endif +#ifdef TIM_MODULE_13 +static const hal_ll_base_addr_t HAL_LL_TIM13_BASE_ADDR = 0x40078D00UL; #endif typedef enum { @@ -97,16 +115,153 @@ typedef struct { /*!< TIM pins. */ static const hal_ll_tim_pin_map_t hal_ll_tim_pin_map[] = { - #ifdef TIM4_P302 - {GPIO_P302, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM0_P107 - {GPIO_P107, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM2_P102 - {GPIO_P102, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_PIN_B}, - #endif - + #ifdef TIM0_P108_CHB_AF3 + {GPIO_P108, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM0_P212_CHB_AF3 + {GPIO_P212, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM0_P213_CHA_AF3 + {GPIO_P213, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM0_P300_CHA_AF3 + {GPIO_P300, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM1_P109_CHA_AF3 + {GPIO_P109, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM1_P110_CHB_AF3 + {GPIO_P110, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM2_P102_CHB_AF3 + {GPIO_P102, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM3_P111_CHA_AF3 + {GPIO_P111, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM3_P112_CHB_AF3 + {GPIO_P112, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM4_P301_CHB_AF3 + {GPIO_P301, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM5_P100_CHB_AF3 + {GPIO_P100, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM5_P101_CHA_AF3 + {GPIO_P101, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM5_P408_CHB_AF3 + {GPIO_P408, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM0_P106_CHB_AF3 + {GPIO_P106, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM0_P107_CHA_AF3 + {GPIO_P107, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM1_P104_CHB_AF3 + {GPIO_P104, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM1_P105_CHA_AF3 + {GPIO_P105, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM2_P103_CHA_AF3 + {GPIO_P103, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM2_P113_CHA_AF3 + {GPIO_P113, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM2_P500_CHA_AF3 + {GPIO_P500, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM2_P501_CHB_AF3 + {GPIO_P501, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM3_P502_CHB_AF3 + {GPIO_P502, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM4_P204_CHB_AF3 + {GPIO_P204, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM4_P205_CHA_AF3 + {GPIO_P205, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM4_P302_CHA_AF3 + {GPIO_P302, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM5_P409_CHA_AF3 + {GPIO_P409, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM6_P400_CHA_AF3 + {GPIO_P400, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM6_P401_CHB_AF3 + {GPIO_P401, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM6_P410_CHB_AF3 + {GPIO_P410, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM6_P411_CHA_AF3 + {GPIO_P411, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM7_P303_CHB_AF3 + {GPIO_P303, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM7_P304_CHA_AF3 + {GPIO_P304, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM0_P414_CHB_AF3 + {GPIO_P414, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM0_P415_CHA_AF3 + {GPIO_P415, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM1_P405_CHA_AF3 + {GPIO_P405, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM1_P406_CHB_AF3 + {GPIO_P406, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM2_P114_CHB_AF3 + {GPIO_P114, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM3_P403_CHA_AF3 + {GPIO_P403, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM3_P404_CHB_AF3 + {GPIO_P404, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM4_P115_CHA_AF3 + {GPIO_P115, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM4_P608_CHB_AF3 + {GPIO_P608, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM5_P202_CHB_AF3 + {GPIO_P202, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM5_P203_CHA_AF3 + {GPIO_P203, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM5_P609_CHA_AF3 + {GPIO_P609, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM5_P610_CHB_AF3 + {GPIO_P610, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM6_P600_CHB_AF3 + {GPIO_P600, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM6_P601_CHA_AF3 + {GPIO_P601, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM7_P602_CHB_AF3 + {GPIO_P602, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM7_P603_CHA_AF3 + {GPIO_P603, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_A}, + #endif { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC } }; diff --git a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h index 482773367e..907292844a 100644 --- a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h +++ b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h @@ -98,24 +98,90 @@ typedef struct { /*!< UART TX Pins. */ static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { - #ifdef UART0_TX_P411 - {hal_ll_uart_module_num(UART_MODULE_0), GPIO_P411, HAL_LL_UART0_BASE_ADDRESS, 4}, - #endif - #ifdef UART1_TX_P401 - {hal_ll_uart_module_num(UART_MODULE_1), GPIO_P401, HAL_LL_UART1_BASE_ADDRESS, 5}, - #endif + #ifdef UART0_TX_P101_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P101, HAL_LL_UART0_BASE_ADDR, 4}, + #endif + #ifdef UART1_TX_P213_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P213, HAL_LL_UART1_BASE_ADDR, 5}, + #endif + #ifdef UART2_TX_P102_AF4 + {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P102, HAL_LL_UART2_BASE_ADDR, 4}, + #endif + #ifdef UART2_TX_P112_AF4 + {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P112, HAL_LL_UART2_BASE_ADDR, 4}, + #endif + #ifdef UART9_TX_P109_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P109, HAL_LL_UART9_BASE_ADDR, 5}, + #endif + #ifdef UART0_TX_P205_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P205, HAL_LL_UART0_BASE_ADDR, 4}, + #endif + #ifdef UART0_TX_P411_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P411, HAL_LL_UART0_BASE_ADDR, 4}, + #endif + #ifdef UART1_TX_P401_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P401, HAL_LL_UART1_BASE_ADDR, 5}, + #endif + #ifdef UART1_TX_P501_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P501, HAL_LL_UART1_BASE_ADDR, 5}, + #endif + #ifdef UART2_TX_P302_AF4 + {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P302, HAL_LL_UART2_BASE_ADDR, 4}, + #endif + #ifdef UART9_TX_P409_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P409, HAL_LL_UART9_BASE_ADDR, 5}, + #endif + #ifdef UART9_TX_P203_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P203, HAL_LL_UART9_BASE_ADDR, 5}, + #endif + #ifdef UART9_TX_P602_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P602, HAL_LL_UART9_BASE_ADDR, 5}, + #endif {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} }; /*!< UART RX Pins. */ static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = { - #ifdef UART0_RX_P410 - {hal_ll_uart_module_num(UART_MODULE_0), GPIO_P410, HAL_LL_UART0_BASE_ADDRESS, 4}, - #endif - #ifdef UART1_RX_P402 - {hal_ll_uart_module_num(UART_MODULE_1), GPIO_P402, HAL_LL_UART1_BASE_ADDRESS, 5}, - #endif + #ifdef UART0_RX_P100_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P100, HAL_LL_UART0_BASE_ADDR, 4}, + #endif + #ifdef UART1_RX_P212_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P212, HAL_LL_UART1_BASE_ADDR, 5}, + #endif + #ifdef UART2_RX_P301_AF4 + {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P301, HAL_LL_UART2_BASE_ADDR, 4}, + #endif + #ifdef UART9_RX_P110_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P110, HAL_LL_UART9_BASE_ADDR, 5}, + #endif + #ifdef UART9_RX_P408_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P408, HAL_LL_UART9_BASE_ADDR, 5}, + #endif + #ifdef UART0_RX_P104_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P104, HAL_LL_UART0_BASE_ADDR, 4}, + #endif + #ifdef UART0_RX_P206_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P206, HAL_LL_UART0_BASE_ADDR, 4}, + #endif + #ifdef UART0_RX_P410_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P410, HAL_LL_UART0_BASE_ADDR, 4}, + #endif + #ifdef UART1_RX_P402_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P402, HAL_LL_UART1_BASE_ADDR, 5}, + #endif + #ifdef UART1_RX_P502_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P502, HAL_LL_UART1_BASE_ADDR, 5}, + #endif + #ifdef UART1_RX_P708_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P708, HAL_LL_UART1_BASE_ADDR, 5}, + #endif + #ifdef UART9_RX_P202_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P202, HAL_LL_UART9_BASE_ADDR, 5}, + #endif + #ifdef UART9_RX_P601_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P601, HAL_LL_UART9_BASE_ADDR, 5}, + #endif {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} }; From 9c24a5369929e41bb4803062eb310758e71b18d8 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Tue, 5 Aug 2025 10:59:19 +0200 Subject: [PATCH 49/62] Pin maps update --- .../implementation_1/hal_ll_adc_pin_map.h | 150 ++++++++--------- .../hal_ll_spi_master_pin_map.h | 41 ++++- .../implementation_1/hal_ll_uart_pin_map.h | 156 +++++++++--------- 3 files changed, 190 insertions(+), 157 deletions(-) diff --git a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h index f116f83d5b..6f4af094a4 100644 --- a/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h +++ b/targets/arm/mikroe/renesas/include/adc/hal_ll_adc_pin_map/implementation_1/hal_ll_adc_pin_map.h @@ -107,81 +107,81 @@ typedef struct static const hal_ll_pin_channel_list_t hal_ll_analog_in_register_list[] = { - #ifdef ADC0_P000_AN000 - {GPIO_P000, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_00}, - #endif - #ifdef ADC0_P001_AN001 - {GPIO_P001, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_01}, - #endif - #ifdef ADC0_P010_AN005 - {GPIO_P010, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_05}, - #endif - #ifdef ADC0_P011_AN006 - {GPIO_P011, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_06}, - #endif - #ifdef ADC0_P012_AN007 - {GPIO_P012, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_07}, - #endif - #ifdef ADC0_P013_AN008 - {GPIO_P013, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_08}, - #endif - #ifdef ADC0_P014_AN009 - {GPIO_P014, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_09}, - #endif - #ifdef ADC0_P015_AN010 - {GPIO_P015, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_10}, - #endif - #ifdef ADC0_P100_AN022 - {GPIO_P100, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_22}, - #endif - #ifdef ADC0_P101_AN021 - {GPIO_P101, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_21}, - #endif - #ifdef ADC0_P102_AN020 - {GPIO_P102, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_20}, - #endif - #ifdef ADC0_P002_AN002 - {GPIO_P002, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_02}, - #endif - #ifdef ADC0_P003_AN003 - {GPIO_P003, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_03}, - #endif - #ifdef ADC0_P004_AN004 - {GPIO_P004, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_04}, - #endif - #ifdef ADC0_P103_AN019 - {GPIO_P103, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_19}, - #endif - #ifdef ADC0_P500_AN016 - {GPIO_P500, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_16}, - #endif - #ifdef ADC0_P501_AN017 - {GPIO_P501, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_17}, - #endif - #ifdef ADC0_P502_AN018 - {GPIO_P502, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_18}, - #endif - #ifdef ADC0_P005_AN011 - {GPIO_P005, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_11}, - #endif - #ifdef ADC0_P006_AN012 - {GPIO_P006, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_12}, - #endif - #ifdef ADC0_P007_AN013 - {GPIO_P007, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_13}, - #endif - #ifdef ADC0_P008_AN014 - {GPIO_P008, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_14}, - #endif - #ifdef ADC0_P503_AN023 - {GPIO_P503, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_23}, - #endif - #ifdef ADC0_P504_AN024 - {GPIO_P504, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_24}, - #endif - #ifdef ADC0_P505_AN025 - {GPIO_P505, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_25}, - #endif + #ifdef ADC0_P000_AN000 + {GPIO_P000, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_0}, + #endif + #ifdef ADC0_P001_AN001 + {GPIO_P001, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC0_P010_AN005 + {GPIO_P010, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC0_P011_AN006 + {GPIO_P011, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC0_P012_AN007 + {GPIO_P012, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC0_P013_AN008 + {GPIO_P013, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC0_P014_AN009 + {GPIO_P014, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC0_P015_AN010 + {GPIO_P015, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC0_P100_AN022 + {GPIO_P100, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_22}, + #endif + #ifdef ADC0_P101_AN021 + {GPIO_P101, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_21}, + #endif + #ifdef ADC0_P102_AN020 + {GPIO_P102, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_20}, + #endif + #ifdef ADC0_P002_AN002 + {GPIO_P002, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC0_P003_AN003 + {GPIO_P003, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC0_P004_AN004 + {GPIO_P004, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC0_P103_AN019 + {GPIO_P103, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_19}, + #endif + #ifdef ADC0_P500_AN016 + {GPIO_P500, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC0_P501_AN017 + {GPIO_P501, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC0_P502_AN018 + {GPIO_P502, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_18}, + #endif + #ifdef ADC0_P005_AN011 + {GPIO_P005, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC0_P006_AN012 + {GPIO_P006, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC0_P007_AN013 + {GPIO_P007, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC0_P008_AN014 + {GPIO_P008, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC0_P503_AN023 + {GPIO_P503, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_23}, + #endif + #ifdef ADC0_P504_AN024 + {GPIO_P504, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_24}, + #endif + #ifdef ADC0_P505_AN025 + {GPIO_P505, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_ADC_CHANNEL_25}, + #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} //------------ END diff --git a/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h index 69afa2f297..6fbe0597c0 100644 --- a/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h +++ b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h @@ -57,7 +57,13 @@ extern "C"{ /*!< SPI module base addresses. */ #ifdef SPI_MODULE_0 -static const hal_ll_base_addr_t HAL_LL_SPI0_MASTER_BASE_ADDR = 0x40072000; +static const hal_ll_base_addr_t HAL_LL_SPI0_MASTER_BASE_ADDR = 0x40072000UL; +#endif +#ifdef SPI_MODULE_1 +static const hal_ll_base_addr_t HAL_LL_SPI1_MASTER_BASE_ADDR = 0x40072100UL; +#endif +#ifdef SPI_MODULE_2 +static const hal_ll_base_addr_t HAL_LL_SPI2_MASTER_BASE_ADDR = 0x40072200UL; #endif /*!< @brief SPI pin structure. */ @@ -71,7 +77,16 @@ typedef struct { /*!< SPI SCK pins. */ static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_sck_map[] = { #ifdef SPI0_SCK_P102_AF6 - {GPIO_P102, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 6}, + {GPIO_P102, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_0 ), 6}, + #endif + #ifdef SPI1_SCK_P111_AF6 + {GPIO_P111, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_1 ), 6}, + #endif + #ifdef SPI1_SCK_P204_AF6 + {GPIO_P204, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_1 ), 6}, + #endif + #ifdef SPI0_SCK_P412_AF6 + {GPIO_P412, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_0 ), 6}, #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} @@ -80,7 +95,16 @@ static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_sck_map[] = { /*!< SPI MISO pins. */ static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_miso_map[] = { #ifdef SPI0_MISO_P100_AF6 - {GPIO_P100, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 6}, + {GPIO_P100, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_0 ), 6}, + #endif + #ifdef SPI1_MISO_P110_AF6 + {GPIO_P110, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_1 ), 6}, + #endif + #ifdef SPI0_MISO_P410_AF6 + {GPIO_P410, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_0 ), 6}, + #endif + #ifdef SPI1_MISO_P202_AF6 + {GPIO_P202, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_1 ), 6}, #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} @@ -89,7 +113,16 @@ static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_miso_map[] = { /*!< SPI MOSI pins. */ static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_mosi_map[] = { #ifdef SPI0_MOSI_P101_AF6 - {GPIO_P101, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 6}, + {GPIO_P101, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_0 ), 6}, + #endif + #ifdef SPI1_MOSI_P109_AF6 + {GPIO_P109, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_1 ), 6}, + #endif + #ifdef SPI0_MOSI_P411_AF6 + {GPIO_P411, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_0 ), 6}, + #endif + #ifdef SPI1_MOSI_P203_AF6 + {GPIO_P203, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_1 ), 6}, #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} diff --git a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h index 907292844a..b70aa4f0df 100644 --- a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h +++ b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h @@ -98,90 +98,90 @@ typedef struct { /*!< UART TX Pins. */ static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { - #ifdef UART0_TX_P101_AF4 - {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P101, HAL_LL_UART0_BASE_ADDR, 4}, - #endif - #ifdef UART1_TX_P213_AF5 - {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P213, HAL_LL_UART1_BASE_ADDR, 5}, - #endif - #ifdef UART2_TX_P102_AF4 - {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P102, HAL_LL_UART2_BASE_ADDR, 4}, - #endif - #ifdef UART2_TX_P112_AF4 - {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P112, HAL_LL_UART2_BASE_ADDR, 4}, - #endif - #ifdef UART9_TX_P109_AF5 - {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P109, HAL_LL_UART9_BASE_ADDR, 5}, - #endif - #ifdef UART0_TX_P205_AF4 - {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P205, HAL_LL_UART0_BASE_ADDR, 4}, - #endif - #ifdef UART0_TX_P411_AF4 - {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P411, HAL_LL_UART0_BASE_ADDR, 4}, - #endif - #ifdef UART1_TX_P401_AF5 - {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P401, HAL_LL_UART1_BASE_ADDR, 5}, - #endif - #ifdef UART1_TX_P501_AF5 - {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P501, HAL_LL_UART1_BASE_ADDR, 5}, - #endif - #ifdef UART2_TX_P302_AF4 - {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P302, HAL_LL_UART2_BASE_ADDR, 4}, - #endif - #ifdef UART9_TX_P409_AF5 - {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P409, HAL_LL_UART9_BASE_ADDR, 5}, - #endif - #ifdef UART9_TX_P203_AF5 - {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P203, HAL_LL_UART9_BASE_ADDR, 5}, - #endif - #ifdef UART9_TX_P602_AF5 - {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P602, HAL_LL_UART9_BASE_ADDR, 5}, - #endif + #ifdef UART0_TX_P101_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P101, HAL_LL_UART0_BASE_ADDRESS, 4}, + #endif + #ifdef UART1_TX_P213_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P213, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif + #ifdef UART2_TX_P102_AF4 + {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P102, HAL_LL_UART2_BASE_ADDRESS, 4}, + #endif + #ifdef UART2_TX_P112_AF4 + {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P112, HAL_LL_UART2_BASE_ADDRESS, 4}, + #endif + #ifdef UART9_TX_P109_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P109, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif + #ifdef UART0_TX_P205_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P205, HAL_LL_UART0_BASE_ADDRESS, 4}, + #endif + #ifdef UART0_TX_P411_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P411, HAL_LL_UART0_BASE_ADDRESS, 4}, + #endif + #ifdef UART1_TX_P401_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P401, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif + #ifdef UART1_TX_P501_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P501, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif + #ifdef UART2_TX_P302_AF4 + {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P302, HAL_LL_UART2_BASE_ADDRESS, 4}, + #endif + #ifdef UART9_TX_P409_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P409, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif + #ifdef UART9_TX_P203_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P203, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif + #ifdef UART9_TX_P602_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P602, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} }; /*!< UART RX Pins. */ static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = { - #ifdef UART0_RX_P100_AF4 - {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P100, HAL_LL_UART0_BASE_ADDR, 4}, - #endif - #ifdef UART1_RX_P212_AF5 - {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P212, HAL_LL_UART1_BASE_ADDR, 5}, - #endif - #ifdef UART2_RX_P301_AF4 - {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P301, HAL_LL_UART2_BASE_ADDR, 4}, - #endif - #ifdef UART9_RX_P110_AF5 - {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P110, HAL_LL_UART9_BASE_ADDR, 5}, - #endif - #ifdef UART9_RX_P408_AF5 - {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P408, HAL_LL_UART9_BASE_ADDR, 5}, - #endif - #ifdef UART0_RX_P104_AF4 - {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P104, HAL_LL_UART0_BASE_ADDR, 4}, - #endif - #ifdef UART0_RX_P206_AF4 - {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P206, HAL_LL_UART0_BASE_ADDR, 4}, - #endif - #ifdef UART0_RX_P410_AF4 - {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P410, HAL_LL_UART0_BASE_ADDR, 4}, - #endif - #ifdef UART1_RX_P402_AF5 - {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P402, HAL_LL_UART1_BASE_ADDR, 5}, - #endif - #ifdef UART1_RX_P502_AF5 - {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P502, HAL_LL_UART1_BASE_ADDR, 5}, - #endif - #ifdef UART1_RX_P708_AF5 - {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P708, HAL_LL_UART1_BASE_ADDR, 5}, - #endif - #ifdef UART9_RX_P202_AF5 - {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P202, HAL_LL_UART9_BASE_ADDR, 5}, - #endif - #ifdef UART9_RX_P601_AF5 - {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P601, HAL_LL_UART9_BASE_ADDR, 5}, - #endif + #ifdef UART0_RX_P100_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P100, HAL_LL_UART0_BASE_ADDRESS, 4}, + #endif + #ifdef UART1_RX_P212_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P212, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif + #ifdef UART2_RX_P301_AF4 + {hal_ll_uart_module_num( UART_MODULE_2 ), GPIO_P301, HAL_LL_UART2_BASE_ADDRESS, 4}, + #endif + #ifdef UART9_RX_P110_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P110, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif + #ifdef UART9_RX_P408_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P408, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif + #ifdef UART0_RX_P104_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P104, HAL_LL_UART0_BASE_ADDRESS, 4}, + #endif + #ifdef UART0_RX_P206_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P206, HAL_LL_UART0_BASE_ADDRESS, 4}, + #endif + #ifdef UART0_RX_P410_AF4 + {hal_ll_uart_module_num( UART_MODULE_0 ), GPIO_P410, HAL_LL_UART0_BASE_ADDRESS, 4}, + #endif + #ifdef UART1_RX_P402_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P402, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif + #ifdef UART1_RX_P502_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P502, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif + #ifdef UART1_RX_P708_AF5 + {hal_ll_uart_module_num( UART_MODULE_1 ), GPIO_P708, HAL_LL_UART1_BASE_ADDRESS, 5}, + #endif + #ifdef UART9_RX_P202_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P202, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif + #ifdef UART9_RX_P601_AF5 + {hal_ll_uart_module_num( UART_MODULE_9 ), GPIO_P601, HAL_LL_UART9_BASE_ADDRESS, 5}, + #endif {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} }; From b43ccfbedaf7abd1eef1ecf237b0aa25446b5881 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Tue, 5 Aug 2025 11:02:54 +0200 Subject: [PATCH 50/62] pin maps update --- .../implementation_1/hal_ll_i2c_pin_map.h | 54 ++-- .../implementation_1/hal_ll_tim_pin_map.h | 294 +++++++++--------- 2 files changed, 174 insertions(+), 174 deletions(-) diff --git a/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h index 026a06ec68..8ca61d04ff 100644 --- a/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h +++ b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_pin_map/implementation_1/hal_ll_i2c_pin_map.h @@ -72,39 +72,39 @@ typedef struct { /*!< I2C SCL Pins. */ static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = { - #ifdef I2C0_SCL_P408_AF7 - {GPIO_P408, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, - #endif - #ifdef I2C1_SCL_P100_AF7 - {GPIO_P100, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, - #endif - #ifdef I2C0_SCL_P204_AF7 - {GPIO_P204, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, - #endif - #ifdef I2C0_SCL_P400_AF7 - {GPIO_P400, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, - #endif - #ifdef I2C1_SCL_P205_AF7 - {GPIO_P205, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, - #endif + #ifdef I2C0_SCL_P408_AF7 + {GPIO_P408, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, + #endif + #ifdef I2C1_SCL_P100_AF7 + {GPIO_P100, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, + #endif + #ifdef I2C0_SCL_P204_AF7 + {GPIO_P204, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, + #endif + #ifdef I2C0_SCL_P400_AF7 + {GPIO_P400, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, + #endif + #ifdef I2C1_SCL_P205_AF7 + {GPIO_P205, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, + #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; /*!< I2C SDA Pins. */ static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = { - #ifdef I2C0_SDA_P407_AF7 - {GPIO_P407, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, - #endif - #ifdef I2C1_SDA_P101_AF7 - {GPIO_P101, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, - #endif - #ifdef I2C0_SDA_P401_AF7 - {GPIO_P401, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, - #endif - #ifdef I2C1_SDA_P206_AF7 - {GPIO_P206, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, - #endif + #ifdef I2C0_SDA_P407_AF7 + {GPIO_P407, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, + #endif + #ifdef I2C1_SDA_P101_AF7 + {GPIO_P101, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, + #endif + #ifdef I2C0_SDA_P401_AF7 + {GPIO_P401, HAL_LL_I2C0_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_0 ), 7}, + #endif + #ifdef I2C1_SDA_P206_AF7 + {GPIO_P206, HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num( I2C_MODULE_1 ), 7}, + #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; diff --git a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h index 7e75e0e64f..759b753669 100644 --- a/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h +++ b/targets/arm/mikroe/renesas/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h @@ -115,153 +115,153 @@ typedef struct { /*!< TIM pins. */ static const hal_ll_tim_pin_map_t hal_ll_tim_pin_map[] = { - #ifdef TIM0_P108_CHB_AF3 - {GPIO_P108, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM0_P212_CHB_AF3 - {GPIO_P212, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM0_P213_CHA_AF3 - {GPIO_P213, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM0_P300_CHA_AF3 - {GPIO_P300, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM1_P109_CHA_AF3 - {GPIO_P109, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM1_P110_CHB_AF3 - {GPIO_P110, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM2_P102_CHB_AF3 - {GPIO_P102, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM3_P111_CHA_AF3 - {GPIO_P111, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM3_P112_CHB_AF3 - {GPIO_P112, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM4_P301_CHB_AF3 - {GPIO_P301, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM5_P100_CHB_AF3 - {GPIO_P100, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM5_P101_CHA_AF3 - {GPIO_P101, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM5_P408_CHB_AF3 - {GPIO_P408, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM0_P106_CHB_AF3 - {GPIO_P106, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM0_P107_CHA_AF3 - {GPIO_P107, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM1_P104_CHB_AF3 - {GPIO_P104, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM1_P105_CHA_AF3 - {GPIO_P105, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM2_P103_CHA_AF3 - {GPIO_P103, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM2_P113_CHA_AF3 - {GPIO_P113, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM2_P500_CHA_AF3 - {GPIO_P500, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM2_P501_CHB_AF3 - {GPIO_P501, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM3_P502_CHB_AF3 - {GPIO_P502, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM4_P204_CHB_AF3 - {GPIO_P204, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM4_P205_CHA_AF3 - {GPIO_P205, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM4_P302_CHA_AF3 - {GPIO_P302, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM5_P409_CHA_AF3 - {GPIO_P409, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM6_P400_CHA_AF3 - {GPIO_P400, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM6_P401_CHB_AF3 - {GPIO_P401, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM6_P410_CHB_AF3 - {GPIO_P410, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM6_P411_CHA_AF3 - {GPIO_P411, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM7_P303_CHB_AF3 - {GPIO_P303, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM7_P304_CHA_AF3 - {GPIO_P304, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM0_P414_CHB_AF3 - {GPIO_P414, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM0_P415_CHA_AF3 - {GPIO_P415, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM1_P405_CHA_AF3 - {GPIO_P405, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM1_P406_CHB_AF3 - {GPIO_P406, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM2_P114_CHB_AF3 - {GPIO_P114, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM3_P403_CHA_AF3 - {GPIO_P403, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM3_P404_CHB_AF3 - {GPIO_P404, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM4_P115_CHA_AF3 - {GPIO_P115, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM4_P608_CHB_AF3 - {GPIO_P608, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM5_P202_CHB_AF3 - {GPIO_P202, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM5_P203_CHA_AF3 - {GPIO_P203, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM5_P609_CHA_AF3 - {GPIO_P609, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM5_P610_CHB_AF3 - {GPIO_P610, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM6_P600_CHB_AF3 - {GPIO_P600, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM6_P601_CHA_AF3 - {GPIO_P601, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_A}, - #endif - #ifdef TIM7_P602_CHB_AF3 - {GPIO_P602, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_B}, - #endif - #ifdef TIM7_P603_CHA_AF3 - {GPIO_P603, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_A}, - #endif + #ifdef TIM0_P108_CHB_AF3 + {GPIO_P108, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM0_P212_CHB_AF3 + {GPIO_P212, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM0_P213_CHA_AF3 + {GPIO_P213, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM0_P300_CHA_AF3 + {GPIO_P300, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM1_P109_CHA_AF3 + {GPIO_P109, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM1_P110_CHB_AF3 + {GPIO_P110, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM2_P102_CHB_AF3 + {GPIO_P102, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM3_P111_CHA_AF3 + {GPIO_P111, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM3_P112_CHB_AF3 + {GPIO_P112, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM4_P301_CHB_AF3 + {GPIO_P301, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM5_P100_CHB_AF3 + {GPIO_P100, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM5_P101_CHA_AF3 + {GPIO_P101, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM5_P408_CHB_AF3 + {GPIO_P408, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM0_P106_CHB_AF3 + {GPIO_P106, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM0_P107_CHA_AF3 + {GPIO_P107, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM1_P104_CHB_AF3 + {GPIO_P104, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM1_P105_CHA_AF3 + {GPIO_P105, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM2_P103_CHA_AF3 + {GPIO_P103, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM2_P113_CHA_AF3 + {GPIO_P113, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM2_P500_CHA_AF3 + {GPIO_P500, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM2_P501_CHB_AF3 + {GPIO_P501, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM3_P502_CHB_AF3 + {GPIO_P502, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM4_P204_CHB_AF3 + {GPIO_P204, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM4_P205_CHA_AF3 + {GPIO_P205, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM4_P302_CHA_AF3 + {GPIO_P302, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM5_P409_CHA_AF3 + {GPIO_P409, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM6_P400_CHA_AF3 + {GPIO_P400, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM6_P401_CHB_AF3 + {GPIO_P401, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM6_P410_CHB_AF3 + {GPIO_P410, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM6_P411_CHA_AF3 + {GPIO_P411, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM7_P303_CHB_AF3 + {GPIO_P303, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM7_P304_CHA_AF3 + {GPIO_P304, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM0_P414_CHB_AF3 + {GPIO_P414, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM0_P415_CHA_AF3 + {GPIO_P415, HAL_LL_TIM0_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_0 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM1_P405_CHA_AF3 + {GPIO_P405, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM1_P406_CHB_AF3 + {GPIO_P406, HAL_LL_TIM1_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_1 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM2_P114_CHB_AF3 + {GPIO_P114, HAL_LL_TIM2_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_2 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM3_P403_CHA_AF3 + {GPIO_P403, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM3_P404_CHB_AF3 + {GPIO_P404, HAL_LL_TIM3_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_3 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM4_P115_CHA_AF3 + {GPIO_P115, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM4_P608_CHB_AF3 + {GPIO_P608, HAL_LL_TIM4_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_4 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM5_P202_CHB_AF3 + {GPIO_P202, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM5_P203_CHA_AF3 + {GPIO_P203, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM5_P609_CHA_AF3 + {GPIO_P609, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM5_P610_CHB_AF3 + {GPIO_P610, HAL_LL_TIM5_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_5 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM6_P600_CHB_AF3 + {GPIO_P600, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM6_P601_CHA_AF3 + {GPIO_P601, HAL_LL_TIM6_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_6 ), HAL_LL_TIM_PIN_A}, + #endif + #ifdef TIM7_P602_CHB_AF3 + {GPIO_P602, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_B}, + #endif + #ifdef TIM7_P603_CHA_AF3 + {GPIO_P603, HAL_LL_TIM7_BASE_ADDR, 3, hal_ll_tim_module_num( TIM_MODULE_7 ), HAL_LL_TIM_PIN_A}, + #endif { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC } }; From 14a15c1b62df8c9b81cc5a556eca2c74a1e505ef Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Tue, 5 Aug 2025 11:14:27 +0200 Subject: [PATCH 51/62] bsp added --- .../include/boards/clicker_ra4m1/board.h | 33 +++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/bsp/board/include/boards/clicker_ra4m1/board.h b/bsp/board/include/boards/clicker_ra4m1/board.h index e078ea5b28..6720f0c4ce 100644 --- a/bsp/board/include/boards/clicker_ra4m1/board.h +++ b/bsp/board/include/boards/clicker_ra4m1/board.h @@ -49,10 +49,39 @@ extern "C" { #endif +// Hardware revision number +#define BOARD_REV_MAJOR (1) +#define BOARD_REV_MINOR (01) + #define BOARD_NAME "RA4M1 Clicker" -// Mapping -// Only Bare Metal support is available at the moment +#include "mikrobus.h" + +/// Mapping +#define MIKROBUS_1 1 +#define MIKROBUS_1_AN GPIO_P000 +#define MIKROBUS_1_RST GPIO_P407 +#define MIKROBUS_1_CS GPIO_P103 +#define MIKROBUS_1_SCK GPIO_P102 +#define MIKROBUS_1_MISO GPIO_P100 +#define MIKROBUS_1_MOSI GPIO_P101 +#define MIKROBUS_1_PWM GPIO_P107 +#define MIKROBUS_1_INT GPIO_P302 +#define MIKROBUS_1_RX GPIO_P410 +#define MIKROBUS_1_TX GPIO_P411 +#define MIKROBUS_1_SCL GPIO_P205 +#define MIKROBUS_1_SDA GPIO_P206 + +// LEDs +#define LED_1 GPIO_P409 +#define LED_2 GPIO_P408 + +// Buttons +#define BUTTON_1 GPIO_P304 +#define BUTTON_2 GPIO_P301 + +#define USB_UART_TX HAL_PIN_NC +#define USB_UART_RX HAL_PIN_NC #ifdef __cplusplus } From 3d6ae36d0aab011473d86f56aca237c1b5cdcce7 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 6 Aug 2025 10:23:14 +0200 Subject: [PATCH 52/62] GPIO description adjustment --- .../renesas/include/gpio/hal_ll_gpio_port.h | 51 +++++++++++-------- 1 file changed, 30 insertions(+), 21 deletions(-) diff --git a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h index 3add15a7b8..d7a1c87d34 100644 --- a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h +++ b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio_port.h @@ -105,7 +105,11 @@ typedef struct } module_struct; /** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + * @brief Pin Function Select Register (PmnPFS) structure. + * + * Represents the configuration settings for a single pin using the + * Port Function Select (PFS) register. This includes direction, mode, + * drive strength, and peripheral selection. */ typedef struct { @@ -115,40 +119,45 @@ typedef struct struct { - volatile uint32_t podr : 1; - volatile uint32_t pidr : 1; - volatile uint32_t pdr : 1; - uint32_t : 1; - volatile uint32_t pcr : 1; - volatile uint32_t pim : 1; - volatile uint32_t ncodr : 1; - uint32_t : 3; - volatile uint32_t dscr : 2; - volatile uint32_t eofr : 2; - volatile uint32_t isel : 1; - volatile uint32_t asel : 1; - volatile uint32_t pmr : 1; - uint32_t : 7; - volatile uint32_t psel : 5; - uint32_t : 3; + volatile uint32_t podr : 1; /**< Output data. */ + volatile uint32_t pidr : 1; /**< Input data. */ + volatile uint32_t pdr : 1; /**< Direction (0: input, 1: output). */ + uint32_t : 1; /**< Reserved. */ + volatile uint32_t pcr : 1; /**< Pull-up control (0: disabled, 1: enabled). */ + uint32_t : 1; /**< Reserved. */ + volatile uint32_t ncodr : 1; /**< N-ch open-drain control (0: CMOS, 1: NMOS open-drain). */ + uint32_t : 3; /**< Reserved. */ + volatile uint32_t dscr : 2; /**< Drive capacity control. */ + volatile uint32_t eofr : 2; /**< Event on falling/rising edge. */ + volatile uint32_t isel : 1; /**< IRQ input select (0: disabled, 1: enabled). */ + volatile uint32_t asel : 1; /**< Analog select (0: digital, 1: analog). */ + volatile uint32_t pmr : 1; /**< Peripheral mode select (0: GPIO, 1: peripheral). */ + uint32_t : 7; /**< Reserved. */ + volatile uint32_t psel : 5; /**< Peripheral function select. */ + uint32_t : 3; /**< Reserved. */ } pmnpfs_b; }; } hal_ll_gpio_pfs_pin_t; /** - * @brief R_PFS_PORT [PORT] (Port [0..14]) + * @brief Port-level PFS register map. + * + * Represents the PFS register set for all 16 pins of a given port. */ typedef struct { - volatile hal_ll_gpio_pfs_pin_t pin[16]; + volatile hal_ll_gpio_pfs_pin_t pin[16]; /**< PFS configuration for pins 0 to 15. */ } hal_ll_gpio_pfs_port_t; /** - * @brief I/O Ports-PFS (R_PFS) + * @brief Entire PFS register map for all ports. + * + * Represents all available ports in the microcontroller that support + * Port Function Select configuration. */ typedef struct { - volatile hal_ll_gpio_pfs_port_t port[10]; + volatile hal_ll_gpio_pfs_port_t port[10]; /**< Port array supporting PFS. */ } hal_ll_gpio_pfs_t; /** From cb1f4609b0a7c7e625970c5432ceadaab87e875b Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 6 Aug 2025 11:53:11 +0200 Subject: [PATCH 53/62] Update targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h --- targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h index 7ee0dbf26f..15458945d4 100644 --- a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h +++ b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h @@ -146,9 +146,9 @@ void hal_ll_gpio_write_pin_output(hal_ll_gpio_pin_t *pin, uint8_t value); */ #if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) #define hal_ll_gpio_toggle_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ - ((((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr & ((hal_ll_gpio_pin_t *)_handle)->mask))) ? \ - (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr &= ~((hal_ll_gpio_pin_t *)_handle)->mask) : \ - (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr |= ((hal_ll_gpio_pin_t *)_handle)->mask)) : \ + ((((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr & ((hal_ll_gpio_pin_t *)_handle)->mask))) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr &= ~((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->podr |= ((hal_ll_gpio_pin_t *)_handle)->mask)) : \ (0)) #else void hal_ll_gpio_toggle_pin_output(hal_ll_gpio_pin_t *pin); From 972fc267d2c243121c7af5e266ed51774737f65d Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 6 Aug 2025 11:53:18 +0200 Subject: [PATCH 54/62] Update targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h --- targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h index 15458945d4..33a4528631 100644 --- a/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h +++ b/targets/arm/mikroe/renesas/include/gpio/hal_ll_gpio.h @@ -261,8 +261,8 @@ hal_ll_port_size_t hal_ll_gpio_read_port_output(hal_ll_gpio_port_t *port); */ #if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) #define hal_ll_gpio_write_port_output(_handle,_value) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ - (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->podr = \ - ((hal_ll_gpio_port_t *)_handle)->mask & (hal_ll_port_size_t)_value) : \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->podr = \ + ((hal_ll_gpio_port_t *)_handle)->mask & (hal_ll_port_size_t)_value) : \ (0)) #else void hal_ll_gpio_write_port_output(hal_ll_gpio_port_t *port, hal_ll_port_size_t value); From 28ea46461645e5141820a362e219b735ec87cc85 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 6 Aug 2025 11:53:27 +0200 Subject: [PATCH 55/62] Update targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_master.h --- targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_master.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_master.h b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_master.h index 2bb7db69e6..02c683f928 100644 --- a/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_master.h +++ b/targets/arm/mikroe/renesas/include/i2c/hal_ll_i2c_master.h @@ -219,7 +219,11 @@ hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, * Returns one of pre-defined values. * Take into consideration that this is hardware specific. */ -hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ); +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, + uint8_t *write_data_buf, + size_t len_write_data, + uint8_t *read_data_buf, + size_t len_read_data ); /** * @brief Closes I2C master HAL and HAL_LOW_LEVEL context object. From df10d1791476b955014a49dae05db846062d0944 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 6 Aug 2025 11:53:41 +0200 Subject: [PATCH 56/62] Update targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h --- .../mikroe/renesas/include/spi_master/hal_ll_spi_master.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h index ef8850fa70..6c61e5aa46 100644 --- a/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h +++ b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h @@ -117,8 +117,11 @@ typedef struct { * Returns one of pre-defined error values. * Take into consideration that this is hardware specific. */ -hal_ll_err_t hal_ll_spi_master_register_handle( hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, - hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id ); +hal_ll_err_t hal_ll_spi_master_register_handle( hal_ll_pin_name_t sck, + hal_ll_pin_name_t miso, + hal_ll_pin_name_t mosi, + hal_ll_spi_master_handle_register_t *handle_map, + uint8_t *hal_module_id ); /** * @brief Configures specified module. From e1dbfdc5a5bbbda3e98675d4a98c91eb68beb818 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 6 Aug 2025 11:54:45 +0200 Subject: [PATCH 57/62] Update targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h --- .../mikroe/renesas/include/spi_master/hal_ll_spi_master.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h index 6c61e5aa46..bba04635fb 100644 --- a/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h +++ b/targets/arm/mikroe/renesas/include/spi_master/hal_ll_spi_master.h @@ -209,7 +209,11 @@ hal_ll_err_t hal_ll_spi_master_read( handle_t *handle, uint8_t *read_data_buffer * Returns one of pre-defined values. * Take into consideration that this is hardware specific. */ -hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data ); +hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, + uint8_t *write_data_buffer, + size_t length_write_data, + uint8_t *read_data_buffer, + size_t length_read_data ); /** * @brief Performs simultaneous write and read on SPI bus. From 72007950eef206d750ece729c90e4b2a92943ad4 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 6 Aug 2025 11:54:54 +0200 Subject: [PATCH 58/62] Update targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h --- targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h index fb18eb9750..b94cda84fe 100644 --- a/targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h +++ b/targets/arm/mikroe/renesas/include/uart/hal_ll_uart.h @@ -146,7 +146,10 @@ typedef struct * Returns one of pre-defined values. * Take into consideration that this is hardware specific. */ -hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ); +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, + hal_ll_pin_name_t rx_pin, + hal_ll_uart_handle_register_t *handle_map, + uint8_t *hal_module_id ); /** * @brief Configures specified module. From 5cecc996c8ccf96e5882b2fb19c619d1852a0e34 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 6 Aug 2025 11:57:07 +0200 Subject: [PATCH 59/62] Update targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c --- targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c b/targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c index 2a33f32449..641f8ae6a1 100644 --- a/targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c +++ b/targets/arm/mikroe/renesas/src/gpio/hal_ll_gpio.c @@ -123,7 +123,8 @@ void hal_ll_gpio_clear_pin_output(hal_ll_gpio_pin_t *pin) { /******************************************************************************* * */ -void hal_ll_gpio_configure_port(hal_ll_gpio_port_t *port, hal_ll_port_name_t name, hal_ll_gpio_mask_t mask, hal_ll_gpio_direction_t direction) { +void hal_ll_gpio_configure_port(hal_ll_gpio_port_t *port, hal_ll_port_name_t name, + hal_ll_gpio_mask_t mask, hal_ll_gpio_direction_t direction) { port->base = hal_ll_gpio_port_base(name); port->mask = mask; From 02c03da332e26dd5fbffbb9fb08b51e24a759a24 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 6 Aug 2025 11:57:17 +0200 Subject: [PATCH 60/62] Update targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c --- .../mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c | 1 - 1 file changed, 1 deletion(-) diff --git a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c index c216d60a43..397c6da9fc 100644 --- a/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/renesas/src/i2c/implementation_1/hal_ll_i2c_master.c @@ -631,7 +631,6 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m dummy_read = read_reg( &hal_ll_hw_reg->icdrr ); } else { dummy_read = read_reg( &hal_ll_hw_reg->icdrr ); - // set_reg_bit( &hal_ll_hw_reg->icmr3, HAL_LL_I2C_ICMR3_WAIT ); if( 1 != len_read_data ) { for( uint8_t i = 0; i < len_read_data - 2; i++ ) { time_counter = map->timeout; From 8e26b8203074cc3b60be6cf2b5af49398ecd6c02 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 6 Aug 2025 12:13:34 +0200 Subject: [PATCH 61/62] tests folder update --- tests/CMakeLists.txt | 1 - tests/gpio/src/main.c | 44 +-- tests/i2c/main.c | 4 +- tests/pwm/default/main.c | 4 +- tests/renesas/CMakeLists.txt | 10 - tests/renesas/ReadMe.txt | 9 - tests/renesas/src/main.c | 543 ----------------------------------- 7 files changed, 9 insertions(+), 606 deletions(-) delete mode 100644 tests/renesas/CMakeLists.txt delete mode 100644 tests/renesas/ReadMe.txt delete mode 100644 tests/renesas/src/main.c diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index aa5a1ac302..ad027b29c7 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -18,7 +18,6 @@ endif() add_subdirectory(gpio) add_subdirectory(button_simulation) -add_subdirectory(renesas) ## 8K Flash and 2K RAM minimum for this test. memory_sdk_test_check(memory_issue 8192 2048) diff --git a/tests/gpio/src/main.c b/tests/gpio/src/main.c index 5997aa2691..e83f08e1ce 100644 --- a/tests/gpio/src/main.c +++ b/tests/gpio/src/main.c @@ -24,8 +24,8 @@ // -------------------------------------------------------------------- MACROS // TODO -#define TEST_CLOCK false -#define CLOCK_TEST_PORT PORT_4 +#define TEST_CLOCK true +#define CLOCK_TEST_PORT HAL_PORT_NC #define TEST_FLATTENER false @@ -38,7 +38,7 @@ #else #define PIN_TEST false #define PORT_TEST false -#define BUTTON_TEST true +#define BUTTON_TEST false #endif // TODO // Define port used for signaling errors. @@ -74,11 +74,7 @@ static port_t test_port; // PORT driver context structure. static digital_in_t input_pin; // Digital input driver context structure. static digital_out_t output_pin; // Digital output driver context structure. -static uint8_t port_counter = port_count_size; // Defined in CMakeLists.txt file. - -#define PWPR_REGISTER_BASE (*( volatile uint8_t * )0x40040D03UL) -#include "mcu.h" - +static uint8_t port_counter = port_count_size; // Defined in memake file. // ----------------------------------------------------------------- USER CODE int main( void ) { /* Do not remove this line or clock might not be set correctly. */ @@ -86,41 +82,11 @@ int main( void ) { preinit(); #endif - - // // Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register. - // // PWPR_REGISTER_BASE &= ~0x80; // Clear B0WI bit - // R_PMISC->PWPR_b.B0WI = 0; - // // Set 1 to the PFSWE bit in the PWPR register. This enables writing to the PmnPFS register. - // // PWPR_REGISTER_BASE |= 0x40; // Set PFSWE bit - // R_PMISC->PWPR_b.PFSWE = 1; - - // // R_PFS->PORT[0].PIN[0].PmnPFS_b.PDR = 1; - // // R_PFS->PORT[0].PIN[0].PmnPFS_b.PMR = 0; - // // R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR = 1; - - // R_PFS->PORT[0].PIN[0].PmnPFS = 0x00000000; // GPIO mode - // R_PORT0->PDR_b.PDR0 = 1; // Direction: output - // R_PORT0->PODR_b.PODR0 = 0; // Initial state: low - // R_PORT0->PODR |= 1; - // while(1); - - // // Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register. - // R_PMISC->PWPR_b.PFSWE = 0; - // // Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register - // R_PMISC->PWPR_b.B0WI = 1; - volatile pin_name_t fetch_pin = hal_gpio_fetch_pin(LED); volatile port_name_t fetch_port = hal_gpio_fetch_port(LED); #if TEST_CLOCK - // CLOCK_TEST( CLOCK_TEST_PORT ); - port_init( &test_port, CLOCK_TEST_PORT, 0xFFFF, PIN_DIRECTION_DIGITAL_OUTPUT ); \ - while(1) { \ - port_write( &test_port, 0xFFFF ); \ - Delay_1sec(); \ - port_write( &test_port, 0x00 ); \ - Delay_1sec(); \ - } + CLOCK_TEST( CLOCK_TEST_PORT ); #endif #if TEST_FLATTENER diff --git a/tests/i2c/main.c b/tests/i2c/main.c index 0e8bc19bd7..880dc3e50b 100644 --- a/tests/i2c/main.c +++ b/tests/i2c/main.c @@ -18,8 +18,8 @@ #endif // -------------------------------------------------------------------- MACROS -#define TEST_PIN_I2C_SCL GPIO_P205 // TODO define I2C SCL pin//MIKROBUS_1_SCL// -#define TEST_PIN_I2C_SDA GPIO_P206 // TODO define I2C SDA pin//MIKROBUS_1_SDA// +#define TEST_PIN_I2C_SCL HAL_PIN_NC // TODO define I2C SCL pin +#define TEST_PIN_I2C_SDA HAL_PIN_NC // TODO define I2C SDA pin // TODO // Define an existing pin to check the accuracy of write and read functions diff --git a/tests/pwm/default/main.c b/tests/pwm/default/main.c index 246fefbdaa..8f198aef62 100644 --- a/tests/pwm/default/main.c +++ b/tests/pwm/default/main.c @@ -15,7 +15,7 @@ // -------------------------------------------------------------------- MACROS -#define TEST_PIN_PWM_TIM GPIO_P107 // TODO define pin used in test +#define TEST_PIN_PWM_TIM HAL_PIN_NC // TODO define pin used in test #define TEST_PWM_FREQUENCY 5000 // TODO define frequency used in last test @@ -201,4 +201,4 @@ int main( void ) { return 0; } -// ----------------------------------------------------------------------- END \ No newline at end of file +// ----------------------------------------------------------------------- END diff --git a/tests/renesas/CMakeLists.txt b/tests/renesas/CMakeLists.txt deleted file mode 100644 index b103097af0..0000000000 --- a/tests/renesas/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -## ./tests/renesas/CMakeLists.txt - -add_executable(test_renesas - src/main.c - ReadMe.txt -) - -target_link_libraries(test_renesas PUBLIC - MikroC.Core -) diff --git a/tests/renesas/ReadMe.txt b/tests/renesas/ReadMe.txt deleted file mode 100644 index 62f2865a92..0000000000 --- a/tests/renesas/ReadMe.txt +++ /dev/null @@ -1,9 +0,0 @@ -Example is meant for testing GPIO module using mikroSDK 2.0 - -If board exists, pins can be defined using following macro template: - -* #define LED MIKROBUS_1_PWM -* #define BUTTON MIKROBUS_1_INT -* etc. - -Go step by step through the example and follow instructions for testing. diff --git a/tests/renesas/src/main.c b/tests/renesas/src/main.c deleted file mode 100644 index 5e319d4912..0000000000 --- a/tests/renesas/src/main.c +++ /dev/null @@ -1,543 +0,0 @@ -// ------------------------------------------------------------------ INCLUDES -/** - * Any initialization code needed for MCU to function properly. - * Do not remove this line or clock might not be set correctly. - */ -#ifdef PREINIT_SUPPORTED -#include "preinit.h" -#endif - -#include "mcu.h" -#include "interrupts.h" -#define PWPR_REGISTER_BASE (* ( volatile uint8_t * )0x40040D03UL) - -// #define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ -// #define SCI0_RXI_IRQn ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ -// #define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ -// #define SCI0_TXI_IRQn ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ -// #define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ -// #define SCI0_TEI_IRQn ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ -// #define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ -// #define SCI0_ERI_IRQn ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ -// #define VECTOR_NUMBER_SCI1_RXI ((IRQn_Type)4) /* SCI1 RXI (Received data full) */ -// #define SCI1_RXI_IRQn ((IRQn_Type)4) /* SCI1 RXI (Received data full) */ -// #define VECTOR_NUMBER_SCI1_TXI ((IRQn_Type)5) /* SCI1 TXI (Transmit data empty) */ -// #define SCI1_TXI_IRQn ((IRQn_Type)5) /* SCI1 TXI (Transmit data empty) */ -// #define VECTOR_NUMBER_SCI1_TEI ((IRQn_Type)6) /* SCI1 TEI (Transmit end) */ -// #define SCI1_TEI_IRQn ((IRQn_Type)6) /* SCI1 TEI (Transmit end) */ -// #define VECTOR_NUMBER_SCI1_ERI ((IRQn_Type)7) /* SCI1 ERI (Receive error) */ -// #define SCI1_ERI_IRQn ((IRQn_Type)7) /* SCI1 ERI (Receive error) */ -// #define VECTOR_NUMBER_SCI2_RXI ((IRQn_Type)8) /* SCI2 RXI (Received data full) */ -// #define SCI2_RXI_IRQn ((IRQn_Type)8) /* SCI2 RXI (Received data full) */ -// #define VECTOR_NUMBER_SCI2_TXI ((IRQn_Type)9) /* SCI2 TXI (Transmit data empty) */ -// #define SCI2_TXI_IRQn ((IRQn_Type)9) /* SCI2 TXI (Transmit data empty) */ -// #define VECTOR_NUMBER_SCI2_TEI ((IRQn_Type)10) /* SCI2 TEI (Transmit end) */ -// #define SCI2_TEI_IRQn ((IRQn_Type)10) /* SCI2 TEI (Transmit end) */ -// #define VECTOR_NUMBER_SCI2_ERI ((IRQn_Type)11) /* SCI2 ERI (Receive error) */ -// #define SCI2_ERI_IRQn ((IRQn_Type)11) /* SCI2 ERI (Receive error) */ -// #define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ -// #define RTC_ALARM_IRQn ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ -// #define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ -// #define RTC_PERIOD_IRQn ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ -// #define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ -// #define RTC_CARRY_IRQn ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ -// #define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ -// #define AGT0_INT_IRQn ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ -// #define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */ -// #define ICU_IRQ0_IRQn ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */ -// #define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)17) /* SPI0 RXI (Receive buffer full) */ -// #define SPI0_RXI_IRQn ((IRQn_Type)17) /* SPI0 RXI (Receive buffer full) */ -// #define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)18) /* SPI0 TXI (Transmit buffer empty) */ -// #define SPI0_TXI_IRQn ((IRQn_Type)18) /* SPI0 TXI (Transmit buffer empty) */ -// #define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)19) /* SPI0 TEI (Transmission complete event) */ -// #define SPI0_TEI_IRQn ((IRQn_Type)19) /* SPI0 TEI (Transmission complete event) */ -// #define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)20) /* SPI0 ERI (Error) */ -// #define SPI0_ERI_IRQn ((IRQn_Type)20) /* SPI0 ERI (Error) */ - -typedef void (* fsp_vector_t)(void); -#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) - #define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" - - /* ISR prototypes */ -void ICU_IELSR0_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR1_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR2_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR3_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR4_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR5_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR6_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR7_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR8_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR9_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR10_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR11_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR12_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR13_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR14_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR15_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR16_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR17_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR18_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR19_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR20_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR21_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR22_Handler(void); -void ICU_IELSR23_Handler(void); -void ICU_IELSR24_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR25_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR26_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR27_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR28_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR29_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR30_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); -void ICU_IELSR31_Handler(void) __attribute__((weak, alias("ICU_IELSR23_Handler"))); - -const fsp_vector_t g_vector_table[32] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = -{ - ICU_IELSR0_Handler, - ICU_IELSR1_Handler, - ICU_IELSR2_Handler, - ICU_IELSR3_Handler, - ICU_IELSR4_Handler, - ICU_IELSR5_Handler, - ICU_IELSR6_Handler, - ICU_IELSR7_Handler, - ICU_IELSR8_Handler, - ICU_IELSR9_Handler, - ICU_IELSR10_Handler, - ICU_IELSR11_Handler, - ICU_IELSR12_Handler, - ICU_IELSR13_Handler, - ICU_IELSR14_Handler, - ICU_IELSR15_Handler, - ICU_IELSR16_Handler, - ICU_IELSR17_Handler, - ICU_IELSR18_Handler, - ICU_IELSR19_Handler, - ICU_IELSR20_Handler, - ICU_IELSR21_Handler, - ICU_IELSR22_Handler, - ICU_IELSR23_Handler, - ICU_IELSR24_Handler, - ICU_IELSR25_Handler, - ICU_IELSR26_Handler, - ICU_IELSR27_Handler, - ICU_IELSR28_Handler, - ICU_IELSR29_Handler, - ICU_IELSR30_Handler, - ICU_IELSR31_Handler -}; - -typedef enum e_elc_event_ra4m1 -{ - ELC_EVENT_NONE = (0x0), // Link disabled - ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 - ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 - ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 - ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 - ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 - ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 - ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 - ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 - ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 - ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 - ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 - ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 - ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 - ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 - ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 - ELC_EVENT_DMAC0_INT = (0x011), // DMAC0 transfer end - ELC_EVENT_DMAC1_INT = (0x012), // DMAC1 transfer end - ELC_EVENT_DMAC2_INT = (0x013), // DMAC2 transfer end - ELC_EVENT_DMAC3_INT = (0x014), // DMAC3 transfer end - ELC_EVENT_DTC_COMPLETE = (0x015), // DTC transfer complete - ELC_EVENT_DTC_END = (0x016), // DTC transfer end - ELC_EVENT_ICU_SNOOZE_CANCEL = (0x017), // Canceling from Snooze mode - ELC_EVENT_FCU_FRDYI = (0x018), // Flash ready interrupt - ELC_EVENT_LVD_LVD1 = (0x019), // Voltage monitor 1 interrupt - ELC_EVENT_LVD_LVD2 = (0x01A), // Voltage monitor 2 interrupt - ELC_EVENT_LVD_VBATT = (0x01B), // VBATT low voltage detect - ELC_EVENT_CGC_MOSC_STOP = (0x01C), // Main Clock oscillation stop - ELC_EVENT_LPM_SNOOZE_REQUEST = (0x01D), // Snooze entry - ELC_EVENT_AGT0_INT = (0x01E), // AGT interrupt - ELC_EVENT_AGT0_COMPARE_A = (0x01F), // Compare match A - ELC_EVENT_AGT0_COMPARE_B = (0x020), // Compare match B - ELC_EVENT_AGT1_INT = (0x021), // AGT interrupt - ELC_EVENT_AGT1_COMPARE_A = (0x022), // Compare match A - ELC_EVENT_AGT1_COMPARE_B = (0x023), // Compare match B - ELC_EVENT_IWDT_UNDERFLOW = (0x024), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x025), // WDT underflow - ELC_EVENT_RTC_ALARM = (0x026), // Alarm interrupt - ELC_EVENT_RTC_PERIOD = (0x027), // Periodic interrupt - ELC_EVENT_RTC_CARRY = (0x028), // Carry interrupt - ELC_EVENT_ADC0_SCAN_END = (0x029), // End of A/D scanning operation - ELC_EVENT_ADC0_SCAN_END_B = (0x02A), // A/D scan end interrupt for group B - ELC_EVENT_ADC0_WINDOW_A = (0x02B), // Window A Compare match interrupt - ELC_EVENT_ADC0_WINDOW_B = (0x02C), // Window B Compare match interrupt - ELC_EVENT_ADC0_COMPARE_MATCH = (0x02D), // Compare match - ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x02E), // Compare mismatch - ELC_EVENT_ACMPLP0_INT = (0x02F), // Low Power Comparator channel 0 interrupt - ELC_EVENT_ACMPLP1_INT = (0x030), // Low Power Comparator channel 1 interrupt - ELC_EVENT_USBFS_FIFO_0 = (0x031), // DMA/DTC transfer request 0 - ELC_EVENT_USBFS_FIFO_1 = (0x032), // DMA/DTC transfer request 1 - ELC_EVENT_USBFS_INT = (0x033), // USBFS interrupt - ELC_EVENT_USBFS_RESUME = (0x034), // USBFS resume interrupt - ELC_EVENT_IIC0_RXI = (0x035), // Receive data full - ELC_EVENT_IIC0_TXI = (0x036), // Transmit data empty - ELC_EVENT_IIC0_TEI = (0x037), // Transmit end - ELC_EVENT_IIC0_ERI = (0x038), // Transfer error - ELC_EVENT_IIC0_WUI = (0x039), // Wakeup interrupt - ELC_EVENT_IIC1_RXI = (0x03A), // Receive data full - ELC_EVENT_IIC1_TXI = (0x03B), // Transmit data empty - ELC_EVENT_IIC1_TEI = (0x03C), // Transmit end - ELC_EVENT_IIC1_ERI = (0x03D), // Transfer error - ELC_EVENT_SSI0_TXI = (0x03E), // Transmit data empty - ELC_EVENT_SSI0_RXI = (0x03F), // Receive data full - ELC_EVENT_SSI0_INT = (0x041), // Error interrupt - ELC_EVENT_CTSU_WRITE = (0x042), // Write request interrupt - ELC_EVENT_CTSU_READ = (0x043), // Measurement data transfer request interrupt - ELC_EVENT_CTSU_END = (0x044), // Measurement end interrupt - ELC_EVENT_KEY_INT = (0x045), // Key interrupt - ELC_EVENT_DOC_INT = (0x046), // Data operation circuit interrupt - ELC_EVENT_CAC_FREQUENCY_ERROR = (0x047), // Frequency error interrupt - ELC_EVENT_CAC_MEASUREMENT_END = (0x048), // Measurement end interrupt - ELC_EVENT_CAC_OVERFLOW = (0x049), // Overflow interrupt - ELC_EVENT_CAN0_ERROR = (0x04A), // Error interrupt - ELC_EVENT_CAN0_FIFO_RX = (0x04B), // Receive FIFO interrupt - ELC_EVENT_CAN0_FIFO_TX = (0x04C), // Transmit FIFO interrupt - ELC_EVENT_CAN0_MAILBOX_RX = (0x04D), // Reception complete interrupt - ELC_EVENT_CAN0_MAILBOX_TX = (0x04E), // Transmission complete interrupt - ELC_EVENT_IOPORT_EVENT_1 = (0x04F), // Port 1 event - ELC_EVENT_IOPORT_EVENT_2 = (0x050), // Port 2 event - ELC_EVENT_IOPORT_EVENT_3 = (0x051), // Port 3 event - ELC_EVENT_IOPORT_EVENT_4 = (0x052), // Port 4 event - ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x053), // Software event 0 - ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x054), // Software event 1 - ELC_EVENT_POEG0_EVENT = (0x055), // Port Output disable 0 interrupt - ELC_EVENT_POEG1_EVENT = (0x056), // Port Output disable 1 interrupt - ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x057), // Capture/Compare match A - ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x058), // Capture/Compare match B - ELC_EVENT_GPT0_COMPARE_C = (0x059), // Compare match C - ELC_EVENT_GPT0_COMPARE_D = (0x05A), // Compare match D - ELC_EVENT_GPT0_COMPARE_E = (0x05B), // Compare match E - ELC_EVENT_GPT0_COMPARE_F = (0x05C), // Compare match F - ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x05D), // Overflow - ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x05E), // Underflow - ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x05F), // Capture/Compare match A - ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x060), // Capture/Compare match B - ELC_EVENT_GPT1_COMPARE_C = (0x061), // Compare match C - ELC_EVENT_GPT1_COMPARE_D = (0x062), // Compare match D - ELC_EVENT_GPT1_COMPARE_E = (0x063), // Compare match E - ELC_EVENT_GPT1_COMPARE_F = (0x064), // Compare match F - ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x065), // Overflow - ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x066), // Underflow - ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x067), // Capture/Compare match A - ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x068), // Capture/Compare match B - ELC_EVENT_GPT2_COMPARE_C = (0x069), // Compare match C - ELC_EVENT_GPT2_COMPARE_D = (0x06A), // Compare match D - ELC_EVENT_GPT2_COMPARE_E = (0x06B), // Compare match E - ELC_EVENT_GPT2_COMPARE_F = (0x06C), // Compare match F - ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x06D), // Overflow - ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x06E), // Underflow - ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x06F), // Capture/Compare match A - ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x070), // Capture/Compare match B - ELC_EVENT_GPT3_COMPARE_C = (0x071), // Compare match C - ELC_EVENT_GPT3_COMPARE_D = (0x072), // Compare match D - ELC_EVENT_GPT3_COMPARE_E = (0x073), // Compare match E - ELC_EVENT_GPT3_COMPARE_F = (0x074), // Compare match F - ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x075), // Overflow - ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x076), // Underflow - ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x077), // Capture/Compare match A - ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x078), // Capture/Compare match B - ELC_EVENT_GPT4_COMPARE_C = (0x079), // Compare match C - ELC_EVENT_GPT4_COMPARE_D = (0x07A), // Compare match D - ELC_EVENT_GPT4_COMPARE_E = (0x07B), // Compare match E - ELC_EVENT_GPT4_COMPARE_F = (0x07C), // Compare match F - ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x07D), // Overflow - ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x07E), // Underflow - ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x07F), // Capture/Compare match A - ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x080), // Capture/Compare match B - ELC_EVENT_GPT5_COMPARE_C = (0x081), // Compare match C - ELC_EVENT_GPT5_COMPARE_D = (0x082), // Compare match D - ELC_EVENT_GPT5_COMPARE_E = (0x083), // Compare match E - ELC_EVENT_GPT5_COMPARE_F = (0x084), // Compare match F - ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x085), // Overflow - ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x086), // Underflow - ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x087), // Capture/Compare match A - ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x088), // Capture/Compare match B - ELC_EVENT_GPT6_COMPARE_C = (0x089), // Compare match C - ELC_EVENT_GPT6_COMPARE_D = (0x08A), // Compare match D - ELC_EVENT_GPT6_COMPARE_E = (0x08B), // Compare match E - ELC_EVENT_GPT6_COMPARE_F = (0x08C), // Compare match F - ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x08D), // Overflow - ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x08E), // Underflow - ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x08F), // Capture/Compare match A - ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x090), // Capture/Compare match B - ELC_EVENT_GPT7_COMPARE_C = (0x091), // Compare match C - ELC_EVENT_GPT7_COMPARE_D = (0x092), // Compare match D - ELC_EVENT_GPT7_COMPARE_E = (0x093), // Compare match E - ELC_EVENT_GPT7_COMPARE_F = (0x094), // Compare match F - ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x095), // Overflow - ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x096), // Underflow - ELC_EVENT_OPS_UVW_EDGE = (0x097), // UVW edge event - ELC_EVENT_SCI0_RXI = (0x098), // Receive data full - ELC_EVENT_SCI0_TXI = (0x099), // Transmit data empty - ELC_EVENT_SCI0_TEI = (0x09A), // Transmit end - ELC_EVENT_SCI0_ERI = (0x09B), // Receive error - ELC_EVENT_SCI0_AM = (0x09C), // Address match event - ELC_EVENT_SCI0_RXI_OR_ERI = (0x09D), // Receive data full/Receive error - ELC_EVENT_SCI1_RXI = (0x09E), // Receive data full - ELC_EVENT_SCI1_TXI = (0x09F), // Transmit data empty - ELC_EVENT_SCI1_TEI = (0x0A0), // Transmit end - ELC_EVENT_SCI1_ERI = (0x0A1), // Receive error - ELC_EVENT_SCI1_AM = (0x0A2), // Address match event - ELC_EVENT_SCI2_RXI = (0x0A3), // Receive data full - ELC_EVENT_SCI2_TXI = (0x0A4), // Transmit data empty - ELC_EVENT_SCI2_TEI = (0x0A5), // Transmit end - ELC_EVENT_SCI2_ERI = (0x0A6), // Receive error - ELC_EVENT_SCI2_AM = (0x0A7), // Address match event - ELC_EVENT_SCI9_RXI = (0x0A8), // Receive data full - ELC_EVENT_SCI9_TXI = (0x0A9), // Transmit data empty - ELC_EVENT_SCI9_TEI = (0x0AA), // Transmit end - ELC_EVENT_SCI9_ERI = (0x0AB), // Receive error - ELC_EVENT_SCI9_AM = (0x0AC), // Address match event - ELC_EVENT_SPI0_RXI = (0x0AD), // Receive buffer full - ELC_EVENT_SPI0_TXI = (0x0AE), // Transmit buffer empty - ELC_EVENT_SPI0_IDLE = (0x0AF), // Idle - ELC_EVENT_SPI0_ERI = (0x0B0), // Error - ELC_EVENT_SPI0_TEI = (0x0B1), // Transmission complete event - ELC_EVENT_SPI1_RXI = (0x0B2), // Receive buffer full - ELC_EVENT_SPI1_TXI = (0x0B3), // Transmit buffer empty - ELC_EVENT_SPI1_IDLE = (0x0B4), // Idle - ELC_EVENT_SPI1_ERI = (0x0B5), // Error - ELC_EVENT_SPI1_TEI = (0x0B6) // Transmission complete event -} elc_event_t; - -typedef elc_event_t bsp_interrupt_event_t; - -const bsp_interrupt_event_t g_interrupt_event_link_select[32] = -{ - [0] = ELC_EVENT_SCI0_RXI, /* SCI0 RXI (Receive data full) */ - [1] = ELC_EVENT_SCI0_TXI, /* SCI0 TXI (Transmit data empty) */ - [2] = ELC_EVENT_SCI0_TEI, /* SCI0 TEI (Transmit end) */ - [3] = ELC_EVENT_SCI0_ERI, /* SCI0 ERI (Receive error) */ - [4] = ELC_EVENT_SCI1_RXI, /* SCI1 RXI (Received data full) */ - [5] = ELC_EVENT_SCI1_TXI, /* SCI1 TXI (Transmit data empty) */ - [6] = ELC_EVENT_SCI1_TEI, /* SCI1 TEI (Transmit end) */ - [7] = ELC_EVENT_SCI1_ERI, /* SCI1 ERI (Receive error) */ - [8] = ELC_EVENT_SCI2_RXI, /* SCI2 RXI (Received data full) */ - [9] = ELC_EVENT_SCI2_TXI, /* SCI2 TXI (Transmit data empty) */ - [10] = ELC_EVENT_SCI2_TEI, /* SCI2 TEI (Transmit end) */ - [11] = ELC_EVENT_SCI2_ERI, /* SCI2 ERI (Receive error) */ - [12] = ELC_EVENT_RTC_ALARM, /* RTC ALARM (Alarm interrupt) */ - [13] = ELC_EVENT_RTC_PERIOD, /* RTC PERIOD (Periodic interrupt) */ - [14] = ELC_EVENT_RTC_CARRY, /* RTC CARRY (Carry interrupt) */ - [15] = ELC_EVENT_AGT0_INT, /* AGT0 INT (AGT interrupt) */ - [16] = ELC_EVENT_ICU_IRQ0, /* ICU IRQ0 (External pin interrupt 0) */ - [17] = ELC_EVENT_SPI0_RXI, /* SPI0 RXI (Receive buffer full) */ - [18] = ELC_EVENT_SPI0_TXI, /* SPI0 TXI (Transmit buffer empty) */ - [19] = ELC_EVENT_SPI0_TEI, /* SPI0 TEI (Transmission complete event) */ - [20] = ELC_EVENT_SPI0_ERI, /* SPI0 ERI (Error) */ -}; - -__attribute__((always_inline)) static inline void ra_enable_irq(__attribute__((unused)) uint32_t state) { - __asm__ volatile ("cpsie f" - : - : - : "memory"); -} - -__attribute__((always_inline)) static inline uint32_t ra_disable_irq(void) { - uint32_t state; - __asm__ volatile ("cpsid f" - : "=r" (state) - : - : "memory"); - return state; -} - -uint32_t check; - -void uart_init(void) -{ - // 1. Enable SCI0 in the Module Stop Register - R_SYSTEM->PRCR = 0xa502; - R_MSTP->MSTPCRB_b.MSTPB31 = 0; // Enable SCI0 (MSTPB31 = 0) - R_SYSTEM->PRCR = 0xa500; - - // 2. Configure P411 as TXD0 and P410 as RXD0 via IOPORT - // TXD0 (P411) = Peripheral function: 0x0A - // RXD0 (P410) = Peripheral function: 0x0A - - // Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register. - PWPR_REGISTER_BASE &= ~0x80; // Clear B0WI bit - // Set 1 to the PFSWE bit in the PWPR register. This enables writing to the PmnPFS register. - PWPR_REGISTER_BASE |= 0x40; // Set PFSWE bit - - // Write PFS registers directly (PFS write-protected by default) - // ra_gpio_config(pin, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_LOW_POWER, af); - R_PFS->PORT[4].PIN[11].PmnPFS_b.PMR = 0; // TXD0 - R_PFS->PORT[4].PIN[11].PmnPFS_b.PCR = 1; // TXD0 - R_PFS->PORT[4].PIN[11].PmnPFS_b.PSEL = 0x04; // TXD0 - R_PFS->PORT[4].PIN[11].PmnPFS_b.PMR = 1; // TXD0 - - // ra_gpio_config(pin, GPIO_MODE_INPUT, GPIO_PULLUP, GPIO_LOW_POWER, af); - R_PFS->PORT[4].PIN[10].PmnPFS_b.PMR = 0; // RXD0 - R_PFS->PORT[4].PIN[10].PmnPFS_b.PCR = 1; // RXD0 - R_PFS->PORT[4].PIN[10].PmnPFS_b.PSEL = 0x04; // RXD0 - R_PFS->PORT[4].PIN[10].PmnPFS_b.PMR = 1; // RXD0 - - // Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register. - PWPR_REGISTER_BASE &= ~0x40; // Set PFSWE bit - // Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register - PWPR_REGISTER_BASE |= 0x80; // Set B0WI bit - - // 3. Initialize SCI1 registers - - uint32_t state = ra_disable_irq(); - - // Disable TE and RE - R_SCI0->SCR = 0x00; - while (R_SCI0->SCR != 0); - - R_SCI0->SMR = 0x00; - R_SCI0->SCMR = 0xF3; - R_SCI0->SEMR = 0xC0; - - R_SCI0->FCR_b.FM = 1; - R_SCI0->FCR_b.TFRST = 1; - R_SCI0->FCR_b.RFRST = 1; - R_SCI0->FCR_b.TTRG = 0; - R_SCI0->FCR_b.RTRG = 0; - R_SCI0->FCR_b.RSTRG = 0; - - R_SCI0->SCR_b.CKE = 0x00; - R_SCI0->SMR_b.CKS = 0x00; - R_SCI0->BRR = 106; - - // Async, 8N1, PCLK/1 - - - - // R_SCI0->FCR_b.TFRST = 0; - // R_SCI0->FCR_b.RFRST = 0; - - - // Delay at least 1 bit time (~8.6 us at 115200 baud) - // for (volatile int i = 0; i < 1000; ++i) { __asm__("nop"); } - - // Enable transmit and receive AND their interrupts - // NVIC_SetVector((IRQn_Type) INTERRUPTS_IELSR22, (uint32_t) sci_uart_rxi_isr); // SCI0_RXI_IRQn - // NVIC_SetVector((IRQn_Type) INTERRUPTS_IELSR23, (uint32_t) sci_uart_txi_isr); // SCI0_TXI_IRQn - R_ICU->IELSR[22] = (uint32_t) g_interrupt_event_link_select[0]; - R_ICU->IELSR[23] = (uint32_t) g_interrupt_event_link_select[1]; - NVIC_EnableIRQ(38); - NVIC_EnableIRQ(39); - interrupts_enable(); - R_SCI0->SSR_b.RDRF = 0; - R_SCI0->SSR_b.TDRE = 0; - R_SCI0->SCR = 0x30; // TE + RE - R_SCI0->SCR |= 0xC0; // TIE + RIE -} - -volatile char tx_buffer[128]; -volatile int tx_head = 0, tx_tail = 0; - -volatile char rx_buffer[128]; -volatile int rx_head = 0, rx_tail = 0; - -void uart_send_char(char c) -{ - // Wait until there is space in the transmit FIFO (TDFE = 1) - while (!(R_SCI0->SSR_b.TDRE)); - R_SCI0->TDR = c; - - // Clear TDFE by writing 0 - R_SCI0->SSR_b.TDRE = 0; -} - -char uart_receive_char(void) -{ - // Wait until there is data in the receive FIFO (RDF = 1) - while (!(R_SCI0->SSR_b.RDRF)); - char c = R_SCI0->RDR; - - // Clear RDF by writing 0 - R_SCI0->SSR_b.RDRF = 0; - - return c; -} - -static void ra_sci_isr_rx(uint32_t ch) { - if (R_SCI0->SSR_b.RDRF) - { - char c = R_SCI0->RDR; - R_SCI0->SSR_b.RDRF = 0; // Clear flag - - int next = (rx_head + 1) % sizeof(rx_buffer); - if (next != rx_tail) - { - rx_buffer[rx_head] = c; - rx_head = next; - } - } -} - -static void ra_sci_isr_tx(uint32_t ch) { - if (R_SCI0->SSR_b.TDRE) - { - if (tx_head != tx_tail) - { - R_SCI0->TDR = tx_buffer[tx_tail]; - tx_tail = (tx_tail + 1) % sizeof(tx_buffer); - } - else - { - R_SCI0->SCR_b.TIE = 0; // Disable TX interrupt if nothing to send - } - - R_SCI0->SSR_b.TDRE = 0; // Clear flag - } -} - -/* rx-interrupt */ -void ICU_IELSR22_Handler(void) { - // IRQn_Type irq = R_FSP_CurrentIrqGet(); - uint32_t ch = 0; - ra_sci_isr_rx(ch); -} - -/* tx-interrupt */ -void ICU_IELSR23_Handler(void) { - // IRQn_Type irq = R_FSP_CurrentIrqGet(); - uint32_t ch = 1; - ra_sci_isr_tx(ch); -} - -int main( void ) { - /* Do not remove this line or clock might not be set correctly. */ - #ifdef PREINIT_SUPPORTED - preinit(); - #endif - - SCB->VTOR = (uint32_t)&g_vector_table; - - uart_init(); - - check = R_ICU->IELSR[23]; - uart_send_char('H'); - check = R_ICU->IELSR[23]; - uart_send_char('i'); - uart_send_char('\r'); - uart_send_char('\n'); - - while (1) - { - // char c = uart_receive_char(); - // uart_send_char(c); // Echo received char - } - - return 0; -} - -// ----------------------------------------------------------------------- END From b012e7a506758faef81071d628733aa7f1d6da42 Mon Sep 17 00:00:00 2001 From: esmaniksic Date: Wed, 6 Aug 2025 12:15:49 +0200 Subject: [PATCH 62/62] ring comment --- platform/ring/lib/src/ring.c | 1 + 1 file changed, 1 insertion(+) diff --git a/platform/ring/lib/src/ring.c b/platform/ring/lib/src/ring.c index a8f5821557..adb3089d6f 100644 --- a/platform/ring/lib/src/ring.c +++ b/platform/ring/lib/src/ring.c @@ -71,6 +71,7 @@ uint8_t ring_buf8_pop( ring_buf8_t *ring ) { uint8_t result; + // TODO // GCC & Clang compiler files for Renesas are not included into the project. #if ( vendor != renesas ) assert( ring->size > 0 );