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<h2>About OSVVM<aclass="headerlink" href="#id1" title="Link to this heading">¶</a></h2>
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<p>OSVVM is an advanced verification methodology that
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defines a VHDL verification framework, verification utility library,
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verification component library, scripting API, and co-simulation capability
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that simplifies your FPGA or ASIC verification project from start to finish.
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Using these libraries you can create a simple, readable,
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and powerful testbench that will boost productivity for either
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low level block tests (unit tests) or complex FPGA and ASIC tests.</p>
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<p>OSVVM is developed by the same VHDL experts who
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have helped develop VHDL standards.
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We have used our expert VHDL skills to create
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advanced verification capabilities that provide:</p>
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<ulclass="simple">
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<li><p>A structured transaction-based framework using verification components that is suitable for all verification tasks - from Unit/RTL to full chip/system level testing.</p></li>
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<li><p>Test cases and verification components that can be written any VHDL Engineer.</p></li>
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<li><p>Test cases that are readable and reviewable by the whole team including software and system engineers.</p></li>
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<li><p>Unmatched reuse through the entire verification process.</p></li>
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<li><p>Unmatched test reporting with HTML based test suite reports, test case reports, and logs that facilitate debug and test artifact collection.</p></li>
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<li><p>Support for continuous integration (CI/CD) with JUnit XML test suite reporting.</p></li>
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<li><p>Powerful and concise verification capabilities including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering that are simple to use and work like built-in language features.</p></li>
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<li><p>A common scripting API to run all simulators - including GHDL, NVC, Aldec Riviera-PRO and ActiveHDL, Siemens Questa and ModelSim, Synopsys VCS, and Cadence Xcelium.</p></li>
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<li><p>A Co-simulation capability that supports running software (C++) in a hardware simulation environment.</p></li>
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<li><p>A Model Independent Transaction (MIT) library that defines a transaction API (procedures such as read, write, send, get, …) and transaction interface (a record) that simplifies writing verification components and test cases.</p></li>
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<li><p>A rival to the verification capabilities of SystemVerilog + UVM.</p></li>
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</ul>
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<p>Looking to improve your VHDL verification methodology?
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OSVVM provides a complete solution for VHDL ASIC or FPGA verification.
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There is no new language to learn.
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It is simple, powerful, and concise.
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Each piece can be used separately.
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Hence, you can learn and adopt pieces as you need them.</p>
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<p>Important benefits of OSVVM:</p>
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<ulclass="simple">
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<li><dlclass="simple">
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<dt>Each piece is independent</dt><dd><ul>
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<li><p>Add them to your current VHDL testbench incrementally.</p></li>
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