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update of ply.yacc for faster compilation. Thanks to Sam Skalicky for your suggestion!
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pyverilog/vparser/ply/yacc.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1818,7 +1818,7 @@ def __init__(self):
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self.lr_productions = None
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self.lr_method = None
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def read_table(self,module,outputdir)
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def read_table(self,module,outputdir):
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if isinstance(module,types.ModuleType):
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parsetab = module
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else:

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