Merge branch 'rc-1.4.3'

Author: shtaxxx

tests/extension/thread_/stream_dump_mask/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/extension/thread_/stream_dump_mask/test_thread_stream_dump_mask.py

@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_stream_dump_mask
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_stream_dump_mask.run(filename=None, simtype=simtype,
+                                       outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')

tests/extension/thread_/stream_dump_mask/thread_stream_dump_mask.py

@@ -0,0 +1,143 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
+    ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
+    ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
+    ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
+
+    strm = vthread.Stream(m, 'mystream', clk, rst,
+                          dump=True, dump_base=10, dump_mode='all')
+    a = strm.source('a')
+    b = strm.source('b')
+    c = a + b
+    strm.sink(c, 'c')
+
+    def comp_stream(size, offset):
+        strm.set_source('a', ram_a, offset, size)
+        strm.set_source('b', ram_b, offset, size)
+        strm.set_sink('c', ram_c, offset, size)
+        strm.run()
+        strm.join()
+        strm.disable_dump()
+
+    def comp_sequential(size, offset):
+        sum = 0
+        for i in range(size):
+            a = ram_a.read(i + offset)
+            b = ram_b.read(i + offset)
+            sum = a + b
+            ram_c.write(i + offset, sum)
+
+    def check(size, offset_stream, offset_seq):
+        all_ok = True
+        for i in range(size):
+            st = ram_c.read(i + offset_stream)
+            sq = ram_c.read(i + offset_seq)
+            if vthread.verilog.NotEql(st, sq):
+                all_ok = False
+        if all_ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+    def comp(size):
+        # stream
+        offset = 0
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_stream(size, offset)
+        comp_stream(size, offset)  # dump disabled
+        myaxi.dma_write(ram_c, offset, 1024, size)
+
+        # sequential
+        offset = size
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_sequential(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024 * 2, size)
+
+        # verification
+        check(size, 0, offset)
+
+        vthread.finish()
+
+    th = vthread.Thread(m, 'th_comp', clk, rst, comp)
+    fsm = th.start(32)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    #simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)

veriloggen/fsm/fsm.py

@@ -83,7 +83,7 @@ def __init__(self, m, name, clk, rst, width=32, initname='init',
         if not nohook:
             self.m.add_hook(self.implement)
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def goto(self, dst, cond=None, else_dst=None):
         if cond is None and 'cond' in self.next_kwargs:
             cond = self.next_kwargs['cond']
@@ -130,7 +130,7 @@ def goto_from(self, src, dst, cond=None, else_dst=None):
     def inc(self):
         self._set_index(None)
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def add(self, *statement, **kwargs):
         """ add new assignments """
         kwargs.update(self.next_kwargs)
@@ -152,11 +152,15 @@ def add(self, *statement, **kwargs):
         self._clear_last_if_statement()
         return self._add_statement(statement, **kwargs)
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
+    def add_reset(self, v):
+        return self.seq.add_reset(v)
+
+    # -------------------------------------------------------------------------
     def Prev(self, var, delay, initval=0, cond=None, prefix=None):
         return self.seq.Prev(var, delay, initval, cond, prefix)
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def If(self, *cond):
         self._clear_elif_cond()
 
@@ -267,7 +271,7 @@ def Clear(self):
         self._clear_elif_cond()
         return self
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     @property
     def current(self):
         return self.state_count
@@ -314,15 +318,15 @@ def then(self):
     def here(self):
         return self.state == self.current
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def implement(self):
         if self.as_module:
             self.make_module()
             return
 
         self.make_always()
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def make_always(self, reset=(), body=(), case=True):
         if self.done:
             #raise ValueError('make_always() has been already called.')
@@ -340,7 +344,7 @@ def make_always(self, reset=(), body=(), case=True):
                 part_body,
             ))
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def make_module(self, reset=(), body=(), case=True):
         if self.done:
             #raise ValueError('make_always() has been already called.')
@@ -530,7 +534,7 @@ def make_module(self, reset=(), body=(), case=True):
         sub = Submodule(self.m, m, 'inst_' + m.name, '_%s_' % self.name,
                         arg_params=arg_params, arg_ports=arg_ports)
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def make_case(self):
         indexes = set(self.body.keys())
         indexes.update(set(self.jump.keys()))
@@ -578,7 +582,7 @@ def make_if(self):
                     for index in sorted(indexes, key=lambda x:x)])
         return ret
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def make_reset(self, reset):
         ret = collections.OrderedDict()
 
@@ -621,19 +625,19 @@ def make_reset(self, reset):
 
         return list(ret.values())
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def set_index(self, index):
         return self._set_index(index)
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def _go(self, src, dst, cond=None, else_dst=None):
         self._add_jump(src, dst, cond, else_dst)
         return self
 
     def _add_jump(self, src, dst, cond=None, else_dst=None):
         self.jump[src].append((dst, cond, else_dst))
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def _add_statement(self, statement, index=None, keep=None, delay=None, cond=None,
                        lazy_cond=False, eager_val=False, no_delay_cond=False):
 
@@ -686,7 +690,7 @@ def _add_statement(self, statement, index=None, keep=None, delay=None, cond=None
 
         return self
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def _add_dst_var(self, statement):
         for s in statement:
             values = self.dst_visitor.visit(s)
@@ -695,7 +699,7 @@ def _add_dst_var(self, statement):
                 if k not in self.dst_var:
                     self.dst_var[k] = v
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def _add_delayed_cond(self, statement, index, delay):
         name_prefix = '_'.join(
             ['', self.name, 'cond', str(index), str(self.tmp_count)])
@@ -709,7 +713,7 @@ def _add_delayed_cond(self, statement, index, delay):
             prev = tmp
         return prev
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def _add_delayed_subst(self, subst, index, delay):
         if not isinstance(subst, vtypes.Subst):
             return subst
@@ -734,7 +738,7 @@ def _add_delayed_subst(self, subst, index, delay):
             prev = tmp
         return left(prev)
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def _clear_next_kwargs(self):
         self.next_kwargs = {}
 
@@ -756,7 +760,7 @@ def _make_cond(self, condlist):
                 ret = vtypes.Ands(ret, cond)
         return ret
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def _set_index(self, index=None):
         if index is None:
             self.state_count += 1
@@ -784,7 +788,7 @@ def _get_mark_index(self, s):
                 return index
         raise KeyError("No such mark in FSM marks: %s" % s.name)
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def _add_mark(self, index):
         index = self._to_index(index)
         if index not in self.mark:
@@ -797,7 +801,7 @@ def _to_index(self, index):
             index = self._get_mark_index(index)
         return index
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def _add_delayed_state(self, value):
         if not isinstance(value, int):
             raise TypeError("Delay amount must be int, not '%s'" %
@@ -851,7 +855,7 @@ def _to_state_assign(self, dst, cond=None, else_dst=None):
                 value = value.Else(self.state(else_dst_mark))
         return value
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def _cond_case(self, index):
         if index not in self.mark:
             self._set_mark(index)
@@ -895,7 +899,7 @@ def _get_if_statement(self, index):
     def _get_delayed_if_statement(self, index, delay):
         return vtypes.If(self._delayed_cond_if(index, delay))(*self.delayed_body[delay][index])
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def __call__(self, *statement, **kwargs):
         return self.add(*statement, **kwargs)