README

Author: shtaxxx

README.md

@@ -211,50 +211,45 @@ python hello_led.py
 You will have a complete Verilog HDL source code named 'tmp.v' as below, which is generated by the source code generator.
 
 ```verilog
-module test #
-(
-  parameter WIDTH = 8
-)
+module test
 (
 
 );
 
-  reg CLK;
-  reg RST;
-  wire [WIDTH-1:0] LED;
+  localparam uut_WIDTH = 8;
+  reg uut_CLK;
+  reg uut_RST;
+  wire [uut_WIDTH-1:0] uut_LED;
 
   blinkled
-  #(
-    .WIDTH(WIDTH)
-  )
   uut
   (
-    .CLK(CLK),
-    .RST(RST),
-    .LED(LED)
+    .CLK(uut_CLK),
+    .RST(uut_RST),
+    .LED(uut_LED)
   );
 
 
   initial begin
     $dumpfile("uut.vcd");
-    $dumpvars(0, uut, CLK, RST, LED);
+    $dumpvars(0, uut, uut_CLK, uut_RST, uut_LED);
   end
 
 
   initial begin
-    CLK = 0;
+    uut_CLK = 0;
     forever begin
-      #5 CLK = !CLK;
+      #5 uut_CLK = !uut_CLK;
     end
   end
 
 
   initial begin
-    RST = 0;
+    uut_RST = 0;
     #100;
-    RST = 1;
+    uut_RST = 1;
     #100;
-    RST = 0;
+    uut_RST = 0;
     #100000;
     $finish;
   end

README.rst

@@ -236,50 +236,45 @@ which is generated by the source code generator.
 
 .. code:: verilog
 
-    module test #
-    (
-      parameter WIDTH = 8
-    )
+    module test
     (
 
     );
 
-      reg CLK;
-      reg RST;
-      wire [WIDTH-1:0] LED;
+      localparam uut_WIDTH = 8;
+      reg uut_CLK;
+      reg uut_RST;
+      wire [uut_WIDTH-1:0] uut_LED;
 
       blinkled
-      #(
-        .WIDTH(WIDTH)
-      )
       uut
       (
-        .CLK(CLK),
-        .RST(RST),
-        .LED(LED)
+        .CLK(uut_CLK),
+        .RST(uut_RST),
+        .LED(uut_LED)
       );
 
 
       initial begin
         $dumpfile("uut.vcd");
-        $dumpvars(0, uut, CLK, RST, LED);
+        $dumpvars(0, uut, uut_CLK, uut_RST, uut_LED);
       end
 
 
       initial begin
-        CLK = 0;
+        uut_CLK = 0;
         forever begin
-          #5 CLK = !CLK;
+          #5 uut_CLK = !uut_CLK;
         end
       end
 
 
       initial begin
-        RST = 0;
+        uut_RST = 0;
         #100;
-        RST = 1;
+        uut_RST = 1;
         #100;
-        RST = 0;
+        uut_RST = 0;
         #100000;
         $finish;
       end