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‎README.md

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ for pull requests
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Please check "CONTRIBUTORS.md" for the contributors who provided pull requests.
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72-
Veriloggen uses **pytest** for the integration testing. **When you send a pull request, please include a testing example with pytest.**
72+
Veriloggen uses **pytest** for the integration testing. **When you send a pull request, please include a testing example with pytest.**
7373
To write a testing code, please refer the existing testing examples in "tests" directory.
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If the pull request code passes all the tests successfully and has no obvious problem, it will be merged to the *develop* branch by the main committers.
@@ -89,7 +89,7 @@ sudo apt install iverilog
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```
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- Jinja2: 2.10 or later
92-
- Pyverilog: 1.2.0 or later
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- Pyverilog: 1.2.1 or later
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- NumPy: 1.17 or later
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```

‎by_examples.ipynb

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,325 @@
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{
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"cells": [
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"Veriloggen by examples\n",
8+
"====================\n"
9+
]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"Empty Module\n",
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"--------------------"
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]
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},
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{
20+
"cell_type": "code",
21+
"execution_count": 2,
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"metadata": {},
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"outputs": [
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{
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"name": "stdout",
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"output_type": "stream",
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"text": [
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"\n",
29+
"\n",
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"module empty\n",
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"(\n",
32+
" input CLK,\n",
33+
" input RST\n",
34+
");\n",
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"\n",
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"\n",
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"endmodule\n",
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"\n",
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"\n"
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]
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}
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],
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"source": [
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"from __future__ import absolute_import\n",
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"from __future__ import print_function\n",
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"from veriloggen import *\n",
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"\n",
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"m = Module('empty')\n",
49+
"clk = m.Input('CLK')\n",
50+
"rst = m.Input('RST')\n",
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"\n",
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"rtl = m.to_verilog()\n",
53+
"print(rtl)"
54+
]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"Combinational Circuit\n",
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"--------------------"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"### Input/Output/Reg/Wire"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 14,
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"metadata": {},
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"outputs": [
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{
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"name": "stdout",
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"output_type": "stream",
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"text": [
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"\n",
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"\n",
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"module comb\n",
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"(\n",
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" input CLK,\n",
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" input RST,\n",
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" input a,\n",
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" output b\n",
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");\n",
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"\n",
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" reg c;\n",
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" wire d;\n",
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"\n",
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"endmodule\n",
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"\n",
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"\n"
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]
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}
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],
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"source": [
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"m = Module('comb')\n",
101+
"clk = m.Input('CLK')\n",
102+
"rst = m.Input('RST')\n",
103+
"\n",
104+
"a = m.Input('a')\n",
105+
"b = m.Output('b')\n",
106+
"c = m.Reg('c')\n",
107+
"d = m.Wire('d')\n",
108+
"\n",
109+
"rtl = m.to_verilog()\n",
110+
"print(rtl)"
111+
]
112+
},
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{
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"cell_type": "markdown",
115+
"metadata": {},
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"source": [
117+
"### Multi-bit signal"
118+
]
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},
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{
121+
"cell_type": "code",
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"execution_count": 15,
123+
"metadata": {},
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"outputs": [
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{
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"name": "stdout",
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"output_type": "stream",
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"text": [
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"\n",
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"\n",
131+
"module comb\n",
132+
"(\n",
133+
" input CLK,\n",
134+
" input RST,\n",
135+
" input [8-1:0] a,\n",
136+
" output [8-1:0] b\n",
137+
");\n",
138+
"\n",
139+
" reg [16-1:0] c;\n",
140+
" wire [20-1:0] d;\n",
141+
"\n",
142+
"endmodule\n",
143+
"\n",
144+
"\n"
145+
]
146+
}
147+
],
148+
"source": [
149+
"m = Module('comb')\n",
150+
"clk = m.Input('CLK')\n",
151+
"rst = m.Input('RST')\n",
152+
"\n",
153+
"a = m.Input('a', 8)\n",
154+
"b = m.Output('b', width=a.width)\n",
155+
"c = m.Reg('c', 16)\n",
156+
"d = m.Wire('d', c.width + 4)\n",
157+
"\n",
158+
"rtl = m.to_verilog()\n",
159+
"print(rtl)"
160+
]
161+
},
162+
{
163+
"cell_type": "markdown",
164+
"metadata": {},
165+
"source": [
166+
"### Parameter and Localparam"
167+
]
168+
},
169+
{
170+
"cell_type": "code",
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"execution_count": 16,
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"metadata": {},
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"outputs": [
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{
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"name": "stdout",
176+
"output_type": "stream",
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"text": [
178+
"\n",
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"\n",
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"module comb #\n",
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"(\n",
182+
" parameter sig_width = 8\n",
183+
")\n",
184+
"(\n",
185+
" input CLK,\n",
186+
" input RST,\n",
187+
" input [sig_width-1:0] a,\n",
188+
" output [sig_width-1:0] b\n",
189+
");\n",
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"\n",
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" reg [sig_width-1:0] c;\n",
192+
" wire [sig_width+4-1:0] d;\n",
193+
"\n",
194+
"endmodule\n",
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"\n",
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"\n"
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]
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}
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],
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"source": [
201+
"m = Module('comb')\n",
202+
"clk = m.Input('CLK')\n",
203+
"rst = m.Input('RST')\n",
204+
"\n",
205+
"sig_width = m.Parameter('sig_width', 8)\n",
206+
"\n",
207+
"a = m.Input('a', sig_width)\n",
208+
"b = m.Output('b', a.width)\n",
209+
"c = m.Reg('c', a.width)\n",
210+
"d = m.Wire('d', c.width + 4)\n",
211+
"\n",
212+
"rtl = m.to_verilog()\n",
213+
"print(rtl)"
214+
]
215+
},
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{
217+
"cell_type": "markdown",
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"metadata": {},
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"source": [
220+
"### Substitution and Assign"
221+
]
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},
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{
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"cell_type": "code",
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"execution_count": 21,
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"metadata": {},
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"outputs": [
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{
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"data": {
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"text/plain": [
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"<veriloggen.core.vtypes.Subst at 0x10c721ad0>"
232+
]
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},
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"execution_count": 21,
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"metadata": {},
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"output_type": "execute_result"
237+
}
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],
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"source": [
240+
"m = Module('comb')\n",
241+
"clk = m.Input('CLK')\n",
242+
"rst = m.Input('RST')\n",
243+
"\n",
244+
"a = m.Input('a', 8)\n",
245+
"b = m.Output('b', 8)\n",
246+
"c = m.Wire('c', 8)\n",
247+
"d = m.Wire('d', 8)\n",
248+
"\n",
249+
"# Substitusion\n",
250+
"c(a + 1) # --> Subst object representing \"c <- a + 1\""
251+
]
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},
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{
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"cell_type": "code",
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"execution_count": 25,
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"metadata": {},
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"outputs": [
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{
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"name": "stdout",
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"output_type": "stream",
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"text": [
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"\n",
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"\n",
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"module comb\n",
265+
"(\n",
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" input CLK,\n",
267+
" input RST,\n",
268+
" input [8-1:0] a,\n",
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" output [8-1:0] b\n",
270+
");\n",
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"\n",
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" wire [8-1:0] c;\n",
273+
" wire [8-1:0] d;\n",
274+
" assign c = a + 1;\n",
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" assign d = a + 2;\n",
276+
"\n",
277+
"endmodule\n",
278+
"\n",
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"\n"
280+
]
281+
}
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],
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"source": [
284+
"m = Module('comb')\n",
285+
"clk = m.Input('CLK')\n",
286+
"rst = m.Input('RST')\n",
287+
"\n",
288+
"a = m.Input('a', 8)\n",
289+
"b = m.Output('b', 8)\n",
290+
"c = m.Wire('c', 8)\n",
291+
"d = m.Wire('d', 8)\n",
292+
"\n",
293+
"# Assign requires Substitution object\n",
294+
"m.Assign(c(a + 1))\n",
295+
"\n",
296+
"# var.assign() method returns same result\n",
297+
"d.assign(a + 2)\n",
298+
"\n",
299+
"rtl = m.to_verilog()\n",
300+
"print(rtl)"
301+
]
302+
}
303+
],
304+
"metadata": {
305+
"kernelspec": {
306+
"display_name": "Python 3",
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"language": "python",
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"name": "python3"
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},
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"language_info": {
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"codemirror_mode": {
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"name": "ipython",
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"version": 3
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},
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"file_extension": ".py",
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"mimetype": "text/x-python",
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"name": "python",
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"nbconvert_exporter": "python",
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"pygments_lexer": "ipython3",
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"version": "3.7.5"
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}
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},
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"nbformat": 4,
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"nbformat_minor": 2
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}

‎setup.py

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@@ -23,7 +23,7 @@ def read(filename):
2323
'veriloggen.simulation': ['*.cpp'],
2424
},
2525
install_requires=['Jinja2>=2.10',
26-
'pyverilog>=1.2.0',
26+
'pyverilog>=1.2.1',
2727
'numpy>=1.17'],
2828
extras_require={
2929
'test': ['pytest>=3.8.1', 'pytest-pythonpath>=0.7.3'],

‎tests/extension/stream_/average/test_stream_average.py

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@@ -147,8 +147,8 @@
147147
reg signed [32-1:0] __delay_data_31;
148148
reg signed [32-1:0] _plus_data_25;
149149
reg signed [32-1:0] __delay_data_32;
150-
reg signed [32-1:0] _sra_data_26;
151-
reg signed [32-1:0] __delay_data_33;
150+
wire signed [32-1:0] _sra_data_26;
151+
assign _sra_data_26 = _plus_data_25 >>> 3'sd3;
152152
reg signed [32-1:0] _plus_data_28;
153153
assign zdata = _plus_data_28;
154154
@@ -173,8 +173,6 @@
173173
__delay_data_31 <= 0;
174174
_plus_data_25 <= 0;
175175
__delay_data_32 <= 0;
176-
_sra_data_26 <= 0;
177-
__delay_data_33 <= 0;
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_plus_data_28 <= 0;
179177
end else begin
180178
_plus_data_2 <= xdata + 1'sd0;
@@ -196,9 +194,7 @@
196194
__delay_data_31 <= __delay_data_30;
197195
_plus_data_25 <= _plus_data_21 + _plus_data_24;
198196
__delay_data_32 <= __delay_data_31;
199-
_sra_data_26 <= _plus_data_25 >>> 3'sd3;
200-
__delay_data_33 <= __delay_data_32;
201-
_plus_data_28 <= _sra_data_26 + __delay_data_33;
197+
_plus_data_28 <= _sra_data_26 + __delay_data_32;
202198
end
203199
end
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