ArrayReg question #444
Replies: 4 comments
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join(ghz_state(2), zero_state(3)) |
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@Roger-luo gives the simplest way. And there are two ways I could figure out.
using Yao
# method 1
reg1 = arrayreg(ComplexF64[0, 1/sqrt(2), 1/sqrt(2), 0])
insert_qubits!(reg1, 3, 3)
# method 2
reg2 = zero_state(5)
circ = chain(5, put(5, 1=>H), control(5, 1, 2=>X), put(5, 1=>X))
reg2 |> circ
# check if their are equivalent
@show fidelity(reg1, reg2)
By the way, I suggest to use |
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I think an additional X gate is still needed here because what he want is |01>+|10> instead of |00>+|11>. join(
ghz_state(2) |> put(2, 1=>X),
zero_state(3)
) |
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Thank you both for your fast responses. I shall test your suggestions. |
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For this circuit:
How do I run it on such this input with ArrayReg?

Thanks,
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