Merge pull request #2831 from ChrisRackauckas-Claude/add-simd-rk-sublibrary

Add OrdinaryDiffEqSIMDRK as a standalone sublibrary

Author: ChrisRackauckas

.github/workflows/CI.yml

@@ -51,6 +51,7 @@ jobs:
           - OrdinaryDiffEqRKN
           - OrdinaryDiffEqRosenbrock
           - OrdinaryDiffEqSDIRK
+          - OrdinaryDiffEqSIMDRK
           - OrdinaryDiffEqSSPRK
           - OrdinaryDiffEqStabilizedIRK
           - OrdinaryDiffEqStabilizedRK

lib/OrdinaryDiffEqSIMDRK/LICENSE.md

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2022 Yingbo Ma <mayingbo5@gmail.com> and contributors
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

lib/OrdinaryDiffEqSIMDRK/Project.toml

@@ -0,0 +1,39 @@
+name = "OrdinaryDiffEqSIMDRK"
+uuid = "dc97f408-7a72-40e4-9b0d-228a53b292f8"
+authors = ["Yingbo Ma <mayingbo5@gmail.com>", "Chris Elrod <elrodc@gmail.com>"]
+version = "1.0.0"
+
+[deps]
+MuladdMacro = "46d2c3a1-f734-5fdb-9937-b9b9aeba4221"
+OrdinaryDiffEqCore = "bbf590c4-e513-4bbe-9b18-05decba2e5d8"
+Reexport = "189a3867-3050-52da-a836-e630ba90ab69"
+SLEEFPirates = "476501e8-09a2-5ece-8869-fb82de89a1fa"
+Static = "aedffcd0-7271-4cad-89d0-dc628f76c6d3"
+UnPack = "3a884ed6-31ef-47d7-9d2a-63182c4928ed"
+VectorizationBase = "3d5dd08c-fd9d-11e8-17fa-ed2836048c2f"
+
+[compat]
+DiffEqDevTools = "2.44"
+MuladdMacro = "0.2"
+OrdinaryDiffEqCore = "1"
+Reexport = "1"
+SafeTestsets = "0.1"
+SLEEFPirates = "0.6"
+Static = "0.7, 0.8, 1"
+StaticArrays = "1.9"
+Test = "1"
+UnPack = "1"
+VectorizationBase = "0.21"
+julia = "1.10"
+
+[extras]
+DiffEqDevTools = "f3b72e0c-5b89-59e1-b016-84e28bfd966d"
+SafeTestsets = "1bc83da4-3b8d-516f-aca4-4fe02f6d838f"
+StaticArrays = "90137ffa-7385-5640-81b9-e52037218182"
+Test = "8dfed614-e22c-5e08-85e1-65c5234f0b40"
+
+[targets]
+test = ["DiffEqDevTools", "SafeTestsets", "StaticArrays", "Test"]
+
+[sources.OrdinaryDiffEqCore]
+path = "../OrdinaryDiffEqCore"

lib/OrdinaryDiffEqSIMDRK/src/OrdinaryDiffEqSIMDRK.jl

@@ -0,0 +1,17 @@
+module OrdinaryDiffEqSIMDRK
+
+using MuladdMacro, UnPack, Static
+using OrdinaryDiffEqCore: OrdinaryDiffEqAdaptiveAlgorithm, OrdinaryDiffEqConstantCache,
+                          trivial_limiter!, calculate_residuals, constvalue
+import OrdinaryDiffEqCore: initialize!, perform_step!, alg_cache
+
+using Reexport: @reexport
+@reexport using OrdinaryDiffEqCore
+
+include("algorithms.jl")
+include("caches.jl")
+include("perform_step.jl")
+
+export MER5v2, MER6v2, RK6v4
+
+end

lib/OrdinaryDiffEqSIMDRK/src/algorithms.jl

@@ -0,0 +1,66 @@
+struct MER5v2{StageLimiter, StepLimiter, Thread} <: OrdinaryDiffEqAdaptiveAlgorithm
+    stage_limiter!::StageLimiter
+    step_limiter!::StepLimiter
+    thread::Thread
+end
+
+function MER5v2(; stage_limiter! = trivial_limiter!, step_limiter! = trivial_limiter!,
+        thread = False())
+    MER5v2{typeof(stage_limiter!), typeof(step_limiter!), typeof(thread)}(stage_limiter!,
+        step_limiter!,
+        thread)
+end
+
+# for backwards compatibility
+function MER5v2(stage_limiter!, step_limiter! = trivial_limiter!)
+    MER5v2{typeof(stage_limiter!), typeof(step_limiter!), False}(stage_limiter!,
+        step_limiter!, False())
+end
+
+struct MER6v2{StageLimiter, StepLimiter, Thread} <: OrdinaryDiffEqAdaptiveAlgorithm
+    stage_limiter!::StageLimiter
+    step_limiter!::StepLimiter
+    thread::Thread
+end
+
+function MER6v2(; stage_limiter! = trivial_limiter!, step_limiter! = trivial_limiter!,
+        thread = False())
+    MER6v2{typeof(stage_limiter!), typeof(step_limiter!), typeof(thread)}(stage_limiter!,
+        step_limiter!,
+        thread)
+end
+
+# for backwards compatibility
+function MER6v2(stage_limiter!, step_limiter! = trivial_limiter!)
+    MER6v2{typeof(stage_limiter!), typeof(step_limiter!), False}(stage_limiter!,
+        step_limiter!, False())
+end
+
+struct RK6v4{StageLimiter, StepLimiter, Thread} <: OrdinaryDiffEqAdaptiveAlgorithm
+    stage_limiter!::StageLimiter
+    step_limiter!::StepLimiter
+    thread::Thread
+end
+
+function RK6v4(; stage_limiter! = trivial_limiter!, step_limiter! = trivial_limiter!,
+        thread = False())
+    RK6v4{typeof(stage_limiter!), typeof(step_limiter!), typeof(thread)}(stage_limiter!,
+        step_limiter!,
+        thread)
+end
+
+# for backwards compatibility
+function RK6v4(stage_limiter!, step_limiter! = trivial_limiter!)
+    RK6v4{typeof(stage_limiter!), typeof(step_limiter!), False}(stage_limiter!,
+        step_limiter!, False())
+end
+
+function Base.show(io::IO, alg::Union{MER5v2, MER6v2, RK6v4})
+    print(io, "$(nameof(typeof(alg)))(stage_limiter! = ", alg.stage_limiter!,
+        ", step_limiter! = ", alg.step_limiter!,
+        ", thread = ", alg.thread, ")")
+end
+
+OrdinaryDiffEqCore.alg_order(alg::MER5v2) = 5
+OrdinaryDiffEqCore.alg_order(alg::MER6v2) = 6
+OrdinaryDiffEqCore.alg_order(alg::RK6v4) = 6