Discard LSbs of address for AXI4-Lite CPUIF to properly handle unaligned transfers. #60

Author: amykyta3

src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv

@@ -13,7 +13,7 @@ always_ff {{get_always_ff_event(cpuif.reset)}} begin
                 is_active <= '1;
                 cpuif_req <= '1;
                 cpuif_req_is_wr <= {{cpuif.signal("pwrite")}};
-                {%- if cpuif.data_width == 8 %}
+                {%- if cpuif.data_width_bytes == 1 %}
                 cpuif_addr <= {{cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:0];
                 {%- else %}
                 cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};

src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv

@@ -14,7 +14,7 @@ always_ff {{get_always_ff_event(cpuif.reset)}} begin
                 is_active <= '1;
                 cpuif_req <= '1;
                 cpuif_req_is_wr <= {{cpuif.signal("pwrite")}};
-                {%- if cpuif.data_width == 8 %}
+                {%- if cpuif.data_width_bytes == 1 %}
                 cpuif_addr <= {{cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:0];
                 {%- else %}
                 cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};

src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv

@@ -83,17 +83,29 @@ always_comb begin
         if(axil_arvalid && !axil_prev_was_rd) begin
             cpuif_req = '1;
             cpuif_req_is_wr = '0;
+            {%- if cpuif.data_width_bytes == 1 %}
             cpuif_addr = axil_araddr;
+            {%- else %}
+            cpuif_addr = {axil_araddr[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
+            {%- endif %}
             if(!cpuif_req_stall_rd) axil_ar_accept = '1;
         end else if(axil_awvalid && axil_wvalid) begin
             cpuif_req = '1;
             cpuif_req_is_wr = '1;
+            {%- if cpuif.data_width_bytes == 1 %}
             cpuif_addr = axil_awaddr;
+            {%- else %}
+            cpuif_addr = {axil_awaddr[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
+            {%- endif %}
             if(!cpuif_req_stall_wr) axil_aw_accept = '1;
         end else if(axil_arvalid) begin
             cpuif_req = '1;
             cpuif_req_is_wr = '0;
+            {%- if cpuif.data_width_bytes == 1 %}
             cpuif_addr = axil_araddr;
+            {%- else %}
+            cpuif_addr = {axil_araddr[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
+            {%- endif %}
             if(!cpuif_req_stall_rd) axil_ar_accept = '1;
         end
     end