File tree Expand file tree Collapse file tree 2 files changed +8
-1
lines changed Expand file tree Collapse file tree 2 files changed +8
-1
lines changed Original file line number Diff line number Diff line change @@ -9,4 +9,4 @@ Compile SystemRDL into a SystemVerilog control/status register (CSR) block.
9
9
For the command line tool, see the [ PeakRDL project] ( https://peakrdl.readthedocs.io ) .
10
10
11
11
## Documentation
12
- See the [ PeakRDL-regblock Documentation] ( http ://peakrdl-regblock.readthedocs.io) for more details
12
+ See the [ PeakRDL-regblock Documentation] ( https ://peakrdl-regblock.readthedocs.io) for more details
Original file line number Diff line number Diff line change @@ -25,6 +25,13 @@ The easiest way to use PeakRDL-regblock is via the `PeakRDL command line tool <
25
25
peakrdl regblock atxmega_spi.rdl -o regblock/ --cpuif axi4-lite
26
26
27
27
28
+ Looking for VHDL?
29
+ -----------------
30
+ This project generates SystemVerilog RTL. If you prefer using VHDL, check out
31
+ the sister project which aims to be a feature-equivalent fork of
32
+ PeakRDL-regblock: `PeakRDL-regblock-VHDL <https://peakrdl-regblock-vhdl.readthedocs.io >`_
33
+
34
+
28
35
Links
29
36
-----
30
37
You can’t perform that action at this time.
0 commit comments