Add simulation-time width assertions to SV interfaces. #128

Author: amykyta3

src/peakrdl_regblock/cpuif/apb3/__init__.py

@@ -2,6 +2,7 @@
 
 class APB3_Cpuif(CpuifBase):
     template_path = "apb3_tmpl.sv"
+    is_interface = True
 
     @property
     def port_declaration(self) -> str:
@@ -12,6 +13,8 @@ def signal(self, name:str) -> str:
 
 
 class APB3_Cpuif_flattened(APB3_Cpuif):
+    is_interface = False
+
     @property
     def port_declaration(self) -> str:
         lines = [

src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv

@@ -1,3 +1,15 @@
+{%- if cpuif.is_interface -%}
+`ifndef SYNTHESIS
+    initial begin
+        assert($bits({{cpuif.signal("paddr")}}) >= {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH)
+            else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("paddr")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH);
+        assert($bits({{cpuif.signal("pwdata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
+            else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("pwdata")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH);
+    end
+`endif
+
+{% endif -%}
+
 // Request
 logic is_active;
 always_ff {{get_always_ff_event(cpuif.reset)}} begin

src/peakrdl_regblock/cpuif/apb4/__init__.py

@@ -2,6 +2,7 @@
 
 class APB4_Cpuif(CpuifBase):
     template_path = "apb4_tmpl.sv"
+    is_interface = True
 
     @property
     def port_declaration(self) -> str:
@@ -12,6 +13,8 @@ def signal(self, name:str) -> str:
 
 
 class APB4_Cpuif_flattened(APB4_Cpuif):
+    is_interface = False
+
     @property
     def port_declaration(self) -> str:
         lines = [

src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv

@@ -1,3 +1,15 @@
+{%- if cpuif.is_interface -%}
+`ifndef SYNTHESIS
+    initial begin
+        assert($bits({{cpuif.signal("paddr")}}) >= {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH)
+            else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("paddr")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH);
+        assert($bits({{cpuif.signal("pwdata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
+            else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("pwdata")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH);
+    end
+`endif
+
+{% endif -%}
+
 // Request
 logic is_active;
 always_ff {{get_always_ff_event(cpuif.reset)}} begin

src/peakrdl_regblock/cpuif/avalon/__init__.py

@@ -3,6 +3,7 @@
 
 class Avalon_Cpuif(CpuifBase):
     template_path = "avalon_tmpl.sv"
+    is_interface = True
 
     @property
     def port_declaration(self) -> str:
@@ -17,6 +18,8 @@ def word_addr_width(self) -> int:
         return self.addr_width - clog2(self.data_width_bytes)
 
 class Avalon_Cpuif_flattened(Avalon_Cpuif):
+    is_interface = False
+
     @property
     def port_declaration(self) -> str:
         lines = [

src/peakrdl_regblock/cpuif/avalon/avalon_tmpl.sv

@@ -1,3 +1,15 @@
+{%- if cpuif.is_interface -%}
+`ifndef SYNTHESIS
+    initial begin
+        assert($bits({{cpuif.signal("address")}}) >= {{cpuif.word_addr_width}})
+            else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("address")}}), {{cpuif.word_addr_width}});
+        assert($bits({{cpuif.signal("writedata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
+            else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("writedata")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH);
+    end
+`endif
+
+{% endif -%}
+
 // Request
 always_comb begin
     cpuif_req = {{cpuif.signal("read")}} | {{cpuif.signal("write")}};

src/peakrdl_regblock/cpuif/axi4lite/__init__.py

@@ -2,6 +2,7 @@
 
 class AXI4Lite_Cpuif(CpuifBase):
     template_path = "axi4lite_tmpl.sv"
+    is_interface = True
 
     @property
     def port_declaration(self) -> str:
@@ -34,6 +35,8 @@ def resp_buffer_size(self) -> int:
 
 
 class AXI4Lite_Cpuif_flattened(AXI4Lite_Cpuif):
+    is_interface = False
+
     @property
     def port_declaration(self) -> str:
         lines = [

src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv

@@ -1,3 +1,15 @@
+{%- if cpuif.is_interface -%}
+`ifndef SYNTHESIS
+    initial begin
+        assert($bits({{cpuif.signal("araddr")}}) >= {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH)
+            else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("araddr")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH);
+        assert($bits({{cpuif.signal("wdata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
+            else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("wdata")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH);
+    end
+`endif
+
+{% endif -%}
+
 // Max Outstanding Transactions: {{cpuif.max_outstanding}}
 logic [{{clog2(cpuif.max_outstanding+1)-1}}:0] axil_n_in_flight;
 logic axil_prev_was_rd;

src/peakrdl_regblock/cpuif/base.py

@@ -69,6 +69,7 @@ def get_implementation(self) -> str:
             "clog2": clog2,
             "is_pow2": is_pow2,
             "roundup_pow2": roundup_pow2,
+            "ds": self.exp.ds,
         }
 
         template = jj_env.get_template(self.template_path)