Bias alpha test LODs

TellowKrinkle · TellowKrinkle · commit 1573f2b650b6 · 2023-10-21T01:18:55.000-05:00
Higher mip levels don't alpha test well
diff --git a/Environment.hlsl b/Environment.hlsl
@@ -139,7 +139,7 @@ float4 main(float4 pos : SV_Position, PSInput input COVERAGE_OUT) : SV_TARGET {
 		coverage = 0;
 		[unroll]
 		for (uint bit = 0; bit < MSAA_SAMPLE_COUNT; bit++) {
-			coverage |= (sStage0.Sample(smpsStage0, EvaluateAttributeAtSample(input.litCoord, bit).TEXADDR_SWIZZLE).a > aref) << bit;
+			coverage |= (sStage0.SampleBias(smpsStage0, EvaluateAttributeAtSample(input.litCoord, bit).TEXADDR_SWIZZLE, MSAA_SAMPLE_COUNT > 4 ? -2 : -1).a > aref) << bit;
 		}
 #if MSAA_SAMPLE_COUNT == 16
 		// 16 is the max we compile for

Original file line number	Diff line number	Diff line change
`@@ -139,7 +139,7 @@ float4 main(float4 pos : SV_Position, PSInput input COVERAGE_OUT) : SV_TARGET {`
`139`	`139`	`coverage = 0;`
`140`	`140`	`[unroll]`
`141`	`141`	`for (uint bit = 0; bit < MSAA_SAMPLE_COUNT; bit++) {`
`142`		`- coverage \|= (sStage0.Sample(smpsStage0, EvaluateAttributeAtSample(input.litCoord, bit).TEXADDR_SWIZZLE).a > aref) << bit;`
	`142`	`+ coverage \|= (sStage0.SampleBias(smpsStage0, EvaluateAttributeAtSample(input.litCoord, bit).TEXADDR_SWIZZLE, MSAA_SAMPLE_COUNT > 4 ? -2 : -1).a > aref) << bit;`
`143`	`143`	`}`
`144`	`144`	`#if MSAA_SAMPLE_COUNT == 16`
`145`	`145`	`// 16 is the max we compile for`