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export DESIGN_NAME = ca53_cpu
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export PLATFORM = gf12
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+ export SYNTH_HIERARCHICAL = 1
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+ export RTLMP_FLOW = True
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+
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export VERILOG_FILES = $(PLATFORM_DIR ) /$(DESIGN_NAME ) /rtl/ca53_cpu.v
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export SDC_FILE = $(PLATFORM_DIR ) /$(DESIGN_NAME ) /sdc/ca53_cpu.sdc
@@ -43,11 +46,15 @@ export ADDITIONAL_GDS += $(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_128X
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export DIE_AREA = 0 0 1400 1400
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export CORE_AREA = 10 10 1390 1390
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export PLACE_DENSITY_LB_ADDON = 0.05
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+
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+ export HAS_IO_CONSTRAINTS = 1
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export PLACE_PINS_ARGS = -exclude left :0-600 -exclude left:1350-1400 -exclude right:* -exclude top:* -exclude bottom:*
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+ export MACRO_PLACE_HALO = 7 7
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+ export MACRO_PLACE_CHANNEL = 14 14
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+
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export MACRO_WRAPPERS = $(dir $(DESIGN_CONFIG ) ) /wrappers.tcl
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- export MACRO_BLOCKAGE_HALO = 25
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# export MAX_ROUTING_LAYER = H2
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export FASTROUTE_TCL = $(dir $(DESIGN_CONFIG ) ) /fastroute.tcl
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#
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