Merge pull request ZigEmbeddedGroup/aviron#22 from Grazfather/patch-2

Actually store result for add

Author: ikskuh

simulators/aviron/src/lib/Cpu.zig

@@ -371,7 +371,6 @@ const instructions = struct {
         const src = cpu.regs[info.d.num()];
 
         const res = src -% 1;
-
         cpu.regs[info.d.num()] = res;
 
         cpu.sreg.z = (res == 0);
@@ -387,6 +386,7 @@ const instructions = struct {
         const Rr: Bits8 = @bitCast(rhs);
 
         const res: u8 = lhs +% rhs +% @intFromBool(c);
+        cpu.regs[info.d.num()] = res;
 
         const R: Bits8 = @bitCast(res);
 

simulators/aviron/testsuite/instructions/add.S

@@ -0,0 +1,27 @@
+//! {
+//!   "exit_code": 0,
+//!   "stdout": "",
+//!   "stderr": "Hi"
+//! }
+
+#include "../regs.inc"
+
+.global _start
+_start:
+
+    ; '\' + '!' = 'H'
+    ldi r16, '\''
+    ldi r18, '!'
+    add r16, r18
+    out IO_STDERR, r16
+    ldi r16, 0x80
+    ldi r18, 0x80
+    add r16, r18
+    ; '4' + '4' + carry = 'i'
+    ldi r17, '4'
+    ldi r19, '4'
+    adc r17, r19
+    out IO_STDERR, r17
+
+    clr r16
+    out IO_EXIT, r16

simulators/aviron/testsuite/instructions/sub.S

@@ -0,0 +1,27 @@
+//! {
+//!   "exit_code": 0,
+//!   "stdout": "",
+//!   "stderr": "Hi"
+//! }
+
+#include "../regs.inc"
+
+.global _start
+_start:
+
+    ; 'q' - ')' = 'H'
+    ldi r16, 'q'
+    ldi r18, ')'
+    sub r16, r18
+    out IO_STDERR, r16
+    ldi r16, 0x80
+    ldi r18, 0x80
+    add r16, r18
+    ; '~' - 0x14 - carry = 'i'
+    ldi r17, '~'
+    ldi r19, 0x14
+    sbc r17, r19
+    out IO_STDERR, r17
+
+    clr r16
+    out IO_EXIT, r16