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Commit fed905d

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Add initial enhancments for loopback testing
Signed-off-by: Travis F. Collins <travis.collins@analog.com>
1 parent c0ef382 commit fed905d

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+21
-3
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+21
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CI/scripts/build_bsp.sh

Lines changed: 21 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,9 @@ cd ..
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if [ -d "hdl" ]; then
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rm -rf "hdl"
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fi
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if [ -d "ghdl" ]; then
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rm -rf "ghdl"
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fi
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for i in {1..5}
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do
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if git clone --single-branch -b $HDLBRANCH https://github.com/analogdevicesinc/hdl.git
@@ -47,6 +50,23 @@ VIVADO=${VER}
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# Setup
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source /opt/Xilinx/Vivado/$VIVADO/settings64.sh
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# Get ghdl dependencies
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git clone git@ghe.com:adi-innersource/ghdl.git -b dev_apollo
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mv ghdl/projects/apollo hdl/projects/
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mv hdl/projects/apollo/axi_hsci hdl/library/
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# Within the hdl/projects/apollo directory replace:
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# ../../../../hdl/ with $ad_hdl_dir/
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files_in_apollo_folder_recersive=$(find hdl/projects/apollo -type f)
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for file in $files_in_apollo_folder_recersive
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do
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if [ -f "$file" ]; then
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echo "Updating file: $file"
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sed -i 's|../../../../hdl/|$ad_hdl_dir/|g' "$file"
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fi
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done
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# Pre-build IP library
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# cd hdl/library
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# make
@@ -73,8 +93,6 @@ TARGET="../hdl/vendor/AnalogDevices/vivado"
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if [ -d "$TARGET" ]; then
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rm -rf "$TARGET"
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fi
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# Increase rx_clk period to fix timing failures for Pluto designs in R2021b
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sed -i 's/16.27/30/' hdl/projects/pluto/system_constr.xdc
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mv hdl $TARGET
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# Post-process ports.json
@@ -84,7 +102,7 @@ cp ports.json ../hdl/vendor/AnalogDevices/+AnalogDevices/
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# Updates
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cp scripts/matlab_processors.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl
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cp scripts/adi_project_xilinx.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_project_xilinx.tcl
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#cp scripts/adi_project_xilinx.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_project_xilinx.tcl
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cp scripts/system_project_rxtx.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/system_project_rxtx.tcl
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cp scripts/adi_build.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_build.tcl
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cp scripts/adi_build_win.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_build_win.tcl
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