Language Conversion Brainstorm

Verilog to EDIF

EDIF Composer:

• Make sure the can handle multi bit cables and ports
• Ensure this can handle the verilog namespace

Verilog Parser:

• Make a new element that is an assign element
• Apply the new assign element for the port remapping function

EDIF to Verilog

EDIF Parser:

• Make sure this create mutli bit cables and ports
• use the complex name instead of the rename by default
  • https://www.xilinx.com/support/answers/1554.html
  • http://electrosofts.com/verilog/identifiers.html#:~:text=An%20identifier%20is%20any%20sequence,are%20considered%20to%20be%20different.

Verilog Composer:

• Make it deal with the new assign element
• make it undo the new assign element to a port remapping where applicable (optional, probably won't implement)
• Do something meaningful with EDIF rename