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SpyDrNet Feature Road Map

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jordi1215 edited this page May 6, 2021 · 46 revisions

Previous Releases

  • 1.0.0: 12/19/2019
  • 1.1.0: 1/20/2020
  • 1.2.0: 2/7/2020
  • 1.3.0: 4/20/2020
  • 1.4.0: 4/21/2020
  • 1.5.0: 9/1/2020
  • 1.6.0: 9/24/2020
  • 1.7.0: 1/21/2021
  • 1.8.0: 4/23/2021

Current Release

Release 1.4 - April 3rd

Research

  • Read more LGRAPH papers

Documentation

  • Simple tutorial - how to do basic things, more detailed than the read me
  • Creation of all things
  • Hierarchical references
  • Other getter functions
  • Improve Documentation (organize the API, ensure clone uniquify hrefs all makes sense)
  • Work on spydrnet paper. (create outline, create introduction)
  • Discussion on clone

API

  • Flatten (and compare the results)

Future Releases

Release 1.5 - August 31st

Documentation

  • None

API

  • Verilog parsing
  • Verilog composer

Release 1.6 - September 11th

Documentation UML like diagram of the netlist data structure

  • Diagram explaining Hierarchical References
  • Document Flatten
  • How to release
  • Documentation on how to build the docs
    • How to publish to pypi
    • How to build the package
  • Organization in our documentation much like how it is seen in Networkx

Release 1.6.1 - September 25th

Documentation

  • Tighten up for the end of summer

API

  • Address as many known bugs as we can, to tighten existing code base for summer

Release 1.7 - October 9th, 2020

Documentation

  • How to build a parser/composer on SpyDrNet API
  • EDIF to verilog
  • Verilog to EDIF
  • Shortcuts

Release 1.8

Verilog to VQM

  • VQM Composer
  • Edif to Verilog?
  • Verilog to EDIF?
  • Get input from dr. Wirthlin to polish for shrec

Release 1.9

  • Some form of accelerators for parsing
  • GUIs for visualization

Release 2.0 features

require a 2.0 release before they can be included.

  • Rename some components
  • hierarchical instance simplifications
  • remove return lists instead of generators
  • Pin simplifications
  • remove href port and cable layers, have the parent of all things be instances #89

Future Release

  • Connectivity graph, sequential graph, graph analysis (NetworkX support). <- SHREC?
  • vendor primitive library support <- SHREC?
  • DRC check. for example no pointers crossing netlist boundries.
  • connectors / inverters (useful for VQM support and Verilog support);
    • assign wire1 = wire2; u0 module_def(.clk(!clkn)) or module_def(.clk(~clkn))
  • resource utilization tracker (budget for partial TMR/DWC). <-SHREC related?
  • device support (bad cuts, resource tracking). <-SHREC?
  • factories for parameterizable primitives. <- May be important for VQM support.
  • Pyeda support.
  • FOSS EDA ecosystem support? <- Really interesting to look into: Proprietary Vivado, Verific, (Mentor Graphics TMR?, Synopsis TMR?); FOSS - LiveHD, Yosis, BYU EDIF Tools, ABC, MyHDL, PyMTL
  • C++ implementation?
  • more languages
  • TMR across hierarchy (targeting microblaze). <- SHREC?
  • DWC across hierarchy <- SHREC?
  • Flattening a design. (done? What about doing it to only a part of the design though?)
  • Make non-leaf definitions unique. (Done? What about doing it to only a part of the design though?)
  • Translation from one netlist format into another.
  • Report leaf-cell utilization
  • Report how many nets a netlist has
  • topological sort of libraries, definitions, cells, detect dependency loops (this library uses a definition in another library, but that definition instances a definition in the same library.
  • clock domain analysis: <- SHREC
    • Identify clock sources.
    • Identify clock domain crossings.
    • Identify synchronizers.
  • Shortcuts on Hrefs:
    • There are a lot of things we could shortcut when it comes to hrefs but in general if there were a way to pass through to the item's calls from the href it would be nice. Lets just start with the instance calls. example long ways:
    • for an instance: href.item.reference href.item.parent
    • could be shortened to href.reference href.parent
  • Support Constraint files

Demos:

  • Hello world, low level
  • Hello world, parser
  • Hello world, more advanced
  • showing how to iterate though the netlist
  • reports
    • report all leaf cells and total instances of each
    • report total nets
    • report total instances

EDIF to generic netlist transformations:

  • Merge scalar cables into a single array cable.
  • Naming, go with a single name, caching EDIF.identifier is fine, but'NAME' is where it is at.
  • array to scalar
  • reordering of pins
  • ofuscations of netlist for security
  • actually changing how a lut is wired without changing functionality

Future Work

For the release: We need good API examples Complete API, object removal We need good documentation

Prerelease for before the holidays

  • check the projects tab on github for some information on this.
  • we need to define the documentation pre-release as well.

We need a release check

1.1.0 new formats merge netlists constraint handling

Serializer of the itermediate representation look into pickle (for now) and json Coordinate with other open source tools Properties and names need work callbacks property management

EDIF parser rework to use the creation API EDIF composer rework to use the analysis API

Add plugin capability. - this should probably be discussed more with nailed down details.

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