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SpyDrNet Feature Road Map

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thunder-hammer edited this page Jun 3, 2021 · 46 revisions

Previous Releases

  • 1.0.0: 12/19/2019
  • 1.1.0: 1/20/2020
  • 1.2.0: 2/7/2020
  • 1.3.0: 4/20/2020
  • 1.4.0: 4/21/2020
  • 1.5.0: 9/1/2020
  • 1.6.0: 9/24/2020
  • 1.7.0: 1/21/2021

Current Release

  • 1.8.0: 4/23/2021

Release 1.8 - April 23, 2021

Documentation:

  • Added an example to build the diagram in API Reference called minimal.py
  • Incorporated the example in the documentation

API:

  • Edif parser combines nets into a cable when they have sequential numbering in using vivado style naming.
  • Edif composer will split multi bit cables into individual nets that attempt to follow vivado style naming syntax.
  • Most Intermediate representation elements have a better print function.

Known issues:

  • Documentation number is currently unspecified. Will fix in 1.8.1
  • Verilog support is alpha. Issues are known to exist. Will improve in 1.8.1
  • some features may not work in Python 3.5 please use 1.7 planned fix in 1.8.1

Future Releases

Release 1.8.1 planned May 19, 2021

Documentation:

  • add additional examples to the documentation including some examples of visualization
  • add a link in the documentation to a graph-viz plugin that leverages SpyDrNet to visualize smaller netlists.
  • correct some spelling and minor issues

API

  • Fix bugs with the Verilog Parser and composer
  • Many additional tests related to Verilog

Release 1.9

Documentation

  • Diagrams and examples for every part of the IR,
  • More Documentation in the examples
  • Vivado examples.
    • how to generate an edif file
  • Add comments to inner and outer pins information on the minimal.py
  • Piece out the reference section in the documentation
    • move the api summary to it's own section.
    • combine installation sections
    • move the metadata introduction to
  • Add better section on metadata
    • add a section on how the metadata is used
    • include Name and edif identifier and properties.
  • Document how to use the get_cable functions
  • better documentation for the hierarchical references (used in TMR)
  • Documentation on the namespace manager
  • Document the callbacks features.

Development

  • add a shortcut to get the higher index on a cable and port
    • create a shortcut to get a cable or pin by real index instead of just indexing in the pin or wire list. (adjust for the lower index)
    • Shortcut for the width.
  • add a shortcut to get the properties of the object
    • these are currently stored in the metadata as something like "edif.properties" and "verilog.parameters" or something. Look into this.
  • make a shortcut to cable.wire be cable.wires[0] and port.pin to port.pins[0]
  • add the examples to the tests.

Release 1.10

Verilog to VQM

  • VQM Composer
  • Edif to Verilog?
  • Verilog to EDIF?
  • Get input from dr. Wirthlin to polish for shrec

Release 1.11

  • Some form of accelerators for parsing
  • GUIs for visualization

Release 2.0 features

require a 2.0 release before they can be included.

  • Rename some components
  • hierarchical instance simplifications
  • remove return lists instead of generators
  • Pin simplifications
  • remove href port and cable layers, have the parent of all things be instances #89

Future Release

  • improve the Pretty print
  • Connectivity graph, sequential graph, graph analysis (NetworkX support). <- SHREC?
  • vendor primitive library support <- SHREC?
  • DRC check. for example no pointers crossing netlist boundries.
  • connectors / inverters (useful for VQM support and Verilog support);
    • assign wire1 = wire2; u0 module_def(.clk(!clkn)) or module_def(.clk(~clkn))
  • resource utilization tracker (budget for partial TMR/DWC). <-SHREC related?
  • device support (bad cuts, resource tracking). <-SHREC?
  • factories for parameterizable primitives. <- May be important for VQM support.
  • Pyeda support.
  • FOSS EDA ecosystem support? <- Really interesting to look into: Proprietary Vivado, Verific, (Mentor Graphics TMR?, Synopsis TMR?); FOSS - LiveHD, Yosis, BYU EDIF Tools, ABC, MyHDL, PyMTL
  • C++ implementation?
  • more languages
  • TMR across hierarchy (targeting microblaze). <- SHREC?
  • DWC across hierarchy <- SHREC?
  • Flattening a design. (done? What about doing it to only a part of the design though?)
  • Make non-leaf definitions unique. (Done? What about doing it to only a part of the design though?)
  • Translation from one netlist format into another.
  • Report leaf-cell utilization
  • Report how many nets a netlist has
  • topological sort of libraries, definitions, cells, detect dependency loops (this library uses a definition in another library, but that definition instances a definition in the same library.
  • clock domain analysis: <- SHREC
    • Identify clock sources.
    • Identify clock domain crossings.
    • Identify synchronizers.
  • Shortcuts on Hrefs:
    • There are a lot of things we could shortcut when it comes to hrefs but in general if there were a way to pass through to the item's calls from the href it would be nice. Lets just start with the instance calls. example long ways:
    • for an instance: href.item.reference href.item.parent
    • could be shortened to href.reference href.parent
  • Support Constraint files
  • improve netlist comparator.

Demos:

  • Hello world, low level
  • Hello world, parser
  • Hello world, more advanced
  • showing how to iterate though the netlist
  • reports
    • report all leaf cells and total instances of each
    • report total nets
    • report total instances

EDIF to generic netlist transformations:

  • Merge scalar cables into a single array cable.
  • Naming, go with a single name, caching EDIF.identifier is fine, but'NAME' is where it is at.
  • array to scalar
  • reordering of pins
  • ofuscations of netlist for security
  • actually changing how a lut is wired without changing functionality

Future Work

For the release: We need good API examples Complete API, object removal We need good documentation

Prerelease for before the holidays

  • check the projects tab on github for some information on this.
  • we need to define the documentation pre-release as well.

We need a release check

1.1.0 new formats merge netlists constraint handling

Serializer of the itermediate representation look into pickle (for now) and json Coordinate with other open source tools Properties and names need work callbacks property management

EDIF parser rework to use the creation API EDIF composer rework to use the analysis API

Add plugin capability. - this should probably be discussed more with nailed down details.

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