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SpyDrNet Feature Road Map

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thunder-hammer edited this page May 4, 2020 · 46 revisions

Previous Releases

  • 1.0: 12/18/2019
  • 1.1: 1/18/2020
  • 1.2: 2/7/2020
  • 1.3: 4/20/2020

Current Release

Release 1.4 - April 3rd

Research

  • Read more LGRAPH papers

Documentation

  • Simple tutorial - how to do basic things, more detailed than the read me
  • Creation of all things
  • Hierarchical references
  • Other getter functions
  • Improve Documentation (organize the API, ensure clone uniquify hrefs all makes sense)
  • Work on spydrnet paper. (create outline, create introduction)
  • Discussion on clone

API

  • Flatten (and compare the results)

Future Releases

Release 1.5 - April 17th

Research

  • Read more LGRAPH papers

Documentation

  • Continue to work on the paper. (full draft)
  • Document Flatten
  • Discussion on flatten
  • How to release
  • Documentation on how to build the docs
    • How to publish to pypi
    • How to build the package

API

  • Verilog parsing

Release 1.6 - May 1st

Documentation

API

  • Composer verilog
  • VQM parser

Release 1.7 - May 15th

Documentation

  • How to build a parser/composer on SpyDrNet API
  • VQM Composer

Release 1.8 - May 29th

Verilog to VQM

  • Edif to Verilog?
  • Verilog to EDIF?
  • Get input from dr. Wirthlin to polish for shrec

Release 1.9

  • Some form of accelerators for parsing
  • GUIs for visualization

Release 2.0 features

require a 2.0 release before they can be included.

  • Rename some components
  • hierarchical instance simplifications
  • remove return lists instead of generators
  • Pin simplifications

Future Release

  • Connectivity graph, sequential graph, graph analysis (NetworkX support).
  • vendor primitive library support
  • DRC check. for example no pointers crossing netlist boundries.
  • connectors / inverters
  • resource utilization tracker
  • device support (bad cuts, resource tracking).
  • factories for parameterizable primitives.
  • Pyeda support.
  • FOSS EDA ecosystem support?
  • C++ implementation?
  • more languages
  • TMR across hierarchy (targeting microblaze).
  • DWC across hierarchy
  • Flattening a design.
  • Make non-leaf definitions unique.
  • Translation from one netlist format into another.
  • Report leaf-cell utilization
  • Report how many nets a netlist has
  • topological sort of libraries, definitions, cells, detect dependency loops (this library uses a definition in another library, but that definition instances a definition in the same library.
  • clock domain analysis:
    • Identify clock sources.
    • Identify clock domain crossings.
    • Identify synchronizers.

Demos:

  • Hello world, low level
  • Hello world, parser
  • Hello world, more advanced
  • showing how to iterate though the netlist
  • reports
    • report all leaf cells and total instances of each
    • report total nets
    • report total instances

EDIF to generic netlist transformations:

  • Merge scalar cables into a single array cable.
  • Naming, go with a single name, caching EDIF.identifier is fine, but'NAME' is where it is at.
  • array to scalar
  • reordering of pins
  • ofuscations of netlist for security
  • actually changing how a lut is wired without changing functionality

Future Work

For the release: We need good API examples Complete API, object removal We need good documentation

Prerelease for before the holidays

  • check the projects tab on github for some information on this.
  • we need to define the documentation pre-release as well.

We need a release check

1.1.0 new formats merge netlists constraint handling

Serializer of the itermediate representation look into pickle (for now) and json Coordinate with other open source tools Properties and names need work callbacks property management

EDIF parser rework to use the creation API EDIF composer rework to use the analysis API

Add plugin capability. - this should probably be discussed more with nailed down details.

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