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SpyDrNet Feature Road Map

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thunder-hammer edited this page Mar 9, 2020 · 46 revisions

Previous Releases

  • 1.0: 12/18/2019
  • 1.1: 1/18/2020

Current Release

Release 1.2.0

  • API
    • EDIF Data manager (Dallin)
    • ['NAME'] property (Andrew)
    • Definition.references
  • Documentation:
    • simple circuit figure added to the API specification
  • Parser
    • Convert all edif examples to verilog using vivado (Michael) Targeted release date: 4 Feb 2020

Future Releases

Release 1.3.0

  • API
    • Cloning / Deep Copy (Dallin)
    • "Virtual Instances" (Dallin)
    • EDIF.properties to top_level (Andrew)
    • EDIF Datamagager in the parser (Andrew)
    • EDIF parser to use the defacto name property (andrew)
  • Documentation
    • API Section: consider cleaning up organization a bit (Andrew)
  • Parser
    • Update parser to use data manager and ['NAME'] property (Andrew)
    • Verilog tokenizer using ply (Michael)
    • Automated script that converts netlists
  • Examples
    • Simple TMR example (brute force triplication with single output voters) (Andrew)
  • Target date: February 14, 2020

Release 1.4.0

  • API
    • h-ref getcables, getwires... (dallin)
    • TMR (SpyDrNet-SHREC)
    • Serialization (JSON Parser and Composer) (Dallin)
    • cloning sub circuits
    • Uniquify (all instances have unique definitions)
    • DWC?
  • Documentation
    • Document TMR, Clone, Uniquify
  • Parser
    • Finalize Verilog conversion/parser/composer (more tests and examples)
    • Verilog parser (Michael)
    • Verilog composer (Michael)
    • Verilog to EDIF attempt (Michael)
  • Examples
    • Edif to Verilog attempt (Michael)
  • Target Date: March 6, 2020

Release 1.5.0

  • Connectivity graph, sequential graph, graph analysis (NetworkX support).
  • vendor primitive library support

Future Release

  • DRC check. for example no pointers crossing netlist boundries.
  • connectors / inverters
  • resource utilization tracker
  • device support (bad cuts, resource tracking).
  • factories for parameterizable primitives.
  • Pyeda support.
  • FOSS EDA ecosystem support?
  • C++ implementation?
  • more languages
  • TMR across hierarchy (targeting microblaze).
  • DWC across hierarchy
  • Flattening a design.
  • Make non-leaf definitions unique.
  • Translation from one netlist format into another.
  • Report leaf-cell utilization
  • Report how many nets a netlist has
  • topological sort of libraries, definitions, cells, detect dependency loops (this library uses a definition in another library, but that definition instances a definition in the same library.
  • clock domain analysis:
    • Identify clock sources.
    • Identify clock domain crossings.
    • Identify synchronizers.

Demos:

  • Hello world, low level
  • Hello world, parser
  • Hello world, more advanced
  • showing how to iterate though the netlist
  • reports
    • report all leaf cells and total instances of each
    • report total nets
    • report total instances

EDIF to generic netlist transformations:

  • Merge scalar cables into a single array cable.
  • Naming, go with a single name, caching EDIF.identifier is fine, but'NAME' is where it is at.
  • array to scalar
  • reordering of pins
  • ofuscations of netlist for security
  • actually changing how a lut is wired without changing functionality

Future Work

For the release: We need good API examples Complete API, object removal We need good documentation

Prerelease for before the holidays

  • check the projects tab on github for some information on this.
  • we need to define the documentation pre-release as well.

We need a release check

1.1.0 new formats merge netlists constraint handling

Serializer of the itermediate representation look into pickle (for now) and json Properties and names need work callbacks property management

EDIF parser rework to use the creation API EDIF composer rework to use the analysis API

Add plugin capability. - this should probably be discussed more with nailed down details.

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