Verilog emission refactor (#133)

Author: matth2k

src/asic.rs

@@ -21,7 +21,7 @@ define_language! {
         Const(bool),
         Var(Symbol),
         "AND" = And([Id; 2]),
-        "OR" = Xor([Id; 2]),
+        "OR" = Or([Id; 2]),
         "INV" = Inv([Id; 1]),
         Cell(Symbol, Vec<Id>), // or Box<[Id]>?
     }
@@ -46,6 +46,17 @@ impl CellLang {
             _ => Ok(()),
         }
     }
+
+    /// Get the drive strength of a cell
+    pub fn get_drive_strength(&self) -> Option<usize> {
+        match self {
+            CellLang::Cell(s, _) => match s.as_str().split_once("_X") {
+                Some((_, strength)) => strength.parse::<usize>().ok(),
+                None => None,
+            },
+            _ => None,
+        }
+    }
 }
 
 /// A cost function that extracts a circuit with the least depth
@@ -285,8 +296,8 @@ pub fn asic_rewrites() -> Vec<egg::Rewrite<CellLang, CellAnalysis>> {
     rules
         .push(rewrite!("xor2_x1"; "(OR (AND ?b (INV ?a)) (AND ?a (INV ?b)))" => "(XOR2_X1 ?a ?b)"));
     rules.push(rewrite!("inv_x1"; "(INV ?a)" => "(INV_X1 ?a)"));
-    rules.push(rewrite!("aoi_x1"; "(INV (OR (AND ?a ?b) ?c))" => "(AOI_X1 ?a ?b ?c)"));
-    rules.push(rewrite!("oai_x1"; "(INV (AND (OR ?a ?b) ?c))" => "(OAI_X1 ?a ?b ?c)"));
+    rules.push(rewrite!("aoi_x1"; "(INV (OR (AND ?a ?b) ?c))" => "(AOI21_X1 ?a ?b ?c)"));
+    rules.push(rewrite!("oai_x1"; "(INV (AND (OR ?a ?b) ?c))" => "(OAI21_X1 ?a ?b ?c)"));
 
     rules
 }

src/bin/cellmap.rs

@@ -3,6 +3,7 @@ use egg::{FromOpError, RecExpr, RecExprParseError};
 use lut_synth::{
     asic::{CellAnalysis, CellLang, CellRpt, asic_rewrites},
     driver::{SynthRequest, process_string_expression, simple_reader},
+    verilog::SVModule,
 };
 use std::path::PathBuf;
 
@@ -78,6 +79,10 @@ struct Args {
     #[arg(short = 'v', long, default_value_t = false)]
     verbose: bool,
 
+    /// Output Verilog
+    #[arg(long, default_value_t = false)]
+    verilog: bool,
+
     /// Extract for minimum circuit depth
     #[arg(long, default_value_t = false)]
     min_depth: bool,
@@ -170,7 +175,18 @@ fn main() -> std::io::Result<()> {
             args.verbose,
         )?;
         if !result.is_empty() {
-            println!("{}", result);
+            if args.verilog {
+                let module = SVModule::from_cells(
+                    result.get_expr().to_owned(),
+                    "top".to_string(),
+                    Vec::new(),
+                );
+                let module =
+                    module.map_err(|s| std::io::Error::new(std::io::ErrorKind::Other, s))?;
+                println!("{}", module);
+            } else {
+                println!("{}", result);
+            }
         }
     }
     Ok(())

src/driver.rs

@@ -14,7 +14,6 @@ use egg::{
 };
 use indicatif::{MultiProgress, ProgressBar, ProgressStyle};
 use std::collections::{BTreeMap, HashSet};
-use std::rc::Rc;
 use std::sync::Arc;
 use std::sync::atomic::{AtomicBool, Ordering};
 use std::time::{Duration, Instant};
@@ -212,7 +211,7 @@ where
         })
     }
 
-    fn get_rule_uses_rec(map: &mut BTreeMap<String, usize>, expl: &[Rc<TreeTerm<L>>]) {
+    fn get_rule_uses_rec(map: &mut BTreeMap<String, usize>, expl: &[std::rc::Rc<TreeTerm<L>>]) {
         for t in expl {
             if let Some(r) = t.backward_rule {
                 let name = r.to_string();

src/lib.rs

@@ -855,4 +855,41 @@ endmodule\n"
         assert!(CellLang::verify_expr(&expr).is_ok());
         assert!(matches!(expr.as_ref().last().unwrap(), CellLang::And(_)));
     }
+
+    #[test]
+    fn test_emit_celllang() {
+        let expr: RecExpr<CellLang> = "(NOR2_X1 b (NAND2_X1 a false))".parse().unwrap();
+        let module = SVModule::from_cells(expr, "gate_list".to_string(), Vec::new());
+        assert!(module.is_ok());
+        let module = module.unwrap();
+        let golden = "module gate_list (
+    b,
+    a,
+    y
+);
+  input b;
+  wire b;
+  input a;
+  wire a;
+  output y;
+  wire y;
+  wire __0__;
+  wire __1__;
+  assign __0__ = 1'b0;
+  NAND2_X1 #(
+  ) __3__ (
+      .A1(a),
+      .A2(__0__),
+      .ZN(__1__)
+  );
+  NOR2_X1 #(
+  ) __4__ (
+      .A1(b),
+      .A2(__1__),
+      .ZN(y)
+  );
+endmodule\n"
+            .to_string();
+        assert_eq!(module.to_string(), golden);
+    }
 }