Support Verilog instances with constant inputs (#103)

Co-authored-by: matth2k <mrh259@cornell.edu>

Author: arnavm30

src/lib.rs

@@ -423,6 +423,46 @@ endmodule"
         );
     }
 
+    #[test]
+    fn test_constant_parse() {
+        let module = "module my_gates (
+            y
+        );
+        output y;
+        wire y;
+        wire tmp1;
+        wire tmp2;
+
+        AND2 _0_ (
+            .A(1'd1),
+            .B(1'h01),
+            .Y(tmp1)
+        );
+
+        AND2 _1_ (
+            .A(1'b00),
+            .B(1'd0),
+            .Y(tmp2)
+        );
+
+        AND2 _2_ (
+            .A(tmp1),
+            .B(tmp2),
+            .Y(y)
+        );
+
+        endmodule"
+            .to_string();
+        let ast = sv_parse_wrapper(&module, None).unwrap();
+        let module = SVModule::from_ast(&ast);
+        assert!(module.is_ok());
+        let module = module.unwrap();
+        assert_eq!(
+            module.to_single_expr().unwrap().to_string(),
+            "(AND (AND true true) (AND false false))".to_string()
+        );
+    }
+
     #[test]
     fn test_verilog_emitter() {
         let mux: RecExpr<LutLang> = "(LUT 202 s1 (LUT 202 s0 a b) (LUT 202 s0 c d))"

src/verilog.rs

@@ -65,6 +65,52 @@ pub fn get_identifier(node: RefNode, ast: &sv_parser::SyntaxTree) -> Result<Stri
     }
 }
 
+/// Parse a literal `node` in the `ast` into a boolean value
+fn parse_literal_as_bool(node: RefNode, ast: &sv_parser::SyntaxTree) -> Result<bool, String> {
+    let value = unwrap_node!(node, BinaryValue, HexValue, UnsignedNumber);
+
+    if value.is_none() {
+        return Err(
+            "Expected a BinaryValue, HexValue, or UnsignedNumber Node under the Literal"
+                .to_string(),
+        );
+    }
+
+    match value.unwrap() {
+        RefNode::BinaryValue(b) => {
+            let loc = b.nodes.0;
+            let val = ast.get_str(&loc).unwrap();
+            let num = u64::from_str_radix(val, 2).unwrap();
+            match num {
+                1 => Ok(true),
+                0 => Ok(false),
+                _ => Err(format!("Expected a 1 bit constant. Found {}", num)),
+            }
+        }
+        RefNode::HexValue(b) => {
+            let loc = b.nodes.0;
+            let val = ast.get_str(&loc).unwrap();
+            let num = u64::from_str_radix(val, 16).unwrap();
+            match num {
+                1 => Ok(true),
+                0 => Ok(false),
+                _ => Err(format!("Expected a 1 bit constant. Found {}", num)),
+            }
+        }
+        RefNode::UnsignedNumber(b) => {
+            let loc = b.nodes.0;
+            let val = ast.get_str(&loc).unwrap();
+            let num = val.parse::<u64>().unwrap();
+            match num {
+                1 => Ok(true),
+                0 => Ok(false),
+                _ => Err(format!("Expected a 1 bit constant. Found {}", num)),
+            }
+        }
+        _ => unreachable!(),
+    }
+}
+
 fn init_format(program: u64, k: usize) -> Result<String, ()> {
     let w = 1 << k;
     match k {
@@ -633,20 +679,45 @@ impl SVModule {
                                 .add_signal(port_name, arg_name.unwrap())?;
                         }
                         None => {
-                            // Ignore clock enable and resets
+                            // Ignore clock enable and reset signals,
+                            // because they are not along the data path
+                            // The verilog emitter just re-inserts them at the end
+                            // This means we can only use D Flip-flops that are constantly *ON*.
                             if port_name == "CE" || port_name == "R" {
                                 if unwrap_node!(arg, PrimaryLiteral).is_none() {
                                     return Err(format!(
-                                        "Port {} should be driven constant",
+                                        "Non-data port {} should be driven constant",
                                         port_name
                                     ));
                                 }
-                                continue;
                             } else {
-                                return Err(format!(
-                                    "Expected a HierarchicalIdentifier for port {}",
-                                    port_name
-                                ));
+                                // If we don't have a identifier, it must be a constant connection
+                                let arg_name = cur_insts.last().unwrap().name.clone()
+                                    + port_name.as_str()
+                                    + "_const";
+                                cur_signals.push(SVSignal::new(1, arg_name.clone()));
+                                cur_insts
+                                    .last_mut()
+                                    .unwrap()
+                                    .add_signal(port_name.clone(), arg_name.clone())?;
+
+                                // Create the constant
+                                let literal = unwrap_node!(arg, PrimaryLiteral);
+                                if literal.is_none() {
+                                    return Err(format!(
+                                        "Expected a literal for connection on port {}",
+                                        port_name
+                                    ));
+                                }
+                                let value = parse_literal_as_bool(literal.unwrap(), ast)?;
+                                let const_inst = SVPrimitive::new_const(
+                                    value,
+                                    arg_name.clone(),
+                                    arg_name.clone() + "_inst",
+                                );
+
+                                // Insert the constant before the current instance
+                                cur_insts.insert(cur_insts.len() - 1, const_inst);
                             }
                         }
                     }
@@ -671,7 +742,7 @@ impl SVModule {
                     let lhs_id = unwrap_node!(lhs, Identifier).unwrap();
                     let lhs_name = get_identifier(lhs_id, ast).unwrap();
                     let rhs = unwrap_node!(net_assign, Expression).unwrap();
-                    let rhs_id = unwrap_node!(rhs, Identifier, BinaryNumber, HexNumber).unwrap();
+                    let rhs_id = unwrap_node!(rhs, Identifier, PrimaryLiteral).unwrap();
                     let assignment = unwrap_node!(net_assign, Symbol).unwrap();
                     match assignment {
                         RefNode::Symbol(sym) => {
@@ -685,47 +756,20 @@ impl SVModule {
                             return Err("Expected an assignment operator".to_string());
                         }
                     }
-                    match rhs_id {
-                        RefNode::Identifier(_) => {
-                            let rhs_name = get_identifier(rhs_id, ast).unwrap();
-                            cur_insts.push(SVPrimitive::new_wire(
-                                rhs_name.clone(),
-                                lhs_name.clone(),
-                                lhs_name + "_wire_" + &rhs_name,
-                            ));
-                        }
-                        RefNode::BinaryNumber(b) => {
-                            let loc = b.nodes.2.nodes.0;
-                            let val = ast.get_str(&loc).unwrap();
-                            let val = match val {
-                                "0" => false,
-                                "1" => true,
-                                _ => {
-                                    return Err(format!(
-                                        "Expected a 1 bit constant. Found {}",
-                                        val
-                                    ));
-                                }
-                            };
-                            cur_insts.push(SVPrimitive::new_const(
-                                val,
-                                lhs_name.clone(),
-                                lhs_name + "_const_binary",
-                            ));
-                        }
-                        RefNode::HexNumber(b) => {
-                            let loc = b.nodes.2.nodes.0;
-                            let val = ast.get_str(&loc).unwrap();
-                            let val = !matches!(val, "0");
-                            cur_insts.push(SVPrimitive::new_const(
-                                val,
-                                lhs_name.clone(),
-                                lhs_name + "_const_hex",
-                            ));
-                        }
-                        _ => {
-                            return Err("Expected a Identifier or PrimaryLiteral".to_string());
-                        }
+                    if matches!(rhs_id, RefNode::Identifier(_)) {
+                        let rhs_name = get_identifier(rhs_id, ast).unwrap();
+                        cur_insts.push(SVPrimitive::new_wire(
+                            rhs_name.clone(),
+                            lhs_name.clone(),
+                            lhs_name + "_wire_" + &rhs_name,
+                        ));
+                    } else {
+                        let val = parse_literal_as_bool(rhs_id, ast)?;
+                        cur_insts.push(SVPrimitive::new_const(
+                            val,
+                            lhs_name.clone(),
+                            lhs_name + "_const_binary",
+                        ));
                     }
                 }
                 NodeEvent::Leave(RefNode::NetAssignment(_net_assign)) => (),