CellLang support multiple module outputs (#140)

Author: matth2k

src/asic.rs

@@ -23,7 +23,8 @@ define_language! {
         "AND" = And([Id; 2]),
         "OR" = Or([Id; 2]),
         "INV" = Inv([Id; 1]),
-        Cell(Symbol, Vec<Id>), // or Box<[Id]>?
+        Cell(Symbol, Vec<Id>),
+        "BUS" = Bus(Box<[Id]>),
     }
 }
 

src/bin/cellmap.rs

@@ -161,7 +161,7 @@ fn main() -> std::io::Result<()> {
 
     eprintln!("INFO: Compiling Verilog...");
     let expr = f
-        .to_expr()
+        .to_single_cell_expr()
         .map_err(|s| std::io::Error::new(std::io::ErrorKind::Other, s))?;
 
     eprintln!("INFO: Building e-graph...");

src/verilog.rs

@@ -776,7 +776,11 @@ impl VerilogEmission for CellLang {
         if expr.is_empty() {
             return vec![];
         }
-        vec![(expr.len() - 1).into()]
+
+        match expr.last().unwrap() {
+            CellLang::Bus(l) => l.to_vec(),
+            _ => vec![(expr.len() - 1).into()],
+        }
     }
 
     fn get_var(&self) -> Option<String> {
@@ -1606,8 +1610,6 @@ impl SVModule {
                     module.signals.push(SVSignal::new(1, output));
                 }
                 mapping.insert(id.into(), sname);
-            } else {
-                return Err(format!("Unsupported node type: {:?}", node));
             }
         }
 
@@ -1753,6 +1755,27 @@ impl SVModule {
         Ok(expr)
     }
 
+    /// Get a single [CellLang] expression for the module as a bus
+    pub fn to_single_cell_expr(&self) -> Result<RecExpr<CellLang>, String> {
+        if let Err(s) = self.contains_cycles() {
+            return Err(format!(
+                "Cannot convert module with feedback on signal {}",
+                s
+            ));
+        }
+
+        let mut expr: RecExpr<CellLang> = RecExpr::default();
+        let mut map = HashMap::new();
+        let mut outputs: Vec<Id> = vec![];
+        for output in self.outputs.iter() {
+            outputs.push(CellLang::get_expr(&output.name, self, &mut expr, &mut map)?);
+        }
+        if outputs.len() > 1 {
+            expr.add(CellLang::Bus(outputs.into()));
+        }
+        Ok(expr)
+    }
+
     /// Convert the module to a [Language] expression
     pub fn to_expr<L>(&self) -> Result<RecExpr<L>, String>
     where

tests/lutlang/bus.txt

@@ -1,4 +1,4 @@
-// RUN: opt %s -k 4 -n 24 2>>/dev/null | FileCheck %s
+// RUN: opt %s -k 4 -n 5 2>>/dev/null | FileCheck %s
 
 // MUX with exact inputs
 (BUS (MUX s1 (MUX s0 a b) (MUX s0 c d)) (MUX s1 (MUX s0 a b) (MUX s0 a b)))