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Initial CMD646U2 Ultra ATA controller emulation.
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‎devices/common/ata/cmd646.cpp

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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file CMD646U2 PCI Ultra ATA controller emulation. */
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#include <devices/common/ata/cmd646.h>
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#include <devices/deviceregistry.h>
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#include <loguru.hpp>
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#include <machines/machinebase.h>
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CmdIdeCtrl::CmdIdeCtrl() : PCIDevice("cmd-ide") {
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this->supports_types(HWCompType::PCI_DEV | HWCompType::IDE_HOST);
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// set up PCI configuration space header
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this->vendor_id = this->subsys_vndr = PCI_VENDOR_SILICON_IMAGE;
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this->device_id = this->subsys_id = DEV_ID_CMD646;
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this->class_rev = ((MY_DEV_CLASS | this->prog_if) << 8) | MY_REV_ID;
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this->max_lat = 4;
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this->min_gnt = 2;
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this->irq_pin = 1;
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this->bars_cfg[0] = 0xFFFFFFF9; // Command block I/O space, primary channel
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this->bars_cfg[1] = 0xFFFFFFFD; // Control block I/O space, primary channel
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this->bars_cfg[2] = 0xFFFFFFF9; // Command block I/O space, secondary channel
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this->bars_cfg[3] = 0xFFFFFFFD; // Control block I/O space, secondary channel
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this->bars_cfg[4] = 0xFFFFFFF1; // Bus master I/O space, both channels
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this->finish_config_bars();
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this->pci_notify_bar_change = [this](int bar_num) {
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this->notify_bar_change(bar_num);
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};
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gMachineObj->add_device("CmdAta0", std::unique_ptr<IdeChannel>(new IdeChannel("CmdAta0")));
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gMachineObj->add_device("CmdAta1", std::unique_ptr<IdeChannel>(new IdeChannel("CmdAta1")));
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this->ch0 = dynamic_cast<IdeChannel*>(gMachineObj->get_comp_by_name("CmdAta0"));
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this->ch1 = dynamic_cast<IdeChannel*>(gMachineObj->get_comp_by_name("CmdAta1"));
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this->ch0->set_irq_callback([this](const uint8_t intrq_state) {
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LOG_F(INFO, "CmdAta0 INTRQ updated to %d", intrq_state);
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this->update_irq(0, intrq_state);
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});
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this->ch1->set_irq_callback([this](const uint8_t intrq_state) {
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LOG_F(INFO, "CmdAta1 INTRQ updated to %d", intrq_state);
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this->update_irq(1, intrq_state);
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});
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}
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uint32_t CmdIdeCtrl::pci_cfg_read(uint32_t reg_offs, AccessDetails &details) {
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if (reg_offs < 64)
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return PCIDevice::pci_cfg_read(reg_offs, details);
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if (details.size != 1)
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ABORT_F("%s: non-byte read from PCI config reg 0x%X", this->name.c_str(),
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reg_offs + details.offset);
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if (reg_offs < 112)
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return this->read_config_reg(reg_offs + details.offset);
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LOG_F(WARNING, "%s: reading config reg at 0x%X", this->name.c_str(), reg_offs);
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return 0;
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}
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void CmdIdeCtrl::pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details) {
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if (reg_offs < 64) {
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PCIDevice::pci_cfg_write(reg_offs, value, details);
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return;
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}
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if (details.size != 1)
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ABORT_F("%s: non-byte write to PCI config reg 0x%X", this->name.c_str(),
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reg_offs + details.offset);
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if (reg_offs < 112)
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this->write_config_reg(reg_offs + details.offset, value);
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else
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LOG_F(WARNING, "%s: writing config reg at 0x%X", this->name.c_str(), reg_offs);
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}
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void CmdIdeCtrl::notify_bar_change(int bar_num) {
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if (bar_num >= 0 && bar_num <= 4)
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this->io_bases[bar_num] = this->bars[bar_num] & ~3;
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}
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bool CmdIdeCtrl::pci_io_read(uint32_t offset, uint32_t size, uint32_t* res) {
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*res = 0;
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if ((offset & ~7) == this->io_bases[0]) {
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*res = this->ch0->read(offset & 7, size);
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} else if ((offset & ~7) == this->io_bases[2]) {
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*res = this->ch1->read(offset & 7, size);
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} else if ((offset & ~3) == this->io_bases[1]) {
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*res = this->ch0->read((offset & 3) + DEV_CTRL_BLK_OFFSET, size);
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} else if ((offset & ~3) == this->io_bases[3]) {
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*res = this->ch1->read((offset & 3) + DEV_CTRL_BLK_OFFSET, size);
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} else if ((offset & ~0xF) == this->io_bases[4]) {
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*res = this->read_bus_master_reg(offset & 0xF);
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} else {
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*res = 0xFFFFFFFFUL;
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return false;
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}
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return true;
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}
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bool CmdIdeCtrl::pci_io_write(uint32_t offset, uint32_t value, uint32_t size) {
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if ((offset & ~7) == this->io_bases[0]) {
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this->ch0->write(offset & 7, value, size);
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} else if ((offset & ~7) == this->io_bases[2]) {
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this->ch1->write(offset & 7, value, size);
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} else if ((offset & ~3) == this->io_bases[1]) {
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this->ch0->write((offset & 3) + DEV_CTRL_BLK_OFFSET, value, size);
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} else if ((offset & ~3) == this->io_bases[3]) {
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this->ch1->write((offset & 3) + DEV_CTRL_BLK_OFFSET, value, size);
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} else if ((offset & ~0xF) == this->io_bases[4]) {
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this->write_bus_master_reg(offset & 0xF, value & 0xFFU);
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} else
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return false;
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return true;
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};
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uint8_t CmdIdeCtrl::read_config_reg(uint32_t reg_offset) {
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switch(reg_offset) {
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case ARTTIM0:
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return this->addr_setup_time_0;
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case DRWTIM0:
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return this->data_rw_time_0;
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case ARTTIM1:
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return this->addr_setup_time_1;
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case DRWTIM1:
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return this->data_rw_time_1;
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default:
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LOG_F(ERROR, "%s: unimplemented config reg at 0x%X", this->name.c_str(),
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reg_offset);
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}
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return 0;
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}
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void CmdIdeCtrl::write_config_reg(uint32_t reg_offset, uint8_t val) {
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switch(reg_offset) {
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case ARTTIM0:
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this->addr_setup_time_0 = val;
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LOG_F(9, "%s: ARTTIM0 set to 0x%X", this->name.c_str(), val);
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break;
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case DRWTIM0:
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this->data_rw_time_0 = val;
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LOG_F(9, "%s: DRWTIM0 set to 0x%X", this->name.c_str(), val);
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break;
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case ARTTIM1:
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this->addr_setup_time_1 = val;
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LOG_F(9, "%s: ARTTIM1 set to 0x%X", this->name.c_str(), val);
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break;
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case DRWTIM1:
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this->data_rw_time_1 = val;
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LOG_F(9, "%s: DRWTIM1 set to 0x%X", this->name.c_str(), val);
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break;
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default:
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LOG_F(ERROR, "%s: unimplemented config reg at 0x%X", this->name.c_str(),
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reg_offset);
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}
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}
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uint8_t CmdIdeCtrl::read_bus_master_reg(const uint8_t reg_offset) {
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switch(reg_offset) {
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case MRDMODE:
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return this->mrdmode;
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default:
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LOG_F(ERROR, "%s: unimplemented bus master reg at 0x%X", this->name.c_str(),
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reg_offset);
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}
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return 0;
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}
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void CmdIdeCtrl::write_bus_master_reg(const uint8_t reg_offset, const uint8_t val) {
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switch(reg_offset) {
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case MRDMODE:
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if (val & BM_CH0_INT)
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this->mrdmode &= ~BM_CH0_INT;
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if (val & BM_CH1_INT)
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this->mrdmode &= ~BM_CH1_INT;
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this->mrdmode = (this->mrdmode & ~(BM_BLOCK_CH0_INT | BM_BLOCK_CH1_INT)) |
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(val & (BM_BLOCK_CH0_INT | BM_BLOCK_CH1_INT));
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LOG_F(INFO, "%s: MRDMODE set to 0x%X", this->name.c_str(), val);
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if ((this->mrdmode & BM_CH0_INT) && !(this->mrdmode & BM_BLOCK_CH0_INT))
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this->update_irq(0, 1);
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if ((this->mrdmode & BM_CH1_INT) && !(this->mrdmode & BM_BLOCK_CH1_INT))
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this->update_irq(1, 1);
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break;
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case UDIDETCR0:
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this->udma_time_cr = val;
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break;
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default:
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LOG_F(ERROR, "%s: unimplemented bus master reg at 0x%X", this->name.c_str(),
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reg_offset);
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}
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}
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void CmdIdeCtrl::update_irq(const int ch_num, const uint8_t irq_level) {
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bool forward_irq = !(this->mrdmode & (ch_num ? BM_BLOCK_CH1_INT : BM_BLOCK_CH0_INT));
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if (irq_level)
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this->mrdmode |= ch_num ? BM_CH1_INT : BM_CH0_INT;
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else
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this->mrdmode &= ~(ch_num ? BM_CH1_INT : BM_CH0_INT);
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if (!irq_level || forward_irq)
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this->irq_info.int_ctrl_obj->ack_int(this->irq_info.irq_id, irq_level);
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}
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static const DeviceDescription CmdIde_Descriptor = {
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CmdIdeCtrl::create, {}, {}
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};
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REGISTER_DEVICE(CmdAta, CmdIde_Descriptor);

‎devices/common/ata/cmd646.h

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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
3+
Copyright (C) 2018-24 divingkatae and maximum
4+
(theweirdo) spatium
5+
6+
(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
7+
8+
This program is free software: you can redistribute it and/or modify
9+
it under the terms of the GNU General Public License as published by
10+
the Free Software Foundation, either version 3 of the License, or
11+
(at your option) any later version.
12+
13+
This program is distributed in the hope that it will be useful,
14+
but WITHOUT ANY WARRANTY; without even the implied warranty of
15+
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16+
GNU General Public License for more details.
17+
18+
You should have received a copy of the GNU General Public License
19+
along with this program. If not, see <https://www.gnu.org/licenses/>.
20+
*/
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/** @file CMD646U2 PCI Ultra ATA controller definitions. */
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#ifndef CMD646_IDE_H
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#define CMD646_IDE_H
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#include <devices/common/hwcomponent.h>
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#include <devices/common/hwinterrupt.h>
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#include <devices/common/ata/idechannel.h>
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#include <devices/common/pci/pcidevice.h>
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#include <memory>
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#define DEV_ID_CMD646 0x646
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#define MY_DEV_CLASS 0x010180 // mass storage | IDE controller | IDE master
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#define MY_REV_ID 7
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// Offset for converting addresses of the device control block registers
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// defined in the PCI IDE Controller specification, rev. 1.0 3/4/94
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// to the addresses used in IdeChannel
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#define DEV_CTRL_BLK_OFFSET 0x14
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/** CMD646 control/status registers. */
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enum {
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ARTTIM0 = 0x53,
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DRWTIM0 = 0x54,
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ARTTIM1 = 0x55,
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DRWTIM1 = 0x56,
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};
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/** CMD646 bus master registers. */
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enum {
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MRDMODE = 1, // misnomer, contains interrupt control/status bits (CMD646U2 specific)
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UDIDETCR0 = 3, // Ultra DMA timing control register (CMD646U2 specific)
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};
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/** Bit definitions for the MRDMODE register. */
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enum {
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BM_CH0_INT = 1 << 2,
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BM_CH1_INT = 1 << 3,
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BM_BLOCK_CH0_INT = 1 << 4,
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BM_BLOCK_CH1_INT = 1 << 5,
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};
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class CmdIdeCtrl : public PCIDevice {
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public:
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CmdIdeCtrl();
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~CmdIdeCtrl() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<CmdIdeCtrl>(new CmdIdeCtrl());
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}
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// PCIDevice methods
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uint32_t pci_cfg_read(uint32_t reg_offs, AccessDetails &details) override;
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void pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details) override;
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bool pci_io_read(uint32_t offset, uint32_t size, uint32_t* res) override;
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bool pci_io_write(uint32_t offset, uint32_t value, uint32_t size) override;
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int device_postinit() override {
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this->irq_info = this->host_instance->register_pci_int(this);
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return 0;
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};
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private:
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void notify_bar_change(int bar_num);
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uint8_t read_config_reg(uint32_t reg_offset);
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void write_config_reg(uint32_t reg_offset, uint8_t val);
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uint8_t read_bus_master_reg(const uint8_t reg_offset);
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void write_bus_master_reg(const uint8_t reg_offset, const uint8_t val);
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void update_irq(const int ch_num, const uint8_t irq_level);
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// on reset, programming interface defaults to
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// "both channels operating in native mode"
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uint8_t prog_if = 0x0F;
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uint32_t io_bases[5] = {};
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IdeChannel *ch0 = nullptr;
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IdeChannel *ch1 = nullptr;
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// unknown default, set it to 2 clocks (60 ns)
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uint8_t addr_setup_time_0 = 0x40; // address setup time for drive 0
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uint8_t addr_setup_time_1 = 0x40; // address setup time for drive 1
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uint8_t data_rw_time_0 = 0x00; // data read/write time for drive 0
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uint8_t data_rw_time_1 = 0x00; // data read/write time for drive 1
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uint8_t mrdmode = 0;
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uint8_t udma_time_cr = 0;
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IntDetails irq_info = {};
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};
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#endif // CMD646_IDE_H

‎devices/common/pci/pcibase.h

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@@ -52,11 +52,12 @@ enum {
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/** PCI Vendor IDs for devices used in Power Macintosh computers. */
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enum {
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PCI_VENDOR_ATI = 0x1002,
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PCI_VENDOR_DEC = 0x1011,
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PCI_VENDOR_MOTOROLA = 0x1057,
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PCI_VENDOR_APPLE = 0x106B,
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PCI_VENDOR_NVIDIA = 0x10DE,
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PCI_VENDOR_ATI = 0x1002,
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PCI_VENDOR_DEC = 0x1011,
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PCI_VENDOR_MOTOROLA = 0x1057,
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PCI_VENDOR_APPLE = 0x106B,
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PCI_VENDOR_SILICON_IMAGE = 0x1095,
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PCI_VENDOR_NVIDIA = 0x10DE,
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};
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/** PCI BAR types */

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