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‎zdocs/developers/awacs.md

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@@ -26,6 +26,16 @@ All registers are 32-bit here.
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| Codec Status | 0x20 |
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| Clipping Count | 0x30 |
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| Byte Swapping | 0x40 |
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| Frame Count | 0x50 |
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##Sound Control Register bits
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| Register | Bit Mask |
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|:-------------------------:|:--------:|
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| Input Subframe Select | 0x000F |
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| Output Subframe Select | 0x00F0 |
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| Sound Rate | 0x0700 |
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| Error | 0x0800 |
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Separate volume controls exist for the CD drive and the microphone.

‎zdocs/developers/bebox.md

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@@ -10,6 +10,7 @@ It also has a unique 37-pin connector dubbed the Geekport to allow hobbyists to
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* MPC105 PCI Bridge (Codename: Eagle) - Predecessor to the MPC106 (Grackle); Used for bridging between the motherboard and PCI slots
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* Intel 82378ZB - Used for bridging between the motherboard and ISA slots
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* SYM53C810A - SCSI I/O Processor
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* bq3285 - Used for the Real-Time Clock
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### Motherboard registers

‎zdocs/developers/powerpc.md renamed to ‎zdocs/developers/cpu/powerpc/powerpc.md

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The PowerPC is the main processor behind Power Macs. Currently, DingusPPC only implements the 32-bit variant.
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The PowerPC is the main processor used for Power Macs. Currently, DingusPPC only implements the 32-bit variant.
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# General Notes
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All instructions are 32 bits wide, regardless of whether the PowerPC is in 32-bit or 64-bit mode.
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Code execution generally begins at 0xFFF00100, which the reset exception vector.
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# BATs
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The 601 BATs are emulated by the Open Firmware.
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# Registers
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| Register Type | Number | Purpose |
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| :-------------------------------- | :--------------------- | :---------------------------------------------------- |
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| General Purpose (GPR) | 32 | Calculate, Store, and Load 32-bit fixed-point numbers |
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| Floating Point (FPR) | 32 | Calculate, Store, and Load 32-bit or 64-bit floating-point numbers |
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| Special Purpose (SPR) | Up to 1024 (in theory) | Store and load specialized 32-bit fixed-point numbers |
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| Segment (SR) | 16 | Calculate, Store, and Load 32-bit fixed-point numbers |
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| Time Base Facility (TBR) | 2 | Calculate, Store, and Load 32-bit fixed-point numbers |
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| Condition Register | 1 | Stores conditions based on the results of fixed-point operations |
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| Floating Point Condition Register | 1 | Stores conditions based on the results of floating-point operations |
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| Vector Status and Control Register (VSCR) | 1 | Stores conditions based on the results of vector operations |
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| Machine State Register | 1 | |
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| Register Type | Number | Purpose |
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| :----------------------------------------- | :--------------------- | :------------------------------------------------------------------ |
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| General Purpose (GPR) | 32 | Calculate, Store, and Load 32-bit fixed-point numbers |
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| Floating Point (FPR) | 32 | Calculate, Store, and Load 32-bit or 64-bit floating-point numbers |
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| Special Purpose (SPR) | Up to 1024 (in theory) | Store and load specialized 32-bit fixed-point numbers |
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| Segment (SR) | 16 | Calculate, Store, and Load 32-bit fixed-point numbers |
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| Time Base Facility (TBR) | 2 | Calculate, Store, and Load 32-bit fixed-point numbers |
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| Condition Register | 1 | Stores conditions based on the results of fixed-point operations |
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| Floating Point Condition Register | 1 | Stores conditions based on the results of floating-point operations |
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| Vector Status and Control Register (VSCR) | 1 | Stores conditions based on the results of vector operations |
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| Machine State Register (MSR) | 1 | Stores the state of the processor |
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# Special Registers
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| RTC Lower Register (RTCL) | 5 | (601 only) |
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| Link Register (LR) | 8 | |
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| Counter Quotient Register (CTR) | 9 | |
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| Search Description Register (SDR1)| 25 | Specifies starting address of the page table |
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| Save and Restore Register 0 (SRR0)| 26 | |
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| Save and Restore Register 1 (SRR1)| 27 | |
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| Vector Save/Restore | 256 | (G4+) |
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| Time Base Lower (TBL) | 268 | (603+) |
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| Time Base Upper (TBU) | 269 | (603+) |
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| Hardware Implementation 0 (HID0) | 1008 | |
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| Hardware Implementation 1 (HID1) | 1009 | |
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# HID 0
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## HID 0
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| Model | Bits Enabled |
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| :------------ | :------------------ |
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| 604E | NHR |
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| 750 (G3) | NHR, DOZE/NAP/SLEEP |
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# Exceptions
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nnn is either 0x000 or 0xFFF, depending on the 25th bit (0x40) set in the MSR. Usually, the 25th bit is set when booting up a system and unset after it is set.
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| Exception | Address |
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| :------------------------------------ | :--------- |
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| System Reset | 0xnnn00100 |
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| Machine Check | 0xnnn00200 |
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| DSI | 0xnnn00300 |
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| ISI | 0xnnn00400 |
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| External Interrupt | 0xnnn00500 |
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| Alignment | 0xnnn00600 |
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| Program | 0xnnn00700 |
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| Floating Point Unavailable | 0xnnn00800 |
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| Decrementer | 0xnnn00900 |
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| System Call | 0xnnn00C00 |
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| Trace | 0xnnn00D00 |
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| Performance Monitor (G3+) | 0xnnn00F00 |
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| AltiVec Unavailable (G4+) | 0xnnn00F20 |
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| Instruction Address Breakpoint (G3+) | 0xnnn01300 |
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| System Management Interrupt (G3+) | 0xnnn01400 |
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| AltiVec Assist (G4+) | 0xnnn01600 |
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| Thermal Management Interrupt (G3+) | 0xnnn01700 |
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# Endianness
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PowerPC supports both big-endian and little-endian modes. Mac OS largely operates in big-endian mode, due to its 68k heritage.
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# Eccentricities
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* The HW Init routine used in the ROMs uses the DEC (decrement; SPR 22) register to measure CPU speed. With a PowerPC 601, the DEC register operates on the same frequency as RTC - 7.8125 MHz but uses only 25 most significant bits. In other words, it decrements by 128 at 1/7.8125 MHz.

‎zdocs/developers/dbdma.md

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| AUDIO IN | 0x9 |
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| SCSI1 | 0xA |
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What's notable about the registers is that they are in little-endian format.
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What's notable about the registers is that they are in little-endian format, thus Mac OS uses the stwbrx and lwbrx instructions to store values.
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| Register | Offset |
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|:-----------------:|:------:|
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| KEY_SYSTEM | 0x6 |
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| KEY_DEVICE | 0x7 |
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# References
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## Control Register
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| Value | Offset |
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|:-----------:|:------:|
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| Branch | 0x100 |
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| Active | 0x400 |
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| Dead | 0x800 |
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| Wake | 0x1000 |
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| Flush | 0x2000 |
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| Pause | 0x4000 |
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| Run | 0x8000 |
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## References
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* https://stuff.mit.edu/afs/sipb/contrib/doc/specs/protocol/chrp/chrp_io.pdf
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* https://stuff.mit.edu/afs/sipb/contrib/doc/specs/protocol/chrp/chrp_hrpa.pdf

‎zdocs/developers/valkyrie.md

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The Valkyrie video chip is included in some Quadras and Performas. The Marathon games (2 and Infinity, at least) use this chip to blit 16-bit video.
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| Register Name | Offset |
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|:-------------------------:|:------:|
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| CLUT Address | 0x4000 |
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| CLUT Graphic | 0x4004 |
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| CLUT Video Data | 0x4008 |
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| CLUT Color Key | 0x400C |
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| Subsystem Config | 0xA00C |
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| Video In Control | 0xA020 |
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| Window X Start | 0xA060 |
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| Window Y Start | 0xA064 |
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| Window Width | 0xA070 |
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| Window Height | 0xA074 |
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| Video Field X Start | 0xA080 |
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| Video Field Y Start | 0xA084 |

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