Skip to content

Commit f1e1a9d

Browse files
dpretetdpretet
committed
Clean up one false failing test and prepare almost full/empty flags
1 parent 023976c commit f1e1a9d

File tree

9 files changed

+246
-121
lines changed

9 files changed

+246
-121
lines changed

‎.gitignore

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,3 @@
11
*.out
22
*.vcd
3+
*.lxt

‎sim/test/async_fifo_unit_test.sv

Lines changed: 68 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -15,11 +15,13 @@ module async_fifo_unit_test;
1515
reg winc;
1616
reg [DSIZE-1:0] wdata;
1717
wire wfull;
18+
wire awfull;
1819
reg rclk;
1920
reg rrst_n;
2021
reg rinc;
2122
wire [DSIZE-1:0] rdata;
2223
wire rempty;
24+
wire arempty;
2325

2426
async_fifo
2527
#(
@@ -33,11 +35,13 @@ module async_fifo_unit_test;
3335
winc,
3436
wdata,
3537
wfull,
38+
awfull,
3639
rclk,
3740
rrst_n,
3841
rinc,
3942
rdata,
40-
rempty
43+
rempty,
44+
arempty
4145
);
4246

4347
// An example to create a clock
@@ -47,10 +51,13 @@ module async_fifo_unit_test;
4751
always #3 rclk <= ~rclk;
4852

4953
// An example to dump data for visualization
50-
initial $dumpvars(0,async_fifo_unit_test);
54+
initial begin
55+
$dumpvars(0, async_fifo_unit_test);
56+
end
5157

5258
task setup();
5359
begin
60+
5461
wrst_n = 1'b0;
5562
winc = 1'b0;
5663
wdata = 0;
@@ -61,6 +68,7 @@ module async_fifo_unit_test;
6168
rrst_n = 1;
6269
#200;
6370
@(posedge wclk);
71+
6472
end
6573
endtask
6674

@@ -74,75 +82,114 @@ module async_fifo_unit_test;
7482

7583
`UNIT_TEST(IDLE)
7684

77-
`INFO("Start IDLE test");
85+
`INFO("Test: IDLE");
7886
`FAIL_IF(wfull);
7987
`FAIL_IF(!rempty);
8088

8189
`UNIT_TEST_END
8290

8391
`UNIT_TEST(SIMPLE_WRITE_AND_READ)
8492

85-
`INFO("Simple write then read");
93+
`INFO("Test: Simple write then read");
8694

8795
@(posedge wclk)
96+
8897
winc = 1;
8998
wdata = 32'hA;
99+
90100
@(posedge wclk)
101+
91102
winc = 0;
103+
92104
@(posedge rclk)
93-
wait (rempty == 0);
105+
106+
wait (rempty == 1'b0);
107+
94108
`FAIL_IF_NOT_EQUAL(rdata, 32'hA);
95109

96110
`UNIT_TEST_END
97111

98112
`UNIT_TEST(MULTIPLE_WRITE_AND_READ)
99113

100-
`INFO("Multiple write then read");
114+
`INFO("Test: Multiple write then read");
101115

102-
for (i=0; i<20; i = i+1) begin
103-
@(posedge wclk)
116+
for (i=0; i<10; i=i+1) begin
117+
@(negedge wclk);
104118
winc = 1;
105119
wdata = i;
106-
@(posedge wclk)
107-
winc = 0;
108-
@(posedge rclk)
109-
wait (rempty == 0);
120+
// $display("DEBUG: [%g]: %x", $time, i);
121+
end
122+
@(negedge wclk);
123+
winc = 0;
124+
125+
#100;
126+
127+
@(posedge rclk);
128+
129+
rinc = 1;
130+
for (i=0; i<10; i=i+1) begin
131+
@(posedge rclk);
110132
`FAIL_IF_NOT_EQUAL(rdata, i);
133+
// $display("DEBUG: [%g]: %x", $time, rdata);
111134
end
112135

113136
`UNIT_TEST_END
114137

115138
`UNIT_TEST(TEST_FULL_FLAG)
116139

117-
`INFO("Test full flag test");
140+
`INFO("Test: full flag test");
118141

119-
for (i=0; i<2**ASIZE; i = i+1) begin
120-
@(posedge wclk)
121-
winc = 1;
142+
winc = 1;
143+
144+
for (i=0; i<2**ASIZE; i=i+1) begin
145+
@(negedge wclk)
122146
wdata = i;
123147
end
124-
@(posedge wclk)
125-
@(posedge wclk)
148+
149+
@(negedge wclk);
150+
winc = 0;
151+
126152
@(posedge wclk)
127153
`FAIL_IF_NOT_EQUAL(wfull, 1);
154+
128155
#50;
129156

130157
`UNIT_TEST_END
131158

132159
`UNIT_TEST(TEST_EMPTY_FLAG)
133160

134-
`INFO("Test empty flag test");
161+
`INFO("Test: empty flag test");
135162

136-
for (i=0; i<2**ASIZE; i = i+1) begin
163+
for (i=0; i<2**ASIZE; i=i+1) begin
137164
@(posedge wclk)
138165
winc = 1;
139166
wdata = i;
140167
end
141-
`FAIL_IF_NOT_EQUAL(rempty, 1);
168+
`FAIL_IF_NOT_EQUAL(rempty, 0);
142169
#50;
143170

144171
`UNIT_TEST_END
145172

173+
`UNIT_TEST(TEST_SIMPLE_ALMOST_FULL_FLAG)
174+
175+
`INFO("Test: Almost full flag simple test");
176+
177+
winc = 1;
178+
for (i=0; i<2**ASIZE; i=i+1) begin
179+
@(negedge wclk)
180+
wdata = i;
181+
end
182+
183+
@(negedge wclk);
184+
winc = 0;
185+
186+
@(posedge wclk)
187+
`FAIL_IF_NOT_EQUAL(wfull, 1);
188+
189+
#50;
190+
191+
`UNIT_TEST_END
192+
146193
`UNIT_TESTS_END
147194

148195
endmodule

‎sim/test/wave.gtkw

Lines changed: 78 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1,42 +1,96 @@
11
[*]
2-
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
3-
[*] Fri Sep 1 12:55:43 2017
2+
[*] GTKWave Analyzer v3.3.85 (w)1999-2017 BSI
3+
[*] Wed Oct 4 21:08:19 2017
44
[*]
5-
[dumpfile] "/home/damien/workspace/async_fifo/sim/test/dump.lxt"
6-
[dumpfile_mtime] "Fri Sep 1 12:55:22 2017"
7-
[dumpfile_size] 3913
8-
[savefile] "/home/damien/workspace/async_fifo/sim/test/wave.gtkw"
9-
[timestart] 0
10-
[size] 1000 600
11-
[pos] -1 -1
12-
*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
5+
[dumpfile] "/Users/damien/dev/verilog/async_fifo/sim/test/dump.lxt"
6+
[dumpfile_mtime] "Wed Oct 4 20:53:16 2017"
7+
[dumpfile_size] 3687
8+
[savefile] "/Users/damien/dev/verilog/async_fifo/sim/test/wave.gtkw"
9+
[timestart] 1089250
10+
[size] 1920 1056
11+
[pos] -1 0
12+
*-13.241215 1077000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
13+
[treeopen] async_fifo_unit_test.
14+
[treeopen] async_fifo_unit_test.dut.
1315
[sst_width] 196
14-
[signals_width] 238
16+
[signals_width] 332
1517
[sst_expanded] 1
16-
[sst_vpaned_height] 150
18+
[sst_vpaned_height] 575
19+
@200
20+
-TB
1721
@22
22+
async_fifo_unit_test.svut_error[31:0]
23+
async_fifo_unit_test.svut_nb_test[31:0]
24+
async_fifo_unit_test.svut_nb_test_success[31:0]
1825
async_fifo_unit_test.i[31:0]
1926
@28
27+
async_fifo_unit_test.wclk[0]
28+
async_fifo_unit_test.wrst_n[0]
29+
async_fifo_unit_test.winc[0]
30+
@22
31+
async_fifo_unit_test.wdata[31:0]
32+
@28
33+
async_fifo_unit_test.wfull[0]
2034
async_fifo_unit_test.rclk[0]
35+
async_fifo_unit_test.rrst_n[0]
36+
async_fifo_unit_test.rinc[0]
2137
@22
2238
async_fifo_unit_test.rdata[31:0]
2339
@28
2440
async_fifo_unit_test.rempty[0]
25-
async_fifo_unit_test.rinc[0]
26-
async_fifo_unit_test.rrst_n[0]
41+
@200
42+
-DUT
43+
@28
44+
async_fifo_unit_test.dut.rclk[0]
45+
async_fifo_unit_test.dut.rrst_n[0]
46+
async_fifo_unit_test.dut.rinc[0]
2747
@22
28-
async_fifo_unit_test.svut_error[31:0]
29-
async_fifo_unit_test.svut_nb_test[31:0]
30-
async_fifo_unit_test.svut_nb_test_success[31:0]
31-
async_fifo_unit_test.svut_timeout[31:0]
32-
async_fifo_unit_test.svut_timeout_max[31:0]
48+
async_fifo_unit_test.dut.raddr[3:0]
49+
async_fifo_unit_test.dut.rdata[31:0]
3350
@28
34-
async_fifo_unit_test.wclk[0]
51+
async_fifo_unit_test.dut.rempty[0]
3552
@22
36-
async_fifo_unit_test.wdata[31:0]
53+
async_fifo_unit_test.dut.rptr[4:0]
54+
async_fifo_unit_test.dut.rq2_wptr[4:0]
3755
@28
38-
async_fifo_unit_test.wfull[0]
39-
async_fifo_unit_test.winc[0]
40-
async_fifo_unit_test.wrst_n[0]
56+
async_fifo_unit_test.dut.wclk[0]
57+
async_fifo_unit_test.dut.wrst_n[0]
58+
async_fifo_unit_test.dut.winc[0]
59+
async_fifo_unit_test.dut.wfull[0]
60+
@22
61+
async_fifo_unit_test.dut.wdata[31:0]
62+
async_fifo_unit_test.dut.wptr[4:0]
63+
async_fifo_unit_test.dut.wq2_rptr[4:0]
64+
@200
65+
-FIFO MEM
66+
@28
67+
async_fifo_unit_test.dut.fifomem.wclk[0]
68+
async_fifo_unit_test.dut.fifomem.wclken[0]
69+
@22
70+
async_fifo_unit_test.dut.fifomem.waddr[3:0]
71+
async_fifo_unit_test.dut.fifomem.wdata[31:0]
72+
@28
73+
async_fifo_unit_test.dut.fifomem.wfull[0]
74+
@22
75+
async_fifo_unit_test.dut.fifomem.raddr[3:0]
76+
async_fifo_unit_test.dut.fifomem.rdata[31:0]
77+
@200
78+
-RD PTR EMPTY
79+
@28
80+
async_fifo_unit_test.dut.rptr_empty.rclk[0]
81+
async_fifo_unit_test.dut.rptr_empty.rrst_n[0]
82+
async_fifo_unit_test.dut.rptr_empty.rinc[0]
83+
async_fifo_unit_test.dut.rptr_empty.rempty[0]
84+
@22
85+
async_fifo_unit_test.dut.rptr_empty.raddr[3:0]
86+
async_fifo_unit_test.dut.rptr_empty.rbin[4:0]
87+
async_fifo_unit_test.dut.rptr_empty.rbinnext[4:0]
88+
@28
89+
async_fifo_unit_test.dut.rptr_empty.rempty_val[0]
90+
@22
91+
async_fifo_unit_test.dut.rptr_empty.rgraynext[4:0]
92+
async_fifo_unit_test.dut.rptr_empty.rptr[4:0]
93+
@23
94+
async_fifo_unit_test.dut.rptr_empty.rq2_wptr[4:0]
4195
[pattern_trace] 1
4296
[pattern_trace] 0

0 commit comments

Comments
 (0)