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PaebbelsPaebbels
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Merged VerilogVersion and SystemVerilogVersion.
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2 files changed

+173
-90
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2 files changed

+173
-90
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‎pySVModel/__init__.py

Lines changed: 42 additions & 81 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@
3434
:copyright: Copyright 2021-2023 Patrick Lehmann - Bötzingen, Germany
3535
:license: Apache License, Version 2.0
3636
"""
37-
from enum import unique, Enum
37+
from enum import unique, Enum
3838
from typing import Dict, Union
3939

4040
from pyTooling.Decorators import export
@@ -44,97 +44,50 @@
4444
__email__ = "Paebbels@gmail.com"
4545
__copyright__ = "2021-2023, Patrick Lehmann"
4646
__license__ = "Apache License, Version 2.0"
47-
__version__ = "0.3.6"
48-
49-
50-
@export
51-
@unique
52-
class VerilogVersion(Enum):
53-
Any = -1
54-
Verilog95 = 95
55-
Verilog2001 = 2001
56-
Verilog2005 = 2005
57-
58-
__VERSION_MAPPINGS__: Dict[Union[int, str], Enum] = {
59-
95: Verilog95,
60-
1: Verilog2001,
61-
5: Verilog2005,
62-
1995: Verilog95,
63-
2001: Verilog2001,
64-
2005: Verilog2005,
65-
"Any": Any,
66-
"95": Verilog95,
67-
"01": Verilog2001,
68-
"05": Verilog2005,
69-
"1995": Verilog95,
70-
"2001": Verilog2001,
71-
"2005": Verilog2005,
72-
}
73-
74-
def __init__(self, *_):
75-
"""Patch the embedded MAP dictionary"""
76-
for k, v in self.__class__.__VERSION_MAPPINGS__.items():
77-
if (not isinstance(v, self.__class__)) and (v == self.value):
78-
self.__class__.__VERSION_MAPPINGS__[k] = self
79-
80-
@classmethod
81-
def Parse(cls, value):
82-
try:
83-
return cls.__VERSION_MAPPINGS__[value]
84-
except KeyError:
85-
ValueError("Value '{0!s}' cannot be parsed to member of {1}.".format(value, cls.__name__))
86-
87-
def __lt__(self, other):
88-
return self.value < other.value
89-
90-
def __le__(self, other):
91-
return self.value <= other.value
92-
93-
def __gt__(self, other):
94-
return self.value > other.value
95-
96-
def __ge__(self, other):
97-
return self.value >= other.value
98-
99-
def __ne__(self, other):
100-
return self.value != other.value
101-
102-
def __eq__(self, other):
103-
if (self is self.__class__.Any) or (other is self.__class__.Any):
104-
return True
105-
else:
106-
return self.value == other.value
107-
108-
def __str__(self):
109-
return "Verilog'" + str(self.value)[-2:]
110-
111-
def __repr__(self):
112-
return str(self.value)
47+
__version__ = "0.4.0"
11348

11449

11550
@export
11651
@unique
11752
class SystemVerilogVersion(Enum):
11853
Any = -1
54+
55+
Verilog95 = 95
56+
Verilog2001 = 1
57+
Verilog2005 = 5
58+
11959
SystemVerilog2005 = 2005
12060
SystemVerilog2009 = 2009
12161
SystemVerilog2012 = 2012
12262
SystemVerilog2017 = 2017
12363

12464
__VERSION_MAPPINGS__: Dict[Union[int, str], Enum] = {
125-
5: SystemVerilog2005,
65+
-1: Any,
66+
95: Verilog95,
67+
1: Verilog2001,
68+
5: Verilog2005,
69+
# 5: SystemVerilog2005, # prefer Verilog on numbers below 2000
12670
9: SystemVerilog2009,
12771
12: SystemVerilog2012,
12872
17: SystemVerilog2017,
73+
1995: Verilog95,
74+
2001: Verilog2001,
75+
# 2005: Verilog2005, # prefer SystemVerilog on numbers above 2000
12976
2005: SystemVerilog2005,
13077
2009: SystemVerilog2009,
13178
2012: SystemVerilog2012,
13279
2017: SystemVerilog2017,
13380
"Any": Any,
134-
"05": SystemVerilog2005,
81+
"95": Verilog95,
82+
"01": Verilog2001,
83+
"05": Verilog2005,
84+
# "05": SystemVerilog2005, # prefer Verilog on numbers below 2000
13585
"09": SystemVerilog2009,
13686
"12": SystemVerilog2012,
13787
"17": SystemVerilog2017,
88+
"1995": Verilog95,
89+
"2001": Verilog2001,
90+
# "2005": Verilog2005, # prefer SystemVerilog on numbers above 2000
13891
"2005": SystemVerilog2005,
13992
"2009": SystemVerilog2009,
14093
"2012": SystemVerilog2012,
@@ -148,35 +101,43 @@ def __init__(self, *_):
148101
self.__class__.__VERSION_MAPPINGS__[k] = self
149102

150103
@classmethod
151-
def Parse(cls, value):
104+
def Parse(cls, value: Union[int, str]) -> "SystemVerilogVersion":
152105
try:
153106
return cls.__VERSION_MAPPINGS__[value]
154107
except KeyError:
155-
ValueError("Value '{0!s}' cannot be parsed to member of {1}.".format(value, cls.__name__))
108+
raise ValueError("Value '{0!s}' cannot be parsed to member of {1}.".format(value, cls.__name__))
156109

157-
def __lt__(self, other):
110+
def __lt__(self, other) -> bool:
158111
return self.value < other.value
159112

160-
def __le__(self, other):
113+
def __le__(self, other) -> bool:
161114
return self.value <= other.value
162115

163-
def __gt__(self, other):
116+
def __gt__(self, other) -> bool:
164117
return self.value > other.value
165118

166-
def __ge__(self, other):
119+
def __ge__(self, other) -> bool:
167120
return self.value >= other.value
168121

169-
def __ne__(self, other):
122+
def __ne__(self, other) -> bool:
170123
return self.value != other.value
171124

172-
def __eq__(self, other):
125+
def __eq__(self, other) -> bool:
173126
if (self is self.__class__.Any) or (other is self.__class__.Any):
174127
return True
175128
else:
176129
return self.value == other.value
177130

178-
def __str__(self):
179-
return "SV'" + str(self.value)[-2:]
131+
def __str__(self) -> str:
132+
if self.value == -1:
133+
return "SV'Any"
134+
elif self.value < self.SystemVerilog2005.value:
135+
return "Verilog'" + str(self.value)[-2:]
136+
else:
137+
return "SV'" + str(self.value)[-2:]
180138

181-
def __repr__(self):
182-
return str(self.value)
139+
def __repr__(self) -> str:
140+
if self.value == -1:
141+
return "Any"
142+
else:
143+
return str(self.value)

‎tests/unit/Instantiate.py

Lines changed: 131 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -29,9 +29,9 @@
2929
# ==================================================================================================================== #
3030
#
3131
"""Instantiation tests for the language model."""
32-
from unittest import TestCase
32+
from unittest import TestCase
3333

34-
from pySVModel import VerilogVersion, SystemVerilogVersion
34+
from pySVModel import SystemVerilogVersion
3535

3636

3737
if __name__ == "__main__": # pragma: no cover
@@ -40,13 +40,135 @@
4040
exit(1)
4141

4242

43-
class Instantiate(TestCase):
44-
def test_VerilogVersion(self):
45-
version = VerilogVersion.Parse("95")
43+
class SVVersion(TestCase):
44+
def test_Any(self):
45+
versions = (
46+
SystemVerilogVersion.Parse(-1),
47+
SystemVerilogVersion.Parse("Any"),
48+
)
4649

47-
self.assertIsNotNone(version)
50+
for version in versions:
51+
self.assertIs(SystemVerilogVersion.Any, version)
4852

49-
def test_SystemVerilogVersion(self):
50-
version = SystemVerilogVersion.Parse("2017")
53+
print()
54+
print(version)
55+
print(version.value)
5156

52-
self.assertIsNotNone(version)
57+
def test_V1995(self):
58+
versions = (
59+
SystemVerilogVersion.Parse(95),
60+
SystemVerilogVersion.Parse(1995),
61+
SystemVerilogVersion.Parse("95"),
62+
SystemVerilogVersion.Parse("1995"),
63+
)
64+
65+
for version in versions:
66+
self.assertIs(SystemVerilogVersion.Verilog95, version)
67+
68+
print()
69+
print(version)
70+
print(version.value)
71+
72+
def test_V2001(self):
73+
versions = (
74+
SystemVerilogVersion.Parse(1),
75+
SystemVerilogVersion.Parse(2001),
76+
SystemVerilogVersion.Parse("01"),
77+
SystemVerilogVersion.Parse("2001"),
78+
)
79+
80+
for version in versions:
81+
self.assertIs(SystemVerilogVersion.Verilog2001, version)
82+
83+
print()
84+
print(version)
85+
print(version.value)
86+
87+
def test_V2005(self):
88+
versions = (
89+
SystemVerilogVersion.Parse(5),
90+
# SystemVerilogVersion.Parse(2005),
91+
SystemVerilogVersion.Parse("05"),
92+
# SystemVerilogVersion.Parse("2005"),
93+
)
94+
95+
for version in versions:
96+
self.assertIs(SystemVerilogVersion.Verilog2005, version)
97+
98+
print()
99+
print(version)
100+
print(version.value)
101+
102+
def test_SV2005(self):
103+
versions = (
104+
# SystemVerilogVersion.Parse(5),
105+
SystemVerilogVersion.Parse(2005),
106+
# SystemVerilogVersion.Parse("05"),
107+
SystemVerilogVersion.Parse("2005"),
108+
)
109+
110+
for version in versions:
111+
self.assertIs(SystemVerilogVersion.SystemVerilog2005, version)
112+
113+
print()
114+
print(version)
115+
print(version.value)
116+
117+
def test_SV2009(self):
118+
versions = (
119+
SystemVerilogVersion.Parse(9),
120+
SystemVerilogVersion.Parse(2009),
121+
SystemVerilogVersion.Parse("09"),
122+
SystemVerilogVersion.Parse("2009"),
123+
)
124+
125+
for version in versions:
126+
self.assertIs(SystemVerilogVersion.SystemVerilog2009, version)
127+
128+
print()
129+
print(version)
130+
print(version.value)
131+
132+
def test_SV2012(self):
133+
versions = (
134+
SystemVerilogVersion.Parse(12),
135+
SystemVerilogVersion.Parse(2012),
136+
SystemVerilogVersion.Parse("12"),
137+
SystemVerilogVersion.Parse("2012"),
138+
)
139+
140+
for version in versions:
141+
self.assertIs(SystemVerilogVersion.SystemVerilog2012, version)
142+
143+
print()
144+
print(version)
145+
print(version.value)
146+
147+
def test_SV2017(self):
148+
versions = (
149+
SystemVerilogVersion.Parse(17),
150+
SystemVerilogVersion.Parse(2017),
151+
SystemVerilogVersion.Parse("17"),
152+
SystemVerilogVersion.Parse("2017"),
153+
)
154+
155+
for version in versions:
156+
self.assertIs(SystemVerilogVersion.SystemVerilog2017, version)
157+
158+
print()
159+
print(version)
160+
print(version.value)
161+
162+
def test_IntError(self):
163+
with self.assertRaises(ValueError):
164+
_ = SystemVerilogVersion.Parse(0)
165+
166+
with self.assertRaises(ValueError):
167+
_ = SystemVerilogVersion.Parse(13)
168+
169+
def test_StrError(self):
170+
with self.assertRaises(ValueError):
171+
_ = SystemVerilogVersion.Parse("0")
172+
173+
with self.assertRaises(ValueError):
174+
_ = SystemVerilogVersion.Parse("13")

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