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Serwb: Add s6serdes
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‎README.md

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@@ -31,7 +31,7 @@ design flow by generating the verilog rtl that you will use as a standard core.
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-----------
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SerWB:
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- Wishbone over 3 LVDS I/Os (high speed) or 3 Single-Ended I/Os (low speed).
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- Artix7, Kintex7, Virtex7, Kintex Ultrascale high-speed PHYs.
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- Spartan6, Artix7, Kintex7, Virtex7, Kintex Ultrascale high-speed PHYs.
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- Vendor agnostic low-speed PHY.
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- 8B/10B, integrated gearbox.
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- Up to 1.25Gbps linerate / 32 bits @ 31.25Mhz user interface.

‎liteiclink/serwb/phy.py

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@@ -14,6 +14,7 @@
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from liteiclink.serwb.kuserdes import KUSerdes
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from liteiclink.serwb.s7serdes import S7Serdes
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from liteiclink.serwb.s6serdes import S6Serdes
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from liteiclink.serwb.efinixserdes import EfinixSerdes
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@@ -417,7 +418,18 @@ def __init__(self, device, pads, mode="master", init_timeout=2**16, clk="sys", c
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assert clk_ratio == "1:1"
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taps = 32
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self.serdes = S7Serdes(pads, mode, serdes_data_width)
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# Xilinx Spartan6
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elif device[:4] == "xc6s":
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# See Design Advisory for Spartan-6 Table2:
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# https://support.xilinx.com/s/article/38408?language=en_US
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max_taps = {188: 107, 200: 101, 266:72, 333: 54, 400: 43, 533: 28, 625: 22,
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667: 20, 800: 14, 945: 9, 1000: 8, 1050: 7, 1080: 6}
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sys_freq = 50 # todo: how to get that information?
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datarate = sys_freq * serdes_data_width
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datarate_in_max_taps = max((x for x in max_taps.keys() if x <= datarate))
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taps = max_taps[datarate_in_max_taps]
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self.serdes = S6Serdes(pads, mode, serdes_data_width)
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# Efinix Titanium.
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elif device[:2] == "Ti":

‎liteiclink/serwb/s6serdes.py

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@@ -0,0 +1,246 @@
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#
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# This file is part of LiteICLink.
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#
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# Copyright (c) 2023 Christian Klarhorst <cklarhor@techfak.uni-bielefeld.de>
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# Copyright (c) 2023 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.gen import *
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from litex.gen.genlib.misc import BitSlip, WaitTimer
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from litex.build.io import *
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from litex.soc.interconnect import stream
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from litex.soc.cores.code_8b10b import Encoder, Decoder
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from liteiclink.serwb.datapath import TXDatapath, RXDatapath
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# S6 SerDes Clocking -------------------------------------------------------------------------------
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class _S6SerdesClockingSimple(LiteXModule):
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def __init__(self, pads, mode="master"):
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self.refclk = Signal()
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# In Master mode, generate the clock with 180° phase shift so that Slave can use this clock
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# to sample data.
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if mode == "master":
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self.specials += DDROutput(0, 1, self.refclk)
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if hasattr(pads, "clk_p"):
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self.specials += DifferentialOutput(self.refclk, pads.clk_p, pads.clk_n)
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else:
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self.comb += pads.clk.eq(self.refclk)
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# In Slave mode, use the clock provided by Master.
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elif mode == "slave":
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if hasattr(pads, "clk_p"):
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self.specials += DifferentialInput(pads.clk_p, pads.clk_n, self.refclk)
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else:
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self.comb += self.refclk.eq(pads.clk)
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else: # Unknown mode
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raise ValueError
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class _S6SerdesClocking(LiteXModule):
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def __init__(self, pads, mode="master", data_width=4):
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assert data_width in [1,2,3,4] # valid serdes2 sdr rates
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self.refclk = Signal()
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self.serdes_clk = Signal()
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self.serdes_strobe = Signal()
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# In Master mode, generate the linerate/10 clock. Slave will re-multiply it.
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if mode == "master":
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self.converter = converter = stream.Converter(40, data_width)
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self.comb += [
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converter.sink.valid.eq(1),
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converter.source.ready.eq(1),
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converter.sink.data.eq(Replicate(Signal(10, reset=0b1111100000), 4)),
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]
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self.test = Signal()
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self.sync += [self.test.eq(~self.test)]
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self.specials += [
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Instance("OSERDES2",
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p_DATA_WIDTH = data_width,
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p_DATA_RATE_OQ = "SDR",
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p_DATA_RATE_OT = "SDR",
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p_SERDES_MODE = "None",
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p_OUTPUT_MODE = "SINGLE_ENDED",
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i_OCE = 1,
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i_IOCE = ClockSignal("strobe"),
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i_RST = 0,
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i_CLK0 = ClockSignal(f"sys{data_width}x"),
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i_CLK1 = 0,
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i_CLKDIV = ClockSignal("sys"),
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**{f"i_D{i+1}" : converter.source.data[i] for i in range(data_width)},
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i_TRAIN = 0,
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i_TCE=0,
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i_SHIFTIN1=0,
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i_SHIFTIN2=0,
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i_SHIFTIN3=0,
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i_SHIFTIN4=0,
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o_OQ = self.refclk,
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)
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]
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if hasattr(pads, "clk_p"):
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self.specials += DifferentialOutput(self.refclk, pads.clk_p, pads.clk_n)
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else:
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self.comb += self.refclk.eq(pads.clk)
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# In Slave mode, multiply the clock provided by Master with a PLL/MMCM.
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elif mode == "slave":
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if hasattr(pads, "clk_p"):
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self.specials += DifferentialInput(pads.clk_p, pads.clk_n, self.refclk)
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else:
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self.comb += self.refclk.eq(pads.clk)
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# S6 SerDes TX -------------------------------------------------------------------------------------
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class _S6SerdesTX(LiteXModule):
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def __init__(self, pads, data_width=4):
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assert data_width in [1,2,3,4] # valid serdes2 sdr rates
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# Control
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self.idle = idle = Signal()
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self.comma = comma = Signal()
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# Datapath
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self.sink = sink = stream.Endpoint([("data", 32)])
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self.datapath = datapath = TXDatapath(data_width)
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self.comb += [
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sink.connect(datapath.sink),
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datapath.source.ready.eq(1),
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datapath.idle.eq(idle),
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datapath.comma.eq(comma)
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]
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# Data output
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self.data = data = Signal(data_width)
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data_serialized = Signal()
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self.comb += data.eq(datapath.source.data)
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self.specials += [
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Instance("OSERDES2",
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p_DATA_WIDTH = data_width,
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p_DATA_RATE_OQ = "SDR",
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p_DATA_RATE_OT = "SDR",
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p_SERDES_MODE = "NONE",
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p_OUTPUT_MODE = "SINGLE_ENDED",
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i_OCE = 1,
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i_IOCE = ClockSignal("strobe"),
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i_RST = 0,
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i_CLK0 = ClockSignal(f"sys{data_width}x"),
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i_CLK1 = 0,
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i_CLKDIV = ClockSignal("sys"),
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**{f"i_D{i+1}" : data[i] for i in range(data_width)},
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i_TRAIN = 0,
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i_TCE=0,
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i_SHIFTIN1=0,
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i_SHIFTIN2=0,
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i_SHIFTIN3=0,
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i_SHIFTIN4=0,
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o_OQ = data_serialized,
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)
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]
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if hasattr(pads, "tx_p"):
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self.specials += DifferentialOutput(data_serialized, pads.tx_p, pads.tx_n)
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else:
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self.comb += pads.tx.eq(data_serialized)
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# S6 SerDes RX -------------------------------------------------------------------------------------
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class _S6SerdesRX(LiteXModule):
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def __init__(self, pads, data_width=4):
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assert data_width in [1,2,3,4] # valid serdes2 sdr rates
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# Control
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self.delay_rst = delay_rst = Signal()
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self.delay_inc = delay_inc = Signal()
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self.shift_inc = shift_inc = Signal()
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# Status
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self.idle = idle = Signal()
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self.comma = comma = Signal()
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# Datapath
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self.source = source = stream.Endpoint([("data", 32)])
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_shift = Signal(max=data_width)
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self.sync += If(self.shift_inc, _shift.eq(_shift + 1))
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# Data input
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data_nodelay = Signal()
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data_delayed = Signal()
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self.data = data = Signal(data_width)
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if hasattr(pads, "rx_p"):
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self.specials += DifferentialInput(pads.rx_p, pads.rx_n, data_nodelay)
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else:
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self.comb += data_nodelay.eq(pads.rx)
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self.specials += [
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Instance("IODELAY2",
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p_DELAY_SRC = "IDATAIN",
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p_DATA_RATE = "SDR",
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p_IDELAY_TYPE = "VARIABLE_FROM_ZERO",
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p_IDELAY_VALUE = 0,
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p_IDELAY2_VALUE = 0,
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p_IDELAY_MODE = "NORMAL",
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p_ODELAY_VALUE = 0,
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p_COUNTER_WRAPAROUND = "STAY_AT_LIMIT",
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p_SERDES_MODE = "NONE",
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i_T = 1,
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i_ODATAIN = 0,
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i_CAL = ResetSignal("sys"), # calibrate once on reset
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i_CLK = ClockSignal("sys"),
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i_IOCLK0 = ClockSignal(f"sys{data_width}x"),
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i_IOCLK1 = 0,
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i_RST = delay_rst,
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i_CE = delay_inc,
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i_INC = 1,
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i_IDATAIN = data_nodelay,
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o_DATAOUT = data_delayed,
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),
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Instance("ISERDES2",
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p_BITSLIP_ENABLE = 1,
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p_DATA_WIDTH = data_width,
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p_DATA_RATE = "SDR",
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p_SERDES_MODE = "NONE",
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p_INTERFACE_TYPE = "RETIMED",
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i_CLK0 = ClockSignal(f"sys{data_width}x"),
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i_CLK1 = 0,
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i_CLKDIV = ClockSignal("sys"),
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i_CE0 = 1,
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i_BITSLIP = shift_inc,
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i_D = data_delayed,
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i_RST = ResetSignal("sys"),
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i_IOCE = ClockSignal("strobe"),
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i_SHIFTIN=0,
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**{f"o_Q{i+1}" : data[i] for i in range(data_width)},
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)
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]
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# Datapath
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self.datapath = datapath = RXDatapath(data_width)
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self.comb += [
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datapath.sink.valid.eq(1),
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datapath.sink.data.eq(data),
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datapath.shift_inc.eq(self.shift_inc & (_shift == data_width-1)),
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datapath.source.connect(source),
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idle.eq(datapath.idle),
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comma.eq(datapath.comma)
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]
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# S6 SerDes ----------------------------------------------------------------------------------------
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@ResetInserter()
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class S6Serdes(LiteXModule):
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def __init__(self, pads, mode="master", data_width=4, simple_clk=True):
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if simple_clk:
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self.clocking = _S6SerdesClockingSimple(pads, mode)
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else:
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self.clocking = _S6SerdesClocking(pads, mode, data_width)
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self.tx = _S6SerdesTX(pads, data_width)
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self.rx = _S6SerdesRX(pads, data_width)

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