esynr3z corsair Discussions
Discussions
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You must be logged in to vote Add AHB interface
kind: featureNew feature or request of enhancement scope: hw generatorsRelated to HDL generators -
You must be logged in to vote Avalon master read fails
kind: bugSomething isn't working scope: hw generatorsRelated to HDL generators -
You must be logged in to vote Verilog build failed when using multistring description
kind: bugSomething isn't working scope: register modelRelated to register model structure and representation -
You must be logged in to vote c-headers: struct and bit field layout are implementation defined...
kind: featureNew feature or request of enhancement scope: sw generatorsRelated to software headers/sources generation -
You must be logged in to vote Addressing mode support
kind: featureNew feature or request of enhancement scope: register modelRelated to register model structure and representation -
You must be logged in to vote Enumeration types support
kind: featureNew feature or request of enhancement scope: register modelRelated to register model structure and representation -
You must be logged in to vote Interrupt support
kind: featureNew feature or request of enhancement scope: archRelated to internal architecture of the code -
You must be logged in to vote Memory interface support
kind: featureNew feature or request of enhancement scope: register modelRelated to register model structure and representation -
You must be logged in to vote Acess mode 'roc' can miss a latch
kind: bugSomething isn't working scope: register modelRelated to register model structure and representation scope: hw generatorsRelated to HDL generators -
You must be logged in to vote Optional timeout on reads and writes
kind: featureNew feature or request of enhancement scope: hw generatorsRelated to HDL generators -
You must be logged in to vote Confusing terminology: MSB & LSB vs Offset & Width
scope: register modelRelated to register model structure and representation kind: refactoringRewriting existing code without new features being introduced -
You must be logged in to vote Add informative header to all auto-generated files
scope: documentationRelated to project documentation kind: featureNew feature or request of enhancement scope: hw generatorsRelated to HDL generators scope: sw generatorsRelated to software headers/sources generation scope: doc generatorsRelated to Markdown/Asciidoc/etc. generators -
You must be logged in to vote Add generator for reStructuredText
kind: featureNew feature or request of enhancement scope: doc generatorsRelated to Markdown/Asciidoc/etc. generators -
You must be logged in to vote Add generator for CMSIS SVD
kind: featureNew feature or request of enhancement scope: sw generatorsRelated to software headers/sources generation -
You must be logged in to vote Return explicit error on access violations
kind: featureNew feature or request of enhancement scope: hw generatorsRelated to HDL generators -
You must be logged in to vote Add option to override csrconfig values via cli
kind: featureNew feature or request of enhancement scope: cliRelated to CLI and configuration parsing -
You must be logged in to vote Prove that generated Verilog/VHDL is equivalent
kind: featureNew feature or request of enhancement scope: hw generatorsRelated to HDL generators scope: testsRelated to project testing -
You must be logged in to vote Add wishbone b3
kind: featureNew feature or request of enhancement scope: hw generatorsRelated to HDL generators -
You must be logged in to vote Add wishbone B4 interface
kind: featureNew feature or request of enhancement scope: hw generatorsRelated to HDL generators
