Updated shift register primitives

Author: Frédéric REQUIN

SRL16E.v

@@ -10,6 +10,10 @@
 //
 
 module SRL16E
+#(
+    parameter [15:0] INIT = 16'h0,
+    parameter  [0:0] IS_CLK_INVERTED = 1'b0
+)
 (
     // Clock
     input  wire CLK,
@@ -22,7 +26,6 @@ module SRL16E
     // Data out
     output wire Q
 );
-    parameter [15:0] INIT = 16'h0000;
 
     wire  [3:0] _w_addr = { A3, A2, A1, A0 };
 
@@ -35,12 +38,24 @@ module SRL16E
     end
 
     // Shifter logic
-    always @(posedge CLK) begin : SHIFTER_16B
-    
-        if (CE) begin
-            _r_srl <= { _r_srl[14:0], D };
+    generate
+        if (IS_CLK_INVERTED) begin : GEN_CLK_NEG
+            always @(negedge CLK) begin : SHIFTER_16B
+            
+                if (CE) begin
+                    _r_srl <= { _r_srl[14:0], D };
+                end
+            end
         end
-    end
+        else begin : GEN_CLK_POS
+            always @(posedge CLK) begin : SHIFTER_16B
+            
+                if (CE) begin
+                    _r_srl <= { _r_srl[14:0], D };
+                end
+            end
+        end
+    endgenerate
 
     // Data out
     assign Q = _r_srl[_w_addr];

SRL32E.v

@@ -10,6 +10,10 @@
 //
 
 module SRL32E
+#(
+    parameter [31:0] INIT = 32'h0,
+    parameter  [0:0] IS_CLK_INVERTED = 1'b0
+)
 (
     // Clock
     input  wire       CLK,
@@ -22,8 +26,6 @@ module SRL32E
     // Data out
     output wire       Q
 );
-    parameter [31:0] INIT = 32'h00000000;
-    parameter  [0:0] IS_CLK_INVERTED = 1'b0;
 
     // 32-bit shift register
     reg [31:0] _r_srl;
@@ -36,14 +38,14 @@ module SRL32E
     // Shifter logic
     generate
         if (IS_CLK_INVERTED) begin : GEN_CLK_NEG
-            always @(negedge CLK) begin
+            always @(negedge CLK) begin : SHIFTER_32B
                 if (CE) begin
                     _r_srl <= { _r_srl[30:0], D };
                 end
             end
         end
         else begin : GEN_CLK_POS
-            always @(posedge CLK) begin
+            always @(posedge CLK) begin : SHIFTER_32B
                 if (CE) begin
                     _r_srl <= { _r_srl[30:0], D };
                 end

SRLC16E.v

@@ -10,6 +10,10 @@
 //
 
 module SRLC16E
+#(
+    parameter [15:0] INIT = 16'h0,
+    parameter  [0:0] IS_CLK_INVERTED = 1'b0
+)
 (
     // Clock
     input  wire       CLK,
@@ -24,8 +28,6 @@ module SRLC16E
     // Cascading data out
     output wire       Q15
 );
-    parameter [15:0] INIT = 16'h0000;
-    parameter  [0:0] IS_CLK_INVERTED = 1'b0;
 
     // 32-bit shift register
     reg  [15:0] _r_srl;
@@ -41,14 +43,16 @@ module SRLC16E
     // Shifter logic
     generate
         if (IS_CLK_INVERTED) begin : GEN_CLK_NEG
-            always @(negedge CLK) begin
+            always @(negedge CLK) begin : SHIFTER_16B
+            
                 if (CE) begin
                     _r_srl <= { _r_srl[14:0], D };
                 end
             end
         end
         else begin : GEN_CLK_POS
-            always @(posedge CLK) begin
+            always @(posedge CLK) begin : SHIFTER_16B
+            
                 if (CE) begin
                     _r_srl <= { _r_srl[14:0], D };
                 end

SRLC32E.v

@@ -10,6 +10,10 @@
 //
 
 module SRLC32E
+#(
+    parameter [31:0] INIT = 32'h0,
+    parameter  [0:0] IS_CLK_INVERTED = 1'b0
+)
 (
     // Clock
     input  wire       CLK,
@@ -24,7 +28,6 @@ module SRLC32E
     // Cascading data out
     output wire       Q31
 );
-    parameter [31:0] INIT = 32'h00000000;
 
     // 32-bit shift register
     reg  [31:0] _r_srl;
@@ -35,12 +38,24 @@ module SRLC32E
     end
 
     // Shifter logic
-    always @(posedge CLK) begin : SHIFTER_32B
-    
-        if (CE) begin
-            _r_srl <= { _r_srl[30:0], D };
+    generate
+        if (IS_CLK_INVERTED) begin : GEN_CLK_NEG
+            always @(negedge CLK) begin : SHIFTER_32B
+            
+                if (CE) begin
+                    _r_srl <= { _r_srl[30:0], D };
+                end
+            end
         end
-    end
+        else begin : GEN_CLK_POS
+            always @(posedge CLK) begin : SHIFTER_32B
+            
+                if (CE) begin
+                    _r_srl <= { _r_srl[30:0], D };
+                end
+            end
+        end
+    endgenerate
 
     // Data out
     assign Q   = _r_srl[A];