Pipelined TMDS encoder

[steve-m]

I'm using the IP core in my project (hsdaoh-fpga), and was looking to improve the performance on the lower end devices of the Tang Nano series (especially Tang Nano 9K due to the speed grade of the FPGA).

The TMDS encoder caused the most timing issues, so I adapted an existing pipelined TMDS encoder and added the video/data guard symbols and TERC4 to be compatible with the existing encoder. I'm getting quite a timing and performance improvement, allowing much higher pixel clocks on the Nano 9K.

So if anyone needs a higher resolution or better timing, you can give it a try:
https://github.com/steve-m/hsdaoh-fpga/blob/master/common/hdmi/tmds_channel.v

The only difference is the additional reset input, otherwise it can be used as a drop-in replacement.

[xolod79]

Hi Steve! Great job. How do you think this solution is applicable to other manufacturers' FPGAs?
I also adapted hdl-util/hdmi to work on FPGAs without LVDS output support, using DDR.
#47
#25 (comment)

[steve-m]

How do you think this solution is applicable to other manufacturers' FPGAs?

As there is nothing vendor specific, it should work out of the box on other FPGAs.