Location of General purpose registers (GPRs) in SRV32

[taruns07]

Hey folks,
So, I was going through the SRV32 microarchitecture as detailed on: https://hackmd.io/@sysprog/S1Udn1Xtt#srv32MIT-Simple-3-stage-pipeline-RISC-V-processor. Based on my understanding of RTL code, the register read occurs in the execute stage, and the register write takes place in the writeback stage. In the block diagram of the above link, the location of GPRs is in the writeback stage. However, this leads to a slight confusion.

Consider an instruction "add r1, r2, r3". The registers r2 and r3 need to be read before the addition operation takes place in the ALU. However, if the registers are present in the writeback stage (which is present after the ALU), how can they be read before the execution? To the best of my understanding, the GPRs will be present before the ALU, either in the IF/ID or EX stage. Please let me know if my understanding is correct in this aspect.