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Merge branch 'main' into cir_complex_deref_expr
2 parents dd7792b + 61051cf commit 7d363a8

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17 files changed

+488
-93
lines changed

17 files changed

+488
-93
lines changed

‎clang-tools-extra/unittests/CMakeLists.txt

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,4 +11,5 @@ add_subdirectory(clang-doc)
1111
add_subdirectory(clang-include-fixer)
1212
add_subdirectory(clang-move)
1313
add_subdirectory(clang-query)
14-
add_subdirectory(clang-tidy)
14+
# Workaround https://github.com/llvm/clangir/issues/1836
15+
# add_subdirectory(clang-tidy)

‎clang/include/clang/CIR/Dialect/IR/CIROps.td

Lines changed: 4 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -3010,31 +3010,22 @@ def CIR_ExtractMemberOp : CIR_Op<"extract_member", [Pure]> {
30103010
```
30113011
}];
30123012

3013-
let arguments = (ins CIRRecordType:$record, IndexAttr:$index_attr);
3013+
let arguments = (ins CIRRecordType:$record, I64Attr:$index);
30143014
let results = (outs CIR_AnyType:$result);
30153015

30163016
let assemblyFormat = [{
3017-
$record `[` $index_attr `]` attr-dict
3017+
$record `[` $index `]` attr-dict
30183018
`:` qualified(type($record)) `->` qualified(type($result))
30193019
}];
30203020

30213021
let builders = [
3022-
OpBuilder<(ins "mlir::Type":$type, "mlir::Value":$record, "uint64_t":$index), [{
3023-
mlir::APInt fieldIdx(64, index);
3024-
build($_builder, $_state, type, record, fieldIdx);
3025-
}]>,
30263022
OpBuilder<(ins "mlir::Value":$record, "uint64_t":$index), [{
30273023
auto recordTy = mlir::cast<cir::RecordType>(record.getType());
30283024
mlir::Type memberTy = recordTy.getMembers()[index];
30293025
build($_builder, $_state, memberTy, record, index);
30303026
}]>
30313027
];
30323028

3033-
let extraClassDeclaration = [{
3034-
/// Get the index of the record member being accessed.
3035-
uint64_t getIndex() { return getIndexAttr().getZExtValue(); }
3036-
}];
3037-
30383029
let hasVerifier = 1;
30393030
}
30403031

@@ -3075,25 +3066,12 @@ def CIR_InsertMemberOp : CIR_Op<"insert_member", [
30753066
```
30763067
}];
30773068

3078-
let arguments = (ins CIRRecordType:$record, IndexAttr:$index_attr,
3069+
let arguments = (ins CIRRecordType:$record, I64Attr:$index,
30793070
CIR_AnyType:$value);
30803071
let results = (outs CIRRecordType:$result);
30813072

3082-
let builders = [
3083-
OpBuilder<(ins "mlir::Value":$record, "uint64_t":$index,
3084-
"mlir::Value":$value), [{
3085-
mlir::APInt fieldIdx(64, index);
3086-
build($_builder, $_state, record, fieldIdx, value);
3087-
}]>
3088-
];
3089-
3090-
let extraClassDeclaration = [{
3091-
/// Get the index of the record member being accessed.
3092-
uint64_t getIndex() { return getIndexAttr().getZExtValue(); }
3093-
}];
3094-
30953073
let assemblyFormat = [{
3096-
$record `[` $index_attr `]` `,` $value attr-dict
3074+
$record `[` $index `]` `,` $value attr-dict
30973075
`:` qualified(type($record)) `,` qualified(type($value))
30983076
}];
30993077

‎clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp

Lines changed: 89 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -725,8 +725,95 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned BuiltinID,
725725
case X86::BI__builtin_ia32_gathersiv8di:
726726
case X86::BI__builtin_ia32_gathersiv16si:
727727
case X86::BI__builtin_ia32_gatherdiv8di:
728-
case X86::BI__builtin_ia32_gatherdiv16si:
729-
llvm_unreachable("gather3div2df NYI");
728+
case X86::BI__builtin_ia32_gatherdiv16si: {
729+
StringRef intrinsicName;
730+
switch (BuiltinID) {
731+
default:
732+
llvm_unreachable("Unexpected builtin");
733+
case X86::BI__builtin_ia32_gather3div2df:
734+
intrinsicName = "x86.avx512.mask.gather3div2.df";
735+
break;
736+
case X86::BI__builtin_ia32_gather3div2di:
737+
intrinsicName = "x86.avx512.mask.gather3div2.di";
738+
break;
739+
case X86::BI__builtin_ia32_gather3div4df:
740+
intrinsicName = "x86.avx512.mask.gather3div4.df";
741+
break;
742+
case X86::BI__builtin_ia32_gather3div4di:
743+
intrinsicName = "x86.avx512.mask.gather3div4.di";
744+
break;
745+
case X86::BI__builtin_ia32_gather3div4sf:
746+
intrinsicName = "x86.avx512.mask.gather3div4.sf";
747+
break;
748+
case X86::BI__builtin_ia32_gather3div4si:
749+
intrinsicName = "x86.avx512.mask.gather3div4.si";
750+
break;
751+
case X86::BI__builtin_ia32_gather3div8sf:
752+
intrinsicName = "x86.avx512.mask.gather3div8.sf";
753+
break;
754+
case X86::BI__builtin_ia32_gather3div8si:
755+
intrinsicName = "x86.avx512.mask.gather3div8.si";
756+
break;
757+
case X86::BI__builtin_ia32_gather3siv2df:
758+
intrinsicName = "x86.avx512.mask.gather3siv2.df";
759+
break;
760+
case X86::BI__builtin_ia32_gather3siv2di:
761+
intrinsicName = "x86.avx512.mask.gather3siv2.di";
762+
break;
763+
case X86::BI__builtin_ia32_gather3siv4df:
764+
intrinsicName = "x86.avx512.mask.gather3siv4.df";
765+
break;
766+
case X86::BI__builtin_ia32_gather3siv4di:
767+
intrinsicName = "x86.avx512.mask.gather3siv4.di";
768+
break;
769+
case X86::BI__builtin_ia32_gather3siv4sf:
770+
intrinsicName = "x86.avx512.mask.gather3siv4.sf";
771+
break;
772+
case X86::BI__builtin_ia32_gather3siv4si:
773+
intrinsicName = "x86.avx512.mask.gather3siv4.si";
774+
break;
775+
case X86::BI__builtin_ia32_gather3siv8sf:
776+
intrinsicName = "x86.avx512.mask.gather3siv8.sf";
777+
break;
778+
case X86::BI__builtin_ia32_gather3siv8si:
779+
intrinsicName = "x86.avx512.mask.gather3siv8.si";
780+
break;
781+
case X86::BI__builtin_ia32_gathersiv8df:
782+
intrinsicName = "x86.avx512.mask.gather.dpd.512";
783+
break;
784+
case X86::BI__builtin_ia32_gathersiv16sf:
785+
intrinsicName = "x86.avx512.mask.gather.dps.512";
786+
break;
787+
case X86::BI__builtin_ia32_gatherdiv8df:
788+
intrinsicName = "x86.avx512.mask.gather.qpd.512";
789+
break;
790+
case X86::BI__builtin_ia32_gatherdiv16sf:
791+
intrinsicName = "x86.avx512.mask.gather.qps.512";
792+
break;
793+
case X86::BI__builtin_ia32_gathersiv8di:
794+
intrinsicName = "x86.avx512.mask.gather.dpq.512";
795+
break;
796+
case X86::BI__builtin_ia32_gathersiv16si:
797+
intrinsicName = "x86.avx512.mask.gather.dpi.512";
798+
break;
799+
case X86::BI__builtin_ia32_gatherdiv8di:
800+
intrinsicName = "x86.avx512.mask.gather.qpq.512";
801+
break;
802+
case X86::BI__builtin_ia32_gatherdiv16si:
803+
intrinsicName = "x86.avx512.mask.gather.qpi.512";
804+
break;
805+
}
806+
807+
unsigned minElts =
808+
std::min(cast<cir::VectorType>(Ops[0].getType()).getSize(),
809+
cast<cir::VectorType>(Ops[2].getType()).getSize());
810+
Ops[3] = getMaskVecValue(*this, Ops[3], minElts, getLoc(E->getExprLoc()));
811+
return builder
812+
.create<cir::LLVMIntrinsicCallOp>(
813+
getLoc(E->getExprLoc()), builder.getStringAttr(intrinsicName.str()),
814+
convertType(E->getType()), Ops)
815+
.getResult();
816+
}
730817
case X86::BI__builtin_ia32_scattersiv8df:
731818
case X86::BI__builtin_ia32_scattersiv16sf:
732819
case X86::BI__builtin_ia32_scatterdiv8df:

‎clang/lib/CIR/CodeGen/CIRGenCall.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -723,8 +723,12 @@ RValue CIRGenFunction::emitCall(const CIRGenFunctionInfo &CallInfo,
723723

724724
return RValue::get(Results[0]);
725725
}
726-
default:
727-
llvm_unreachable("NYI");
726+
case cir::TEK_Complex: {
727+
mlir::ResultRange results = theCall->getOpResults();
728+
assert(!results.empty() &&
729+
"Expected at least one result for complex rvalue");
730+
return RValue::getComplex(results[0]);
731+
}
728732
}
729733
}();
730734

‎clang/lib/CIR/CodeGen/CIRGenClass.cpp

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -795,24 +795,21 @@ void CIRGenFunction::initializeVTablePointer(mlir::Location loc,
795795
}
796796

797797
// Apply the offsets.
798-
Address VTableField = LoadCXXThisAddress();
798+
Address ClassAddr = LoadCXXThisAddress();
799799
if (!NonVirtualOffset.isZero() || VirtualOffset) {
800-
VTableField = ApplyNonVirtualAndVirtualOffset(
801-
loc, *this, VTableField, NonVirtualOffset, VirtualOffset,
800+
ClassAddr = ApplyNonVirtualAndVirtualOffset(
801+
loc, *this, ClassAddr, NonVirtualOffset, VirtualOffset,
802802
Vptr.VTableClass, Vptr.NearestVBase, BaseValueTy);
803803
}
804804

805805
// Finally, store the address point. Use the same CIR types as the field.
806806
//
807807
// vtable field is derived from `this` pointer, therefore they should be in
808808
// the same addr space.
809-
// TODO(cir): We should be using cir.get_vptr rather than a bitcast to get
810-
// the vptr field, but the call to ApplyNonVirtualAndVirtualOffset
811-
// will also need to be adjusted. That should probably be using
812-
// cir.base_class_addr.
813809
assert(!cir::MissingFeatures::addressSpace());
814-
VTableField = builder.createElementBitCast(loc, VTableField,
815-
VTableAddressPoint.getType());
810+
auto VTablePtr = builder.create<cir::VTableGetVPtrOp>(
811+
loc, builder.getPtrToVPtrType(), ClassAddr.getPointer());
812+
Address VTableField = Address(VTablePtr, ClassAddr.getAlignment());
816813
auto storeOp = builder.createStore(loc, VTableAddressPoint, VTableField);
817814
TBAAAccessInfo TBAAInfo =
818815
CGM.getTBAAVTablePtrAccessInfo(VTableAddressPoint.getType());

‎clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -174,9 +174,13 @@ class ComplexExprEmitter : public StmtVisitor<ComplexExprEmitter, mlir::Value> {
174174
Scope.ForceCleanup({&V});
175175
return V;
176176
}
177+
177178
mlir::Value VisitCXXScalarValueInitExpr(CXXScalarValueInitExpr *E) {
178-
llvm_unreachable("NYI");
179+
mlir::Location loc = CGF.getLoc(E->getExprLoc());
180+
mlir::Type complexTy = CGF.convertType(E->getType());
181+
return Builder.getNullValue(complexTy, loc);
179182
}
183+
180184
mlir::Value VisitImplicitValueInitExpr(ImplicitValueInitExpr *E) {
181185
llvm_unreachable("NYI");
182186
}

‎clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2054,16 +2054,18 @@ mlir::Value ScalarExprEmitter::VisitReal(const UnaryOperator *E) {
20542054

20552055
Expr *Op = E->getSubExpr();
20562056
if (Op->getType()->isAnyComplexType()) {
2057+
mlir::Location Loc = CGF.getLoc(E->getExprLoc());
2058+
20572059
// If it's an l-value, load through the appropriate subobject l-value.
20582060
// Note that we have to ask E because Op might be an l-value that
20592061
// this won't work for, e.g. an Obj-C property.
20602062
if (E->isGLValue()) {
2061-
mlir::Location Loc = CGF.getLoc(E->getExprLoc());
20622063
mlir::Value Complex = CGF.emitComplexExpr(Op);
20632064
return CGF.builder.createComplexReal(Loc, Complex);
20642065
}
2066+
20652067
// Otherwise, calculate and project.
2066-
llvm_unreachable("NYI");
2068+
return Builder.createComplexReal(Loc, CGF.emitComplexExpr(Op));
20672069
}
20682070

20692071
return Visit(Op);

‎clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -993,7 +993,8 @@ mlir::Value CIRGenItaniumCXXABI::getVTableAddressPointInStructorWithVTT(
993993
VTTPtr = CGF.getBuilder().createVTTAddrPoint(Loc, VTTPtr.getType(), VTTPtr,
994994
VirtualPointerIndex);
995995
// And load the address point from the VTT.
996-
return CGF.getBuilder().createAlignedLoad(Loc, CGF.VoidPtrTy, VTTPtr,
996+
auto VPtrType = cir::VPtrType::get(CGF.getBuilder().getContext());
997+
return CGF.getBuilder().createAlignedLoad(Loc, VPtrType, VTTPtr,
997998
CGF.getPointerAlign());
998999
}
9991000

‎clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

Lines changed: 25 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -731,8 +731,9 @@ mlir::Value CirAttrToValue::visitCirAttr(cir::GlobalViewAttr globalAttr) {
731731
}
732732
auto resTy = addrOp.getType();
733733
auto eltTy = converter->convertType(sourceType);
734-
addrOp = rewriter.create<mlir::LLVM::GEPOp>(loc, resTy, eltTy, addrOp,
735-
indices, mlir::LLVM::GEPNoWrapFlags::inbounds);
734+
addrOp = rewriter.create<mlir::LLVM::GEPOp>(
735+
loc, resTy, eltTy, addrOp, indices,
736+
mlir::LLVM::GEPNoWrapFlags::inbounds);
736737
}
737738

738739
if (auto intTy = mlir::dyn_cast<cir::IntType>(globalAttr.getType())) {
@@ -1205,8 +1206,9 @@ mlir::LogicalResult CIRToLLVMVTTAddrPointOpLowering::matchAndRewrite(
12051206
offsets.push_back(0);
12061207
offsets.push_back(adaptor.getOffset());
12071208
}
1208-
rewriter.replaceOpWithNewOp<mlir::LLVM::GEPOp>(op, resultType, eltType,
1209-
llvmAddr, offsets, mlir::LLVM::GEPNoWrapFlags::inbounds);
1209+
rewriter.replaceOpWithNewOp<mlir::LLVM::GEPOp>(
1210+
op, resultType, eltType, llvmAddr, offsets,
1211+
mlir::LLVM::GEPNoWrapFlags::inbounds);
12101212
return mlir::success();
12111213
}
12121214

@@ -1903,9 +1905,18 @@ mlir::LogicalResult CIRToLLVMConstantOpLowering::matchAndRewrite(
19031905
typeConverter->convertType(op.getType()),
19041906
mlir::cast<cir::FPAttr>(op.getValue()).getValue());
19051907
} else if (auto complexTy = mlir::dyn_cast<cir::ComplexType>(op.getType())) {
1908+
mlir::Type complexElemTy = complexTy.getElementType();
1909+
mlir::Type complexElemLLVMTy = typeConverter->convertType(complexElemTy);
1910+
1911+
if (auto zeroInitAttr = mlir::dyn_cast<cir::ZeroAttr>(op.getValue())) {
1912+
mlir::TypedAttr zeroAttr = rewriter.getZeroAttr(complexElemLLVMTy);
1913+
mlir::ArrayAttr array = rewriter.getArrayAttr({zeroAttr, zeroAttr});
1914+
rewriter.replaceOpWithNewOp<mlir::LLVM::ConstantOp>(
1915+
op, getTypeConverter()->convertType(op.getType()), array);
1916+
return mlir::success();
1917+
}
1918+
19061919
auto complexAttr = mlir::cast<cir::ComplexAttr>(op.getValue());
1907-
auto complexElemTy = complexTy.getElementType();
1908-
auto complexElemLLVMTy = typeConverter->convertType(complexElemTy);
19091920

19101921
mlir::Attribute components[2];
19111922
if (mlir::isa<cir::IntType>(complexElemTy)) {
@@ -3881,8 +3892,9 @@ mlir::LogicalResult CIRToLLVMVTableAddrPointOpLowering::matchAndRewrite(
38813892
op.getAddressPointAttr().getOffset()};
38823893

38833894
assert(eltType && "Shouldn't ever be missing an eltType here");
3884-
rewriter.replaceOpWithNewOp<mlir::LLVM::GEPOp>(op, targetType, eltType,
3885-
symAddr, offsets, mlir::LLVM::GEPNoWrapFlags::inbounds);
3895+
rewriter.replaceOpWithNewOp<mlir::LLVM::GEPOp>(
3896+
op, targetType, eltType, symAddr, offsets,
3897+
mlir::LLVM::GEPNoWrapFlags::inbounds);
38863898

38873899
return mlir::success();
38883900
}
@@ -3908,7 +3920,8 @@ mlir::LogicalResult CIRToLLVMVTableGetVirtualFnAddrOpLowering::matchAndRewrite(
39083920
llvm::SmallVector<mlir::LLVM::GEPArg> offsets =
39093921
llvm::SmallVector<mlir::LLVM::GEPArg>{op.getIndex()};
39103922
rewriter.replaceOpWithNewOp<mlir::LLVM::GEPOp>(
3911-
op, targetType, eltType, adaptor.getVptr(), offsets, mlir::LLVM::GEPNoWrapFlags::inbounds);
3923+
op, targetType, eltType, adaptor.getVptr(), offsets,
3924+
mlir::LLVM::GEPNoWrapFlags::inbounds);
39123925
return mlir::success();
39133926
}
39143927

@@ -4000,7 +4013,9 @@ mlir::LogicalResult CIRToLLVMInlineAsmOpLowering::matchAndRewrite(
40004013
op, llResTy, llvmOperands, op.getAsmStringAttr(), op.getConstraintsAttr(),
40014014
op.getSideEffectsAttr(),
40024015
/*is_align_stack*/ mlir::UnitAttr(),
4003-
/*tail_call_kind*/ mlir::LLVM::TailCallKindAttr::get(getContext(), mlir::LLVM::tailcallkind::TailCallKind::None),
4016+
/*tail_call_kind*/
4017+
mlir::LLVM::TailCallKindAttr::get(
4018+
getContext(), mlir::LLVM::tailcallkind::TailCallKind::None),
40044019
mlir::LLVM::AsmDialectAttr::get(getContext(), llDialect),
40054020
rewriter.getArrayAttr(opAttrs));
40064021

‎clang/test/CIR/CodeGen/OpenCL/spir-calling-conv.cl

Lines changed: 2 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,24 +1,16 @@
11
// RUN: %clang_cc1 -fclangir %s -O0 -triple "spirv64-unknown-unknown" -emit-cir -o %t.cir
22
// RUN: FileCheck %s --input-file=%t.cir --check-prefix=CIR
3-
// RUN-DISABLE: %clang_cc1 -fclangir %s -O0 -triple "spirv64-unknown-unknown" -emit-llvm -fno-clangir-call-conv-lowering -o %t.ll
4-
// RUN-DISABLE: FileCheck %s --input-file=%t.ll --check-prefix=LLVM
3+
// RUN: %clang_cc1 -fclangir %s -O0 -triple "spirv64-unknown-unknown" -emit-llvm -fno-clangir-call-conv-lowering -o %t.ll
4+
// RUN: FileCheck %s --input-file=%t.ll --check-prefix=LLVM
55

66
// CIR: cir.func {{.*}}@get_dummy_id{{.*}} cc(spir_function)
77
// LLVM-DAG: declare{{.*}} spir_func i32 @get_dummy_id(
88
int get_dummy_id(int D);
99

10-
// CIR: cir.func {{.*}}@bar{{.*}} cc(spir_kernel)
11-
// LLVM-DAG: declare{{.*}} spir_kernel void @bar(
12-
kernel void bar(global int *A);
13-
1410
// CIR: cir.func {{.*}}@foo{{.*}} cc(spir_kernel)
1511
// LLVM-DAG: define{{.*}} spir_kernel void @foo(
1612
kernel void foo(global int *A) {
1713
int id = get_dummy_id(0);
1814
// CIR: %{{[0-9]+}} = cir.call @get_dummy_id(%2) : (!s32i) -> !s32i cc(spir_function)
1915
// LLVM: %{{[a-z0-9_]+}} = call spir_func i32 @get_dummy_id(
20-
A[id] = id;
21-
bar(A);
22-
// CIR: cir.call @bar(%8) : (!cir.ptr<!s32i, addrspace(offload_global)>) -> () cc(spir_kernel)
23-
// LLVM: call spir_kernel void @bar(ptr addrspace(1)
2416
}

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