Fxp support (#15)

* Starting to lay down some work

* First pass at FXP no testing yet

* Fixing bugs and adding unit tests

* Adding more unit tests

* Have bitfile parsing cast correctly so FXP_Register contains correct values

* Lots of changes Read is working correctly

* Bug fixes

* Pep 8 fixes

* comments

* merge with master

* A few comment updates

* Removing string based implementation

Now both read and write will calculate the read and write values using
the calculated delta.  This as a response to the review. In doing so I
was able to remove the fixedPointHelper, the only thing left in that
file was the warn, which I moved to a method of session._FXPRegister

I updated the tests to now work with the correct implementation my next
commit will include a test clean up

* Unit test clean -up

* Refactor overflow bit

Rather than its own seperate property overflow status is now read as a
tuple and written to as a tuple for a FXP register with overflow
enabled.
Unit tests again all post, required some refactoring

* Increase precision to not have rounding for larger integer words

* Bitfile changes

* Fix bug in reading 64 bit FXP with overflow

automated hardware tests now all work.

* Make FxpRegister inherit from Register not ArrayRegister

* Did not mean to commit these

* Comments

* Flake 8 Fixes

removing check for w503 that flake 8 seems to think
foo(5 + 6 +
7 + 8)
is better than
foo(5 + 6
+ 7 + 8)
Even though Pep 8 says otherwise

* Pep 8

* Fix 3.x builds

* 3.x Does not support error.message

Removing the custom input text. Users must look at documentation now

* Responding to reviews

* Small fixes for reviews

* Remove new line

* Spelling

Author: mgumble

.travis.yml

@@ -8,6 +8,6 @@ install:
   - "pip install flake8"
   - "pip install -r requirements.txt"
 before_script:
-  - "flake8 nifpga --ignore=E501"
+  - "flake8 nifpga --ignore=E501,W503 "
 script:
   - "nosetests --with-doctest"

nifpga/bitfile.py

@@ -28,7 +28,7 @@ def __init__(self, filepath, parse_contents=False):
         self._base_address_on_device = int(nifpga.find("BaseAddressOnDevice").text)
         self._registers = {}
         for reg_xml in tree.find("VI").find("RegisterList"):
-            reg = Register(reg_xml)
+            reg = self.create_register(reg_xml)
             if reg.datatype is not None:
                 assert reg.name not in self._registers, \
                     "One or more registers have the same name '%s', this is not supported" % reg.name
@@ -71,6 +71,19 @@ def base_address_on_device(self):
         """
         return self._base_address_on_device
 
+    def create_register(self, xml):
+        if self._is_register_fxp(xml):
+            return FxpRegister(xml)
+        else:
+            return Register(xml)
+
+    def _is_register_fxp(self, reg_xml):
+        datatype = reg_xml.find("Datatype")
+        for child in datatype.getchildren():
+            if str(DataType.Fxp).lower() not in child.tag.lower():
+                return False
+        return True
+
 
 class Register(object):
     def __init__(self, reg_xml):
@@ -171,6 +184,40 @@ def __str__(self):
                 "\tOffset: %d\n" % self._offset)
 
 
+class FxpRegister(Register):
+    """
+    A fixed point control or indicator from the front panel of the top level
+    FPGA VI.
+    """
+    def __init__(self, reg_xml):
+        super(FxpRegister, self).__init__(reg_xml)
+        datatype = reg_xml.find("Datatype")
+        fxp_xml = datatype.find("FXP")
+        self._signed = True if fxp_xml.find("Signed").text.lower() == 'true' else False
+        self._overflow = True if fxp_xml.find("IncludeOverflowStatus").text.lower() == 'true' else False
+        self._word_length = int(fxp_xml.find("WordLength").text)
+        self._integer_word_length = int(fxp_xml.find("IntegerWordLength").text)
+
+    def __len__(self):
+        return 1
+
+    @property
+    def signed(self):
+        return self._signed
+
+    @property
+    def word_length(self):
+        return self._word_length
+
+    @property
+    def integer_word_length(self):
+        return self._integer_word_length
+
+    @property
+    def overflow(self):
+        return self._overflow
+
+
 class Fifo(object):
     def __init__(self, channel_xml):
         self._name = channel_xml.attrib["name"]

nifpga/nifpga.py

@@ -26,6 +26,7 @@ class DataType(Enum):
     U64 = 9
     Sgl = 10
     Dbl = 11
+    Fxp = 12
 
     def __str__(self):
         return self.name
@@ -44,6 +45,7 @@ def _return_ctype(self):
             DataType.U64: ctypes.c_uint64,
             DataType.Sgl: ctypes.c_float,
             DataType.Dbl: ctypes.c_double,
+            DataType.Fxp: ctypes.c_uint32,
         }
         return _datatype_ctype[self]
 
@@ -369,6 +371,8 @@ def __init__(self):
         ]  # list of function_infos
 
         for datatype in DataType:
+            if datatype == DataType.Fxp:
+                continue  # Fixed point does not have read write entry points.
             type_ctype = datatype._return_ctype()
             library_function_infos.extend([
                 LibraryFunctionInfo(
@@ -452,7 +456,6 @@ def __init__(self):
                         NamedArgtype("elements remaining", ctypes.POINTER(ctypes.c_size_t)),
                     ]),
             ])  # end of library_function_infos.extend() call
-
         for fifoPropertyType in FifoPropertyType:
             type_ctype = fifoPropertyType._return_ctype()
             library_function_infos.extend([
@@ -475,6 +478,7 @@ def __init__(self):
                         NamedArgtype("value", type_ctype),
                     ]),
             ])
+
         try:
             super(_NiFpga, self).__init__(library_name="NiFpga",
                                           library_function_infos=library_function_infos)