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1 file changed
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lines changedSubmodule core-v-verif updated 79 files
- bin/README.md+8
- bin/requirements.txt+2-2
- cv32e40p/sim/core/Makefile+1-1
- lib/cv_dv_utils/python/sim_cmd/README.md+32
- lib/cv_dv_utils/python/sim_cmd/compile.py+46
- lib/cv_dv_utils/python/sim_cmd/get_cmd.py+205
- lib/cv_dv_utils/python/sim_cmd/module1_template.yaml+26
- lib/cv_dv_utils/python/sim_cmd/module2_template.yaml+24
- lib/cv_dv_utils/python/sim_cmd/run_reg.py+102
- lib/cv_dv_utils/python/sim_cmd/run_test.py+51
- lib/cv_dv_utils/python/sim_cmd/top_questa_template.yaml+30
- lib/cv_dv_utils/python/sim_cmd/top_vcs_template.yaml+26
- lib/cv_dv_utils/uvm/generic_agent/README.md+17
- lib/cv_dv_utils/uvm/generic_agent/generic_agent.svh+6-4
- lib/cv_dv_utils/uvm/generic_agent/generic_driver.svh+4-19
- lib/cv_dv_utils/uvm/generic_agent/generic_monitor.svh+1-1
- lib/cv_dv_utils/uvm/generic_agent/generic_sequencer.svh+10-2
- lib/cv_dv_utils/uvm/generic_agent/generic_sequences.svh+8-3
- lib/cv_dv_utils/uvm/memory_partition/memory_partitions_cfg.svh+22-1
- lib/uvm_agents/uvma_axi5/example/README.md+18
- lib/uvm_agents/uvma_axi5/example/simu/cv_dv_utils.yaml+26
- lib/uvm_agents/uvma_axi5/example/simu/run.do+2
- lib/uvm_agents/uvma_axi5/example/simu/run_test.do+2
- lib/uvm_agents/uvma_axi5/example/simu/simulator_questa.yaml+32
- lib/uvm_agents/uvma_axi5/example/simu/simulator_vcs.yaml+31
- lib/uvm_agents/uvma_axi5/example/simu/uvma_axi5.yaml+31
- lib/uvm_agents/uvma_axi5/example/simu/wave.do+29
- lib/uvm_agents/uvma_axi5/example/sv/bp_virtual_sequence.svh+70
- lib/uvm_agents/uvma_axi5/example/sv/dut_cfg_c.svh+55
- lib/uvm_agents/uvma_axi5/example/sv/dut_env.sv+146
- lib/uvm_agents/uvma_axi5/example/sv/dut_env_axi_ohg.sv+151
- lib/uvm_agents/uvma_axi5/example/sv/dut_env_pkg.sv+36
- lib/uvm_agents/uvma_axi5/example/sv/mem_protocol_checker.sv+482
- lib/uvm_agents/uvma_axi5/example/test/base_test_c.svh+67
- lib/uvm_agents/uvma_axi5/example/test/bursty_test_c.svh+111
- lib/uvm_agents/uvma_axi5/example/test/test_pkg.sv+35
- lib/uvm_agents/uvma_axi5/example/top/run.do+1
- lib/uvm_agents/uvma_axi5/example/top/run_test.do+2
- lib/uvm_agents/uvma_axi5/example/top/top.sv+165
- lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_cfg.sv+4
- lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_tdefs.sv+1
- lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_utils.sv+3-2
- lib/uvm_agents/uvma_cvxif/src/comps/uvma_cvxif_drv.sv+44-5
- lib/uvm_agents/uvma_cvxif/src/obj/uvma_cvxif_cfg.sv+5-5
- lib/uvm_agents/uvma_cvxif/src/uvma_cvxif_assert.sv+15-19
- lib/uvm_agents/uvma_isacov/cov/uvma_isacov_cov_model.sv+253-49
- lib/uvm_agents/uvma_isacov/uvma_isacov_macros.sv+84-1
- lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_slv_seq.sv+3-3
- lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_sig_writer_seq.sv+2-2
- lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_1p2_assert.sv+18
- lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_assert.sv+61-31
- lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_macros.sv+1-1
- mk/TOOLCHAIN.md+1-1
- tools/vptool/vptool/vptool.yml+1-7
- vendor/patches/riscv/riscv-isa-sim/0037-make-zifencei-optional.patch+33
- vendor/patches/riscv/riscv-isa-sim/0042-fix-extension-reset.patch+12
- vendor/patches/riscv/riscv-isa-sim/0043-allow-unmapped-mem-access.patch+136
- vendor/patches/riscv/riscv-isa-sim/0044-cvxif-no-more-implicit-x10-dest-reg.patch+80
- vendor/patches/riscv/riscv-isa-sim/0044-don-t-optimize-decode-for-addi.patch+112
- vendor/patches/riscv/riscv-isa-sim/0045-spike-disasm-don-t-optimaze-jump-instructions.patch+72
- vendor/riscv/riscv-isa-sim/customext/cvxif.cc+309-50
- vendor/riscv/riscv-isa-sim/disasm/disasm.cc+10-7
- vendor/riscv/riscv-isa-sim/disasm/isa_parser.cc+12-3
- vendor/riscv/riscv-isa-sim/fesvr/SimDTM.cc+1-1
- vendor/riscv/riscv-isa-sim/fesvr/fesvr_dpi.cc+2-2
- vendor/riscv/riscv-isa-sim/riscv/Proc.cc+22-3
- vendor/riscv/riscv-isa-sim/riscv/Proc.h+6
- vendor/riscv/riscv-isa-sim/riscv/cvxif.h+34-7
- vendor/riscv/riscv-isa-sim/riscv/cvxif_base.cc+4-6
- vendor/riscv/riscv-isa-sim/riscv/encoding.h+26
- vendor/riscv/riscv-isa-sim/riscv/extension.h+3
- vendor/riscv/riscv-isa-sim/riscv/insns/fence_i.h+1
- vendor/riscv/riscv-isa-sim/riscv/isa_parser.h+2
- vendor/riscv/riscv-isa-sim/riscv/mmu.cc+16-6
- vendor/riscv/riscv-isa-sim/riscv/mmu.h+4-1
- vendor/riscv/riscv-isa-sim/riscv/overlap_list.h+7
- vendor/riscv/riscv-isa-sim/riscv/processor.cc+7-3
- vendor/riscv/riscv-isa-sim/riscv/sim.cc+1-1
- vendor/riscv/riscv-isa-sim/spike_main/spike.cc+5
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