From a1d8f76df3375bbb4bf6372fc8cb6ecc874aec3e Mon Sep 17 00:00:00 2001 From: M4s Date: Tue, 29 Apr 2025 16:31:52 +0200 Subject: [PATCH 1/2] implementation cvu118 --- .gitignore | 5 + Makefile | 6 +- corev_apu/fpga/Makefile | 16 +- corev_apu/fpga/constraints/vcu118.xdc | 2175 ++------------- corev_apu/fpga/scripts/run.tcl | 10 +- corev_apu/fpga/src/ariane_xilinx.sv | 411 +-- corev_apu/fpga/src/vcu118.svh | 11 + corev_apu/fpga/vivado_pid1143288.str | 2450 +++++++++++++++++ corev_apu/fpga/vivado_pid1465060.str | 2193 +++++++++++++++ corev_apu/fpga/vivado_pid2437936.str | 1968 +++++++++++++ corev_apu/fpga/xilinx/ariane_xlnx_ip.yml | 18 +- .../xlnx_axi_dwidth_converter_512_64/Makefile | 2 + .../tcl/run.tcl | 17 + corev_apu/fpga/xilinx/xlnx_mig_ddr4/Makefile | 2 + .../fpga/xilinx/xlnx_mig_ddr4/tcl/run.tcl | 21 + 15 files changed, 6965 insertions(+), 2340 deletions(-) create mode 100644 corev_apu/fpga/vivado_pid1143288.str create mode 100644 corev_apu/fpga/vivado_pid1465060.str create mode 100644 corev_apu/fpga/vivado_pid2437936.str create mode 100644 corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_512_64/Makefile create mode 100644 corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_512_64/tcl/run.tcl create mode 100644 corev_apu/fpga/xilinx/xlnx_mig_ddr4/Makefile create mode 100644 corev_apu/fpga/xilinx/xlnx_mig_ddr4/tcl/run.tcl diff --git a/.gitignore b/.gitignore index 43896084e3..940a2865b0 100644 --- a/.gitignore +++ b/.gitignore @@ -52,3 +52,8 @@ Bender.lock # Both following lines are needed to list contents of ISA manual build dir. !/vendor/riscv/riscv-isa-manual/build/ !/vendor/riscv/riscv-isa-manual/build/* + + +#modif par moi +.venv +/corev_apu/fpga/ariane.* diff --git a/Makefile b/Makefile index ce2452c3e6..c7e4f636da 100644 --- a/Makefile +++ b/Makefile @@ -39,7 +39,7 @@ torture-logs := # custom elf bin to run with sim or sim-verilator elf_file ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv # board name for bitstream generation. Currently supported: kc705, genesys2, nexys_video -BOARD ?= genesys2 +BOARD ?= vcu118 ALTERA_BOARD ?= DK-DEV-AGF014E3ES ALTERA_FAMILY ?= "AGILEX" ALTERA_PART ?= AGFB014R24B2E2V @@ -86,6 +86,10 @@ else ifeq ($(BOARD), nexys_video) XILINX_PART := xc7a200tsbg484-1 XILINX_BOARD := digilentinc.com:nexys_video:part0:1.1 CLK_PERIOD_NS := 40 +else ifeq ($(BOARD), vcu118) + XILINX_PART := xcvu9p-flga2104-2L-e + XILINX_BOARD := xilinx.com:vcu118:part0:2.0 + CLK_PERIOD_NS := 20 else $(error Unknown board - please specify a supported FPGA board) endif diff --git a/corev_apu/fpga/Makefile b/corev_apu/fpga/Makefile index 678e224438..52a361aef9 100644 --- a/corev_apu/fpga/Makefile +++ b/corev_apu/fpga/Makefile @@ -1,5 +1,5 @@ VIVADO ?= vivado -VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl +VIVADOFLAGS ?= -nojournal -mode gui -source scripts/prologue.tcl work-dir := work-fpga bit := $(work-dir)/ariane_xilinx.bit @@ -12,7 +12,19 @@ ips := xlnx_axi_clock_converter.xci \ xlnx_axi_quad_spi.xci \ xlnx_axi_gpio.xci \ xlnx_clk_gen.xci \ - xlnx_mig_7_ddr3.xci + xlnx_mig_ddr4.xci \ + xlnx_axi_dwidth_converter_512_64.xci + +ips_standard := xlnx_axi_clock_converter.xci \ + xlnx_axi_dwidth_converter.xci \ + xlnx_axi_quad_spi.xci \ + xlnx_axi_gpio.xci \ + xlnx_clk_gen.xci + +ips_ddr3 := xlnx_mig_7_ddr3.xci + +ips_ddr4 := xlnx_mig_ddr4.xci \ + xlnx_axi_dwidth_converter_512_64.xci ips := $(addprefix $(work-dir)/, $(ips)) ips-target := $(join $(addsuffix /ip/, $(addprefix $(ip-dir)/, $(basename $(ips)))), $(ips)) diff --git a/corev_apu/fpga/constraints/vcu118.xdc b/corev_apu/fpga/constraints/vcu118.xdc index ea71aa8d25..88995f5a27 100644 --- a/corev_apu/fpga/constraints/vcu118.xdc +++ b/corev_apu/fpga/constraints/vcu118.xdc @@ -1,1990 +1,215 @@ ############################################################################ ### VCU118 Rev2.0 XDC 12/08/2017 ############################################################################ -# Buttons -set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS12} [get_ports cpu_reset] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T1U_N12_73 -set_property PULLDOWN true [get_ports cpu_reset] -# PCIe -set_false_path -from [get_ports sys_rst_n] -set_property PULLUP true [get_ports sys_rst_n] -set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_n] -set_property PACKAGE_PIN AM17 [get_ports sys_rst_n] -create_clock -name sys_clk -period 10 [get_ports sys_clk_p] -set_property -dict {PACKAGE_PIN AC9} [get_ports sys_clk_p] -set_property -dict {PACKAGE_PIN AC8} [get_ports sys_clk_n] +##general settings +# some constraints from the example design +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design] +set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property CONFIG_MODE BPI16 [current_design] + +##Reset +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS12} [get_ports cpu_reset] + +##Clocks +#250 MHz Systemclock 1 +set_property PACKAGE_PIN E12 [get_ports c0_sys_clk_p] +set_property PACKAGE_PIN D12 [get_ports c0_sys_clk_n] +set_property IOSTANDARD DIFF_SSTL12 [get_ports -filter NAME=~c0_sys_clk_*] +create_clock -period 4.000 [get_ports c0_sys_clk_p] + +##switches +#set_property PACKAGE_PIN B17 [get_ports {sw[0]}] +#set_property PACKAGE_PIN G16 [get_ports {sw[1]}] +#set_property PACKAGE_PIN J16 [get_ports {sw[2]}] +#set_property PACKAGE_PIN D21 [get_ports {sw[3]}] + +#set_property IOSTANDARD LVCMOS12 [get_ports -filter NAME=~sw*] +#set_false_path -from [get_ports -filter NAME=~sw*] + +##LEDs +#set_property PACKAGE_PIN AT32 [get_ports {led[0]}] +#set_property PACKAGE_PIN AV34 [get_ports {led[1]}] +#set_property PACKAGE_PIN AY30 [get_ports {led[2]}] +#set_property PACKAGE_PIN BB32 [get_ports {led[3]}] +#set_property PACKAGE_PIN BF32 [get_ports {led[4]}] +#set_property PACKAGE_PIN AV36 [get_ports {led[5]}] +#set_property PACKAGE_PIN AY35 [get_ports {led[6]}] +#set_property PACKAGE_PIN BA37 [get_ports {led[7]}] + +#set_property IOSTANDARD LVCMOS12 [get_ports -filter NAME=~led*] +#set_false_path -to [get_ports -filter NAME=~led*] # JTAG -set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVCMOS12} [get_ports tck] ; # PMOD1_0 -set_property -dict {PACKAGE_PIN M30 IOSTANDARD LVCMOS12} [get_ports tdi] ; # PMOD1_1 -set_property -dict {PACKAGE_PIN N30 IOSTANDARD LVCMOS12} [get_ports tdo] ; # PMOD1_2 -set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS12} [get_ports tms] ; # PMOD1_3 -set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS12} [get_ports trst_n] ;# PMOD1_4 +set_property -dict {PACKAGE_PIN AY13 IOSTANDARD LVCMOS18} [get_ports tck] +set_property -dict {PACKAGE_PIN AV11 IOSTANDARD LVCMOS18} [get_ports tdi] +set_property -dict {PACKAGE_PIN AW13 IOSTANDARD LVCMOS18} [get_ports tdo] +set_property -dict {PACKAGE_PIN AU11 IOSTANDARD LVCMOS18} [get_ports tms] +set_property -dict {PACKAGE_PIN AP13 IOSTANDARD LVCMOS18} [get_ports trst_n] + +# Contrainte pour connecter un port à la masse (GND) +set_property -dict { PACKAGE_PIN AN16 IOSTANDARD LVCMOS18 } [get_ports { gnd_jtag }] + +# Contrainte pour connecter un port à l'alimentation (VCC) +set_property -dict { PACKAGE_PIN AP16 IOSTANDARD LVCMOS18 } [get_ports { vcc_jtag }] +set_property -dict { PACKAGE_PIN AR13 IOSTANDARD LVCMOS18 } [get_ports { vcc_reset_jtag }] + # accept sub-optimal placement set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF_inst/O] -set_property -dict {PACKAGE_PIN AW25 IOSTANDARD LVCMOS18} [get_ports tx] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_64 -set_property -dict {PACKAGE_PIN BB21 IOSTANDARD LVCMOS18} [get_ports rx] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_64 -## SD Card **TODO(zarubaf)*** This is wrong for the VCU118 -set_property -dict {PACKAGE_PIN AY14 IOSTANDARD LVCMOS18} [get_ports spi_clk_o] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_47 -set_property -dict {PACKAGE_PIN AY15 IOSTANDARD LVCMOS18} [get_ports spi_clk_o_2] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_47 +#JTAG Clock +create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports tck] +set_input_jitter tck 1.000 + +#set JTAG reset as false path +set_false_path -from [get_ports trst_n] + + +#set DDR reset as false path +set_false_path -from [get_pins i_ddr/inst/div_clk_rst_r1_reg/C] + +#RAM Calibration +#set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] +#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] +#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] +#connect_debug_port dbg_hub/clk [get_nets clk_1] + +##SD CARD +set_property -dict {PACKAGE_PIN AV15 IOSTANDARD LVCMOS18} [get_ports spi_clk_o] +set_property -dict {PACKAGE_PIN AY14 IOSTANDARD LVCMOS18} [get_ports spi_ss] +set_property -dict {PACKAGE_PIN AW15 IOSTANDARD LVCMOS18} [get_ports spi_miso] +set_property -dict {PACKAGE_PIN AW15 IOSTANDARD LVCMOS18} [get_ports spi_miso] +set_property -dict {PACKAGE_PIN AY15 IOSTANDARD LVCMOS18} [get_ports spi_mosi] +#set_property IOSTANDARD LVCMOS18 [get_ports -filter NAME=~spi_*] + +#### UART +set_property -dict {PACKAGE_PIN AW25 IOSTANDARD LVCMOS18} [get_ports rx] +set_property -dict {PACKAGE_PIN BB21 IOSTANDARD LVCMOS18} [get_ports tx] + + + -set_property -dict {PACKAGE_PIN BF16 IOSTANDARD LVCMOS18} [get_ports spi_ss] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L2N_T0L_N3_FWE_FCS2_B_65 -set_property -dict {PACKAGE_PIN BF20 IOSTANDARD LVCMOS18} [get_ports spi_ss_2] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L1N_T0L_N1_DBC_RS1_65 +#set_property -dict {PACKAGE_PIN AV34 IOSTANDARD LVCMOS12 } [get_ports {c0_init_calib_complete}]; # LED0 +set_property PACKAGE_PIN E13 [get_ports c0_ddr4_act_n] +set_property PACKAGE_PIN D14 [get_ports {c0_ddr4_adr[0]}] +set_property PACKAGE_PIN C12 [get_ports {c0_ddr4_adr[10]}] +set_property PACKAGE_PIN B13 [get_ports {c0_ddr4_adr[11]}] +set_property PACKAGE_PIN C13 [get_ports {c0_ddr4_adr[12]}] +set_property PACKAGE_PIN D15 [get_ports {c0_ddr4_adr[13]}] +set_property PACKAGE_PIN H14 [get_ports {c0_ddr4_adr[14]}] +set_property PACKAGE_PIN H15 [get_ports {c0_ddr4_adr[15]}] +set_property PACKAGE_PIN F15 [get_ports {c0_ddr4_adr[16]}] +set_property PACKAGE_PIN B15 [get_ports {c0_ddr4_adr[1]}] +set_property PACKAGE_PIN B16 [get_ports {c0_ddr4_adr[2]}] +set_property PACKAGE_PIN C14 [get_ports {c0_ddr4_adr[3]}] +set_property PACKAGE_PIN C15 [get_ports {c0_ddr4_adr[4]}] +set_property PACKAGE_PIN A13 [get_ports {c0_ddr4_adr[5]}] +set_property PACKAGE_PIN A14 [get_ports {c0_ddr4_adr[6]}] +set_property PACKAGE_PIN A15 [get_ports {c0_ddr4_adr[7]}] +set_property PACKAGE_PIN A16 [get_ports {c0_ddr4_adr[8]}] +set_property PACKAGE_PIN B12 [get_ports {c0_ddr4_adr[9]}] +set_property PACKAGE_PIN G15 [get_ports {c0_ddr4_ba[0]}] +set_property PACKAGE_PIN G13 [get_ports {c0_ddr4_ba[1]}] +set_property PACKAGE_PIN H13 [get_ports {c0_ddr4_bg[0]}] +set_property PACKAGE_PIN F14 [get_ports {c0_ddr4_ck_t[0]}] +set_property PACKAGE_PIN E14 [get_ports {c0_ddr4_ck_c[0]}] +set_property PACKAGE_PIN A10 [get_ports {c0_ddr4_cke[0]}] +set_property PACKAGE_PIN F13 [get_ports {c0_ddr4_cs_n[0]}] +set_property PACKAGE_PIN G11 [get_ports {c0_ddr4_dm_dbi_n[0]}] +set_property PACKAGE_PIN R18 [get_ports {c0_ddr4_dm_dbi_n[1]}] +set_property PACKAGE_PIN K17 [get_ports {c0_ddr4_dm_dbi_n[2]}] +set_property PACKAGE_PIN G18 [get_ports {c0_ddr4_dm_dbi_n[3]}] +set_property PACKAGE_PIN B18 [get_ports {c0_ddr4_dm_dbi_n[4]}] +set_property PACKAGE_PIN P20 [get_ports {c0_ddr4_dm_dbi_n[5]}] +set_property PACKAGE_PIN L23 [get_ports {c0_ddr4_dm_dbi_n[6]}] +set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}] -set_property -dict {PACKAGE_PIN AM18 IOSTANDARD LVCMOS18} [get_ports spi_miso] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_D05_65 -set_property -dict {PACKAGE_PIN AM19 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_D04_65 -set_property -dict {PACKAGE_PIN AP20 IOSTANDARD LVCMOS18} [get_ports spi_miso_2] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21N_T3L_N5_AD8N_D07_65 -set_property -dict {PACKAGE_PIN AN20 IOSTANDARD LVCMOS18} [get_ports spi_mosi_2] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21P_T3L_N4_AD8P_D06_65 +set_property PACKAGE_PIN F11 [get_ports {c0_ddr4_dq[0]}] +set_property PACKAGE_PIN M18 [get_ports {c0_ddr4_dq[10]}] +set_property PACKAGE_PIN M17 [get_ports {c0_ddr4_dq[11]}] +set_property PACKAGE_PIN N19 [get_ports {c0_ddr4_dq[12]}] +set_property PACKAGE_PIN N18 [get_ports {c0_ddr4_dq[13]}] +set_property PACKAGE_PIN N17 [get_ports {c0_ddr4_dq[14]}] +set_property PACKAGE_PIN M16 [get_ports {c0_ddr4_dq[15]}] +set_property PACKAGE_PIN L16 [get_ports {c0_ddr4_dq[16]}] +set_property PACKAGE_PIN K16 [get_ports {c0_ddr4_dq[17]}] +set_property PACKAGE_PIN L18 [get_ports {c0_ddr4_dq[18]}] +set_property PACKAGE_PIN K18 [get_ports {c0_ddr4_dq[19]}] +set_property PACKAGE_PIN E11 [get_ports {c0_ddr4_dq[1]}] +set_property PACKAGE_PIN J17 [get_ports {c0_ddr4_dq[20]}] +set_property PACKAGE_PIN H17 [get_ports {c0_ddr4_dq[21]}] +set_property PACKAGE_PIN H19 [get_ports {c0_ddr4_dq[22]}] +set_property PACKAGE_PIN H18 [get_ports {c0_ddr4_dq[23]}] +set_property PACKAGE_PIN F19 [get_ports {c0_ddr4_dq[24]}] +set_property PACKAGE_PIN F18 [get_ports {c0_ddr4_dq[25]}] +set_property PACKAGE_PIN E19 [get_ports {c0_ddr4_dq[26]}] +set_property PACKAGE_PIN E18 [get_ports {c0_ddr4_dq[27]}] +set_property PACKAGE_PIN G20 [get_ports {c0_ddr4_dq[28]}] +set_property PACKAGE_PIN F20 [get_ports {c0_ddr4_dq[29]}] +set_property PACKAGE_PIN F10 [get_ports {c0_ddr4_dq[2]}] +set_property PACKAGE_PIN E17 [get_ports {c0_ddr4_dq[30]}] +set_property PACKAGE_PIN D16 [get_ports {c0_ddr4_dq[31]}] +set_property PACKAGE_PIN D17 [get_ports {c0_ddr4_dq[32]}] +set_property PACKAGE_PIN C17 [get_ports {c0_ddr4_dq[33]}] +set_property PACKAGE_PIN C19 [get_ports {c0_ddr4_dq[34]}] +set_property PACKAGE_PIN C18 [get_ports {c0_ddr4_dq[35]}] +set_property PACKAGE_PIN D20 [get_ports {c0_ddr4_dq[36]}] +set_property PACKAGE_PIN D19 [get_ports {c0_ddr4_dq[37]}] +set_property PACKAGE_PIN C20 [get_ports {c0_ddr4_dq[38]}] +set_property PACKAGE_PIN B20 [get_ports {c0_ddr4_dq[39]}] +set_property PACKAGE_PIN F9 [get_ports {c0_ddr4_dq[3]}] +set_property PACKAGE_PIN N23 [get_ports {c0_ddr4_dq[40]}] +set_property PACKAGE_PIN M23 [get_ports {c0_ddr4_dq[41]}] +set_property PACKAGE_PIN R21 [get_ports {c0_ddr4_dq[42]}] +set_property PACKAGE_PIN P21 [get_ports {c0_ddr4_dq[43]}] +set_property PACKAGE_PIN R22 [get_ports {c0_ddr4_dq[44]}] +set_property PACKAGE_PIN P22 [get_ports {c0_ddr4_dq[45]}] +set_property PACKAGE_PIN T23 [get_ports {c0_ddr4_dq[46]}] +set_property PACKAGE_PIN R23 [get_ports {c0_ddr4_dq[47]}] +set_property PACKAGE_PIN K24 [get_ports {c0_ddr4_dq[48]}] +set_property PACKAGE_PIN J24 [get_ports {c0_ddr4_dq[49]}] +set_property PACKAGE_PIN H12 [get_ports {c0_ddr4_dq[4]}] +set_property PACKAGE_PIN M21 [get_ports {c0_ddr4_dq[50]}] +set_property PACKAGE_PIN L21 [get_ports {c0_ddr4_dq[51]}] +set_property PACKAGE_PIN K21 [get_ports {c0_ddr4_dq[52]}] +set_property PACKAGE_PIN J21 [get_ports {c0_ddr4_dq[53]}] +set_property PACKAGE_PIN K22 [get_ports {c0_ddr4_dq[54]}] +set_property PACKAGE_PIN J22 [get_ports {c0_ddr4_dq[55]}] +set_property PACKAGE_PIN H23 [get_ports {c0_ddr4_dq[56]}] +set_property PACKAGE_PIN H22 [get_ports {c0_ddr4_dq[57]}] +set_property PACKAGE_PIN E23 [get_ports {c0_ddr4_dq[58]}] +set_property PACKAGE_PIN E22 [get_ports {c0_ddr4_dq[59]}] +set_property PACKAGE_PIN G12 [get_ports {c0_ddr4_dq[5]}] +set_property PACKAGE_PIN F21 [get_ports {c0_ddr4_dq[60]}] +set_property PACKAGE_PIN E21 [get_ports {c0_ddr4_dq[61]}] +set_property PACKAGE_PIN F24 [get_ports {c0_ddr4_dq[62]}] +set_property PACKAGE_PIN F23 [get_ports {c0_ddr4_dq[63]}] -# #Other net PACKAGE_PIN AE17 - DXN Bank 0 - DXN -# #Other net PACKAGE_PIN AE18 - DXP Bank 0 - DXP -# #Other net PACKAGE_PIN AD18 - GND Bank 0 - VREFP -# #Other net PACKAGE_PIN AC17 - GND Bank 0 - VREFN -# #Other net PACKAGE_PIN AC18 - SYSMON_VP Bank 0 - VP -# #Other net PACKAGE_PIN AD17 - SYSMON_VN Bank 0 - VN -# #Other net PACKAGE_PIN U10 - FPGA_M0 Bank 0 - M0_0 -# #Other net PACKAGE_PIN Y11 - FPGA_M1 Bank 0 - M1_0 -# #Other net PACKAGE_PIN AC12 - FPGA_INIT_B Bank 0 - INIT_B_0 -# #Other net PACKAGE_PIN W11 - FPGA_M2 Bank 0 - M2_0 -# #Other net PACKAGE_PIN AB11 - GND Bank 0 - RSVDGND -# #Other net PACKAGE_PIN AD12 - PUDC_B_PIN Bank 0 - PUDC_B_0 -# #Other net PACKAGE_PIN AG12 - POR_OVERRIDE_PIN Bank 0 - POR_OVERRIDE -# #Other net PACKAGE_PIN AE12 - FPGA_DONE Bank 0 - DONE_0 -# #Other net PACKAGE_PIN AH11 - FPGA_PROG_B Bank 0 - PROGRAM_B_0 -# #Other net PACKAGE_PIN AD13 - FPGA_TDO_FMC_TDI Bank 0 - TDO_0 -# #Other net PACKAGE_PIN AD15 - JTAG_TDI Bank 0 - TDI_0 -# #Other net PACKAGE_PIN AJ11 - QSPI0_CS_B Bank 0 - RDWR_FCS_B_0 -# #Other net PACKAGE_PIN AM11 - QSPI0_DQ2 Bank 0 - D02_0 -# #Other net PACKAGE_PIN AP11 - QSPI0_DQ0 Bank 0 - D00_MOSI_0 -# #Other net PACKAGE_PIN AL11 - QSPI0_DQ3 Bank 0 - D03_0 -# #Other net PACKAGE_PIN AN11 - QSPI0_DQ1 Bank 0 - D01_DIN_0 -# #Other net PACKAGE_PIN AF15 - JTAG_TMS Bank 0 - TMS_0 -# #Other net PACKAGE_PIN AF13 - QSPI_CCLK Bank 0 - CCLK_0 -# #Other net PACKAGE_PIN AE13 - JTAG_TCK Bank 0 - TCK_0 -# #Other net PACKAGE_PIN AT11 - FPGA_VBATT Bank 0 - VBATT -# set_property PACKAGE_PIN B25 [get_ports "RLD3_C3_72B_DM3"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM3"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_48 -# set_property PACKAGE_PIN C25 [get_ports "RLD3_C3_72B_DQ71"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ71"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_48 -# set_property PACKAGE_PIN D26 [get_ports "RLD3_C3_72B_DQ70"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ70"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_48 -# set_property PACKAGE_PIN D25 [get_ports "RLD3_C3_72B_DQ69"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ69"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_48 -# set_property PACKAGE_PIN A26 [get_ports "RLD3_C3_72B_DQ68"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ68"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_48 -# set_property PACKAGE_PIN B26 [get_ports "RLD3_C3_72B_DQ67"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ67"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_48 -# set_property PACKAGE_PIN B27 [get_ports "RLD3_C3_72B_DQ66"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ66"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_48 -# set_property PACKAGE_PIN C27 [get_ports "RLD3_C3_72B_DQ65"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ65"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_48 -# set_property PACKAGE_PIN A28 [get_ports "RLD3_C3_72B_DQ64"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ64"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_48 -# set_property PACKAGE_PIN B28 [get_ports "RLD3_C3_72B_DQ63"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ63"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_48 -# set_property PACKAGE_PIN C28 [get_ports "RLD3_C3_72B_QK7_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_48 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK7_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_48 -# set_property PACKAGE_PIN D27 [get_ports "RLD3_C3_72B_QK7_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_48 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK7_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_48 -# #set_property PACKAGE_PIN A25 [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T3U_N12_48 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T3U_N12_48 -# #set_property PACKAGE_PIN H25 [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T2U_N12_48 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T2U_N12_48 -# set_property PACKAGE_PIN F25 [get_ports "RLD3_C3_72B_QVLD3"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD3"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_48 -# set_property PACKAGE_PIN G25 [get_ports "RLD3_C3_72B_DQ62"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ62"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_48 -# set_property PACKAGE_PIN E27 [get_ports "RLD3_C3_72B_DQ61"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ61"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_48 -# set_property PACKAGE_PIN E26 [get_ports "RLD3_C3_72B_DQ60"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ60"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_48 -# set_property PACKAGE_PIN G28 [get_ports "RLD3_C3_72B_DQ59"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ59"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_48 -# set_property PACKAGE_PIN H28 [get_ports "RLD3_C3_72B_DQ58"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ58"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_48 -# set_property PACKAGE_PIN E28 [get_ports "RLD3_C3_72B_DQ57"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ57"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_48 -# set_property PACKAGE_PIN F28 [get_ports "RLD3_C3_72B_DQ56"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ56"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_48 -# set_property PACKAGE_PIN G27 [get_ports "RLD3_C3_72B_DQ55"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ55"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_48 -# set_property PACKAGE_PIN H27 [get_ports "RLD3_C3_72B_DQ54"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ54"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_48 -# set_property PACKAGE_PIN F26 [get_ports "RLD3_C3_72B_QK6_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_48 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK6_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_48 -# set_property PACKAGE_PIN G26 [get_ports "RLD3_C3_72B_QK6_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_48 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK6_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_48 -# set_property PACKAGE_PIN J27 [get_ports "RLD3_C3_72B_QVLD2"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD2"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_48 -# set_property PACKAGE_PIN K27 [get_ports "RLD3_C3_72B_DQ53"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ53"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_48 -# set_property PACKAGE_PIN J26 [get_ports "RLD3_C3_72B_DQ52"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ52"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_48 -# set_property PACKAGE_PIN K26 [get_ports "RLD3_C3_72B_DQ51"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ51"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_48 -# set_property PACKAGE_PIN L25 [get_ports "RLD3_C3_72B_DQ50"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ50"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_48 -# set_property PACKAGE_PIN L24 [get_ports "RLD3_C3_72B_DQ49"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ49"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_48 -# set_property PACKAGE_PIN K28 [get_ports "RLD3_C3_72B_DQ48"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ48"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_48 -# set_property PACKAGE_PIN L28 [get_ports "RLD3_C3_72B_DQ47"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ47"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_48 -# set_property PACKAGE_PIN L26 [get_ports "RLD3_C3_72B_DQ46"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ46"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_48 -# set_property PACKAGE_PIN M25 [get_ports "RLD3_C3_72B_DQ45"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ45"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_48 -# set_property PACKAGE_PIN M28 [get_ports "RLD3_C3_72B_QK5_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_48 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK5_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_48 -# set_property PACKAGE_PIN M27 [get_ports "RLD3_C3_72B_QK5_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_48 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK5_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_48 -# #set_property PACKAGE_PIN J25 [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T1U_N12_48 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T1U_N12_48 -# #set_property PACKAGE_PIN M26 [get_ports "VRP_48"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_48 -# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_48"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_48 -# set_property PACKAGE_PIN N24 [get_ports "RLD3_C3_72B_DM2"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM2"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_48 -# set_property PACKAGE_PIN P24 [get_ports "RLD3_C3_72B_DQ44"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ44"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_48 -# set_property PACKAGE_PIN N27 [get_ports "RLD3_C3_72B_DQ43"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ43"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_48 -# set_property PACKAGE_PIN P26 [get_ports "RLD3_C3_72B_DQ42"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ42"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_48 -# set_property PACKAGE_PIN N25 [get_ports "RLD3_C3_72B_DQ41"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ41"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_48 -# set_property PACKAGE_PIN P25 [get_ports "RLD3_C3_72B_DQ40"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ40"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_48 -# set_property PACKAGE_PIN P27 [get_ports "RLD3_C3_72B_DQ39"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ39"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_48 -# set_property PACKAGE_PIN R27 [get_ports "RLD3_C3_72B_DQ38"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ38"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_48 -# set_property PACKAGE_PIN R24 [get_ports "RLD3_C3_72B_DQ37"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ37"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_48 -# set_property PACKAGE_PIN T24 [get_ports "RLD3_C3_72B_DQ36"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_48 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ36"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_48 -# set_property PACKAGE_PIN R26 [get_ports "RLD3_C3_72B_QK4_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_48 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK4_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_48 -# set_property PACKAGE_PIN T26 [get_ports "RLD3_C3_72B_QK4_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_48 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK4_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_48 -# #Other net PACKAGE_PIN T25 - Bank 48 - VREF_48 -# set_property PACKAGE_PIN C29 [get_ports "RLD3_C3_72B_A1"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A1"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_47 -# set_property PACKAGE_PIN D29 [get_ports "RLD3_C3_72B_A2"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A2"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_47 -# set_property PACKAGE_PIN B30 [get_ports "RLD3_C3_72B_A3"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A3"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_47 -# set_property PACKAGE_PIN C30 [get_ports "RLD3_C3_72B_A4"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A4"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_47 -# set_property PACKAGE_PIN A31 [get_ports "RLD3_C3_72B_A5"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A5"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_47 -# set_property PACKAGE_PIN A30 [get_ports "RLD3_C3_72B_A6"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A6"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_47 -# set_property PACKAGE_PIN A33 [get_ports "RLD3_C3_72B_A7"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A7"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_47 -# set_property PACKAGE_PIN B33 [get_ports "RLD3_C3_72B_A8"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A8"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_47 -# set_property PACKAGE_PIN B32 [get_ports "RLD3_C3_72B_A9"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A9"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_47 -# set_property PACKAGE_PIN B31 [get_ports "RLD3_C3_72B_A10"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A10"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_47 -# set_property PACKAGE_PIN C33 [get_ports "RLD3_C3_72B_A11"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A11"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_47 -# set_property PACKAGE_PIN C32 [get_ports "RLD3_C3_72B_A12"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A12"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_47 -# set_property PACKAGE_PIN A29 [get_ports "RLD3_C3_72B_A0"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T3U_N12_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A0"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T3U_N12_47 -# set_property PACKAGE_PIN D30 [get_ports "RLD3_C3_72B_A13"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T2U_N12_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A13"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T2U_N12_47 -# set_property PACKAGE_PIN E29 [get_ports "RLD3_C3_72B_A14"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A14"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_47 -# set_property PACKAGE_PIN F29 [get_ports "RLD3_C3_72B_A15"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A15"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_47 -# set_property PACKAGE_PIN D32 [get_ports "RLD3_C3_72B_A16"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A16"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_47 -# set_property PACKAGE_PIN E32 [get_ports "RLD3_C3_72B_A17"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A17"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_47 -# set_property PACKAGE_PIN D31 [get_ports "RLD3_C3_72B_A18"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A18"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_47 -# set_property PACKAGE_PIN E31 [get_ports "RLD3_C3_72B_A19"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A19"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_47 -# set_property PACKAGE_PIN E33 [get_ports "RLD3_C3_72B_BA0"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA0"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_47 -# set_property PACKAGE_PIN F33 [get_ports "RLD3_C3_72B_BA1"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA1"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_47 -# set_property PACKAGE_PIN F30 [get_ports "RLD3_C3_72B_BA2"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA2"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_47 -# set_property PACKAGE_PIN G30 [get_ports "RLD3_C3_72B_BA3"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA3"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_47 -# set_property PACKAGE_PIN F31 [get_ports "SYSCLK1_300_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_47 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "SYSCLK1_300_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_47 -# set_property PACKAGE_PIN G31 [get_ports "SYSCLK1_300_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_47 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "SYSCLK1_300_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_47 -# set_property PACKAGE_PIN G32 [get_ports "USER_SI570_CLOCK_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_47 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_CLOCK_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_47 -# set_property PACKAGE_PIN H32 [get_ports "USER_SI570_CLOCK_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_47 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_CLOCK_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_47 -# set_property PACKAGE_PIN H30 [get_ports "RLD3_C3_72B_CK_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_47 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_CK_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_47 -# set_property PACKAGE_PIN H29 [get_ports "RLD3_C3_72B_CK_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_47 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_CK_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_47 -# set_property PACKAGE_PIN G33 [get_ports "RLD3_C3_72B_DK3_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_47 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK3_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_47 -# set_property PACKAGE_PIN H33 [get_ports "RLD3_C3_72B_DK3_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_47 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK3_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_47 -# set_property PACKAGE_PIN J30 [get_ports "RLD3_C3_72B_DK2_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_47 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK2_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_47 -# set_property PACKAGE_PIN J29 [get_ports "RLD3_C3_72B_DK2_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_47 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK2_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_47 -# set_property PACKAGE_PIN J32 [get_ports "RLD3_C3_72B_DK1_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_47 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK1_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_47 -# set_property PACKAGE_PIN K32 [get_ports "RLD3_C3_72B_DK1_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_47 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK1_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_47 -# set_property PACKAGE_PIN J31 [get_ports "RLD3_C3_72B_DK0_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_47 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK0_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_47 -# set_property PACKAGE_PIN K31 [get_ports "RLD3_C3_72B_DK0_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_47 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK0_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_47 -# set_property PACKAGE_PIN K29 [get_ports "RLD3_C3_72B_WE_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T1U_N12_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_WE_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T1U_N12_47 -# #set_property PACKAGE_PIN T29 [get_ports "VRP_47"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_47 -# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_47"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_47 -# set_property PACKAGE_PIN L30 [get_ports "RLD3_C3_72B_REF_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_REF_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_47 -# set_property PACKAGE_PIN L29 [get_ports "RLD3_C3_72B_RESET_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_47 -# set_property IOSTANDARD LVCMOS12 [get_ports "RLD3_C3_72B_RESET_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_47 -# set_property PACKAGE_PIN N29 [get_ports "RLD3_C3_72B_CS_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_CS_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_47 +set_property PACKAGE_PIN E9 [get_ports {c0_ddr4_dq[6]}] +set_property PACKAGE_PIN D9 [get_ports {c0_ddr4_dq[7]}] +set_property PACKAGE_PIN R19 [get_ports {c0_ddr4_dq[8]}] +set_property PACKAGE_PIN P19 [get_ports {c0_ddr4_dq[9]}] -# set_property PACKAGE_PIN R28 [get_ports "RLD3_C3_72B_A20"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_47 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A20"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_47 -# #Other net PACKAGE_PIN T28 - 43N2999 Bank 47 - VREF_47 -# set_property PACKAGE_PIN A35 [get_ports "RLD3_C3_72B_DM1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_46 -# set_property PACKAGE_PIN A34 [get_ports "RLD3_C3_72B_DQ35"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ35"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_46 -# set_property PACKAGE_PIN A36 [get_ports "RLD3_C3_72B_DQ34"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ34"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_46 -# set_property PACKAGE_PIN B35 [get_ports "RLD3_C3_72B_DQ33"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ33"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_46 -# set_property PACKAGE_PIN B37 [get_ports "RLD3_C3_72B_DQ32"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ32"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_46 -# set_property PACKAGE_PIN B36 [get_ports "RLD3_C3_72B_DQ31"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ31"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_46 -# set_property PACKAGE_PIN C34 [get_ports "RLD3_C3_72B_DQ30"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ30"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_46 -# set_property PACKAGE_PIN D34 [get_ports "RLD3_C3_72B_DQ29"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ29"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_46 -# set_property PACKAGE_PIN C35 [get_ports "RLD3_C3_72B_DQ28"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ28"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_46 -# set_property PACKAGE_PIN D35 [get_ports "RLD3_C3_72B_DQ27"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ27"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_46 -# set_property PACKAGE_PIN C37 [get_ports "RLD3_C3_72B_QK3_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_46 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK3_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_46 -# set_property PACKAGE_PIN D37 [get_ports "RLD3_C3_72B_QK3_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_46 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK3_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_46 -# #set_property PACKAGE_PIN D36 [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T3U_N12_46 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T3U_N12_46 -# #set_property PACKAGE_PIN C38 [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T2U_N12_46 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T2U_N12_46 -# set_property PACKAGE_PIN A38 [get_ports "RLD3_C3_72B_QVLD1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_46 -# set_property PACKAGE_PIN B38 [get_ports "RLD3_C3_72B_DQ26"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ26"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_46 -# set_property PACKAGE_PIN C40 [get_ports "RLD3_C3_72B_DQ25"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ25"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_46 -# set_property PACKAGE_PIN D40 [get_ports "RLD3_C3_72B_DQ24"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ24"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_46 -# set_property PACKAGE_PIN A40 [get_ports "RLD3_C3_72B_DQ23"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ23"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_46 -# set_property PACKAGE_PIN A39 [get_ports "RLD3_C3_72B_DQ22"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ22"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_46 -# set_property PACKAGE_PIN B40 [get_ports "RLD3_C3_72B_DQ21"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ21"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_46 -# set_property PACKAGE_PIN C39 [get_ports "RLD3_C3_72B_DQ20"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ20"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_46 -# set_property PACKAGE_PIN E38 [get_ports "RLD3_C3_72B_DQ19"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ19"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_46 -# set_property PACKAGE_PIN E37 [get_ports "RLD3_C3_72B_DQ18"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ18"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_46 -# set_property PACKAGE_PIN D39 [get_ports "RLD3_C3_72B_QK2_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_46 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK2_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_46 -# set_property PACKAGE_PIN E39 [get_ports "RLD3_C3_72B_QK2_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_46 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK2_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_46 -# set_property PACKAGE_PIN G37 [get_ports "RLD3_C3_72B_QVLD0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_46 -# set_property PACKAGE_PIN G36 [get_ports "RLD3_C3_72B_DQ17"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ17"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_46 -# set_property PACKAGE_PIN F36 [get_ports "RLD3_C3_72B_DQ16"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ16"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_46 -# set_property PACKAGE_PIN F35 [get_ports "RLD3_C3_72B_DQ15"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ15"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_46 -# set_property PACKAGE_PIN G35 [get_ports "RLD3_C3_72B_DQ14"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ14"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_46 -# set_property PACKAGE_PIN H34 [get_ports "RLD3_C3_72B_DQ13"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ13"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_46 -# set_property PACKAGE_PIN H37 [get_ports "RLD3_C3_72B_DQ12"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ12"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_46 -# set_property PACKAGE_PIN J36 [get_ports "RLD3_C3_72B_DQ11"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ11"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_46 -# set_property PACKAGE_PIN H35 [get_ports "RLD3_C3_72B_DQ10"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ10"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_46 -# set_property PACKAGE_PIN J35 [get_ports "RLD3_C3_72B_DQ9"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ9"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_46 -# set_property PACKAGE_PIN E34 [get_ports "RLD3_C3_72B_QK1_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_46 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK1_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_46 -# set_property PACKAGE_PIN F34 [get_ports "RLD3_C3_72B_QK1_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_46 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK1_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_46 -# #set_property PACKAGE_PIN E36 [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T1U_N12_46 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T1U_N12_46 -# #set_property PACKAGE_PIN K38 [get_ports "VRP_46"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_46 -# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_46"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_46 -# set_property PACKAGE_PIN F39 [get_ports "RLD3_C3_72B_DM0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_46 -# set_property PACKAGE_PIN F38 [get_ports "RLD3_C3_72B_DQ8"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ8"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_46 -# set_property PACKAGE_PIN J37 [get_ports "RLD3_C3_72B_DQ7"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ7"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_46 -# set_property PACKAGE_PIN K37 [get_ports "RLD3_C3_72B_DQ6"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ6"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_46 -# set_property PACKAGE_PIN G38 [get_ports "RLD3_C3_72B_DQ5"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ5"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_46 -# set_property PACKAGE_PIN H38 [get_ports "RLD3_C3_72B_DQ4"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ4"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_46 -# set_property PACKAGE_PIN F40 [get_ports "RLD3_C3_72B_DQ3"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ3"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_46 -# set_property PACKAGE_PIN G40 [get_ports "RLD3_C3_72B_DQ2"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ2"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_46 -# set_property PACKAGE_PIN H40 [get_ports "RLD3_C3_72B_DQ1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_46 -# set_property PACKAGE_PIN H39 [get_ports "RLD3_C3_72B_DQ0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_46 -# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_46 -# set_property PACKAGE_PIN J40 [get_ports "RLD3_C3_72B_QK0_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_46 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK0_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_46 -# set_property PACKAGE_PIN J39 [get_ports "RLD3_C3_72B_QK0_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_46 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK0_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_46 -# #Other net PACKAGE_PIN J34 - Bank 46 - VREF_46 -# set_property PACKAGE_PIN L35 [get_ports "FMCP_HSPC_LA21_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA21_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_45 -# set_property PACKAGE_PIN M35 [get_ports "FMCP_HSPC_LA21_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA21_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_45 -# set_property PACKAGE_PIN M32 [get_ports "FMCP_HSPC_LA20_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA20_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_45 -# set_property PACKAGE_PIN N32 [get_ports "FMCP_HSPC_LA20_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA20_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_45 -# set_property PACKAGE_PIN M33 [get_ports "FMCP_HSPC_LA19_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA19_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_45 -# set_property PACKAGE_PIN N33 [get_ports "FMCP_HSPC_LA19_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA19_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_45 -# set_property PACKAGE_PIN K33 [get_ports "FMCP_HSPC_LA32_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA32_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_45 -# set_property PACKAGE_PIN L33 [get_ports "FMCP_HSPC_LA32_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA32_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_45 -# set_property PACKAGE_PIN N35 [get_ports "FMCP_HSPC_LA22_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA22_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_45 -# set_property PACKAGE_PIN N34 [get_ports "FMCP_HSPC_LA22_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA22_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_45 -# set_property PACKAGE_PIN K34 [get_ports "FMCP_HSPC_LA33_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA33_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_45 -# set_property PACKAGE_PIN L34 [get_ports "FMCP_HSPC_LA33_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA33_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_45 -# #set_property PACKAGE_PIN K36 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_45 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_45 -# #set_property PACKAGE_PIN R36 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_45 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_45 -# set_property PACKAGE_PIN M38 [get_ports "FMCP_HSPC_LA30_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA30_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_45 -# set_property PACKAGE_PIN N38 [get_ports "FMCP_HSPC_LA30_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA30_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_45 -# set_property PACKAGE_PIN L36 [get_ports "FMCP_HSPC_LA28_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA28_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_45 -# set_property PACKAGE_PIN M36 [get_ports "FMCP_HSPC_LA28_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA28_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_45 -# set_property PACKAGE_PIN N37 [get_ports "FMCP_HSPC_LA31_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA31_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_45 -# set_property PACKAGE_PIN P37 [get_ports "FMCP_HSPC_LA31_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA31_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_45 -# #set_property PACKAGE_PIN L38 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_45 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_45 -# #set_property PACKAGE_PIN M37 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_45 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_45 -# set_property PACKAGE_PIN P36 [get_ports "FMCP_HSPC_CLK1_M2C_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK1_M2C_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_45 -# set_property PACKAGE_PIN P35 [get_ports "FMCP_HSPC_CLK1_M2C_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK1_M2C_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_45 -# set_property PACKAGE_PIN P34 [get_ports "FMCP_HSPC_LA17_CC_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA17_CC_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_45 -# set_property PACKAGE_PIN R34 [get_ports "FMCP_HSPC_LA17_CC_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA17_CC_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_45 -# #set_property PACKAGE_PIN R33 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_45 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_45 -# #set_property PACKAGE_PIN T33 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_45 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_45 -# set_property PACKAGE_PIN P32 [get_ports "USER_SMA_CLOCK_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_45 -# set_property IOSTANDARD LVDS [get_ports "USER_SMA_CLOCK_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_45 -# set_property PACKAGE_PIN R32 [get_ports "USER_SMA_CLOCK_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_45 -# set_property IOSTANDARD LVDS [get_ports "USER_SMA_CLOCK_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_45 -# set_property PACKAGE_PIN P31 [get_ports "FMCP_HSPC_LA18_CC_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA18_CC_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_45 -# set_property PACKAGE_PIN R31 [get_ports "FMCP_HSPC_LA18_CC_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA18_CC_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_45 -# #set_property PACKAGE_PIN W31 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_45 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_45 -# #set_property PACKAGE_PIN Y31 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_45 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_45 -# #set_property PACKAGE_PIN U32 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_45 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_45 -# #set_property PACKAGE_PIN U31 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_45 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_45 -# #set_property PACKAGE_PIN T31 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_45 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_45 -# #set_property PACKAGE_PIN T30 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_45 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_45 -# #set_property PACKAGE_PIN V30 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_45 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_45 -# #set_property PACKAGE_PIN Y33 [get_ports "VRP_45"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_45 -# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_45"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_45 -# set_property PACKAGE_PIN T35 [get_ports "FMCP_HSPC_LA24_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA24_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_45 -# set_property PACKAGE_PIN T34 [get_ports "FMCP_HSPC_LA24_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA24_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_45 -# set_property PACKAGE_PIN V34 [get_ports "FMCP_HSPC_LA27_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA27_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_45 -# set_property PACKAGE_PIN V33 [get_ports "FMCP_HSPC_LA27_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA27_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_45 -# set_property PACKAGE_PIN T36 [get_ports "FMCP_HSPC_LA29_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA29_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_45 -# set_property PACKAGE_PIN U35 [get_ports "FMCP_HSPC_LA29_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA29_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_45 -# set_property PACKAGE_PIN W34 [get_ports "FMCP_HSPC_LA25_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA25_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_45 -# set_property PACKAGE_PIN Y34 [get_ports "FMCP_HSPC_LA25_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA25_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_45 -# set_property PACKAGE_PIN U33 [get_ports "FMCP_HSPC_LA26_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA26_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_45 -# set_property PACKAGE_PIN V32 [get_ports "FMCP_HSPC_LA26_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA26_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_45 -# set_property PACKAGE_PIN W32 [get_ports "FMCP_HSPC_LA23_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA23_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_45 -# set_property PACKAGE_PIN Y32 [get_ports "FMCP_HSPC_LA23_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_45 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA23_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_45 -# #Other net PACKAGE_PIN U30 - VREF_45 Bank 45 - VREF_45 -# set_property PACKAGE_PIN AK13 [get_ports "FMC_HPC1_LA33_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA33_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_67 -# set_property PACKAGE_PIN AK14 [get_ports "FMC_HPC1_LA33_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA33_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_67 -# set_property PACKAGE_PIN AM12 [get_ports "FMC_HPC1_LA31_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA31_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_67 -# set_property PACKAGE_PIN AM13 [get_ports "FMC_HPC1_LA31_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA31_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_67 -# set_property PACKAGE_PIN AJ12 [get_ports "FMC_HPC1_LA32_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA32_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_67 -# set_property PACKAGE_PIN AJ13 [get_ports "FMC_HPC1_LA32_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA32_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_67 -# set_property PACKAGE_PIN AL12 [get_ports "FMC_HPC1_LA30_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA30_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_67 -# set_property PACKAGE_PIN AK12 [get_ports "FMC_HPC1_LA30_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA30_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_67 -# set_property PACKAGE_PIN AL15 [get_ports "FMC_HPC1_LA26_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA26_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_67 -# set_property PACKAGE_PIN AK15 [get_ports "FMC_HPC1_LA26_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA26_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_67 -# set_property PACKAGE_PIN AM14 [get_ports "FMC_HPC1_LA27_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA27_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_67 -# set_property PACKAGE_PIN AL14 [get_ports "FMC_HPC1_LA27_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA27_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_67 -# #set_property PACKAGE_PIN AM16 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_67 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_67 -# #set_property PACKAGE_PIN AR15 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_67 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_67 -# set_property PACKAGE_PIN AP15 [get_ports "FMC_HPC1_LA29_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA29_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_67 -# set_property PACKAGE_PIN AN15 [get_ports "FMC_HPC1_LA29_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA29_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_67 -# set_property PACKAGE_PIN AP16 [get_ports "FMC_HPC1_LA23_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA23_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_67 -# set_property PACKAGE_PIN AN16 [get_ports "FMC_HPC1_LA23_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA23_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_67 -# set_property PACKAGE_PIN AR12 [get_ports "FMC_HPC1_LA18_CC_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA18_CC_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_67 -# set_property PACKAGE_PIN AP12 [get_ports "FMC_HPC1_LA18_CC_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA18_CC_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_67 -# #set_property PACKAGE_PIN AN13 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_67 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_67 -# #set_property PACKAGE_PIN AN14 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_67 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_67 -# set_property PACKAGE_PIN AR13 [get_ports "FMC_HPC1_LA24_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA24_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_67 -# set_property PACKAGE_PIN AP13 [get_ports "FMC_HPC1_LA24_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA24_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_67 -# set_property PACKAGE_PIN AT14 [get_ports "FMC_HPC1_LA17_CC_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA17_CC_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_67 -# set_property PACKAGE_PIN AR14 [get_ports "FMC_HPC1_LA17_CC_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA17_CC_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_67 -# set_property PACKAGE_PIN AV13 [get_ports "FMC_HPC1_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_67 -# set_property PACKAGE_PIN AV14 [get_ports "FMC_HPC1_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_67 -# #set_property PACKAGE_PIN AU13 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_67 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_67 -# #set_property PACKAGE_PIN AU14 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_67 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_67 -# set_property PACKAGE_PIN AY14 [get_ports "PMOD0_0_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_67 -# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_0_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_67 -# set_property PACKAGE_PIN AY15 [get_ports "PMOD0_1_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_67 -# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_1_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_67 -# set_property PACKAGE_PIN AW15 [get_ports "PMOD0_2_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_67 -# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_2_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_67 -# set_property PACKAGE_PIN AV15 [get_ports "PMOD0_3_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_67 -# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_3_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_67 -# set_property PACKAGE_PIN AV16 [get_ports "PMOD0_4_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_67 -# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_4_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_67 -# set_property PACKAGE_PIN AU16 [get_ports "PMOD0_5_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_67 -# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_5_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_67 -# set_property PACKAGE_PIN AT15 [get_ports "PMOD0_6_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_67 -# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_6_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_67 -# set_property PACKAGE_PIN AT16 [get_ports "PMOD0_7_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_67 -# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_7_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_67 -# set_property PACKAGE_PIN AW16 [get_ports "10N8842"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_67 -# set_property IOSTANDARD LVCMOSxx [get_ports "10N8842"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_67 -# #set_property PACKAGE_PIN BA12 [get_ports "VRP_67"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_67 -# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_67"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_67 -# set_property PACKAGE_PIN AV11 [get_ports "FMC_HPC1_LA21_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA21_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_67 -# set_property PACKAGE_PIN AU11 [get_ports "FMC_HPC1_LA21_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA21_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_67 -# set_property PACKAGE_PIN AY13 [get_ports "FMC_HPC1_LA22_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA22_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_67 -# set_property PACKAGE_PIN AW13 [get_ports "FMC_HPC1_LA22_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA22_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_67 -# set_property PACKAGE_PIN AW10 [get_ports "FMC_HPC1_LA28_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA28_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_67 -# set_property PACKAGE_PIN AV10 [get_ports "FMC_HPC1_LA28_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA28_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_67 -# set_property PACKAGE_PIN AY10 [get_ports "FMC_HPC1_LA20_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA20_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_67 -# set_property PACKAGE_PIN AW11 [get_ports "FMC_HPC1_LA20_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA20_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_67 -# set_property PACKAGE_PIN AY12 [get_ports "FMC_HPC1_LA19_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA19_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_67 -# set_property PACKAGE_PIN AW12 [get_ports "FMC_HPC1_LA19_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA19_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_67 -# set_property PACKAGE_PIN AU12 [get_ports "FMC_HPC1_LA25_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA25_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_67 -# set_property PACKAGE_PIN AT12 [get_ports "FMC_HPC1_LA25_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_67 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA25_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_67 -# #Other net PACKAGE_PIN AL16 - VREF_67 Bank 67 - VREF_67 -# set_property PACKAGE_PIN BB12 [get_ports "FMC_HPC1_LA10_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA10_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_66 -# set_property PACKAGE_PIN BB13 [get_ports "FMC_HPC1_LA10_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA10_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_66 -# set_property PACKAGE_PIN BB14 [get_ports "FMC_HPC1_LA09_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA09_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_66 -# set_property PACKAGE_PIN BA14 [get_ports "FMC_HPC1_LA09_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA09_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_66 -# set_property PACKAGE_PIN BA15 [get_ports "FMC_HPC1_LA11_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA11_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_66 -# set_property PACKAGE_PIN BA16 [get_ports "FMC_HPC1_LA11_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA11_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_66 -# set_property PACKAGE_PIN BD15 [get_ports "FMC_HPC1_LA07_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA07_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_66 -# set_property PACKAGE_PIN BC15 [get_ports "FMC_HPC1_LA07_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA07_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_66 -# set_property PACKAGE_PIN BC16 [get_ports "FMC_HPC1_LA15_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA15_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_66 -# set_property PACKAGE_PIN BB16 [get_ports "FMC_HPC1_LA15_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA15_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_66 -# set_property PACKAGE_PIN BC13 [get_ports "FMC_HPC1_LA12_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA12_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_66 -# set_property PACKAGE_PIN BC14 [get_ports "FMC_HPC1_LA12_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA12_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_66 -# set_property PACKAGE_PIN BB11 [get_ports "10N8224"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_66 -# set_property IOSTANDARD LVCMOSxx [get_ports "10N8224"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_66 -# set_property PACKAGE_PIN BA10 [get_ports "10N9644"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_66 -# set_property IOSTANDARD LVCMOSxx [get_ports "10N9644"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_66 -# set_property PACKAGE_PIN AW7 [get_ports "FMC_HPC1_LA14_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA14_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_66 -# set_property PACKAGE_PIN AW8 [get_ports "FMC_HPC1_LA14_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA14_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_66 -# set_property PACKAGE_PIN AY7 [get_ports "FMC_HPC1_LA13_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA13_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_66 -# set_property PACKAGE_PIN AY8 [get_ports "FMC_HPC1_LA13_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA13_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_66 -# set_property PACKAGE_PIN AV8 [get_ports "FMC_HPC1_LA16_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA16_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_66 -# set_property PACKAGE_PIN AV9 [get_ports "FMC_HPC1_LA16_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA16_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_66 -# set_property PACKAGE_PIN BB7 [get_ports "FMC_HPC1_PRSNT_M2C_B_LS"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_66 -# set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_PRSNT_M2C_B_LS"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_66 -# set_property PACKAGE_PIN BA7 [get_ports "FMC_HPC1_PG_M2C_LS"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_66 -# set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_PG_M2C_LS"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_66 -# #set_property PACKAGE_PIN BB8 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_66 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_66 -# #set_property PACKAGE_PIN BB9 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_66 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_66 -# set_property PACKAGE_PIN BA9 [get_ports "FMC_HPC1_LA00_CC_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA00_CC_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_66 -# set_property PACKAGE_PIN AY9 [get_ports "FMC_HPC1_LA00_CC_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA00_CC_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_66 -# set_property PACKAGE_PIN BC8 [get_ports "FMC_HPC1_CLK0_M2C_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK0_M2C_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_66 -# set_property PACKAGE_PIN BC9 [get_ports "FMC_HPC1_CLK0_M2C_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK0_M2C_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_66 -# #set_property PACKAGE_PIN BD10 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_66 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_66 -# #set_property PACKAGE_PIN BC10 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_66 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_66 -# set_property PACKAGE_PIN BF9 [get_ports "FMC_HPC1_LA01_CC_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA01_CC_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_66 -# set_property PACKAGE_PIN BF10 [get_ports "FMC_HPC1_LA01_CC_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA01_CC_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_66 -# #set_property PACKAGE_PIN BE9 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_66 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_66 -# #set_property PACKAGE_PIN BE10 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_66 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_66 -# #set_property PACKAGE_PIN BE7 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_66 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_66 -# #set_property PACKAGE_PIN BE8 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_66 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_66 -# #set_property PACKAGE_PIN BD7 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_66 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_66 -# #set_property PACKAGE_PIN BD8 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_66 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_66 -# #set_property PACKAGE_PIN BF7 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_66 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_66 -# #set_property PACKAGE_PIN BD16 [get_ports "VRP_66"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_66 -# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_66"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_66 -# set_property PACKAGE_PIN BF15 [get_ports "FMC_HPC1_LA08_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA08_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_66 -# set_property PACKAGE_PIN BE15 [get_ports "FMC_HPC1_LA08_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA08_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_66 -# set_property PACKAGE_PIN BF14 [get_ports "FMC_HPC1_LA05_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA05_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_66 -# set_property PACKAGE_PIN BE14 [get_ports "FMC_HPC1_LA05_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA05_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_66 -# set_property PACKAGE_PIN BE13 [get_ports "FMC_HPC1_LA06_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA06_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_66 -# set_property PACKAGE_PIN BD13 [get_ports "FMC_HPC1_LA06_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA06_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_66 -# set_property PACKAGE_PIN BD11 [get_ports "FMC_HPC1_LA02_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA02_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_66 -# set_property PACKAGE_PIN BC11 [get_ports "FMC_HPC1_LA02_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA02_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_66 -# set_property PACKAGE_PIN BF11 [get_ports "FMC_HPC1_LA04_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA04_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_66 -# set_property PACKAGE_PIN BF12 [get_ports "FMC_HPC1_LA04_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA04_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_66 -# set_property PACKAGE_PIN BE12 [get_ports "FMC_HPC1_LA03_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA03_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_66 -# set_property PACKAGE_PIN BD12 [get_ports "FMC_HPC1_LA03_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_66 -# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA03_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_66 -# #Other net PACKAGE_PIN BA11 - VREF_66 Bank 66 - VREF_66 -# #set_property PACKAGE_PIN AL19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L24N_T3U_N11_DOUT_CSO_B_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L24N_T3U_N11_DOUT_CSO_B_65 -# set_property PACKAGE_PIN AL20 [get_ports "FPGA_EMCCLK"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L24P_T3U_N10_EMCCLK_65 -# set_property IOSTANDARD LVCMOS18 [get_ports "FPGA_EMCCLK"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L24P_T3U_N10_EMCCLK_65 -# set_property PACKAGE_PIN AP17 [get_ports "SYSMON_SDA"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 -# set_property IOSTANDARD LVCMOS18 [get_ports "SYSMON_SDA"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 -# set_property PACKAGE_PIN AP18 [get_ports "SYSMON_SCL"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L23P_T3U_N8_I2C_SCLK_65 -# set_property IOSTANDARD LVCMOS18 [get_ports "SYSMON_SCL"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L23P_T3U_N8_I2C_SCLK_65 -# set_property PACKAGE_PIN AM18 [get_ports "QSPI1_DQ1"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_D05_65 -# set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_DQ1"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_D05_65 -# set_property PACKAGE_PIN AM19 [get_ports "QSPI1_DQ0"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_D04_65 -# set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_DQ0"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_D04_65 -# set_property PACKAGE_PIN AP20 [get_ports "QSPI1_DQ3"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21N_T3L_N5_AD8N_D07_65 -# set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_DQ3"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21N_T3L_N5_AD8N_D07_65 -# set_property PACKAGE_PIN AN20 [get_ports "QSPI1_DQ2"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21P_T3L_N4_AD8P_D06_65 -# set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_DQ2"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21P_T3L_N4_AD8P_D06_65 -# #set_property PACKAGE_PIN AN18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L20N_T3L_N3_AD1N_D09_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L20N_T3L_N3_AD1N_D09_65 -# #set_property PACKAGE_PIN AN19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L20P_T3L_N2_AD1P_D08_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L20P_T3L_N2_AD1P_D08_65 -# #set_property PACKAGE_PIN AR17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_D11_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_D11_65 -# #set_property PACKAGE_PIN AR18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_D10_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_D10_65 -# set_property PACKAGE_PIN AM17 [get_ports "PCIE_PERST_LS"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T3U_N12_PERSTN0_65 -# set_property IOSTANDARD LVCMOS18 [get_ports "PCIE_PERST_LS"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T3U_N12_PERSTN0_65 -# #set_property PACKAGE_PIN AW17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T2U_N12_CSI_ADV_B_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T2U_N12_CSI_ADV_B_65 -# #set_property PACKAGE_PIN AT19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L18N_T2U_N11_AD2N_D13_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L18N_T2U_N11_AD2N_D13_65 -# #set_property PACKAGE_PIN AT20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L18P_T2U_N10_AD2P_D12_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L18P_T2U_N10_AD2P_D12_65 -# #set_property PACKAGE_PIN AU17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L17N_T2U_N9_AD10N_D15_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L17N_T2U_N9_AD10N_D15_65 -# #set_property PACKAGE_PIN AT17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L17P_T2U_N8_AD10P_D14_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L17P_T2U_N8_AD10P_D14_65 -# #set_property PACKAGE_PIN AR19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 -# #set_property PACKAGE_PIN AR20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 -# #set_property PACKAGE_PIN AW20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L15N_T2L_N5_AD11N_A03_D19_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L15N_T2L_N5_AD11N_A03_D19_65 -# #set_property PACKAGE_PIN AV20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L15P_T2L_N4_AD11P_A02_D18_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L15P_T2L_N4_AD11P_A02_D18_65 -# #set_property PACKAGE_PIN AU18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L14N_T2L_N3_GC_A05_D21_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L14N_T2L_N3_GC_A05_D21_65 -# #set_property PACKAGE_PIN AU19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L14P_T2L_N2_GC_A04_D20_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L14P_T2L_N2_GC_A04_D20_65 -# #set_property PACKAGE_PIN AV18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 -# #set_property PACKAGE_PIN AV19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 -# #set_property PACKAGE_PIN AY18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L12N_T1U_N11_GC_A09_D25_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L12N_T1U_N11_GC_A09_D25_65 -# #set_property PACKAGE_PIN AW18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L12P_T1U_N10_GC_A08_D24_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L12P_T1U_N10_GC_A08_D24_65 -# #set_property PACKAGE_PIN BA19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L11N_T1U_N9_GC_A11_D27_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L11N_T1U_N9_GC_A11_D27_65 -# #set_property PACKAGE_PIN AY19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L11P_T1U_N8_GC_A10_D26_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L11P_T1U_N8_GC_A10_D26_65 -# #set_property PACKAGE_PIN BB17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 -# #set_property PACKAGE_PIN BA17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 -# #set_property PACKAGE_PIN BC19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L9N_T1L_N5_AD12N_A15_D31_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L9N_T1L_N5_AD12N_A15_D31_65 -# #set_property PACKAGE_PIN BB19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_A14_D30_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_A14_D30_65 -# #set_property PACKAGE_PIN BC18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_A17_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_A17_65 -# #set_property PACKAGE_PIN BB18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L8P_T1L_N2_AD5P_A16_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L8P_T1L_N2_AD5P_A16_65 -# #set_property PACKAGE_PIN BA20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_A19_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_A19_65 -# #set_property PACKAGE_PIN AY20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_A18_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_A18_65 -# #set_property PACKAGE_PIN AY17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T1U_N12_SMBALERT_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T1U_N12_SMBALERT_65 -# #set_property PACKAGE_PIN BF21 [get_ports "VRP_65"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T0U_N12_VRP_A28_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_65"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T0U_N12_VRP_A28_65 -# #set_property PACKAGE_PIN BD17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L6N_T0U_N11_AD6N_A21_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L6N_T0U_N11_AD6N_A21_65 -# #set_property PACKAGE_PIN BD18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L6P_T0U_N10_AD6P_A20_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L6P_T0U_N10_AD6P_A20_65 -# #set_property PACKAGE_PIN BD20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L5N_T0U_N9_AD14N_A23_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L5N_T0U_N9_AD14N_A23_65 -# #set_property PACKAGE_PIN BC20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L5P_T0U_N8_AD14P_A22_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L5P_T0U_N8_AD14P_A22_65 -# #set_property PACKAGE_PIN BE17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_A25_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_A25_65 -# #set_property PACKAGE_PIN BE18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_A24_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_A24_65 -# #set_property PACKAGE_PIN BF19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L3N_T0L_N5_AD15N_A27_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L3N_T0L_N5_AD15N_A27_65 -# #set_property PACKAGE_PIN BE19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L3P_T0L_N4_AD15P_A26_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L3P_T0L_N4_AD15P_A26_65 -# set_property PACKAGE_PIN BF16 [get_ports "QSPI1_CS_B"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L2N_T0L_N3_FWE_FCS2_B_65 -# set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_CS_B"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L2N_T0L_N3_FWE_FCS2_B_65 -# set_property PACKAGE_PIN BF17 [get_ports "BPI_FLASH_OE_B"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L2P_T0L_N2_FOE_B_65 -# set_property IOSTANDARD LVCMOS18 [get_ports "BPI_FLASH_OE_B"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L2P_T0L_N2_FOE_B_65 -# #set_property PACKAGE_PIN BF20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L1N_T0L_N1_DBC_RS1_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L1N_T0L_N1_DBC_RS1_65 -# #set_property PACKAGE_PIN BE20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L1P_T0L_N0_DBC_RS0_65 -# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L1P_T0L_N0_DBC_RS0_65 -# #Other net PACKAGE_PIN AL17 - 8N8196 Bank 65 - VREF_65 -# set_property PACKAGE_PIN AM24 [get_ports "IIC_MAIN_SCL"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L24N_T3U_N11_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "IIC_MAIN_SCL"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L24N_T3U_N11_64 -# set_property PACKAGE_PIN AL24 [get_ports "IIC_MAIN_SDA"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L24P_T3U_N10_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "IIC_MAIN_SDA"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L24P_T3U_N10_64 -# set_property PACKAGE_PIN AM21 [get_ports "QSFP1_MODSELL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L23N_T3U_N9_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_MODSELL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L23N_T3U_N9_64 -# set_property PACKAGE_PIN AL21 [get_ports "QSFP1_MODPRSL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L23P_T3U_N8_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_MODPRSL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L23P_T3U_N8_64 -# set_property PACKAGE_PIN AM22 [get_ports "QSFP1_RECCLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_64 -# set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_64 -# set_property PACKAGE_PIN AM23 [get_ports "QSFP1_RECCLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_64 -# set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_64 -# set_property PACKAGE_PIN AP21 [get_ports "QSFP1_INTL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L21N_T3L_N5_AD8N_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_INTL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L21N_T3L_N5_AD8N_64 -# set_property PACKAGE_PIN AN21 [get_ports "QSFP1_LPMODE_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L21P_T3L_N4_AD8P_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_LPMODE_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L21P_T3L_N4_AD8P_64 -# set_property PACKAGE_PIN AN23 [get_ports "QSFP2_MODSELL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L20N_T3L_N3_AD1N_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP2_MODSELL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L20N_T3L_N3_AD1N_64 -# set_property PACKAGE_PIN AN24 [get_ports "QSFP2_MODPRSL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L20P_T3L_N2_AD1P_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP2_MODPRSL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L20P_T3L_N2_AD1P_64 -# set_property PACKAGE_PIN AP22 [get_ports "QSFP2_RECCLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_64 -# set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_64 -# set_property PACKAGE_PIN AP23 [get_ports "QSFP2_RECCLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_64 -# set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_64 -# set_property PACKAGE_PIN AL25 [get_ports "IIC_MUX_RESET_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T3U_N12_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "IIC_MUX_RESET_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T3U_N12_64 -# set_property PACKAGE_PIN AT21 [get_ports "QSFP2_INTL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T2U_N12_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP2_INTL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T2U_N12_64 -# set_property PACKAGE_PIN AT24 [get_ports "QSFP2_LPMODE_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L18N_T2U_N11_AD2N_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP2_LPMODE_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L18N_T2U_N11_AD2N_64 -# set_property PACKAGE_PIN AR24 [get_ports "PHY1_PDWN_B_I_INT_B_O"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L18P_T2U_N10_AD2P_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_PDWN_B_I_INT_B_O"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L18P_T2U_N10_AD2P_64 -# set_property PACKAGE_PIN AR22 [get_ports "PHY1_GPIO_0"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L17N_T2U_N9_AD10N_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_GPIO_0"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L17N_T2U_N9_AD10N_64 -# set_property PACKAGE_PIN AR23 [get_ports "PHY1_MDIO"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L17P_T2U_N8_AD10P_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_MDIO"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L17P_T2U_N8_AD10P_64 -# set_property PACKAGE_PIN AV24 [get_ports "PHY1_SGMII_OUT_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_64 -# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_OUT_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_64 -# set_property PACKAGE_PIN AU24 [get_ports "PHY1_SGMII_OUT_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_64 -# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_OUT_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_64 -# set_property PACKAGE_PIN AV21 [get_ports "PHY1_SGMII_IN_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L15N_T2L_N5_AD11N_64 -# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_IN_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L15N_T2L_N5_AD11N_64 -# set_property PACKAGE_PIN AU21 [get_ports "PHY1_SGMII_IN_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L15P_T2L_N4_AD11P_64 -# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_IN_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L15P_T2L_N4_AD11P_64 -# set_property PACKAGE_PIN AV23 [get_ports "PHY1_MDC"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L14N_T2L_N3_GC_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_MDC"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L14N_T2L_N3_GC_64 -# set_property PACKAGE_PIN AU23 [get_ports "PHY1_CLKOUT"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L14P_T2L_N2_GC_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_CLKOUT"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L14P_T2L_N2_GC_64 -# set_property PACKAGE_PIN AU22 [get_ports "PHY1_SGMII_CLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_64 -# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_CLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_64 -# set_property PACKAGE_PIN AT22 [get_ports "PHY1_SGMII_CLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_64 -# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_CLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_64 -# set_property PACKAGE_PIN AW22 [get_ports "USER_SI570_CLOCK1_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L12N_T1U_N11_GC_64 -# set_property IOSTANDARD LVDS [get_ports "USER_SI570_CLOCK1_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L12N_T1U_N11_GC_64 -# set_property PACKAGE_PIN AW23 [get_ports "USER_SI570_CLOCK1_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L12P_T1U_N10_GC_64 -# set_property IOSTANDARD LVDS [get_ports "USER_SI570_CLOCK1_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L12P_T1U_N10_GC_64 -# set_property PACKAGE_PIN BA22 [get_ports "QSFP1_RESETL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_RESETL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_64 -# set_property PACKAGE_PIN AY22 [get_ports "QSFP2_RESETL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP2_RESETL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_64 -# set_property PACKAGE_PIN AY25 [get_ports "USB_UART_RTS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L9N_T1L_N5_AD12N_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "USB_UART_RTS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L9N_T1L_N5_AD12N_64 +set_property PACKAGE_PIN D11 [get_ports {c0_ddr4_dqs_t[0]}] +set_property PACKAGE_PIN D10 [get_ports {c0_ddr4_dqs_c[0]}] +set_property PACKAGE_PIN P17 [get_ports {c0_ddr4_dqs_t[1]}] +set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_dqs_c[1]}] +set_property PACKAGE_PIN K19 [get_ports {c0_ddr4_dqs_t[2]}] +set_property PACKAGE_PIN J19 [get_ports {c0_ddr4_dqs_c[2]}] +set_property PACKAGE_PIN F16 [get_ports {c0_ddr4_dqs_t[3]}] +set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_dqs_c[3]}] +set_property PACKAGE_PIN A19 [get_ports {c0_ddr4_dqs_t[4]}] +set_property PACKAGE_PIN A18 [get_ports {c0_ddr4_dqs_c[4]}] +set_property PACKAGE_PIN N22 [get_ports {c0_ddr4_dqs_t[5]}] +set_property PACKAGE_PIN M22 [get_ports {c0_ddr4_dqs_c[5]}] +set_property PACKAGE_PIN M20 [get_ports {c0_ddr4_dqs_t[6]}] +set_property PACKAGE_PIN L20 [get_ports {c0_ddr4_dqs_c[6]}] +set_property PACKAGE_PIN H24 [get_ports {c0_ddr4_dqs_t[7]}] +set_property PACKAGE_PIN G23 [get_ports {c0_ddr4_dqs_c[7]}] -# set_property PACKAGE_PIN BB22 [get_ports "USB_UART_CTS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L8P_T1L_N2_AD5P_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "USB_UART_CTS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L8P_T1L_N2_AD5P_64 -# set_property PACKAGE_PIN BA24 [get_ports "SYSCTLR_GPIO_7"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_GPIO_7"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_64 -# set_property PACKAGE_PIN BA25 [get_ports "SYSCTLR_GPIO_6"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_GPIO_6"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_64 -# set_property PACKAGE_PIN BA21 [get_ports "PHY1_RESET_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T1U_N12_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_RESET_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T1U_N12_64 -# #set_property PACKAGE_PIN BC24 [get_ports "PCIE_WAKE_B_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T0U_N12_VRP_64 -# #set_property IOSTANDARD LVCMOS18 [get_ports "PCIE_WAKE_B_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T0U_N12_VRP_64 -# set_property PACKAGE_PIN BD21 [get_ports "SYSCTLR_GPIO_5"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L6N_T0U_N11_AD6N_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_GPIO_5"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L6N_T0U_N11_AD6N_64 -# set_property PACKAGE_PIN BC21 [get_ports "SI5328_RST_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L6P_T0U_N10_AD6P_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "SI5328_RST_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L6P_T0U_N10_AD6P_64 -# set_property PACKAGE_PIN BB23 [get_ports "PMBUS_ALERT_FPGA"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L5N_T0U_N9_AD14N_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "PMBUS_ALERT_FPGA"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L5N_T0U_N9_AD14N_64 -# set_property PACKAGE_PIN BB24 [get_ports "GPIO_SW_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L5P_T0U_N8_AD14P_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L5P_T0U_N8_AD14P_64 -# set_property PACKAGE_PIN BF22 [get_ports "GPIO_SW_W"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_W"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_64 -# set_property PACKAGE_PIN BE22 [get_ports "GPIO_SW_S"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_S"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_64 -# set_property PACKAGE_PIN BE23 [get_ports "GPIO_SW_E"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L3N_T0L_N5_AD15N_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_E"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L3N_T0L_N5_AD15N_64 -# set_property PACKAGE_PIN BD23 [get_ports "GPIO_SW_C"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L3P_T0L_N4_AD15P_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_C"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L3P_T0L_N4_AD15P_64 -# set_property PACKAGE_PIN BD22 [get_ports "FIREFLY_MODPRS_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L2N_T0L_N3_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "FIREFLY_MODPRS_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L2N_T0L_N3_64 -# set_property PACKAGE_PIN BC23 [get_ports "FIREFLY_MODSEL_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L2P_T0L_N2_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "FIREFLY_MODSEL_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L2P_T0L_N2_64 -# set_property PACKAGE_PIN BF24 [get_ports "FIREFLY_INT_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L1N_T0L_N1_DBC_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "FIREFLY_INT_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L1N_T0L_N1_DBC_64 -# set_property PACKAGE_PIN BE24 [get_ports "FIREFLY_RESET_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L1P_T0L_N0_DBC_64 -# set_property IOSTANDARD LVCMOS18 [get_ports "FIREFLY_RESET_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L1P_T0L_N0_DBC_64 -# #Other net PACKAGE_PIN AL22 - 30N4994 Bank 64 - VREF_64 -# set_property PACKAGE_PIN AG33 [get_ports "FMCP_HSPC_LA15_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA15_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_43 -# set_property PACKAGE_PIN AG32 [get_ports "FMCP_HSPC_LA15_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA15_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_43 -# set_property PACKAGE_PIN AH31 [get_ports "FMCP_HSPC_LA14_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA14_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_43 -# set_property PACKAGE_PIN AG31 [get_ports "FMCP_HSPC_LA14_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA14_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_43 -# set_property PACKAGE_PIN AH35 [get_ports "FMCP_HSPC_LA16_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_43 -# set_property PACKAGE_PIN AG34 [get_ports "FMCP_HSPC_LA16_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_43 -# set_property PACKAGE_PIN AH34 [get_ports "FMCP_HSPC_LA12_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA12_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_43 -# set_property PACKAGE_PIN AH33 [get_ports "FMCP_HSPC_LA12_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA12_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_43 -# set_property PACKAGE_PIN AJ36 [get_ports "FMCP_HSPC_LA13_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA13_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_43 -# set_property PACKAGE_PIN AJ35 [get_ports "FMCP_HSPC_LA13_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA13_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_43 -# set_property PACKAGE_PIN AK33 [get_ports "FMCP_HSPC_LA09_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA09_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_43 -# set_property PACKAGE_PIN AJ33 [get_ports "FMCP_HSPC_LA09_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA09_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_43 -# set_property PACKAGE_PIN AH30 [get_ports "9N9738"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_43 -# set_property IOSTANDARD LVCMOSxx [get_ports "9N9738"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_43 -# set_property PACKAGE_PIN AM31 [get_ports "9N9739"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_43 -# set_property IOSTANDARD LVCMOSxx [get_ports "9N9739"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_43 -# set_property PACKAGE_PIN AK30 [get_ports "FMCP_HSPC_LA08_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA08_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_43 -# set_property PACKAGE_PIN AK29 [get_ports "FMCP_HSPC_LA08_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA08_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_43 -# set_property PACKAGE_PIN AJ31 [get_ports "FMCP_HSPC_LA11_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA11_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_43 -# set_property PACKAGE_PIN AJ30 [get_ports "FMCP_HSPC_LA11_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA11_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_43 -# set_property PACKAGE_PIN AL31 [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_43 -# set_property PACKAGE_PIN AL30 [get_ports "FMCP_HSPC_LA01_CC_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA01_CC_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_43 -# set_property PACKAGE_PIN AM29 [get_ports "FMCP_HSPC_Z_PRSNT_M2C_B_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_43 -# set_property IOSTANDARD LVCMOS18 [get_ports "FMCP_HSPC_Z_PRSNT_M2C_B_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_43 -# set_property PACKAGE_PIN AL29 [get_ports "FMC_VADJ_ON_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_43 -# set_property IOSTANDARD LVCMOS18 [get_ports "FMC_VADJ_ON_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_43 -# set_property PACKAGE_PIN AK32 [get_ports "FMCP_HSPC_LA02_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA02_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_43 -# set_property PACKAGE_PIN AJ32 [get_ports "FMCP_HSPC_LA02_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA02_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_43 -# set_property PACKAGE_PIN AM32 [get_ports "FMCP_HSPC_CLK0_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_43 -# set_property PACKAGE_PIN AL32 [get_ports "FMCP_HSPC_CLK0_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_43 -# set_property PACKAGE_PIN AM34 [get_ports "FMCP_HSPC_PG_M2C_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_PG_M2C_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_43 -# set_property PACKAGE_PIN AM33 [get_ports "FMCP_HSPC_H_PRSNT_M2C_B_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_43 -# set_property IOSTANDARD LVCMOS18 [get_ports "FMCP_HSPC_H_PRSNT_M2C_B_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_43 -# set_property PACKAGE_PIN AL34 [get_ports "FMCP_HSPC_REFCLK_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_43 -# set_property PACKAGE_PIN AK34 [get_ports "FMCP_HSPC_REFCLK_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_43 -# set_property PACKAGE_PIN AP33 [get_ports "FMCP_HSPC_REFCLK_C2M_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_C2M_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_43 -# set_property PACKAGE_PIN AN33 [get_ports "FMCP_HSPC_REFCLK_C2M_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_C2M_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_43 -# set_property PACKAGE_PIN AN36 [get_ports "FMCP_HSPC_SYNC_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_43 -# set_property PACKAGE_PIN AM36 [get_ports "FMCP_HSPC_SYNC_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_43 -# set_property PACKAGE_PIN AN35 [get_ports "FMCP_HSPC_SYNC_C2M_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_C2M_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_43 -# set_property PACKAGE_PIN AN34 [get_ports "FMCP_HSPC_SYNC_C2M_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_C2M_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_43 -# set_property PACKAGE_PIN AL36 [get_ports "FMCP_HSPC_LA00_CC_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA00_CC_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_43 -# set_property PACKAGE_PIN AL35 [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_43 -# set_property PACKAGE_PIN AK35 [get_ports "VADJ_1V8_PGOOD_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_43 -# set_property IOSTANDARD LVCMOS18 [get_ports "VADJ_1V8_PGOOD_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_43 -# #set_property PACKAGE_PIN AR34 [get_ports "VRP_43"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_43 -# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_43"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_43 -# set_property PACKAGE_PIN AT37 [get_ports "FMCP_HSPC_LA04_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA04_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_43 -# set_property PACKAGE_PIN AR37 [get_ports "FMCP_HSPC_LA04_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA04_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_43 -# set_property PACKAGE_PIN AP37 [get_ports "FMCP_HSPC_LA07_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_43 -# set_property PACKAGE_PIN AP36 [get_ports "FMCP_HSPC_LA07_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_43 -# set_property PACKAGE_PIN AT40 [get_ports "FMCP_HSPC_LA03_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA03_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_43 -# set_property PACKAGE_PIN AT39 [get_ports "FMCP_HSPC_LA03_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA03_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_43 -# set_property PACKAGE_PIN AR35 [get_ports "FMCP_HSPC_LA10_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA10_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_43 -# set_property PACKAGE_PIN AP35 [get_ports "FMCP_HSPC_LA10_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA10_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_43 -# set_property PACKAGE_PIN AT36 [get_ports "FMCP_HSPC_LA06_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA06_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_43 -# set_property PACKAGE_PIN AT35 [get_ports "FMCP_HSPC_LA06_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA06_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_43 -# set_property PACKAGE_PIN AR38 [get_ports "FMCP_HSPC_LA05_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA05_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_43 -# set_property PACKAGE_PIN AP38 [get_ports "FMCP_HSPC_LA05_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_43 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA05_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_43 -# #Other net PACKAGE_PIN AJ29 - VREF_43 Bank 43 - VREF_43 -# set_property PACKAGE_PIN AV39 [get_ports "DDR4_C2_DQ63"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ63"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_42 -# set_property PACKAGE_PIN AV38 [get_ports "DDR4_C2_DQ62"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ62"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_42 -# set_property PACKAGE_PIN AU39 [get_ports "DDR4_C2_DQ61"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ61"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_42 -# set_property PACKAGE_PIN AU38 [get_ports "DDR4_C2_DQ60"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ60"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_42 -# set_property PACKAGE_PIN AW38 [get_ports "DDR4_C2_DQS7_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_42 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS7_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_42 -# set_property PACKAGE_PIN AW37 [get_ports "DDR4_C2_DQS7_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_42 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS7_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_42 -# set_property PACKAGE_PIN AV40 [get_ports "DDR4_C2_DQ59"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ59"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_42 -# set_property PACKAGE_PIN AU40 [get_ports "DDR4_C2_DQ58"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ58"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_42 -# set_property PACKAGE_PIN AW36 [get_ports "DDR4_C2_DQ57"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ57"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_42 -# set_property PACKAGE_PIN AW35 [get_ports "DDR4_C2_DQ56"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ56"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_42 -# set_property PACKAGE_PIN AV36 [get_ports "GPIO_LED6"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_42 -# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED6"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_42 -# set_property PACKAGE_PIN AV35 [get_ports "DDR4_C2_DM7"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM7"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_42 -# set_property PACKAGE_PIN AU37 [get_ports "GPIO_LED5"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T3U_N12_42 -# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED5"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T3U_N12_42 -# set_property PACKAGE_PIN AY35 [get_ports "DDR4_C2_TEN"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T2U_N12_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_TEN"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T2U_N12_42 -# set_property PACKAGE_PIN AY39 [get_ports "DDR4_C2_DQ55"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ55"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_42 -# set_property PACKAGE_PIN AY38 [get_ports "DDR4_C2_DQ54"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ54"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_42 -# set_property PACKAGE_PIN AY40 [get_ports "DDR4_C2_DQ53"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ53"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_42 -# set_property PACKAGE_PIN AW40 [get_ports "DDR4_C2_DQ52"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ52"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_42 -# set_property PACKAGE_PIN BA36 [get_ports "DDR4_C2_DQS6_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_42 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS6_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_42 -# set_property PACKAGE_PIN BA35 [get_ports "DDR4_C2_DQS6_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_42 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS6_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_42 -# set_property PACKAGE_PIN BA40 [get_ports "DDR4_C2_DQ51"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ51"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_42 -# set_property PACKAGE_PIN BA39 [get_ports "DDR4_C2_DQ50"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ50"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_42 -# set_property PACKAGE_PIN BB37 [get_ports "DDR4_C2_DQ49"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ49"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_42 -# set_property PACKAGE_PIN BB36 [get_ports "DDR4_C2_DQ48"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ48"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_42 -# set_property PACKAGE_PIN BA37 [get_ports "GPIO_LED7"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_42 -# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED7"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_42 -# set_property PACKAGE_PIN AY37 [get_ports "DDR4_C2_DM6"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM6"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_42 -# set_property PACKAGE_PIN BD38 [get_ports "DDR4_C2_DQ47"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ47"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_42 -# set_property PACKAGE_PIN BC38 [get_ports "DDR4_C2_DQ46"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ46"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_42 -# set_property PACKAGE_PIN BB39 [get_ports "DDR4_C2_DQ45"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ45"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_42 -# set_property PACKAGE_PIN BB38 [get_ports "DDR4_C2_DQ44"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ44"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_42 -# set_property PACKAGE_PIN BF39 [get_ports "DDR4_C2_DQS5_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_42 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS5_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_42 -# set_property PACKAGE_PIN BE39 [get_ports "DDR4_C2_DQS5_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_42 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS5_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_42 -# set_property PACKAGE_PIN BD40 [get_ports "DDR4_C2_DQ43"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ43"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_42 -# set_property PACKAGE_PIN BC39 [get_ports "DDR4_C2_DQ42"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ42"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_42 -# set_property PACKAGE_PIN BE38 [get_ports "DDR4_C2_DQ41"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ41"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_42 -# set_property PACKAGE_PIN BD37 [get_ports "DDR4_C2_DQ40"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ40"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_42 -# set_property PACKAGE_PIN BF40 [get_ports "MAXIM_CABLE_LS_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_42 -# set_property IOSTANDARD LVCMOS12 [get_ports "MAXIM_CABLE_LS_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_42 -# set_property PACKAGE_PIN BE40 [get_ports "DDR4_C2_DM5"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM5"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_42 -# set_property PACKAGE_PIN BC40 [get_ports "FAN_OT_LS_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T1U_N12_42 -# set_property IOSTANDARD LVCMOS12 [get_ports "FAN_OT_LS_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T1U_N12_42 -# #set_property PACKAGE_PIN BB34 [get_ports "VRP_42"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_42 -# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_42"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_42 -# set_property PACKAGE_PIN BF37 [get_ports "DDR4_C2_DQ39"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ39"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_42 -# set_property PACKAGE_PIN BF36 [get_ports "DDR4_C2_DQ38"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ38"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_42 -# set_property PACKAGE_PIN BE37 [get_ports "DDR4_C2_DQ37"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ37"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_42 -# set_property PACKAGE_PIN BD36 [get_ports "DDR4_C2_DQ36"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ36"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_42 -# set_property PACKAGE_PIN BF35 [get_ports "DDR4_C2_DQS4_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_42 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS4_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_42 -# set_property PACKAGE_PIN BE35 [get_ports "DDR4_C2_DQS4_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_42 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS4_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_42 -# set_property PACKAGE_PIN BC36 [get_ports "DDR4_C2_DQ35"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ35"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_42 -# set_property PACKAGE_PIN BC35 [get_ports "DDR4_C2_DQ34"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ34"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_42 -# set_property PACKAGE_PIN BF34 [get_ports "DDR4_C2_DQ33"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ33"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_42 -# set_property PACKAGE_PIN BE34 [get_ports "DDR4_C2_DQ32"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ32"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_42 -# set_property PACKAGE_PIN BD35 [get_ports "DDR4_C2_RESET_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_42 -# set_property IOSTANDARD LVCMOS12 [get_ports "DDR4_C2_RESET_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_42 -# set_property PACKAGE_PIN BC34 [get_ports "DDR4_C2_DM4"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_42 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM4"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_42 -# #Other net PACKAGE_PIN AU36 - 5N11683 Bank 42 - VREF_42 -# set_property PACKAGE_PIN AM27 [get_ports "DDR4_C2_A0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_41 -# set_property PACKAGE_PIN AL27 [get_ports "DDR4_C2_A1"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A1"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_41 -# set_property PACKAGE_PIN AP26 [get_ports "DDR4_C2_A2"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A2"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_41 -# set_property PACKAGE_PIN AP25 [get_ports "DDR4_C2_A3"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A3"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_41 -# set_property PACKAGE_PIN AN28 [get_ports "DDR4_C2_A4"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A4"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_41 -# set_property PACKAGE_PIN AM28 [get_ports "DDR4_C2_A5"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A5"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_41 -# set_property PACKAGE_PIN AP28 [get_ports "DDR4_C2_A6"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A6"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_41 -# set_property PACKAGE_PIN AP27 [get_ports "DDR4_C2_A7"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A7"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_41 -# set_property PACKAGE_PIN AN26 [get_ports "DDR4_C2_A8"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A8"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_41 -# set_property PACKAGE_PIN AM26 [get_ports "DDR4_C2_A9"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A9"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_41 -# set_property PACKAGE_PIN AR28 [get_ports "DDR4_C2_A10"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A10"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_41 -# set_property PACKAGE_PIN AR27 [get_ports "DDR4_C2_A11"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A11"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_41 -# set_property PACKAGE_PIN AN25 [get_ports "DDR4_C2_ACT_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T3U_N12_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_ACT_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T3U_N12_41 -# set_property PACKAGE_PIN AV25 [get_ports "DDR4_C2_A12"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T2U_N12_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A12"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T2U_N12_41 -# set_property PACKAGE_PIN AT25 [get_ports "DDR4_C2_A13"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A13"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_41 -# set_property PACKAGE_PIN AR25 [get_ports "DDR4_C2_BA0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_BA0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_41 -# set_property PACKAGE_PIN AU28 [get_ports "DDR4_C2_BA1"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_BA1"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_41 -# set_property PACKAGE_PIN AU27 [get_ports "DDR4_C2_BG0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_BG0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_41 -# set_property PACKAGE_PIN AT27 [get_ports "DDR4_C2_CK_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_41 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_CK_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_41 -# set_property PACKAGE_PIN AT26 [get_ports "DDR4_C2_CK_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_41 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_CK_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_41 -# set_property PACKAGE_PIN AW28 [get_ports "DDR4_C2_CKE"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_CKE"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_41 -# set_property PACKAGE_PIN AV28 [get_ports "DDR4_C2_A14_WE_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A14_WE_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_41 -# set_property PACKAGE_PIN AV26 [get_ports "DDR4_C2_A16_RAS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A16_RAS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_41 -# set_property PACKAGE_PIN AU26 [get_ports "DDR4_C2_A15_CAS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A15_CAS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_41 -# set_property PACKAGE_PIN AW27 [get_ports "250MHZ_CLK2_N"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_41 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "250MHZ_CLK2_N"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_41 -# set_property PACKAGE_PIN AW26 [get_ports "250MHZ_CLK2_P"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_41 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "250MHZ_CLK2_P"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_41 -# set_property PACKAGE_PIN BB27 [get_ports "DDR4_C2_DQ79"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ79"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_41 -# set_property PACKAGE_PIN BA27 [get_ports "DDR4_C2_DQ78"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ78"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_41 -# set_property PACKAGE_PIN AY28 [get_ports "DDR4_C2_DQ77"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ77"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_41 -# set_property PACKAGE_PIN AY27 [get_ports "DDR4_C2_DQ76"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ76"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_41 -# set_property PACKAGE_PIN BB26 [get_ports "DDR4_C2_DQS9_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_41 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS9_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_41 -# set_property PACKAGE_PIN BA26 [get_ports "DDR4_C2_DQS9_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_41 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS9_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_41 -# set_property PACKAGE_PIN BC28 [get_ports "DDR4_C2_DQ75"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ75"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_41 -# set_property PACKAGE_PIN BB28 [get_ports "DDR4_C2_DQ74"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ74"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_41 -# set_property PACKAGE_PIN BC26 [get_ports "DDR4_C2_DQ73"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ73"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_41 -# set_property PACKAGE_PIN BC25 [get_ports "DDR4_C2_DQ72"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ72"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_41 -# set_property PACKAGE_PIN BB29 [get_ports "DDR4_C2_ODT"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_ODT"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_41 -# set_property PACKAGE_PIN BA29 [get_ports "DDR4_C2_DM9"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_DM9"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_41 -# set_property PACKAGE_PIN AY29 [get_ports "DDR4_C2_CS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T1U_N12_41 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_CS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T1U_N12_41 -# #set_property PACKAGE_PIN BC29 [get_ports "VRP_41"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_41 -# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_41"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_41 -# set_property PACKAGE_PIN BD26 [get_ports "DDR4_C2_DQ71"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ71"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_41 -# set_property PACKAGE_PIN BD25 [get_ports "DDR4_C2_DQ70"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ70"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_41 -# set_property PACKAGE_PIN BE27 [get_ports "DDR4_C2_DQ69"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ69"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_41 -# set_property PACKAGE_PIN BD27 [get_ports "DDR4_C2_DQ68"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ68"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_41 -# set_property PACKAGE_PIN BF25 [get_ports "DDR4_C2_DQS8_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_41 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS8_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_41 -# set_property PACKAGE_PIN BE25 [get_ports "DDR4_C2_DQS8_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_41 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS8_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_41 -# set_property PACKAGE_PIN BE28 [get_ports "DDR4_C2_DQ67"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ67"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_41 -# set_property PACKAGE_PIN BD28 [get_ports "DDR4_C2_DQ66"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ66"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_41 -# set_property PACKAGE_PIN BF27 [get_ports "DDR4_C2_DQ65"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ65"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_41 -# set_property PACKAGE_PIN BF26 [get_ports "DDR4_C2_DQ64"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ64"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_41 -# set_property PACKAGE_PIN BF29 [get_ports "DDR4_C2_PAR"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_PAR"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_41 -# set_property PACKAGE_PIN BE29 [get_ports "DDR4_C2_DM8"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_41 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM8"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_41 -# #Other net PACKAGE_PIN AL26 - 6N5608 Bank 41 - VREF_41 -# set_property PACKAGE_PIN AN31 [get_ports "DDR4_C2_DQ31"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ31"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_40 -# set_property PACKAGE_PIN AN30 [get_ports "DDR4_C2_DQ30"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ30"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_40 -# set_property PACKAGE_PIN AR30 [get_ports "DDR4_C2_DQ29"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ29"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_40 -# set_property PACKAGE_PIN AP30 [get_ports "DDR4_C2_DQ28"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ28"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_40 -# set_property PACKAGE_PIN AP32 [get_ports "DDR4_C2_DQS3_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_40 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS3_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_40 -# set_property PACKAGE_PIN AP31 [get_ports "DDR4_C2_DQS3_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_40 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS3_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_40 -# set_property PACKAGE_PIN AT30 [get_ports "DDR4_C2_DQ27"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ27"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_40 -# set_property PACKAGE_PIN AT29 [get_ports "DDR4_C2_DQ26"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ26"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_40 -# set_property PACKAGE_PIN AT34 [get_ports "DDR4_C2_DQ25"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ25"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_40 -# set_property PACKAGE_PIN AR33 [get_ports "DDR4_C2_DQ24"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ24"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_40 -# set_property PACKAGE_PIN AT32 [get_ports "GPIO_LED0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_40 -# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_40 -# set_property PACKAGE_PIN AR32 [get_ports "DDR4_C2_DM3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_40 -# set_property PACKAGE_PIN AR29 [get_ports "DDR4_C2_ALERT_B"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T3U_N12_40 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_ALERT_B"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T3U_N12_40 -# set_property PACKAGE_PIN AV34 [get_ports "GPIO_LED1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T2U_N12_40 -# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T2U_N12_40 -# set_property PACKAGE_PIN AV31 [get_ports "DDR4_C2_DQ23"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ23"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_40 -# set_property PACKAGE_PIN AU31 [get_ports "DDR4_C2_DQ22"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ22"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_40 -# set_property PACKAGE_PIN AU32 [get_ports "DDR4_C2_DQ21"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ21"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_40 -# set_property PACKAGE_PIN AT31 [get_ports "DDR4_C2_DQ20"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ20"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_40 -# set_property PACKAGE_PIN AV29 [get_ports "DDR4_C2_DQS2_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_40 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS2_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_40 -# set_property PACKAGE_PIN AU29 [get_ports "DDR4_C2_DQS2_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_40 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS2_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_40 -# set_property PACKAGE_PIN AU34 [get_ports "DDR4_C2_DQ19"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ19"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_40 -# set_property PACKAGE_PIN AU33 [get_ports "DDR4_C2_DQ18"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ18"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_40 -# set_property PACKAGE_PIN AW30 [get_ports "DDR4_C2_DQ17"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ17"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_40 -# set_property PACKAGE_PIN AV30 [get_ports "DDR4_C2_DQ16"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ16"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_40 -# set_property PACKAGE_PIN AW33 [get_ports "FAN_FAIL_LS_B"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_40 -# set_property IOSTANDARD LVCMOS12 [get_ports "FAN_FAIL_LS_B"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_40 -# set_property PACKAGE_PIN AV33 [get_ports "DDR4_C2_DM2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_40 -# set_property PACKAGE_PIN AY33 [get_ports "DDR4_C2_DQ15"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ15"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_40 -# set_property PACKAGE_PIN AY32 [get_ports "DDR4_C2_DQ14"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ14"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_40 -# set_property PACKAGE_PIN AW32 [get_ports "DDR4_C2_DQ13"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ13"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_40 -# set_property PACKAGE_PIN AW31 [get_ports "DDR4_C2_DQ12"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ12"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_40 -# set_property PACKAGE_PIN BA34 [get_ports "DDR4_C2_DQS1_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQS1_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_40 -# set_property PACKAGE_PIN AY34 [get_ports "DDR4_C2_DQS1_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQS1_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_40 -# set_property PACKAGE_PIN BA31 [get_ports "DDR4_C2_DQ11"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ11"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_40 -# set_property PACKAGE_PIN BA30 [get_ports "DDR4_C2_DQ10"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ10"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_40 -# set_property PACKAGE_PIN BB33 [get_ports "DDR4_C2_DQ9"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ9"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_40 -# set_property PACKAGE_PIN BA32 [get_ports "DDR4_C2_DQ8"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ8"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_40 -# set_property PACKAGE_PIN BB32 [get_ports "GPIO_LED3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_40 -# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_40 -# set_property PACKAGE_PIN BB31 [get_ports "DDR4_C2_DM1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_40 -# set_property PACKAGE_PIN AY30 [get_ports "GPIO_LED2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T1U_N12_40 -# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T1U_N12_40 -# #set_property PACKAGE_PIN BC30 [get_ports "VRP_40"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_40 -# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_40"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_40 -# set_property PACKAGE_PIN BD31 [get_ports "DDR4_C2_DQ7"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ7"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_40 -# set_property PACKAGE_PIN BC31 [get_ports "DDR4_C2_DQ6"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ6"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_40 -# set_property PACKAGE_PIN BD33 [get_ports "DDR4_C2_DQ5"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ5"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_40 -# set_property PACKAGE_PIN BC33 [get_ports "DDR4_C2_DQ4"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ4"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_40 -# set_property PACKAGE_PIN BF31 [get_ports "DDR4_C2_DQS0_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_40 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS0_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_40 -# set_property PACKAGE_PIN BF30 [get_ports "DDR4_C2_DQS0_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_40 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS0_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_40 -# set_property PACKAGE_PIN BE33 [get_ports "DDR4_C2_DQ3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_40 -# set_property PACKAGE_PIN BD32 [get_ports "DDR4_C2_DQ2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_40 -# set_property PACKAGE_PIN BE30 [get_ports "DDR4_C2_DQ1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_40 -# set_property PACKAGE_PIN BD30 [get_ports "DDR4_C2_DQ0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_40 -# set_property PACKAGE_PIN BF32 [get_ports "GPIO_LED4"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_40 -# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED4"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_40 -# set_property PACKAGE_PIN BE32 [get_ports "DDR4_C2_DM0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_40 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_40 -# #Other net PACKAGE_PIN AN29 - 5N11680 Bank 40 - VREF_40 -# set_property PACKAGE_PIN B20 [get_ports "DDR4_C1_DQ39"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ39"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_73 -# set_property PACKAGE_PIN C20 [get_ports "DDR4_C1_DQ38"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ38"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_73 -# set_property PACKAGE_PIN D19 [get_ports "DDR4_C1_DQ37"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ37"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_73 -# set_property PACKAGE_PIN D20 [get_ports "DDR4_C1_DQ36"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ36"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_73 -# set_property PACKAGE_PIN A18 [get_ports "DDR4_C1_DQS4_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_73 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS4_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_73 -# set_property PACKAGE_PIN A19 [get_ports "DDR4_C1_DQS4_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_73 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS4_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_73 -# set_property PACKAGE_PIN C18 [get_ports "DDR4_C1_DQ35"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ35"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_73 -# set_property PACKAGE_PIN C19 [get_ports "DDR4_C1_DQ34"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ34"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_73 -# set_property PACKAGE_PIN C17 [get_ports "DDR4_C1_DQ33"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ33"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_73 -# set_property PACKAGE_PIN D17 [get_ports "DDR4_C1_DQ32"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ32"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_73 -# set_property PACKAGE_PIN B17 [get_ports "GPIO_DIP_SW1"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_73 -# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW1"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_73 -# set_property PACKAGE_PIN B18 [get_ports "DDR4_C1_DM4"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM4"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_73 -# set_property PACKAGE_PIN A20 [get_ports "DDR4_C1_TEN"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T3U_N12_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_TEN"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T3U_N12_73 -# set_property PACKAGE_PIN G16 [get_ports "GPIO_DIP_SW2"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T2U_N12_73 -# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW2"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T2U_N12_73 -# set_property PACKAGE_PIN D16 [get_ports "DDR4_C1_DQ31"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ31"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_73 -# set_property PACKAGE_PIN E17 [get_ports "DDR4_C1_DQ30"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ30"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_73 -# set_property PACKAGE_PIN F20 [get_ports "DDR4_C1_DQ29"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ29"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_73 -# set_property PACKAGE_PIN G20 [get_ports "DDR4_C1_DQ28"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ28"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_73 -# set_property PACKAGE_PIN E16 [get_ports "DDR4_C1_DQS3_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_73 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS3_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_73 -# set_property PACKAGE_PIN F16 [get_ports "DDR4_C1_DQS3_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_73 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS3_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_73 -# set_property PACKAGE_PIN E18 [get_ports "DDR4_C1_DQ27"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ27"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_73 -# set_property PACKAGE_PIN E19 [get_ports "DDR4_C1_DQ26"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ26"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_73 -# set_property PACKAGE_PIN F18 [get_ports "DDR4_C1_DQ25"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ25"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_73 -# set_property PACKAGE_PIN F19 [get_ports "DDR4_C1_DQ24"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ24"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_73 -# set_property PACKAGE_PIN G17 [get_ports "5329N4285"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_73 -# set_property IOSTANDARD LVCMOSxx [get_ports "5329N4285"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_73 -# set_property PACKAGE_PIN G18 [get_ports "DDR4_C1_DM3"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM3"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_73 -# set_property PACKAGE_PIN H18 [get_ports "DDR4_C1_DQ23"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ23"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_73 -# set_property PACKAGE_PIN H19 [get_ports "DDR4_C1_DQ22"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ22"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_73 -# set_property PACKAGE_PIN H17 [get_ports "DDR4_C1_DQ21"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ21"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_73 -# set_property PACKAGE_PIN J17 [get_ports "DDR4_C1_DQ20"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ20"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_73 -# set_property PACKAGE_PIN J19 [get_ports "DDR4_C1_DQS2_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_73 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS2_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_73 -# set_property PACKAGE_PIN K19 [get_ports "DDR4_C1_DQS2_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_73 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS2_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_73 -# set_property PACKAGE_PIN K18 [get_ports "DDR4_C1_DQ19"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ19"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_73 -# set_property PACKAGE_PIN L18 [get_ports "DDR4_C1_DQ18"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ18"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_73 -# set_property PACKAGE_PIN K16 [get_ports "DDR4_C1_DQ17"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ17"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_73 -# set_property PACKAGE_PIN L16 [get_ports "DDR4_C1_DQ16"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ16"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_73 -# set_property PACKAGE_PIN J16 [get_ports "GPIO_DIP_SW3"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_73 -# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW3"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_73 -# set_property PACKAGE_PIN K17 [get_ports "DDR4_C1_DM2"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM2"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_73 -# #set_property PACKAGE_PIN T18 [get_ports "VRP_73"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_73 -# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_73"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_73 -# set_property PACKAGE_PIN M16 [get_ports "DDR4_C1_DQ15"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ15"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_73 -# set_property PACKAGE_PIN N17 [get_ports "DDR4_C1_DQ14"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ14"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_73 -# set_property PACKAGE_PIN N18 [get_ports "DDR4_C1_DQ13"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ13"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_73 -# set_property PACKAGE_PIN N19 [get_ports "DDR4_C1_DQ12"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ12"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_73 -# set_property PACKAGE_PIN P16 [get_ports "DDR4_C1_DQS1_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_73 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS1_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_73 -# set_property PACKAGE_PIN P17 [get_ports "DDR4_C1_DQS1_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_73 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS1_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_73 -# set_property PACKAGE_PIN M17 [get_ports "DDR4_C1_DQ11"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ11"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_73 -# set_property PACKAGE_PIN M18 [get_ports "DDR4_C1_DQ10"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ10"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_73 -# set_property PACKAGE_PIN P19 [get_ports "DDR4_C1_DQ9"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ9"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_73 -# set_property PACKAGE_PIN R19 [get_ports "DDR4_C1_DQ8"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ8"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_73 -# set_property PACKAGE_PIN R17 [get_ports "DDR4_C1_ALERT_B"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_ALERT_B"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_73 -# set_property PACKAGE_PIN R18 [get_ports "DDR4_C1_DM1"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_73 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM1"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_73 -# #Other net PACKAGE_PIN T19 - 5329N4282 Bank 73 - VREF_73 -# set_property PACKAGE_PIN A21 [get_ports "DDR4_C1_DQ71"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ71"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_72 -# set_property PACKAGE_PIN B21 [get_ports "DDR4_C1_DQ70"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ70"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_72 -# set_property PACKAGE_PIN B22 [get_ports "DDR4_C1_DQ69"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ69"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_72 -# set_property PACKAGE_PIN B23 [get_ports "DDR4_C1_DQ68"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ68"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_72 -# set_property PACKAGE_PIN C22 [get_ports "DDR4_C1_DQS8_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_72 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS8_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_72 -# set_property PACKAGE_PIN D22 [get_ports "DDR4_C1_DQS8_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_72 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS8_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_72 -# set_property PACKAGE_PIN C23 [get_ports "DDR4_C1_DQ67"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ67"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_72 -# set_property PACKAGE_PIN C24 [get_ports "DDR4_C1_DQ66"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ66"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_72 -# set_property PACKAGE_PIN A23 [get_ports "DDR4_C1_DQ65"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ65"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_72 -# set_property PACKAGE_PIN A24 [get_ports "DDR4_C1_DQ64"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ64"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_72 -# set_property PACKAGE_PIN D24 [get_ports "5329N4244"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_72 -# set_property IOSTANDARD LVCMOSxx [get_ports "5329N4244"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_72 -# set_property PACKAGE_PIN E24 [get_ports "DDR4_C1_DM8"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM8"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_72 -# set_property PACKAGE_PIN D21 [get_ports "GPIO_DIP_SW4"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T3U_N12_72 -# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW4"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T3U_N12_72 -# set_property PACKAGE_PIN H20 [get_ports "SI5328_INT_ALM_LS"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T2U_N12_72 -# set_property IOSTANDARD LVCMOS12 [get_ports "SI5328_INT_ALM_LS"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T2U_N12_72 -# set_property PACKAGE_PIN F23 [get_ports "DDR4_C1_DQ63"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ63"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_72 -# set_property PACKAGE_PIN F24 [get_ports "DDR4_C1_DQ62"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ62"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_72 -# set_property PACKAGE_PIN E21 [get_ports "DDR4_C1_DQ61"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ61"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_72 -# set_property PACKAGE_PIN F21 [get_ports "DDR4_C1_DQ60"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ60"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_72 -# set_property PACKAGE_PIN G23 [get_ports "DDR4_C1_DQS7_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_72 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS7_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_72 -# set_property PACKAGE_PIN H24 [get_ports "DDR4_C1_DQS7_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_72 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS7_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_72 -# set_property PACKAGE_PIN E22 [get_ports "DDR4_C1_DQ59"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ59"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_72 -# set_property PACKAGE_PIN E23 [get_ports "DDR4_C1_DQ58"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ58"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_72 -# set_property PACKAGE_PIN H22 [get_ports "DDR4_C1_DQ57"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ57"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_72 -# set_property PACKAGE_PIN H23 [get_ports "DDR4_C1_DQ56"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ56"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_72 -# set_property PACKAGE_PIN G21 [get_ports "5329N4246"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_72 -# set_property IOSTANDARD LVCMOSxx [get_ports "5329N4246"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_72 -# set_property PACKAGE_PIN G22 [get_ports "DDR4_C1_DM7"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM7"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_72 -# set_property PACKAGE_PIN J22 [get_ports "DDR4_C1_DQ55"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ55"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_72 -# set_property PACKAGE_PIN K22 [get_ports "DDR4_C1_DQ54"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ54"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_72 -# set_property PACKAGE_PIN J21 [get_ports "DDR4_C1_DQ53"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ53"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_72 -# set_property PACKAGE_PIN K21 [get_ports "DDR4_C1_DQ52"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ52"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_72 -# set_property PACKAGE_PIN L20 [get_ports "DDR4_C1_DQS6_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_72 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS6_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_72 -# set_property PACKAGE_PIN M20 [get_ports "DDR4_C1_DQS6_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_72 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS6_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_72 -# set_property PACKAGE_PIN L21 [get_ports "DDR4_C1_DQ51"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ51"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_72 -# set_property PACKAGE_PIN M21 [get_ports "DDR4_C1_DQ50"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ50"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_72 -# set_property PACKAGE_PIN J24 [get_ports "DDR4_C1_DQ49"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ49"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_72 -# set_property PACKAGE_PIN K24 [get_ports "DDR4_C1_DQ48"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ48"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_72 -# set_property PACKAGE_PIN K23 [get_ports "5329N4248"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_72 -# set_property IOSTANDARD LVCMOSxx [get_ports "5329N4248"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_72 -# set_property PACKAGE_PIN L23 [get_ports "DDR4_C1_DM6"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM6"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_72 -# set_property PACKAGE_PIN J20 [get_ports "5329N4257"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T1U_N12_72 -# set_property IOSTANDARD LVCMOSxx [get_ports "5329N4257"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T1U_N12_72 -# #set_property PACKAGE_PIN T21 [get_ports "VRP_72"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_72 -# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_72"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_72 -# set_property PACKAGE_PIN R23 [get_ports "DDR4_C1_DQ47"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ47"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_72 -# set_property PACKAGE_PIN T23 [get_ports "DDR4_C1_DQ46"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ46"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_72 -# set_property PACKAGE_PIN P22 [get_ports "DDR4_C1_DQ45"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ45"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_72 -# set_property PACKAGE_PIN R22 [get_ports "DDR4_C1_DQ44"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ44"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_72 -# set_property PACKAGE_PIN M22 [get_ports "DDR4_C1_DQS5_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_72 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS5_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_72 -# set_property PACKAGE_PIN N22 [get_ports "DDR4_C1_DQS5_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_72 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS5_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_72 -# set_property PACKAGE_PIN P21 [get_ports "DDR4_C1_DQ43"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ43"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_72 -# set_property PACKAGE_PIN R21 [get_ports "DDR4_C1_DQ42"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ42"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_72 -# set_property PACKAGE_PIN M23 [get_ports "DDR4_C1_DQ41"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ41"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_72 -# set_property PACKAGE_PIN N23 [get_ports "DDR4_C1_DQ40"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ40"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_72 -# set_property PACKAGE_PIN N20 [get_ports "DDR4_C1_RESET_B"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_72 -# set_property IOSTANDARD LVCMOS12 [get_ports "DDR4_C1_RESET_B"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_72 -# set_property PACKAGE_PIN P20 [get_ports "DDR4_C1_DM5"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_72 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM5"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_72 -# #Other net PACKAGE_PIN T20 - 5329N4288 Bank 72 - VREF_72 -# set_property PACKAGE_PIN B15 [get_ports "DDR4_C1_A1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_71 -# set_property PACKAGE_PIN B16 [get_ports "DDR4_C1_A2"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A2"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_71 -# set_property PACKAGE_PIN C14 [get_ports "DDR4_C1_A3"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A3"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_71 -# set_property PACKAGE_PIN C15 [get_ports "DDR4_C1_A4"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A4"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_71 -# set_property PACKAGE_PIN A13 [get_ports "DDR4_C1_A5"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A5"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_71 -# set_property PACKAGE_PIN A14 [get_ports "DDR4_C1_A6"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A6"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_71 -# set_property PACKAGE_PIN A15 [get_ports "DDR4_C1_A7"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A7"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_71 -# set_property PACKAGE_PIN A16 [get_ports "DDR4_C1_A8"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A8"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_71 -# set_property PACKAGE_PIN B12 [get_ports "DDR4_C1_A9"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A9"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_71 -# set_property PACKAGE_PIN C12 [get_ports "DDR4_C1_A10"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A10"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_71 -# set_property PACKAGE_PIN B13 [get_ports "DDR4_C1_A11"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A11"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_71 -# set_property PACKAGE_PIN C13 [get_ports "DDR4_C1_A12"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A12"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_71 -# set_property PACKAGE_PIN D14 [get_ports "DDR4_C1_A0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T3U_N12_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T3U_N12_71 -# set_property PACKAGE_PIN D15 [get_ports "DDR4_C1_A13"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T2U_N12_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A13"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T2U_N12_71 -# set_property PACKAGE_PIN H14 [get_ports "DDR4_C1_A14_WE_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A14_WE_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_71 -# set_property PACKAGE_PIN H15 [get_ports "DDR4_C1_A15_CAS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A15_CAS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_71 -# set_property PACKAGE_PIN F15 [get_ports "DDR4_C1_A16_RAS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A16_RAS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_71 -# set_property PACKAGE_PIN G15 [get_ports "DDR4_C1_BA0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_BA0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_71 -# set_property PACKAGE_PIN E14 [get_ports "DDR4_C1_CK_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_CK_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_71 -# set_property PACKAGE_PIN F14 [get_ports "DDR4_C1_CK_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_CK_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_71 -# set_property PACKAGE_PIN G13 [get_ports "DDR4_C1_BA1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_BA1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_71 -# set_property PACKAGE_PIN H13 [get_ports "DDR4_C1_BG0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_BG0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_71 -# set_property PACKAGE_PIN E13 [get_ports "DDR4_C1_ACT_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_ACT_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_71 -# set_property PACKAGE_PIN F13 [get_ports "DDR4_C1_CS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_CS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_71 -# set_property PACKAGE_PIN D12 [get_ports "250MHZ_CLK1_N"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "250MHZ_CLK1_N"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71 -# set_property PACKAGE_PIN E12 [get_ports "250MHZ_CLK1_P"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71 -# set_property IOSTANDARD DIFF_SSTL12 [get_ports "250MHZ_CLK1_P"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71 -# set_property PACKAGE_PIN A11 [get_ports "DDR4_C1_DQ79"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ79"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_71 -# set_property PACKAGE_PIN B11 [get_ports "DDR4_C1_DQ78"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ78"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_71 -# set_property PACKAGE_PIN B10 [get_ports "DDR4_C1_DQ77"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ77"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_71 -# set_property PACKAGE_PIN C10 [get_ports "DDR4_C1_DQ76"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ76"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_71 -# set_property PACKAGE_PIN A8 [get_ports "DDR4_C1_DQS9_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_71 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS9_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_71 -# set_property PACKAGE_PIN A9 [get_ports "DDR4_C1_DQS9_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_71 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS9_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_71 -# set_property PACKAGE_PIN B7 [get_ports "DDR4_C1_DQ75"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ75"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_71 -# set_property PACKAGE_PIN B8 [get_ports "DDR4_C1_DQ74"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ74"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_71 -# set_property PACKAGE_PIN C7 [get_ports "DDR4_C1_DQ73"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ73"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_71 -# set_property PACKAGE_PIN D7 [get_ports "DDR4_C1_DQ72"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ72"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_71 -# set_property PACKAGE_PIN C8 [get_ports "DDR4_C1_ODT"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_ODT"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_71 -# set_property PACKAGE_PIN C9 [get_ports "DDR4_C1_DM9"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM9"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_71 -# set_property PACKAGE_PIN A10 [get_ports "DDR4_C1_CKE"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T1U_N12_71 -# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_CKE"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T1U_N12_71 -# #set_property PACKAGE_PIN D8 [get_ports "VRP_71"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_71 -# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_71"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_71 -# set_property PACKAGE_PIN D9 [get_ports "DDR4_C1_DQ7"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ7"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_71 -# set_property PACKAGE_PIN E9 [get_ports "DDR4_C1_DQ6"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ6"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_71 -# set_property PACKAGE_PIN G12 [get_ports "DDR4_C1_DQ5"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ5"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_71 -# set_property PACKAGE_PIN H12 [get_ports "DDR4_C1_DQ4"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ4"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_71 -# set_property PACKAGE_PIN D10 [get_ports "DDR4_C1_DQS0_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_71 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS0_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_71 -# set_property PACKAGE_PIN D11 [get_ports "DDR4_C1_DQS0_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_71 -# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS0_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_71 -# set_property PACKAGE_PIN F9 [get_ports "DDR4_C1_DQ3"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ3"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_71 -# set_property PACKAGE_PIN F10 [get_ports "DDR4_C1_DQ2"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ2"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_71 -# set_property PACKAGE_PIN E11 [get_ports "DDR4_C1_DQ1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_71 -# set_property PACKAGE_PIN F11 [get_ports "DDR4_C1_DQ0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_71 -# set_property PACKAGE_PIN G10 [get_ports "DDR4_C1_PAR"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_PAR"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_71 -# set_property PACKAGE_PIN G11 [get_ports "DDR4_C1_DM0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_71 -# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_71 -# #Other net PACKAGE_PIN J15 - 7N8237 Bank 71 - VREF_71 -# set_property PACKAGE_PIN J12 [get_ports "FMCP_HSPC_HA22_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA22_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_70 -# set_property PACKAGE_PIN K12 [get_ports "FMCP_HSPC_HA22_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA22_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_70 -# set_property PACKAGE_PIN K13 [get_ports "FMCP_HSPC_HA21_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA21_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_70 -# set_property PACKAGE_PIN K14 [get_ports "FMCP_HSPC_HA21_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA21_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_70 -# set_property PACKAGE_PIN L11 [get_ports "FMCP_HSPC_HA14_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA14_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_70 -# set_property PACKAGE_PIN M11 [get_ports "FMCP_HSPC_HA14_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA14_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_70 -# set_property PACKAGE_PIN J11 [get_ports "FMCP_HSPC_HA23_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA23_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_70 -# set_property PACKAGE_PIN K11 [get_ports "FMCP_HSPC_HA23_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA23_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_70 -# set_property PACKAGE_PIN L13 [get_ports "FMCP_HSPC_HA19_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA19_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_70 -# set_property PACKAGE_PIN L14 [get_ports "FMCP_HSPC_HA19_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA19_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_70 -# set_property PACKAGE_PIN M12 [get_ports "FMCP_HSPC_HA15_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA15_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_70 -# set_property PACKAGE_PIN M13 [get_ports "FMCP_HSPC_HA15_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA15_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_70 -# set_property PACKAGE_PIN J14 [get_ports "30N3618"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_70 -# set_property IOSTANDARD LVCMOSxx [get_ports "30N3618"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_70 -# set_property PACKAGE_PIN N12 [get_ports "30N3617"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_70 -# set_property IOSTANDARD LVCMOSxx [get_ports "30N3617"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_70 -# set_property PACKAGE_PIN P12 [get_ports "FMCP_HSPC_HA11_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA11_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_70 -# set_property PACKAGE_PIN R12 [get_ports "FMCP_HSPC_HA11_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA11_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_70 -# set_property PACKAGE_PIN L15 [get_ports "FMCP_HSPC_HA20_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA20_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_70 -# set_property PACKAGE_PIN M15 [get_ports "FMCP_HSPC_HA20_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA20_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_70 -# set_property PACKAGE_PIN P11 [get_ports "FMCP_HSPC_HA17_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA17_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_70 -# set_property PACKAGE_PIN R11 [get_ports "FMCP_HSPC_HA17_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA17_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_70 -# set_property PACKAGE_PIN N15 [get_ports "FMCP_HSPC_HA18_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA18_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_70 -# set_property PACKAGE_PIN P15 [get_ports "FMCP_HSPC_HA18_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA18_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_70 -# set_property PACKAGE_PIN P14 [get_ports "FMCP_HSPC_HA05_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA05_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_70 -# set_property PACKAGE_PIN R14 [get_ports "FMCP_HSPC_HA05_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA05_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_70 -# set_property PACKAGE_PIN N13 [get_ports "FMCP_HSPC_HA00_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA00_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_70 -# set_property PACKAGE_PIN N14 [get_ports "FMCP_HSPC_HA00_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA00_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_70 -# set_property PACKAGE_PIN T13 [get_ports "FMCP_HSPC_HA06_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA06_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_70 -# set_property PACKAGE_PIN U13 [get_ports "FMCP_HSPC_HA06_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA06_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_70 -# set_property PACKAGE_PIN R13 [get_ports "FMCP_HSPC_HA16_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA16_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_70 -# set_property PACKAGE_PIN T14 [get_ports "FMCP_HSPC_HA16_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA16_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_70 -# set_property PACKAGE_PIN T11 [get_ports "FMCP_HSPC_HA08_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA08_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_70 -# set_property PACKAGE_PIN U11 [get_ports "FMCP_HSPC_HA08_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA08_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_70 -# set_property PACKAGE_PIN T15 [get_ports "FMCP_HSPC_HA12_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA12_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_70 -# set_property PACKAGE_PIN T16 [get_ports "FMCP_HSPC_HA12_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA12_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_70 -# set_property PACKAGE_PIN U16 [get_ports "FMCP_HSPC_HA10_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA10_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_70 -# set_property PACKAGE_PIN V16 [get_ports "FMCP_HSPC_HA10_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA10_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_70 -# set_property PACKAGE_PIN U15 [get_ports "FMCP_HSPC_HA01_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA01_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_70 -# set_property PACKAGE_PIN V15 [get_ports "FMCP_HSPC_HA01_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA01_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_70 -# set_property PACKAGE_PIN R16 [get_ports "30N3619"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_70 -# set_property IOSTANDARD LVCMOSxx [get_ports "30N3619"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_70 -# #set_property PACKAGE_PIN W15 [get_ports "VRP_70"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_70 -# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_70"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_70 -# set_property PACKAGE_PIN V14 [get_ports "FMCP_HSPC_HA09_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA09_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_70 -# set_property PACKAGE_PIN W14 [get_ports "FMCP_HSPC_HA09_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA09_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_70 -# set_property PACKAGE_PIN Y12 [get_ports "FMCP_HSPC_HA02_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA02_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_70 -# set_property PACKAGE_PIN AA12 [get_ports "FMCP_HSPC_HA02_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA02_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_70 -# set_property PACKAGE_PIN U12 [get_ports "FMCP_HSPC_HA13_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA13_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_70 -# set_property PACKAGE_PIN V13 [get_ports "FMCP_HSPC_HA13_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA13_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_70 -# set_property PACKAGE_PIN V12 [get_ports "FMCP_HSPC_HA03_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA03_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_70 -# set_property PACKAGE_PIN W12 [get_ports "FMCP_HSPC_HA03_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA03_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_70 -# set_property PACKAGE_PIN Y14 [get_ports "FMCP_HSPC_HA07_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA07_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_70 -# set_property PACKAGE_PIN AA14 [get_ports "FMCP_HSPC_HA07_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA07_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_70 -# set_property PACKAGE_PIN Y13 [get_ports "FMCP_HSPC_HA04_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA04_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_70 -# set_property PACKAGE_PIN AA13 [get_ports "FMCP_HSPC_HA04_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_70 -# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA04_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_70 -# #Other net PACKAGE_PIN AB13 - VREF_70 Bank 70 - VREF_70 -# set_property PACKAGE_PIN AV43 [get_ports "FMCP_HSPC_DP23_C2M_N"] ;# Bank 120 - MGTYTXN3_120 -# set_property PACKAGE_PIN AV42 [get_ports "FMCP_HSPC_DP23_C2M_P"] ;# Bank 120 - MGTYTXP3_120 -# set_property PACKAGE_PIN AU45 [get_ports "FMCP_HSPC_DP23_M2C_P"] ;# Bank 120 - MGTYRXP3_120 -# set_property PACKAGE_PIN AU46 [get_ports "FMCP_HSPC_DP23_M2C_N"] ;# Bank 120 - MGTYRXN3_120 -# set_property PACKAGE_PIN AM39 [get_ports "FMCP_HSPC_GBT1_5_N"] ;# Bank 120 - MGTREFCLK1N_120 -# set_property PACKAGE_PIN AM38 [get_ports "FMCP_HSPC_GBT1_5_P"] ;# Bank 120 - MGTREFCLK1P_120 -# set_property PACKAGE_PIN AY43 [get_ports "FMCP_HSPC_DP22_C2M_N"] ;# Bank 120 - MGTYTXN2_120 -# set_property PACKAGE_PIN AY42 [get_ports "FMCP_HSPC_DP22_C2M_P"] ;# Bank 120 - MGTYTXP2_120 -# set_property PACKAGE_PIN AW45 [get_ports "FMCP_HSPC_DP22_M2C_P"] ;# Bank 120 - MGTYRXP2_120 -# set_property PACKAGE_PIN AW46 [get_ports "FMCP_HSPC_DP22_M2C_N"] ;# Bank 120 - MGTYRXN2_120 -# set_property PACKAGE_PIN BB43 [get_ports "FMCP_HSPC_DP21_C2M_N"] ;# Bank 120 - MGTYTXN1_120 -# set_property PACKAGE_PIN BB42 [get_ports "FMCP_HSPC_DP21_C2M_P"] ;# Bank 120 - MGTYTXP1_120 -# set_property PACKAGE_PIN BA45 [get_ports "FMCP_HSPC_DP21_M2C_P"] ;# Bank 120 - MGTYRXP1_120 -# set_property PACKAGE_PIN BA46 [get_ports "FMCP_HSPC_DP21_M2C_N"] ;# Bank 120 - MGTYRXN1_120 -# set_property PACKAGE_PIN AN41 [get_ports "FMCP_HSPC_GBTCLK5_M2C_C_N"] ;# Bank 120 - MGTREFCLK0N_120 -# set_property PACKAGE_PIN AN40 [get_ports "FMCP_HSPC_GBTCLK5_M2C_C_P"] ;# Bank 120 - MGTREFCLK0P_120 -# set_property PACKAGE_PIN BD43 [get_ports "FMCP_HSPC_DP20_C2M_N"] ;# Bank 120 - MGTYTXN0_120 -# set_property PACKAGE_PIN BD42 [get_ports "FMCP_HSPC_DP20_C2M_P"] ;# Bank 120 - MGTYTXP0_120 -# set_property PACKAGE_PIN BC45 [get_ports "FMCP_HSPC_DP20_M2C_P"] ;# Bank 120 - MGTYRXP0_120 -# set_property PACKAGE_PIN BC46 [get_ports "FMCP_HSPC_DP20_M2C_N"] ;# Bank 120 - MGTYRXN0_120 -# set_property PACKAGE_PIN AL41 [get_ports "FMCP_HSPC_DP3_C2M_N"] ;# Bank 121 - MGTYTXN3_121 -# set_property PACKAGE_PIN AL40 [get_ports "FMCP_HSPC_DP3_C2M_P"] ;# Bank 121 - MGTYTXP3_121 -# set_property PACKAGE_PIN AJ45 [get_ports "FMCP_HSPC_DP3_M2C_P"] ;# Bank 121 - MGTYRXP3_121 -# set_property PACKAGE_PIN AJ46 [get_ports "FMCP_HSPC_DP3_M2C_N"] ;# Bank 121 - MGTYRXN3_121 -# set_property PACKAGE_PIN AH39 [get_ports "FMCP_HSPC_GBT1_0_N"] ;# Bank 121 - MGTREFCLK1N_121 -# set_property PACKAGE_PIN AH38 [get_ports "FMCP_HSPC_GBT1_0_P"] ;# Bank 121 - MGTREFCLK1P_121 -# set_property PACKAGE_PIN AM43 [get_ports "FMCP_HSPC_DP2_C2M_N"] ;# Bank 121 - MGTYTXN2_121 -# set_property PACKAGE_PIN AM42 [get_ports "FMCP_HSPC_DP2_C2M_P"] ;# Bank 121 - MGTYTXP2_121 -# set_property PACKAGE_PIN AL45 [get_ports "FMCP_HSPC_DP2_M2C_P"] ;# Bank 121 - MGTYRXP2_121 -# set_property PACKAGE_PIN AL46 [get_ports "FMCP_HSPC_DP2_M2C_N"] ;# Bank 121 - MGTYRXN2_121 -# #Other net PACKAGE_PIN BF42 - MGTAVTT_FPGA Bank 121 - MGTAVTTRCAL_LS -# set_property PACKAGE_PIN BF43 [get_ports "MGTRREF_121"] ;# Bank 121 - MGTRREF_LS -# set_property PACKAGE_PIN AP43 [get_ports "FMCP_HSPC_DP1_C2M_N"] ;# Bank 121 - MGTYTXN1_121 -# set_property PACKAGE_PIN AP42 [get_ports "FMCP_HSPC_DP1_C2M_P"] ;# Bank 121 - MGTYTXP1_121 -# set_property PACKAGE_PIN AN45 [get_ports "FMCP_HSPC_DP1_M2C_P"] ;# Bank 121 - MGTYRXP1_121 -# set_property PACKAGE_PIN AN46 [get_ports "FMCP_HSPC_DP1_M2C_N"] ;# Bank 121 - MGTYRXN1_121 -# set_property PACKAGE_PIN AK39 [get_ports "FMCP_HSPC_GBT0_0_N"] ;# Bank 121 - MGTREFCLK0N_121 -# set_property PACKAGE_PIN AK38 [get_ports "FMCP_HSPC_GBT0_0_P"] ;# Bank 121 - MGTREFCLK0P_121 -# set_property PACKAGE_PIN AT43 [get_ports "FMCP_HSPC_DP0_C2M_N"] ;# Bank 121 - MGTYTXN0_121 -# set_property PACKAGE_PIN AT42 [get_ports "FMCP_HSPC_DP0_C2M_P"] ;# Bank 121 - MGTYTXP0_121 -# set_property PACKAGE_PIN AR45 [get_ports "FMCP_HSPC_DP0_M2C_P"] ;# Bank 121 - MGTYRXP0_121 -# set_property PACKAGE_PIN AR46 [get_ports "FMCP_HSPC_DP0_M2C_N"] ;# Bank 121 - MGTYRXN0_121 -# set_property PACKAGE_PIN AE41 [get_ports "FMCP_HSPC_DP11_C2M_N"] ;# Bank 122 - MGTYTXN3_122 -# set_property PACKAGE_PIN AE40 [get_ports "FMCP_HSPC_DP11_C2M_P"] ;# Bank 122 - MGTYTXP3_122 -# set_property PACKAGE_PIN AD43 [get_ports "FMCP_HSPC_DP11_M2C_P"] ;# Bank 122 - MGTYRXP3_122 -# set_property PACKAGE_PIN AD44 [get_ports "FMCP_HSPC_DP11_M2C_N"] ;# Bank 122 - MGTYRXN3_122 -# set_property PACKAGE_PIN AD39 [get_ports "FMCP_HSPC_GBT1_2_N"] ;# Bank 122 - MGTREFCLK1N_122 -# set_property PACKAGE_PIN AD38 [get_ports "FMCP_HSPC_GBT1_2_P"] ;# Bank 122 - MGTREFCLK1P_122 -# set_property PACKAGE_PIN AG41 [get_ports "FMCP_HSPC_DP10_C2M_N"] ;# Bank 122 - MGTYTXN2_122 -# set_property PACKAGE_PIN AG40 [get_ports "FMCP_HSPC_DP10_C2M_P"] ;# Bank 122 - MGTYTXP2_122 -# set_property PACKAGE_PIN AE45 [get_ports "FMCP_HSPC_DP10_M2C_P"] ;# Bank 122 - MGTYRXP2_122 -# set_property PACKAGE_PIN AE46 [get_ports "FMCP_HSPC_DP10_M2C_N"] ;# Bank 122 - MGTYRXN2_122 -# set_property PACKAGE_PIN AJ41 [get_ports "FMCP_HSPC_DP9_C2M_N"] ;# Bank 122 - MGTYTXN1_122 -# set_property PACKAGE_PIN AJ40 [get_ports "FMCP_HSPC_DP9_C2M_P"] ;# Bank 122 - MGTYTXP1_122 -# set_property PACKAGE_PIN AF43 [get_ports "FMCP_HSPC_DP9_M2C_P"] ;# Bank 122 - MGTYRXP1_122 -# set_property PACKAGE_PIN AF44 [get_ports "FMCP_HSPC_DP9_M2C_N"] ;# Bank 122 - MGTYRXN1_122 -# set_property PACKAGE_PIN AF39 [get_ports "FMCP_HSPC_GBTCLK2_M2C_C_N"] ;# Bank 122 - MGTREFCLK0N_122 -# set_property PACKAGE_PIN AF38 [get_ports "FMCP_HSPC_GBTCLK2_M2C_C_P"] ;# Bank 122 - MGTREFCLK0P_122 -# set_property PACKAGE_PIN AK43 [get_ports "FMCP_HSPC_DP8_C2M_N"] ;# Bank 122 - MGTYTXN0_122 -# set_property PACKAGE_PIN AK42 [get_ports "FMCP_HSPC_DP8_C2M_P"] ;# Bank 122 - MGTYTXP0_122 -# set_property PACKAGE_PIN AG45 [get_ports "FMCP_HSPC_DP8_M2C_P"] ;# Bank 122 - MGTYRXP0_122 -# set_property PACKAGE_PIN AG46 [get_ports "FMCP_HSPC_DP8_M2C_N"] ;# Bank 122 - MGTYRXN0_122 -# set_property PACKAGE_PIN U41 [get_ports "FMCP_HSPC_DP15_C2M_N"] ;# Bank 125 - MGTYTXN3_125 -# set_property PACKAGE_PIN U40 [get_ports "FMCP_HSPC_DP15_C2M_P"] ;# Bank 125 - MGTYTXP3_125 -# set_property PACKAGE_PIN Y43 [get_ports "FMCP_HSPC_DP15_M2C_P"] ;# Bank 125 - MGTYRXP3_125 -# set_property PACKAGE_PIN Y44 [get_ports "FMCP_HSPC_DP15_M2C_N"] ;# Bank 125 - MGTYRXN3_125 -# set_property PACKAGE_PIN Y39 [get_ports "FMCP_HSPC_GBT1_3_N"] ;# Bank 125 - MGTREFCLK1N_125 -# set_property PACKAGE_PIN Y38 [get_ports "FMCP_HSPC_GBT1_3_P"] ;# Bank 125 - MGTREFCLK1P_125 -# set_property PACKAGE_PIN W41 [get_ports "FMCP_HSPC_DP14_C2M_N"] ;# Bank 125 - MGTYTXN2_125 -# set_property PACKAGE_PIN W40 [get_ports "FMCP_HSPC_DP14_C2M_P"] ;# Bank 125 - MGTYTXP2_125 -# set_property PACKAGE_PIN AA45 [get_ports "FMCP_HSPC_DP14_M2C_P"] ;# Bank 125 - MGTYRXP2_125 -# set_property PACKAGE_PIN AA46 [get_ports "FMCP_HSPC_DP14_M2C_N"] ;# Bank 125 - MGTYRXN2_125 -# set_property PACKAGE_PIN AA41 [get_ports "FMCP_HSPC_DP13_C2M_N"] ;# Bank 125 - MGTYTXN1_125 -# set_property PACKAGE_PIN AA40 [get_ports "FMCP_HSPC_DP13_C2M_P"] ;# Bank 125 - MGTYTXP1_125 -# set_property PACKAGE_PIN AB43 [get_ports "FMCP_HSPC_DP13_M2C_P"] ;# Bank 125 - MGTYRXP1_125 -# set_property PACKAGE_PIN AB44 [get_ports "FMCP_HSPC_DP13_M2C_N"] ;# Bank 125 - MGTYRXN1_125 -# set_property PACKAGE_PIN AB39 [get_ports "FMCP_HSPC_GBTCLK3_M2C_C_N"] ;# Bank 125 - MGTREFCLK0N_125 -# set_property PACKAGE_PIN AB38 [get_ports "FMCP_HSPC_GBTCLK3_M2C_C_P"] ;# Bank 125 - MGTREFCLK0P_125 -# set_property PACKAGE_PIN AC41 [get_ports "FMCP_HSPC_DP12_C2M_N"] ;# Bank 125 - MGTYTXN0_125 -# set_property PACKAGE_PIN AC40 [get_ports "FMCP_HSPC_DP12_C2M_P"] ;# Bank 125 - MGTYTXP0_125 -# set_property PACKAGE_PIN AC45 [get_ports "FMCP_HSPC_DP12_M2C_P"] ;# Bank 125 - MGTYRXP0_125 -# set_property PACKAGE_PIN AC46 [get_ports "FMCP_HSPC_DP12_M2C_N"] ;# Bank 125 - MGTYRXN0_125 -# set_property PACKAGE_PIN K43 [get_ports "FMCP_HSPC_DP7_C2M_N"] ;# Bank 126 - MGTYTXN3_126 -# set_property PACKAGE_PIN K42 [get_ports "FMCP_HSPC_DP7_C2M_P"] ;# Bank 126 - MGTYTXP3_126 -# set_property PACKAGE_PIN N45 [get_ports "FMCP_HSPC_DP7_M2C_P"] ;# Bank 126 - MGTYRXP3_126 -# set_property PACKAGE_PIN N46 [get_ports "FMCP_HSPC_DP7_M2C_N"] ;# Bank 126 - MGTYRXN3_126 -# set_property PACKAGE_PIN T39 [get_ports "FMCP_HSPC_GBT1_1_N"] ;# Bank 126 - MGTREFCLK1N_126 -# set_property PACKAGE_PIN T38 [get_ports "FMCP_HSPC_GBT1_1_P"] ;# Bank 126 - MGTREFCLK1P_126 -# set_property PACKAGE_PIN M43 [get_ports "FMCP_HSPC_DP6_C2M_N"] ;# Bank 126 - MGTYTXN2_126 -# set_property PACKAGE_PIN M42 [get_ports "FMCP_HSPC_DP6_C2M_P"] ;# Bank 126 - MGTYTXP2_126 -# set_property PACKAGE_PIN R45 [get_ports "FMCP_HSPC_DP6_M2C_P"] ;# Bank 126 - MGTYRXP2_126 -# set_property PACKAGE_PIN R46 [get_ports "FMCP_HSPC_DP6_M2C_N"] ;# Bank 126 - MGTYRXN2_126 -# #Other net PACKAGE_PIN L40 - MGTAVTT_FPGA Bank 126 - MGTAVTTRCAL_LN -# set_property PACKAGE_PIN L41 [get_ports "MGTRREF_126"] ;# Bank 126 - MGTRREF_LN -# set_property PACKAGE_PIN P43 [get_ports "FMCP_HSPC_DP5_C2M_N"] ;# Bank 126 - MGTYTXN1_126 -# set_property PACKAGE_PIN P42 [get_ports "FMCP_HSPC_DP5_C2M_P"] ;# Bank 126 - MGTYTXP1_126 -# set_property PACKAGE_PIN U45 [get_ports "FMCP_HSPC_DP5_M2C_P"] ;# Bank 126 - MGTYRXP1_126 -# set_property PACKAGE_PIN U46 [get_ports "FMCP_HSPC_DP5_M2C_N"] ;# Bank 126 - MGTYRXN1_126 -# set_property PACKAGE_PIN V39 [get_ports "FMCP_HSPC_GBT0_1_N"] ;# Bank 126 - MGTREFCLK0N_126 -# set_property PACKAGE_PIN V38 [get_ports "FMCP_HSPC_GBT0_1_P"] ;# Bank 126 - MGTREFCLK0P_126 -# set_property PACKAGE_PIN T43 [get_ports "FMCP_HSPC_DP4_C2M_N"] ;# Bank 126 - MGTYTXN0_126 -# set_property PACKAGE_PIN T42 [get_ports "FMCP_HSPC_DP4_C2M_P"] ;# Bank 126 - MGTYTXP0_126 -# set_property PACKAGE_PIN W45 [get_ports "FMCP_HSPC_DP4_M2C_P"] ;# Bank 126 - MGTYRXP0_126 -# set_property PACKAGE_PIN W46 [get_ports "FMCP_HSPC_DP4_M2C_N"] ;# Bank 126 - MGTYRXN0_126 -# set_property PACKAGE_PIN B43 [get_ports "FMCP_HSPC_DP19_C2M_N"] ;# Bank 127 - MGTYTXN3_127 -# set_property PACKAGE_PIN B42 [get_ports "FMCP_HSPC_DP19_C2M_P"] ;# Bank 127 - MGTYTXP3_127 -# set_property PACKAGE_PIN E45 [get_ports "FMCP_HSPC_DP19_M2C_P"] ;# Bank 127 - MGTYRXP3_127 -# set_property PACKAGE_PIN E46 [get_ports "FMCP_HSPC_DP19_M2C_N"] ;# Bank 127 - MGTYRXN3_127 -# set_property PACKAGE_PIN N41 [get_ports "FMCP_HSPC_GBT1_4_N"] ;# Bank 127 - MGTREFCLK1N_127 -# set_property PACKAGE_PIN N40 [get_ports "FMCP_HSPC_GBT1_4_P"] ;# Bank 127 - MGTREFCLK1P_127 -# set_property PACKAGE_PIN D43 [get_ports "FMCP_HSPC_DP18_C2M_N"] ;# Bank 127 - MGTYTXN2_127 -# set_property PACKAGE_PIN D42 [get_ports "FMCP_HSPC_DP18_C2M_P"] ;# Bank 127 - MGTYTXP2_127 -# set_property PACKAGE_PIN G45 [get_ports "FMCP_HSPC_DP18_M2C_P"] ;# Bank 127 - MGTYRXP2_127 -# set_property PACKAGE_PIN G46 [get_ports "FMCP_HSPC_DP18_M2C_N"] ;# Bank 127 - MGTYRXN2_127 -# set_property PACKAGE_PIN F43 [get_ports "FMCP_HSPC_DP17_C2M_N"] ;# Bank 127 - MGTYTXN1_127 -# set_property PACKAGE_PIN F42 [get_ports "FMCP_HSPC_DP17_C2M_P"] ;# Bank 127 - MGTYTXP1_127 -# set_property PACKAGE_PIN J45 [get_ports "FMCP_HSPC_DP17_M2C_P"] ;# Bank 127 - MGTYRXP1_127 -# set_property PACKAGE_PIN J46 [get_ports "FMCP_HSPC_DP17_M2C_N"] ;# Bank 127 - MGTYRXN1_127 -# set_property PACKAGE_PIN R41 [get_ports "FMCP_HSPC_GBTCLK4_M2C_C_N"] ;# Bank 127 - MGTREFCLK0N_127 -# set_property PACKAGE_PIN R40 [get_ports "FMCP_HSPC_GBTCLK4_M2C_C_P"] ;# Bank 127 - MGTREFCLK0P_127 -# set_property PACKAGE_PIN H43 [get_ports "FMCP_HSPC_DP16_C2M_N"] ;# Bank 127 - MGTYTXN0_127 -# set_property PACKAGE_PIN H42 [get_ports "FMCP_HSPC_DP16_C2M_P"] ;# Bank 127 - MGTYTXP0_127 -# set_property PACKAGE_PIN L45 [get_ports "FMCP_HSPC_DP16_M2C_P"] ;# Bank 127 - MGTYRXP0_127 -# set_property PACKAGE_PIN L46 [get_ports "FMCP_HSPC_DP16_M2C_N"] ;# Bank 127 - MGTYRXN0_127 -# set_property PACKAGE_PIN AW5 [get_ports "PCIE_TX12_P"] ;# Bank 224 - MGTYTXP3_224 -# set_property PACKAGE_PIN AT2 [get_ports "PCIE_RX12_P"] ;# Bank 224 - MGTYRXP3_224 -# set_property PACKAGE_PIN AT1 [get_ports "PCIE_RX12_N"] ;# Bank 224 - MGTYRXN3_224 -# set_property PACKAGE_PIN AW4 [get_ports "PCIE_TX12_N"] ;# Bank 224 - MGTYTXN3_224 -# set_property PACKAGE_PIN AN9 [get_ports "11N8666"] ;# Bank 224 - MGTREFCLK1P_224 -# set_property PACKAGE_PIN AN8 [get_ports "11N8667"] ;# Bank 224 - MGTREFCLK1N_224 -# set_property PACKAGE_PIN BA5 [get_ports "PCIE_TX13_P"] ;# Bank 224 - MGTYTXP2_224 -# set_property PACKAGE_PIN AV2 [get_ports "PCIE_RX13_P"] ;# Bank 224 - MGTYRXP2_224 -# set_property PACKAGE_PIN AV1 [get_ports "PCIE_RX13_N"] ;# Bank 224 - MGTYRXN2_224 -# set_property PACKAGE_PIN BA4 [get_ports "PCIE_TX13_N"] ;# Bank 224 - MGTYTXN2_224 -# set_property PACKAGE_PIN BC5 [get_ports "PCIE_TX14_P"] ;# Bank 224 - MGTYTXP1_224 -# set_property PACKAGE_PIN AY2 [get_ports "PCIE_RX14_P"] ;# Bank 224 - MGTYRXP1_224 -# set_property PACKAGE_PIN AY1 [get_ports "PCIE_RX14_N"] ;# Bank 224 - MGTYRXN1_224 -# set_property PACKAGE_PIN BC4 [get_ports "PCIE_TX14_N"] ;# Bank 224 - MGTYTXN1_224 -# set_property PACKAGE_PIN AR9 [get_ports "11N9044"] ;# Bank 224 - MGTREFCLK0P_224 -# set_property PACKAGE_PIN AR8 [get_ports "11N9045"] ;# Bank 224 - MGTREFCLK0N_224 -# set_property PACKAGE_PIN BE5 [get_ports "PCIE_TX15_P"] ;# Bank 224 - MGTYTXP0_224 -# set_property PACKAGE_PIN BB2 [get_ports "PCIE_RX15_P"] ;# Bank 224 - MGTYRXP0_224 -# set_property PACKAGE_PIN BB1 [get_ports "PCIE_RX15_N"] ;# Bank 224 - MGTYRXN0_224 -# set_property PACKAGE_PIN BE4 [get_ports "PCIE_TX15_N"] ;# Bank 224 - MGTYTXN0_224 -# set_property PACKAGE_PIN AP7 [get_ports "PCIE_TX8_P"] ;# Bank 225 - MGTYTXP3_225 -# set_property PACKAGE_PIN AJ4 [get_ports "PCIE_RX8_P"] ;# Bank 225 - MGTYRXP3_225 -# set_property PACKAGE_PIN AJ3 [get_ports "PCIE_RX8_N"] ;# Bank 225 - MGTYRXN3_225 -# set_property PACKAGE_PIN AP6 [get_ports "PCIE_TX8_N"] ;# Bank 225 - MGTYTXN3_225 -# set_property PACKAGE_PIN AJ9 [get_ports "MGT_SI570_CLOCK1_C_P"] ;# Bank 225 - MGTREFCLK1P_225 -# set_property PACKAGE_PIN AJ8 [get_ports "MGT_SI570_CLOCK1_C_N"] ;# Bank 225 - MGTREFCLK1N_225 -# set_property PACKAGE_PIN AR5 [get_ports "PCIE_TX9_P"] ;# Bank 225 - MGTYTXP2_225 -# set_property PACKAGE_PIN AK2 [get_ports "PCIE_RX9_P"] ;# Bank 225 - MGTYRXP2_225 -# set_property PACKAGE_PIN AK1 [get_ports "PCIE_RX9_N"] ;# Bank 225 - MGTYRXN2_225 -# set_property PACKAGE_PIN AR4 [get_ports "PCIE_TX9_N"] ;# Bank 225 - MGTYTXN2_225 -# set_property PACKAGE_PIN AT7 [get_ports "PCIE_TX10_P"] ;# Bank 225 - MGTYTXP1_225 -# set_property PACKAGE_PIN AM2 [get_ports "PCIE_RX10_P"] ;# Bank 225 - MGTYRXP1_225 -# set_property PACKAGE_PIN AM1 [get_ports "PCIE_RX10_N"] ;# Bank 225 - MGTYRXN1_225 -# set_property PACKAGE_PIN AT6 [get_ports "PCIE_TX10_N"] ;# Bank 225 - MGTYTXN1_225 -# set_property PACKAGE_PIN AL9 [get_ports "PCIE_CLK1_P"] ;# Bank 225 - MGTREFCLK0P_225 -# set_property PACKAGE_PIN AL8 [get_ports "PCIE_CLK1_N"] ;# Bank 225 - MGTREFCLK0N_225 -# set_property PACKAGE_PIN AU5 [get_ports "PCIE_TX11_P"] ;# Bank 225 - MGTYTXP0_225 -# set_property PACKAGE_PIN AP2 [get_ports "PCIE_RX11_P"] ;# Bank 225 - MGTYRXP0_225 -# set_property PACKAGE_PIN AP1 [get_ports "PCIE_RX11_N"] ;# Bank 225 - MGTYRXN0_225 -# set_property PACKAGE_PIN AU4 [get_ports "PCIE_TX11_N"] ;# Bank 225 - MGTYTXN0_225 -# set_property PACKAGE_PIN AH7 [get_ports "PCIE_TX4_P"] ;# Bank 226 - MGTYTXP3_226 -# set_property PACKAGE_PIN AE4 [get_ports "PCIE_RX4_P"] ;# Bank 226 - MGTYRXP3_226 -# set_property PACKAGE_PIN AE3 [get_ports "PCIE_RX4_N"] ;# Bank 226 - MGTYRXN3_226 -# set_property PACKAGE_PIN AH6 [get_ports "PCIE_TX4_N"] ;# Bank 226 - MGTYTXN3_226 -# set_property PACKAGE_PIN AE9 [get_ports "11N5839"] ;# Bank 226 - MGTREFCLK1P_226 -# set_property PACKAGE_PIN AE8 [get_ports "11N5838"] ;# Bank 226 - MGTREFCLK1N_226 -# set_property PACKAGE_PIN AK7 [get_ports "PCIE_TX5_P"] ;# Bank 226 - MGTYTXP2_226 -# set_property PACKAGE_PIN AF2 [get_ports "PCIE_RX5_P"] ;# Bank 226 - MGTYRXP2_226 -# set_property PACKAGE_PIN AF1 [get_ports "PCIE_RX5_N"] ;# Bank 226 - MGTYRXN2_226 -# set_property PACKAGE_PIN AK6 [get_ports "PCIE_TX5_N"] ;# Bank 226 - MGTYTXN2_226 -# set_property PACKAGE_PIN BD2 [get_ports "MGTRREF_226"] ;# Bank 226 - MGTRREF_RS -# #Other net PACKAGE_PIN BD3 - MGTAVTT_FPGA Bank 226 - MGTAVTTRCAL_RS -# set_property PACKAGE_PIN AM7 [get_ports "PCIE_TX6_P"] ;# Bank 226 - MGTYTXP1_226 -# set_property PACKAGE_PIN AG4 [get_ports "PCIE_RX6_P"] ;# Bank 226 - MGTYRXP1_226 -# set_property PACKAGE_PIN AG3 [get_ports "PCIE_RX6_N"] ;# Bank 226 - MGTYRXN1_226 -# set_property PACKAGE_PIN AM6 [get_ports "PCIE_TX6_N"] ;# Bank 226 - MGTYTXN1_226 -# set_property PACKAGE_PIN AG9 [get_ports "MGT226_CLK0_P"] ;# Bank 226 - MGTREFCLK0P_226 -# set_property PACKAGE_PIN AG8 [get_ports "MGT226_CLK0_N"] ;# Bank 226 - MGTREFCLK0N_226 -# set_property PACKAGE_PIN AN5 [get_ports "PCIE_TX7_P"] ;# Bank 226 - MGTYTXP0_226 -# set_property PACKAGE_PIN AH2 [get_ports "PCIE_RX7_P"] ;# Bank 226 - MGTYRXP0_226 -# set_property PACKAGE_PIN AH1 [get_ports "PCIE_RX7_N"] ;# Bank 226 - MGTYRXN0_226 -# set_property PACKAGE_PIN AN4 [get_ports "PCIE_TX7_N"] ;# Bank 226 - MGTYTXN0_226 -# set_property PACKAGE_PIN Y7 [get_ports "PCIE_TX0_P"] ;# Bank 227 - MGTYTXP3_227 -# set_property PACKAGE_PIN AA4 [get_ports "PCIE_RX0_P"] ;# Bank 227 - MGTYRXP3_227 -# set_property PACKAGE_PIN AA3 [get_ports "PCIE_RX0_N"] ;# Bank 227 - MGTYRXN3_227 -# set_property PACKAGE_PIN Y6 [get_ports "PCIE_TX0_N"] ;# Bank 227 - MGTYTXN3_227 -# set_property PACKAGE_PIN AA9 [get_ports "11N8774"] ;# Bank 227 - MGTREFCLK1P_227 -# set_property PACKAGE_PIN AA8 [get_ports "11N8775"] ;# Bank 227 - MGTREFCLK1N_227 -# set_property PACKAGE_PIN AB7 [get_ports "PCIE_TX1_P"] ;# Bank 227 - MGTYTXP2_227 -# set_property PACKAGE_PIN AB2 [get_ports "PCIE_RX1_P"] ;# Bank 227 - MGTYRXP2_227 -# set_property PACKAGE_PIN AB1 [get_ports "PCIE_RX1_N"] ;# Bank 227 - MGTYRXN2_227 -# set_property PACKAGE_PIN AB6 [get_ports "PCIE_TX1_N"] ;# Bank 227 - MGTYTXN2_227 -# set_property PACKAGE_PIN AD7 [get_ports "PCIE_TX2_P"] ;# Bank 227 - MGTYTXP1_227 -# set_property PACKAGE_PIN AC4 [get_ports "PCIE_RX2_P"] ;# Bank 227 - MGTYRXP1_227 -# set_property PACKAGE_PIN AC3 [get_ports "PCIE_RX2_N"] ;# Bank 227 - MGTYRXN1_227 -# set_property PACKAGE_PIN AD6 [get_ports "PCIE_TX2_N"] ;# Bank 227 - MGTYTXN1_227 -# set_property PACKAGE_PIN AC9 [get_ports "PCIE_CLK2_P"] ;# Bank 227 - MGTREFCLK0P_227 -# set_property PACKAGE_PIN AC8 [get_ports "PCIE_CLK2_N"] ;# Bank 227 - MGTREFCLK0N_227 -# set_property PACKAGE_PIN AF7 [get_ports "PCIE_TX3_P"] ;# Bank 227 - MGTYTXP0_227 -# set_property PACKAGE_PIN AD2 [get_ports "PCIE_RX3_P"] ;# Bank 227 - MGTYRXP0_227 -# set_property PACKAGE_PIN AD1 [get_ports "PCIE_RX3_N"] ;# Bank 227 - MGTYRXN0_227 -# set_property PACKAGE_PIN AF6 [get_ports "PCIE_TX3_N"] ;# Bank 227 - MGTYTXN0_227 -# set_property PACKAGE_PIN M7 [get_ports "QSFP1_TX4_P"] ;# Bank 231 - MGTYTXP3_231 -# set_property PACKAGE_PIN U4 [get_ports "QSFP1_RX4_P"] ;# Bank 231 - MGTYRXP3_231 -# set_property PACKAGE_PIN U3 [get_ports "QSFP1_RX4_N"] ;# Bank 231 - MGTYRXN3_231 -# set_property PACKAGE_PIN M6 [get_ports "QSFP1_TX4_N"] ;# Bank 231 - MGTYTXN3_231 -# set_property PACKAGE_PIN U9 [get_ports "SI5328_CLOCK1_C_P"] ;# Bank 231 - MGTREFCLK1P_231 -# set_property PACKAGE_PIN U8 [get_ports "SI5328_CLOCK1_C_N"] ;# Bank 231 - MGTREFCLK1N_231 -# set_property PACKAGE_PIN P7 [get_ports "QSFP1_TX3_P"] ;# Bank 231 - MGTYTXP2_231 -# set_property PACKAGE_PIN V2 [get_ports "QSFP1_RX3_P"] ;# Bank 231 - MGTYRXP2_231 -# set_property PACKAGE_PIN V1 [get_ports "QSFP1_RX3_N"] ;# Bank 231 - MGTYRXN2_231 -# set_property PACKAGE_PIN P6 [get_ports "QSFP1_TX3_N"] ;# Bank 231 - MGTYTXN2_231 -# set_property PACKAGE_PIN A4 [get_ports "MGTRREF_231"] ;# Bank 231 - MGTRREF_RN -# #Other net PACKAGE_PIN A5 - MGTAVTT_FPGA Bank 231 - MGTAVTTRCAL_RN -# set_property PACKAGE_PIN T7 [get_ports "QSFP1_TX2_P"] ;# Bank 231 - MGTYTXP1_231 -# set_property PACKAGE_PIN W4 [get_ports "QSFP1_RX2_P"] ;# Bank 231 - MGTYRXP1_231 -# set_property PACKAGE_PIN W3 [get_ports "QSFP1_RX2_N"] ;# Bank 231 - MGTYRXN1_231 -# set_property PACKAGE_PIN T6 [get_ports "QSFP1_TX2_N"] ;# Bank 231 - MGTYTXN1_231 -# set_property PACKAGE_PIN W9 [get_ports "QSFP_SI570_CLOCK_C_P"] ;# Bank 231 - MGTREFCLK0P_231 -# set_property PACKAGE_PIN W8 [get_ports "QSFP_SI570_CLOCK_C_N"] ;# Bank 231 - MGTREFCLK0N_231 -# set_property PACKAGE_PIN V7 [get_ports "QSFP1_TX1_P"] ;# Bank 231 - MGTYTXP0_231 -# set_property PACKAGE_PIN Y2 [get_ports "QSFP1_RX1_P"] ;# Bank 231 - MGTYRXP0_231 -# set_property PACKAGE_PIN Y1 [get_ports "QSFP1_RX1_N"] ;# Bank 231 - MGTYRXN0_231 -# set_property PACKAGE_PIN V6 [get_ports "QSFP1_TX1_N"] ;# Bank 231 - MGTYTXN0_231 -# set_property PACKAGE_PIN H7 [get_ports "QSFP2_TX4_P"] ;# Bank 232 - MGTYTXP3_232 -# set_property PACKAGE_PIN M2 [get_ports "QSFP2_RX4_P"] ;# Bank 232 - MGTYRXP3_232 -# set_property PACKAGE_PIN M1 [get_ports "QSFP2_RX4_N"] ;# Bank 232 - MGTYRXN3_232 -# set_property PACKAGE_PIN H6 [get_ports "QSFP2_TX4_N"] ;# Bank 232 - MGTYTXN3_232 -# set_property PACKAGE_PIN N9 [get_ports "SI5328_CLOCK2_C_P"] ;# Bank 232 - MGTREFCLK1P_232 -# set_property PACKAGE_PIN N8 [get_ports "SI5328_CLOCK2_C_N"] ;# Bank 232 - MGTREFCLK1N_232 -# set_property PACKAGE_PIN J5 [get_ports "QSFP2_TX3_P"] ;# Bank 232 - MGTYTXP2_232 -# set_property PACKAGE_PIN P2 [get_ports "QSFP2_RX3_P"] ;# Bank 232 - MGTYRXP2_232 -# set_property PACKAGE_PIN P1 [get_ports "QSFP2_RX3_N"] ;# Bank 232 - MGTYRXN2_232 -# set_property PACKAGE_PIN J4 [get_ports "QSFP2_TX3_N"] ;# Bank 232 - MGTYTXN2_232 -# set_property PACKAGE_PIN K7 [get_ports "QSFP2_TX2_P"] ;# Bank 232 - MGTYTXP1_232 -# set_property PACKAGE_PIN R4 [get_ports "QSFP2_RX2_P"] ;# Bank 232 - MGTYRXP1_232 -# set_property PACKAGE_PIN R3 [get_ports "QSFP2_RX2_N"] ;# Bank 232 - MGTYRXN1_232 -# set_property PACKAGE_PIN K6 [get_ports "QSFP2_TX2_N"] ;# Bank 232 - MGTYTXN1_232 -# set_property PACKAGE_PIN R9 [get_ports "MGT_SI570_CLOCK2_C_P"] ;# Bank 232 - MGTREFCLK0P_232 -# set_property PACKAGE_PIN R8 [get_ports "MGT_SI570_CLOCK2_C_N"] ;# Bank 232 - MGTREFCLK0N_232 -# set_property PACKAGE_PIN L5 [get_ports "QSFP2_TX1_P"] ;# Bank 232 - MGTYTXP0_232 -# set_property PACKAGE_PIN T2 [get_ports "QSFP2_RX1_P"] ;# Bank 232 - MGTYRXP0_232 -# set_property PACKAGE_PIN T1 [get_ports "QSFP2_RX1_N"] ;# Bank 232 - MGTYRXN0_232 -# set_property PACKAGE_PIN L4 [get_ports "QSFP2_TX1_N"] ;# Bank 232 - MGTYTXN0_232 -# set_property PACKAGE_PIN C5 [get_ports "FIREFLY_TX4_P"] ;# Bank 233 - MGTYTXP3_233 -# set_property PACKAGE_PIN D2 [get_ports "FIREFLY_RX4_P"] ;# Bank 233 - MGTYRXP3_233 -# set_property PACKAGE_PIN D1 [get_ports "FIREFLY_RX4_N"] ;# Bank 233 - MGTYRXN3_233 -# set_property PACKAGE_PIN C4 [get_ports "FIREFLY_TX4_N"] ;# Bank 233 - MGTYTXN3_233 -# set_property PACKAGE_PIN J9 [get_ports "MGT233_CLK1_P"] ;# Bank 233 - MGTREFCLK1P_233 -# set_property PACKAGE_PIN J8 [get_ports "MGT233_CLK1_N"] ;# Bank 233 - MGTREFCLK1N_233 -# set_property PACKAGE_PIN E5 [get_ports "FIREFLY_TX3_P"] ;# Bank 233 - MGTYTXP2_233 -# set_property PACKAGE_PIN F2 [get_ports "FIREFLY_RX3_P"] ;# Bank 233 - MGTYRXP2_233 -# set_property PACKAGE_PIN F1 [get_ports "FIREFLY_RX3_N"] ;# Bank 233 - MGTYRXN2_233 -# set_property PACKAGE_PIN E4 [get_ports "FIREFLY_TX3_N"] ;# Bank 233 - MGTYTXN2_233 -# set_property PACKAGE_PIN F7 [get_ports "FIREFLY_TX2_P"] ;# Bank 233 - MGTYTXP1_233 -# set_property PACKAGE_PIN H2 [get_ports "FIREFLY_RX2_P"] ;# Bank 233 - MGTYRXP1_233 -# set_property PACKAGE_PIN H1 [get_ports "FIREFLY_RX2_N"] ;# Bank 233 - MGTYRXN1_233 -# set_property PACKAGE_PIN F6 [get_ports "FIREFLY_TX2_N"] ;# Bank 233 - MGTYTXN1_233 -# set_property PACKAGE_PIN L9 [get_ports "MGT_SI570_CLOCK3_C_P"] ;# Bank 233 - MGTREFCLK0P_233 -# set_property PACKAGE_PIN L8 [get_ports "MGT_SI570_CLOCK3_C_N"] ;# Bank 233 - MGTREFCLK0N_233 -# set_property PACKAGE_PIN G5 [get_ports "FIREFLY_TX1_P"] ;# Bank 233 - MGTYTXP0_233 -# set_property PACKAGE_PIN K2 [get_ports "FIREFLY_RX1_P"] ;# Bank 233 - MGTYRXP0_233 -# set_property PACKAGE_PIN K1 [get_ports "FIREFLY_RX1_N"] ;# Bank 233 - MGTYRXN0_233 -# set_property PACKAGE_PIN G4 [get_ports "FIREFLY_TX1_N"] ;# Bank 233 - MGTYTXN0_233 +set_property PACKAGE_PIN C8 [get_ports {c0_ddr4_odt[0]}] +set_property PACKAGE_PIN N20 [get_ports c0_ddr4_reset_n] diff --git a/corev_apu/fpga/scripts/run.tcl b/corev_apu/fpga/scripts/run.tcl index 9ba9d4e187..34fc9be495 100644 --- a/corev_apu/fpga/scripts/run.tcl +++ b/corev_apu/fpga/scripts/run.tcl @@ -24,12 +24,16 @@ if {$::env(BOARD) eq "genesys2"} { add_files -fileset constrs_1 -norecurse constraints/vc707.xdc } elseif {$::env(BOARD) eq "nexys_video"} { add_files -fileset constrs_1 -norecurse constraints/nexys_video.xdc +} elseif {$::env(BOARD) eq "vcu118"} { + add_files -fileset constrs_1 -norecurse constraints/vcu118.xdc } else { exit 1 } read_ip { \ - "xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci" \ + "xilinx/xlnx_axi_dwidth_converter_512_64/xlnx_axi_dwidth_converter_512_64.srcs/sources_1/ip/xlnx_axi_dwidth_converter_512_64/xlnx_axi_dwidth_converter_512_64.xci" \ + "xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.srcs/sources_1/ip/xlnx_mig_ddr4/xlnx_mig_ddr4.xci" \ + "xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci" \ "xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.xci" \ "xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.xci" \ @@ -69,6 +73,10 @@ if {$::env(BOARD) eq "genesys2"} { read_verilog -sv {src/nexys_video.svh ../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh} set file "src/nexys_video.svh" set registers "../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh" +} elseif {$::env(BOARD) eq "vcu118"} { + read_verilog -sv {src/vcu118.svh ../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh} + set file "src/vcu118.svh" + set registers "../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh" } else { exit 1 } diff --git a/corev_apu/fpga/src/ariane_xilinx.sv b/corev_apu/fpga/src/ariane_xilinx.sv index 20e77f77c2..b9ea420c32 100644 --- a/corev_apu/fpga/src/ariane_xilinx.sv +++ b/corev_apu/fpga/src/ariane_xilinx.sv @@ -10,7 +10,7 @@ // Description: Xilinx FPGA top-level // Author: Florian Zaruba - +`include "vcu118.svh" module ariane_xilinx ( // WARNING: Do not define input parameters. This causes the FPGA build to fail. `ifdef GENESYSII @@ -112,6 +112,8 @@ module ariane_xilinx ( input logic [ 7:0] sw , output logic fan_pwm , input logic trst , + + `elsif VCU118 input wire c0_sys_clk_p , // 250 MHz Clock for DDR input wire c0_sys_clk_n , // 250 MHz Clock for DDR @@ -133,11 +135,11 @@ module ariane_xilinx ( output wire c0_ddr4_act_n , output wire [0:0] c0_ddr4_ck_c , output wire [0:0] c0_ddr4_ck_t , - output wire [7:0] pci_exp_txp , - output wire [7:0] pci_exp_txn , - input wire [7:0] pci_exp_rxp , - input wire [7:0] pci_exp_rxn , input logic trst_n , + output wire gnd_jtag , + output wire vcc_jtag , + output wire vcc_reset_jtag , + `elsif NEXYS_VIDEO input logic sys_clk_i , input logic cpu_resetn , @@ -186,6 +188,12 @@ module ariane_xilinx ( output logic tx ); +// Assign values to gnd_jtag and vcc_jtag +assign gnd_jtag = 1'b0; +assign vcc_jtag = 1'b1; +assign vcc_reset_jtag = 1'b1; + + // CVA6 Xilinx configuration function automatic config_pkg::cva6_cfg_t build_fpga_config(config_pkg::cva6_user_cfg_t CVA6UserCfg); config_pkg::cva6_user_cfg_t cfg = CVA6UserCfg; @@ -261,7 +269,8 @@ logic phy_tx_clk; logic sd_clk_sys; logic ddr_sync_reset; -logic ddr_clock_out; +logic ddr_clock_out; //250 mHZ +logic ddr_clock_out_200; logic rst_n, rst; logic rtc; @@ -277,7 +286,7 @@ assign cpu_reset = ~cpu_resetn; assign cpu_resetn = ~cpu_reset; `elsif VC707 assign cpu_resetn = ~cpu_reset; -assign trst_n = ~trst; +//assign trst_n = ~trst; `elsif NEXYS_VIDEO logic cpu_reset; assign cpu_reset = ~cpu_resetn; @@ -876,7 +885,7 @@ ariane_peripherals #( .InclSPI ( 1'b1 ), .InclEthernet ( 1'b0 ) `elsif VCU118 - .InclSPI ( 1'b0 ), + .InclSPI ( 1'b1 ), .InclEthernet ( 1'b0 ) `elsif NEXYS_VIDEO .InclSPI ( 1'b1 ), @@ -896,25 +905,39 @@ ariane_peripherals #( .irq_o ( irq ), .rx_i ( rx ), .tx_o ( tx ), - .eth_txck, - .eth_rxck, - .eth_rxctl, - .eth_rxd, - .eth_rst_n, - .eth_txctl, - .eth_txd, - .eth_mdio, - .eth_mdc, - .phy_tx_clk_i ( phy_tx_clk ), + .sd_clk_i ( sd_clk_sys ), .spi_clk_o ( spi_clk_o ), .spi_mosi ( spi_mosi ), .spi_miso ( spi_miso ), .spi_ss ( spi_ss ), `ifdef KC705 + .eth_txck, + .eth_rxck, + .eth_rxctl, + .eth_rxd, + .eth_rst_n, + .eth_txctl, + .eth_txd, + .eth_mdio, + .eth_mdc, + .phy_tx_clk_i ( phy_tx_clk ), .leds_o ( {led[3:0], unused_led[7:4]}), .dip_switches_i ( {sw, unused_switches} ) + `elsif VCU118 + .leds_o ( led ), + .dip_switches_i ( {sw, unused_switches} ) `else + .eth_txck, + .eth_rxck, + .eth_rxctl, + .eth_rxd, + .eth_rst_n, + .eth_txctl, + .eth_txd, + .eth_mdio, + .eth_mdc, + .phy_tx_clk_i ( phy_tx_clk ), .leds_o ( led ), .dip_switches_i ( sw ) `endif @@ -1089,7 +1112,7 @@ xlnx_axi_clock_converter i_xlnx_axi_clock_converter_ddr ( .s_axi_rvalid ( dram.r_valid ), .s_axi_rready ( dram.r_ready ), // to size converter - .m_axi_aclk ( ddr_clock_out ), + .m_axi_aclk ( ddr_clock_out ), //250 Mhz .m_axi_aresetn ( ndmreset_n ), .m_axi_awid ( s_axi_awid ), .m_axi_awaddr ( s_axi_awaddr ), @@ -1153,9 +1176,9 @@ xlnx_clk_gen i_xlnx_clk_gen ( .clk_out4 ( sd_clk_sys ), // 50 MHz clock .reset ( cpu_reset ), .locked ( pll_locked ), - .clk_in1 ( ddr_clock_out ) + .clk_in1 ( clk_200MHz_ref ) // 200MHz input clock ); -assign clk_200MHz_ref = ddr_clock_out; +assign clk_200MHz_ref = ddr_clock_out_200; `endif @@ -1192,7 +1215,7 @@ xlnx_mig_7_ddr3 i_ddr ( .app_sr_active ( ), // keep open .app_ref_ack ( ), // keep open .app_zq_ack ( ), // keep open - .ui_clk ( ddr_clock_out ), + .ui_clk ( clk_200MHz_ref ), // attention changement ici pour garder 200Mhz (pas nécessaire si pas utilisé ddr3) .ui_clk_sync_rst ( ddr_sync_reset ), .aresetn ( ndmreset_n ), .s_axi_awid, @@ -1269,7 +1292,7 @@ xlnx_mig_7_ddr3 i_ddr ( .app_sr_active ( ), // keep open .app_ref_ack ( ), // keep open .app_zq_ack ( ), // keep open - .ui_clk ( ddr_clock_out ), + .ui_clk ( clk_200MHz_ref ), // attention changement ici pour garder 200Mhz (pas nécessaire si pas utilisé ddr3) .ui_clk_sync_rst ( ddr_sync_reset ), .aresetn ( ndmreset_n ), .s_axi_awid, @@ -1346,7 +1369,7 @@ xlnx_mig_7_ddr3 i_ddr ( .app_sr_active ( ), // keep open .app_ref_ack ( ), // keep open .app_zq_ack ( ), // keep open - .ui_clk ( ddr_clock_out ), + .ui_clk ( clk_200MHz_ref ), .ui_clk_sync_rst ( ddr_sync_reset ), .aresetn ( ndmreset_n ), .s_axi_awid, @@ -1426,8 +1449,8 @@ xlnx_mig_7_ddr3 i_ddr ( logic [1:0] dram_dwidth_axi_rresp; logic [511:0] dram_dwidth_axi_rdata; -axi_dwidth_converter_512_64 i_axi_dwidth_converter_512_64 ( - .s_axi_aclk ( ddr_clock_out ), +xlnx_axi_dwidth_converter_512_64 i_axi_dwidth_converter_512_64 ( + .s_axi_aclk ( ddr_clock_out ), //250 MHz .s_axi_aresetn ( ndmreset_n ), .s_axi_awid ( s_axi_awid ), @@ -1507,7 +1530,7 @@ axi_dwidth_converter_512_64 i_axi_dwidth_converter_512_64 ( .m_axi_rready ( dram_dwidth_axi_rready ) ); - ddr4_0 i_ddr ( + xlnx_mig_ddr4 i_ddr ( .c0_init_calib_complete ( ), .dbg_clk ( ), .c0_sys_clk_p ( c0_sys_clk_p ), @@ -1529,6 +1552,7 @@ axi_dwidth_converter_512_64 i_axi_dwidth_converter_512_64 ( .c0_ddr4_ck_t ( c0_ddr4_ck_t ), .c0_ddr4_ui_clk ( ddr_clock_out ), .c0_ddr4_ui_clk_sync_rst( ddr_sync_reset ), + .addn_ui_clkout1 (clk_200MHz_ref ), .c0_ddr4_aresetn ( ndmreset_n ), .c0_ddr4_s_axi_awid ( '0 ), .c0_ddr4_s_axi_awaddr ( dram_dwidth_axi_awaddr[30:0] ), @@ -1571,339 +1595,6 @@ axi_dwidth_converter_512_64 i_axi_dwidth_converter_512_64 ( ); - logic pcie_ref_clk; - logic pcie_ref_clk_gt; - - logic pcie_axi_clk; - logic pcie_axi_rstn; - - logic pcie_axi_awready; - logic pcie_axi_wready; - logic [3:0] pcie_axi_bid; - logic [1:0] pcie_axi_bresp; - logic pcie_axi_bvalid; - logic pcie_axi_arready; - logic [3:0] pcie_axi_rid; - logic [255:0] pcie_axi_rdata; - logic [1:0] pcie_axi_rresp; - logic pcie_axi_rlast; - logic pcie_axi_rvalid; - logic [3:0] pcie_axi_awid; - logic [63:0] pcie_axi_awaddr; - logic [7:0] pcie_axi_awlen; - logic [2:0] pcie_axi_awsize; - logic [1:0] pcie_axi_awburst; - logic [2:0] pcie_axi_awprot; - logic pcie_axi_awvalid; - logic pcie_axi_awlock; - logic [3:0] pcie_axi_awcache; - logic [255:0] pcie_axi_wdata; - logic [31:0] pcie_axi_wstrb; - logic pcie_axi_wlast; - logic pcie_axi_wvalid; - logic pcie_axi_bready; - logic [3:0] pcie_axi_arid; - logic [63:0] pcie_axi_araddr; - logic [7:0] pcie_axi_arlen; - logic [2:0] pcie_axi_arsize; - logic [1:0] pcie_axi_arburst; - logic [2:0] pcie_axi_arprot; - logic pcie_axi_arvalid; - logic pcie_axi_arlock; - logic [3:0] pcie_axi_arcache; - logic pcie_axi_rready; - - logic [63:0] pcie_dwidth_axi_awaddr; - logic [7:0] pcie_dwidth_axi_awlen; - logic [2:0] pcie_dwidth_axi_awsize; - logic [1:0] pcie_dwidth_axi_awburst; - logic [0:0] pcie_dwidth_axi_awlock; - logic [3:0] pcie_dwidth_axi_awcache; - logic [2:0] pcie_dwidth_axi_awprot; - logic [3:0] pcie_dwidth_axi_awregion; - logic [3:0] pcie_dwidth_axi_awqos; - logic pcie_dwidth_axi_awvalid; - logic pcie_dwidth_axi_awready; - logic [63:0] pcie_dwidth_axi_wdata; - logic [7:0] pcie_dwidth_axi_wstrb; - logic pcie_dwidth_axi_wlast; - logic pcie_dwidth_axi_wvalid; - logic pcie_dwidth_axi_wready; - logic [1:0] pcie_dwidth_axi_bresp; - logic pcie_dwidth_axi_bvalid; - logic pcie_dwidth_axi_bready; - logic [63:0] pcie_dwidth_axi_araddr; - logic [7:0] pcie_dwidth_axi_arlen; - logic [2:0] pcie_dwidth_axi_arsize; - logic [1:0] pcie_dwidth_axi_arburst; - logic [0:0] pcie_dwidth_axi_arlock; - logic [3:0] pcie_dwidth_axi_arcache; - logic [2:0] pcie_dwidth_axi_arprot; - logic [3:0] pcie_dwidth_axi_arregion; - logic [3:0] pcie_dwidth_axi_arqos; - logic pcie_dwidth_axi_arvalid; - logic pcie_dwidth_axi_arready; - logic [63:0] pcie_dwidth_axi_rdata; - logic [1:0] pcie_dwidth_axi_rresp; - logic pcie_dwidth_axi_rlast; - logic pcie_dwidth_axi_rvalid; - logic pcie_dwidth_axi_rready; - - // PCIe Reset - logic sys_rst_n_c; - IBUF sys_reset_n_ibuf (.O(sys_rst_n_c), .I(sys_rst_n)); - - IBUFDS_GTE4 #( - .REFCLK_HROW_CK_SEL ( 2'b00 ) - ) IBUFDS_GTE4_inst ( - .O ( pcie_ref_clk_gt ), - .ODIV2 ( pcie_ref_clk ), - .CEB ( 1'b0 ), - .I ( sys_clk_p ), - .IB ( sys_clk_n ) - ); - - // 250 MHz AXI - xdma_0 i_xdma ( - .sys_clk ( pcie_ref_clk ), - .sys_clk_gt ( pcie_ref_clk_gt ), - .sys_rst_n ( sys_rst_n_c ), - .user_lnk_up ( ), - - // Tx - .pci_exp_txp ( pci_exp_txp ), - .pci_exp_txn ( pci_exp_txn ), - // Rx - .pci_exp_rxp ( pci_exp_rxp ), - .pci_exp_rxn ( pci_exp_rxn ), - .usr_irq_req ( 1'b0 ), - .usr_irq_ack ( ), - .msi_enable ( ), - .msi_vector_width ( ), - .axi_aclk ( pcie_axi_clk ), - .axi_aresetn ( pcie_axi_rstn ), - .m_axi_awready ( pcie_axi_awready ), - .m_axi_wready ( pcie_axi_wready ), - .m_axi_bid ( pcie_axi_bid ), - .m_axi_bresp ( pcie_axi_bresp ), - .m_axi_bvalid ( pcie_axi_bvalid ), - .m_axi_arready ( pcie_axi_arready ), - .m_axi_rid ( pcie_axi_rid ), - .m_axi_rdata ( pcie_axi_rdata ), - .m_axi_rresp ( pcie_axi_rresp ), - .m_axi_rlast ( pcie_axi_rlast ), - .m_axi_rvalid ( pcie_axi_rvalid ), - .m_axi_awid ( pcie_axi_awid ), - .m_axi_awaddr ( pcie_axi_awaddr ), - .m_axi_awlen ( pcie_axi_awlen ), - .m_axi_awsize ( pcie_axi_awsize ), - .m_axi_awburst ( pcie_axi_awburst ), - .m_axi_awprot ( pcie_axi_awprot ), - .m_axi_awvalid ( pcie_axi_awvalid ), - .m_axi_awlock ( pcie_axi_awlock ), - .m_axi_awcache ( pcie_axi_awcache ), - .m_axi_wdata ( pcie_axi_wdata ), - .m_axi_wstrb ( pcie_axi_wstrb ), - .m_axi_wlast ( pcie_axi_wlast ), - .m_axi_wvalid ( pcie_axi_wvalid ), - .m_axi_bready ( pcie_axi_bready ), - .m_axi_arid ( pcie_axi_arid ), - .m_axi_araddr ( pcie_axi_araddr ), - .m_axi_arlen ( pcie_axi_arlen ), - .m_axi_arsize ( pcie_axi_arsize ), - .m_axi_arburst ( pcie_axi_arburst ), - .m_axi_arprot ( pcie_axi_arprot ), - .m_axi_arvalid ( pcie_axi_arvalid ), - .m_axi_arlock ( pcie_axi_arlock ), - .m_axi_arcache ( pcie_axi_arcache ), - .m_axi_rready ( pcie_axi_rready ), - - .cfg_mgmt_addr ( '0 ), - .cfg_mgmt_write ( '0 ), - .cfg_mgmt_write_data ( '0 ), - .cfg_mgmt_byte_enable ( '0 ), - .cfg_mgmt_read ( '0 ), - .cfg_mgmt_read_data ( ), - .cfg_mgmt_read_write_done ( ) - ); - - axi_dwidth_converter_256_64 i_axi_dwidth_converter_256_64 ( - .s_axi_aclk ( pcie_axi_clk ), - .s_axi_aresetn ( pcie_axi_rstn ), - .s_axi_awid ( pcie_axi_awid ), - .s_axi_awaddr ( pcie_axi_awaddr ), - .s_axi_awlen ( pcie_axi_awlen ), - .s_axi_awsize ( pcie_axi_awsize ), - .s_axi_awburst ( pcie_axi_awburst ), - .s_axi_awlock ( pcie_axi_awlock ), - .s_axi_awcache ( pcie_axi_awcache ), - .s_axi_awprot ( pcie_axi_awprot ), - .s_axi_awregion ( '0 ), - .s_axi_awqos ( '0 ), - .s_axi_awvalid ( pcie_axi_awvalid ), - .s_axi_awready ( pcie_axi_awready ), - .s_axi_wdata ( pcie_axi_wdata ), - .s_axi_wstrb ( pcie_axi_wstrb ), - .s_axi_wlast ( pcie_axi_wlast ), - .s_axi_wvalid ( pcie_axi_wvalid ), - .s_axi_wready ( pcie_axi_wready ), - .s_axi_bid ( pcie_axi_bid ), - .s_axi_bresp ( pcie_axi_rresp ), - .s_axi_bvalid ( pcie_axi_bvalid ), - .s_axi_bready ( pcie_axi_bready ), - .s_axi_arid ( pcie_axi_arid ), - .s_axi_araddr ( pcie_axi_araddr ), - .s_axi_arlen ( pcie_axi_arlen ), - .s_axi_arsize ( pcie_axi_arsize ), - .s_axi_arburst ( pcie_axi_arburst ), - .s_axi_arlock ( pcie_axi_arlock ), - .s_axi_arcache ( pcie_axi_arcache ), - .s_axi_arprot ( pcie_axi_arprot ), - .s_axi_arregion ( '0 ), - .s_axi_arqos ( '0 ), - .s_axi_arvalid ( pcie_axi_arvalid ), - .s_axi_arready ( pcie_axi_arready ), - .s_axi_rid ( pcie_axi_rid ), - .s_axi_rdata ( pcie_axi_rdata ), - .s_axi_rresp ( pcie_axi_bresp ), - .s_axi_rlast ( pcie_axi_rlast ), - .s_axi_rvalid ( pcie_axi_rvalid ), - .s_axi_rready ( pcie_axi_rready ), - - .m_axi_awaddr ( pcie_dwidth_axi_awaddr ), - .m_axi_awlen ( pcie_dwidth_axi_awlen ), - .m_axi_awsize ( pcie_dwidth_axi_awsize ), - .m_axi_awburst ( pcie_dwidth_axi_awburst ), - .m_axi_awlock ( pcie_dwidth_axi_awlock ), - .m_axi_awcache ( pcie_dwidth_axi_awcache ), - .m_axi_awprot ( pcie_dwidth_axi_awprot ), - .m_axi_awregion ( pcie_dwidth_axi_awregion ), - .m_axi_awqos ( pcie_dwidth_axi_awqos ), - .m_axi_awvalid ( pcie_dwidth_axi_awvalid ), - .m_axi_awready ( pcie_dwidth_axi_awready ), - .m_axi_wdata ( pcie_dwidth_axi_wdata ), - .m_axi_wstrb ( pcie_dwidth_axi_wstrb ), - .m_axi_wlast ( pcie_dwidth_axi_wlast ), - .m_axi_wvalid ( pcie_dwidth_axi_wvalid ), - .m_axi_wready ( pcie_dwidth_axi_wready ), - .m_axi_bresp ( pcie_dwidth_axi_bresp ), - .m_axi_bvalid ( pcie_dwidth_axi_bvalid ), - .m_axi_bready ( pcie_dwidth_axi_bready ), - .m_axi_araddr ( pcie_dwidth_axi_araddr ), - .m_axi_arlen ( pcie_dwidth_axi_arlen ), - .m_axi_arsize ( pcie_dwidth_axi_arsize ), - .m_axi_arburst ( pcie_dwidth_axi_arburst ), - .m_axi_arlock ( pcie_dwidth_axi_arlock ), - .m_axi_arcache ( pcie_dwidth_axi_arcache ), - .m_axi_arprot ( pcie_dwidth_axi_arprot ), - .m_axi_arregion ( pcie_dwidth_axi_arregion ), - .m_axi_arqos ( pcie_dwidth_axi_arqos ), - .m_axi_arvalid ( pcie_dwidth_axi_arvalid ), - .m_axi_arready ( pcie_dwidth_axi_arready ), - .m_axi_rdata ( pcie_dwidth_axi_rdata ), - .m_axi_rresp ( pcie_dwidth_axi_rresp ), - .m_axi_rlast ( pcie_dwidth_axi_rlast ), - .m_axi_rvalid ( pcie_dwidth_axi_rvalid ), - .m_axi_rready ( pcie_dwidth_axi_rready ) - ); - - -assign slave[1].aw_user = '0; -assign slave[1].ar_user = '0; -assign slave[1].w_user = '0; - -logic [3:0] slave_b_id; -logic [3:0] slave_r_id; - -assign slave[1].b_id = slave_b_id[1:0]; -assign slave[1].r_id = slave_r_id[1:0]; - -// PCIe Clock Converter -axi_clock_converter_0 pcie_axi_clock_converter ( - .m_axi_aclk ( clk ), - .m_axi_aresetn ( ndmreset_n ), - .m_axi_awid ( {2'b0, slave[1].aw_id} ), - .m_axi_awaddr ( slave[1].aw_addr ), - .m_axi_awlen ( slave[1].aw_len ), - .m_axi_awsize ( slave[1].aw_size ), - .m_axi_awburst ( slave[1].aw_burst ), - .m_axi_awlock ( slave[1].aw_lock ), - .m_axi_awcache ( slave[1].aw_cache ), - .m_axi_awprot ( slave[1].aw_prot ), - .m_axi_awregion ( slave[1].aw_region ), - .m_axi_awqos ( slave[1].aw_qos ), - .m_axi_awvalid ( slave[1].aw_valid ), - .m_axi_awready ( slave[1].aw_ready ), - .m_axi_wdata ( slave[1].w_data ), - .m_axi_wstrb ( slave[1].w_strb ), - .m_axi_wlast ( slave[1].w_last ), - .m_axi_wvalid ( slave[1].w_valid ), - .m_axi_wready ( slave[1].w_ready ), - .m_axi_bid ( slave_b_id ), - .m_axi_bresp ( slave[1].b_resp ), - .m_axi_bvalid ( slave[1].b_valid ), - .m_axi_bready ( slave[1].b_ready ), - .m_axi_arid ( {2'b0, slave[1].ar_id} ), - .m_axi_araddr ( slave[1].ar_addr ), - .m_axi_arlen ( slave[1].ar_len ), - .m_axi_arsize ( slave[1].ar_size ), - .m_axi_arburst ( slave[1].ar_burst ), - .m_axi_arlock ( slave[1].ar_lock ), - .m_axi_arcache ( slave[1].ar_cache ), - .m_axi_arprot ( slave[1].ar_prot ), - .m_axi_arregion ( slave[1].ar_region ), - .m_axi_arqos ( slave[1].ar_qos ), - .m_axi_arvalid ( slave[1].ar_valid ), - .m_axi_arready ( slave[1].ar_ready ), - .m_axi_rid ( slave_r_id ), - .m_axi_rdata ( slave[1].r_data ), - .m_axi_rresp ( slave[1].r_resp ), - .m_axi_rlast ( slave[1].r_last ), - .m_axi_rvalid ( slave[1].r_valid ), - .m_axi_rready ( slave[1].r_ready ), - // from size converter - .s_axi_aclk ( pcie_axi_clk ), - .s_axi_aresetn ( ndmreset_n ), - .s_axi_awid ( '0 ), - .s_axi_awaddr ( pcie_dwidth_axi_awaddr ), - .s_axi_awlen ( pcie_dwidth_axi_awlen ), - .s_axi_awsize ( pcie_dwidth_axi_awsize ), - .s_axi_awburst ( pcie_dwidth_axi_awburst ), - .s_axi_awlock ( pcie_dwidth_axi_awlock ), - .s_axi_awcache ( pcie_dwidth_axi_awcache ), - .s_axi_awprot ( pcie_dwidth_axi_awprot ), - .s_axi_awregion ( pcie_dwidth_axi_awregion ), - .s_axi_awqos ( pcie_dwidth_axi_awqos ), - .s_axi_awvalid ( pcie_dwidth_axi_awvalid ), - .s_axi_awready ( pcie_dwidth_axi_awready ), - .s_axi_wdata ( pcie_dwidth_axi_wdata ), - .s_axi_wstrb ( pcie_dwidth_axi_wstrb ), - .s_axi_wlast ( pcie_dwidth_axi_wlast ), - .s_axi_wvalid ( pcie_dwidth_axi_wvalid ), - .s_axi_wready ( pcie_dwidth_axi_wready ), - .s_axi_bid ( ), - .s_axi_bresp ( pcie_dwidth_axi_bresp ), - .s_axi_bvalid ( pcie_dwidth_axi_bvalid ), - .s_axi_bready ( pcie_dwidth_axi_bready ), - .s_axi_arid ( '0 ), - .s_axi_araddr ( pcie_dwidth_axi_araddr ), - .s_axi_arlen ( pcie_dwidth_axi_arlen ), - .s_axi_arsize ( pcie_dwidth_axi_arsize ), - .s_axi_arburst ( pcie_dwidth_axi_arburst ), - .s_axi_arlock ( pcie_dwidth_axi_arlock ), - .s_axi_arcache ( pcie_dwidth_axi_arcache ), - .s_axi_arprot ( pcie_dwidth_axi_arprot ), - .s_axi_arregion ( pcie_dwidth_axi_arregion ), - .s_axi_arqos ( pcie_dwidth_axi_arqos ), - .s_axi_arvalid ( pcie_dwidth_axi_arvalid ), - .s_axi_arready ( pcie_dwidth_axi_arready ), - .s_axi_rid ( ), - .s_axi_rdata ( pcie_dwidth_axi_rdata ), - .s_axi_rresp ( pcie_dwidth_axi_rresp ), - .s_axi_rlast ( pcie_dwidth_axi_rlast ), - .s_axi_rvalid ( pcie_dwidth_axi_rvalid ), - .s_axi_rready ( pcie_dwidth_axi_rready ) -); `endif endmodule diff --git a/corev_apu/fpga/src/vcu118.svh b/corev_apu/fpga/src/vcu118.svh index 47440a844b..552d026a85 100644 --- a/corev_apu/fpga/src/vcu118.svh +++ b/corev_apu/fpga/src/vcu118.svh @@ -12,3 +12,14 @@ // Author: Florian Zaruba `define VCU118 + +`define ARIANE_DATA_WIDTH 64 + +// Instantiate protocl checker +// `define PROTOCOL_CHECKER + +// write-back cache +// `define WB_DCACHE + +// write-through cache +`define WT_DCACHE \ No newline at end of file diff --git a/corev_apu/fpga/vivado_pid1143288.str b/corev_apu/fpga/vivado_pid1143288.str new file mode 100644 index 0000000000..5ecd1ac51a --- /dev/null +++ b/corev_apu/fpga/vivado_pid1143288.str @@ -0,0 +1,2450 @@ +/* + +AMD Vivado v2023.1 (64-bit) [Major: 2023, Minor: 1] +SW Build: 3865809 on Sun May 7 15:04:56 MDT 2023 +IP Build: 3864474 on Sun May 7 20:36:21 MDT 2023 +IP Build: 3864474 on Sun May 7 20:36:21 MDT 2023 + +Process ID (PID): 1143288 +License: Customer +Mode: GUI Mode + +Current time: Tue Apr 29 11:20:14 CEST 2025 +Time zone: Central European Standard Time (Europe/Paris) + +OS: Ubuntu +OS Version: 6.11.0-24-generic +OS Architecture: amd64 +Available processors (cores): 22 + +Display: 1 +Screen size: 1920x1080 +Screen resolution (DPI): 100 +Available screens: 3 +Default font: family=Dialog,name=Dialog,style=plain,size=12 +Scale size: 12 +OS font scaling: 100% + +Java version: 17.0.3 64-bit +JavaFX version: 17.0.1 +Java home: /tools/Xilinx/Vivado/2023.1/tps/lnx64/jre17.0.3_7 +Java executable: /tools/Xilinx/Vivado/2023.1/tps/lnx64/jre17.0.3_7/bin/java +Java arguments: [-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Djdk.gtk.version=2, -Dsun.java2d.uiScale.enabled=false, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, -XX:+UseStringDeduplication, -XX:MaxGCPauseMillis=200, -XX:+ParallelRefProcEnabled, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/java.awt.event=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-exports=java.base/java.nio=ALL-UNNAMED, --add-exports=java.desktop/sun.swing=ALL-UNNAMED, --add-exports=java.desktop/javax.swing=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-exports=java.desktop/sun.swing=ALL-UNNAMED, --add-exports=java.desktop/sun.swing.table=ALL-UNNAMED, --add-exports=java.desktop/sun.swing.plaf.synth=ALL-UNNAMED, --add-exports=java.desktop/sun.awt.shell=ALL-UNNAMED, --add-exports=java.base/sun.security.action=ALL-UNNAMED, --add-exports=java.desktop/sun.font=ALL-UNNAMED, --add-opens=java.desktop/sun.awt.X11=ALL-UNNAMED, -XX:NewSize=80m, -XX:MaxNewSize=80m, -Xms512m, -Xmx4072m, -Xss10m, -Xrs] +Java initial memory (-Xms): 512 MB +Java maximum memory (-Xmx): 3 GB + +User name: stagiaire +User home directory: /home/stagiaire +User working directory: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga +User country: US +User language: en +User locale: en_US + +RDI_BASEROOT: /tools/Xilinx/Vivado +HDI_APPROOT: /tools/Xilinx/Vivado/2023.1 +RDI_DATADIR: /tools/Xilinx/SharedData/2023.1/data:/tools/Xilinx/Vivado/2023.1/data +RDI_BINDIR: /tools/Xilinx/Vivado/2023.1/bin + +Vivado preferences file: /home/stagiaire/.Xilinx/Vivado/2023.1/vivado.xml +Vivado preferences directory: /home/stagiaire/.Xilinx/Vivado/2023.1/ +Vivado layouts directory: /home/stagiaire/.Xilinx/Vivado/2023.1/data/layouts +PlanAhead jar file: /tools/Xilinx/Vivado/2023.1/lib/classes/planAhead.jar +Vivado log file: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/vivado.log +Vivado journal file: +Engine tmp dir: ./.Xil/Vivado-1143288-qdtis2423h +Non-Default Parameters: [] + +Xilinx & AMD Environment Variables +-------------------------------------------------------------------------------------------- +GNOME_SHELL_SESSION_MODE: ubuntu +RDI_APPROOT: /tools/Xilinx/Vivado/2023.1 +RDI_BASEROOT: /tools/Xilinx/Vivado +RDI_BINROOT: /tools/Xilinx/Vivado/2023.1/bin +RDI_BUILD: yes +RDI_DATADIR: /tools/Xilinx/SharedData/2023.1/data:/tools/Xilinx/Vivado/2023.1/data +RDI_INSTALLROOT: /tools/Xilinx +RDI_INSTALLVER: 2023.1 +RDI_JAVA_PLATFORM: +RDI_JAVA_VERSION: 17.0.3_7 +RDI_LIBDIR: /tools/Xilinx/Vivado/2023.1/lib/lnx64.o/Ubuntu:/tools/Xilinx/Vivado/2023.1/lib/lnx64.o +RDI_OPT_EXT: .o +RDI_PATCHROOT: +RDI_PLATFORM: lnx64 +RDI_PREPEND_PATH: /tools/Xilinx/Vitis/2023.1/bin:/tools/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/lin64 +RDI_PROG: /tools/Xilinx/Vivado/2023.1/bin/unwrapped/lnx64.o/vivado +RDI_SESSION_INFO: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga:qdtis2423h_1745918403_1143220 +RDI_SHARED_DATA: /tools/Xilinx/SharedData/2023.1/data +RDI_TPS_ROOT: /tools/Xilinx/Vivado/2023.1/tps/lnx64 +RDI_USE_JDK17: True +SHELL: /bin/bash +XILINX: /tools/Xilinx/Vivado/2023.1/ids_lite/ISE +XILINX_BOARD: xilinx.com:vcu118:part0:2.0 +XILINX_DSP: /tools/Xilinx/Vivado/2023.1/ids_lite/ISE +XILINX_HLS: /tools/Xilinx/Vitis_HLS/2023.1 +XILINX_PART: xcvu9p-flga2104-2L-e +XILINX_PLANAHEAD: /tools/Xilinx/Vivado/2023.1 +XILINX_SDK: /tools/Xilinx/Vitis/2023.1 +XILINX_VITIS: /tools/Xilinx/Vitis/2023.1 +XILINX_VIVADO: /tools/Xilinx/Vivado/2023.1 +XILINX_VIVADO_HLS: /tools/Xilinx/Vivado/2023.1 + + +GUI allocated memory: 512 MB +GUI max memory: 4,072 MB +Engine allocated memory: 2,458 MB + +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + +*/ + +// TclEventType: START_GUI +// TclEventType: START_PROGRESS_DIALOG +// Tcl Message: start_gui +// TclEventType: START_PROGRESS_DIALOG +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: FLOW_ADDED +// Tcl Message: source scripts/prologue.tcl +// Tcl Message: # set project ariane # create_project $project . -force -part $::env(XILINX_PART) +// TclEventType: FILE_SET_NEW +// TclEventType: RUN_ADD +// TclEventType: RUN_CURRENT +// TclEventType: PROJECT_DASHBOARD_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_NEW +// [GUI Memory]: 101 MB (+103447kb) [00:00:08] +// [Engine Memory]: 2,544 MB (+2516257kb) [00:00:08] +// [GUI Memory]: 127 MB (+21953kb) [00:00:09] +// WARNING: HEventQueue.dispatchEvent() is taking 1065 ms. +// TclEventType: FILE_SET_OPTIONS_CHANGE +// HMemoryUtils.trashcanNow. Engine heap size: 2,707 MB. GUI used memory: 75 MB. Current time: 4/29/25, 11:20:15 AM CEST +// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2023.1/data/ip'. +// TclEventType: FILE_SET_OPTIONS_CHANGE +// [Engine Memory]: 2,710 MB (+40355kb) [00:00:09] +// TclEventType: FILE_SET_OPTIONS_CHANGE +// TclEventType: BOARD_MODIFIED +// TclEventType: MSGMGR_REFRESH_MSG +// TclEventType: STOP_PROGRESS_DIALOG +// Tcl Message: create_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 8734.203 ; gain = 533.395 ; free physical = 11039 ; free virtual = 18775 +// Tcl Message: # set_property board_part $::env(XILINX_BOARD) [current_project] # set_param general.maxThreads 8 # set_msg_config -id {[Synth 8-5858]} -new_severity "info" # set_msg_config -id {[Synth 8-4480]} -limit 1000 +dismissDialog("Sourcing Tcl script 'scripts/prologue.tcl'"); // bq +// TclEventType: STOP_PROGRESS_DIALOG +// TclEventType: START_PROGRESS_DIALOG +// TclEventType: FILE_SET_CHANGE +// TclEventType: FILE_SET_OPTIONS_CHANGE +// TclEventType: FILE_SET_CHANGE +// Tcl Message: source scripts/run.tcl +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// Tcl Message: # add_files -fileset constrs_1 -norecurse constraints/$project.xdc # synth_design -rtl -name rtl_1 +// Tcl Message: Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xcvu9p-flga2104-2L-e Top: ariane_xilinx +// TclEventType: ELABORATE_START +// [Engine Memory]: 3,735 MB (+932648kb) [00:00:23] +// HMemoryUtils.trashcanNow. Engine heap size: 4,424 MB. GUI used memory: 77 MB. Current time: 4/29/25, 11:20:35 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 4,875 MB. GUI used memory: 76 MB. Current time: 4/29/25, 11:20:47 AM CEST +// TclEventType: ELABORATE_FINISH +// HMemoryUtils.trashcanNow. Engine heap size: 5,634 MB. GUI used memory: 76 MB. Current time: 4/29/25, 11:21:05 AM CEST +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_CNS_STALE +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: SIGNAL_INTERFACE_ADD +// TclEventType: SIGNAL_HIERARCHY_CHANGED +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// [Engine Memory]: 5,842 MB (+2013560kb) [00:01:06] +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: FLOORPLAN_MODIFY +// TclEventType: DESIGN_NEW +// HMemoryUtils.trashcanNow. Engine heap size: 5,884 MB. GUI used memory: 76 MB. Current time: 4/29/25, 11:21:13 AM CEST +// [GUI Memory]: 170 MB (+38744kb) [00:01:08] +// TclEventType: DESIGN_NEW +// [GUI Memory]: 184 MB (+4868kb) [00:01:08] +// [GUI Memory]: 211 MB (+19580kb) [00:01:08] +// [GUI Memory]: 226 MB (+4440kb) [00:01:09] +// Xgd.load filename: /tools/Xilinx/Vivado/2023.1/data/parts/xilinx/virtexuplus/devint/virtexuplus/xcvu9p/xcvu9p.xgd; ZipEntry: xcvu9p_detail.xgd elapsed time: 0.9s +// DeviceModel: Load Xgds SwingWorker Join Forever elapsed time: 1s +// [GUI Memory]: 249 MB (+12167kb) [00:01:09] +// [Engine Memory]: 6,412 MB (+291514kb) [00:01:09] +// TclEventType: CURR_DESIGN_SET +// WARNING: HEventQueue.dispatchEvent() is taking 1405 ms. +// Tcl Message: INFO: [Device 21-403] Loading part xcvu9p-flga2104-2L-e +// Tcl Message: INFO: [Synth 8-11241] undeclared symbol 'dout', assumed default net type 'wire' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/ariane-ethernet/dualmem_widen8.sv:88] +// Tcl Message: INFO: [Synth 8-11241] undeclared symbol 'led', assumed default net type 'wire' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/ariane_xilinx.sv:919] INFO: [Synth 8-11241] undeclared symbol 'sw', assumed default net type 'wire' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/ariane_xilinx.sv:920] INFO: [Synth 8-11241] undeclared symbol 'unused_switches', assumed default net type 'wire' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/ariane_xilinx.sv:920] +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 10094.648 ; gain = 321.711 ; free physical = 9508 ; free virtual = 17392 +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'ariane_xilinx' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/ariane_xilinx.sv:14] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 4 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 4 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'axi_xbar' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/axi/src/axi_xbar.sv:18] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'addr_decode' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/addr_decode.sv:30] +// Tcl Message: Parameter NoIndices bound to: 32'b00000000000000000000000000001010 Parameter NoRules bound to: 32'b00000000000000000000000000001010 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'addr_decode' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/addr_decode.sv:30] INFO: [Synth 8-6157] synthesizing module 'axi_demux' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/axi/src/axi_demux.sv:19] +// Tcl Message: Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter NoMstPorts bound to: 32'b00000000000000000000000000001011 Parameter MaxTrans bound to: 32'b00000000000000000000000000000001 Parameter AxiLookBits bound to: 32'b00000000000000000000000000000100 Parameter UniqueIds bound to: 1'b0 Parameter FallThrough bound to: 1'b0 Parameter SpillAw bound to: 1'b1 Parameter SpillW bound to: 1'b1 Parameter SpillB bound to: 1'b1 Parameter SpillAr bound to: 1'b1 Parameter SpillR bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'axi_demux_id_counters' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/axi/src/axi_demux.sv:576] +// Tcl Message: Parameter AxiIdBits bound to: 32'b00000000000000000000000000000100 Parameter CounterWidth bound to: 32'b00000000000000000000000000000001 +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-6157] synthesizing module 'delta_counter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000000001 Parameter STICKY_OVERFLOW bound to: 1'b0 +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'fifo_v3' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized1' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized1' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized1' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized1' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000001011 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'lzc' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/lzc.sv:25] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000001011 Parameter MODE bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lzc' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized2' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized2' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized3' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized3' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000001011 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6155] done synthesizing module 'axi_demux' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/axi/src/axi_demux.sv:19] INFO: [Synth 8-6157] synthesizing module 'axi_err_slv' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/axi/src/axi_err_slv.sv:19] +// Tcl Message: Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter Resp bound to: 2'b11 Parameter ATOPs bound to: 1'b1 Parameter MaxTrans bound to: 32'b00000000000000000000000000000100 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'axi_atop_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/axi/src/axi_atop_filter.sv:37] +// Tcl Message: Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter AxiMaxWriteTxns bound to: 32'b00000000000000000000000000000100 +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b1 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized1' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized2' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized3' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'counter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/counter.sv:14] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000001000 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'delta_counter__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000001000 Parameter STICKY_OVERFLOW bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'delta_counter__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] INFO: [Synth 8-6155] done synthesizing module 'counter' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/counter.sv:14] INFO: [Synth 8-6155] done synthesizing module 'axi_err_slv' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/axi/src/axi_err_slv.sv:19] INFO: [Synth 8-6157] synthesizing module 'axi_mux' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/axi/src/axi_mux.sv:27] +// Tcl Message: Parameter SlvAxiIDWidth bound to: 32'b00000000000000000000000000000100 Parameter NoSlvPorts bound to: 32'b00000000000000000000000000000010 Parameter MaxWTrans bound to: 32'b00000000000000000000000000000001 Parameter FallThrough bound to: 1'b0 Parameter SpillAw bound to: 1'b1 Parameter SpillW bound to: 1'b1 Parameter SpillB bound to: 1'b1 Parameter SpillAr bound to: 1'b1 Parameter SpillR bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'axi_id_prepend' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/axi/src/axi_id_prepend.sv:18] +// Tcl Message: Parameter NoBus bound to: 1 - type: integer Parameter AxiIdWidthSlvPort bound to: 32'b00000000000000000000000000000100 Parameter AxiIdWidthMstPort bound to: 32'b00000000000000000000000000000101 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'axi_id_prepend' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/axi/src/axi_id_prepend.sv:18] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree__parameterized1' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000000010 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'lzc__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/lzc.sv:25] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000000010 Parameter MODE bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized1' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized4' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized4' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized4' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized4' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized4' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized4' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized5' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized5' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized5' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized5' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000000010 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized2' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized6' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized6' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized6' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized6' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized7' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized7' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: Parameter IrLength bound to: 32'b00000000000000000000000000000101 Parameter IdcodeValue bound to: 1 - type: integer +// Tcl Message: Parameter NrHarts bound to: 32'b00000000000000000000000000000001 Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter SelectableHarts bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'dm_csrs' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/riscv-dbg/src/dm_csrs.sv:18] +// Tcl Message: Parameter NrHarts bound to: 32'b00000000000000000000000000000001 Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter SelectableHarts bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/riscv-dbg/src/dm_csrs.sv:294] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/riscv-dbg/src/dm_csrs.sv:360] INFO: [Synth 8-6157] synthesizing module 'fifo_v2__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv:13] +// Tcl Message: Parameter DEPTH bound to: 32'b00000000000000000000000000000010 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized5' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized5' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6155] done synthesizing module 'fifo_v2__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv:13] INFO: [Synth 8-6155] done synthesizing module 'dm_csrs' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/riscv-dbg/src/dm_csrs.sv:18] INFO: [Synth 8-6157] synthesizing module 'dm_sba' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/riscv-dbg/src/dm_sba.sv:18] +// Tcl Message: Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter ReadByteEnable bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/riscv-dbg/src/dm_sba.sv:72] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/riscv-dbg/src/dm_sba.sv:101] INFO: [Synth 8-6155] done synthesizing module 'dm_sba' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/riscv-dbg/src/dm_sba.sv:18] INFO: [Synth 8-6157] synthesizing module 'dm_mem' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/riscv-dbg/src/dm_mem.sv:19] +// Tcl Message: Parameter NrHarts bound to: 32'b00000000000000000000000000000001 Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter SelectableHarts bound to: 1'b1 Parameter DmBaseAddress bound to: 32'b00000000000000000001000000000000 +// Tcl Message: Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_ADDR_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cache_subsystem/axi_adapter.sv:486] INFO: [Synth 8-6155] done synthesizing module 'axi_adapter' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cache_subsystem/axi_adapter.sv:19] INFO: [Synth 8-6157] synthesizing module 'ariane' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/src/ariane.sv:17] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'cva6' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cva6.sv:18] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'perf_counters' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/perf_counters.sv:16] +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'perf_counters' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/perf_counters.sv:16] INFO: [Synth 8-6157] synthesizing module 'wt_cache_subsystem' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cache_subsystem/wt_cache_subsystem.sv:22] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'cva6_icache' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cache_subsystem/cva6_icache.sv:28] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'sram_cache' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/common/local/util/sram_cache.sv:21] +// Tcl Message: Parameter DATA_WIDTH bound to: 45 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer Parameter BYTE_ACCESS bound to: 0 - type: integer Parameter TECHNO_CUT bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'sram' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/common/local/util/sram.sv:21] +// Tcl Message: Parameter DATA_WIDTH bound to: 45 - type: integer Parameter USER_WIDTH bound to: 1 - type: integer Parameter USER_EN bound to: 0 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'tc_sram_wrapper' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/common/local/util/tc_sram_fpga_wrapper.sv:10] +// Tcl Message: Parameter NumWords bound to: 256 - type: integer Parameter DataWidth bound to: 32'b00000000000000000000000001000000 Parameter ByteWidth bound to: 8 - type: integer Parameter NumPorts bound to: 1 - type: integer Parameter Latency bound to: 1 - type: integer Parameter SimInit bound to: none - type: string Parameter PrintSimCfg bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'SyncSpRamBeNx64' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv:28] +// Tcl Message: Parameter ADDR_WIDTH bound to: 8 - type: integer Parameter DATA_DEPTH bound to: 256 - type: integer Parameter OUT_REGS bound to: 0 - type: integer Parameter SIM_INIT bound to: 1 - type: integer +// Tcl Message: Parameter DATA_WIDTH bound to: 128 - type: integer Parameter USER_WIDTH bound to: 128 - type: integer Parameter USER_EN bound to: 0 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer Parameter BYTE_ACCESS bound to: 0 - type: integer Parameter TECHNO_CUT bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'sram__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/common/local/util/sram.sv:21] +// Tcl Message: Parameter DATA_WIDTH bound to: 128 - type: integer Parameter USER_WIDTH bound to: 128 - type: integer Parameter USER_EN bound to: 0 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'sram__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/common/local/util/sram.sv:21] INFO: [Synth 8-6155] done synthesizing module 'sram_cache__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/common/local/util/sram_cache.sv:21] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cache_subsystem/cva6_icache.sv:220] INFO: [Synth 8-6157] synthesizing module 'lzc__parameterized1' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/lzc.sv:25] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000000100 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized1' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Synth 8-6157] synthesizing module 'lfsr' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/lfsr.sv:22] +// Tcl Message: Parameter LfsrWidth bound to: 32'b00000000000000000000000000001000 Parameter OutWidth bound to: 32'b00000000000000000000000000000010 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lfsr' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/lfsr.sv:22] INFO: [Synth 8-6155] done synthesizing module 'cva6_icache' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cache_subsystem/cva6_icache.sv:28] INFO: [Synth 8-6157] synthesizing module 'wt_dcache' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cache_subsystem/wt_dcache.sv:16] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'wt_dcache_ctrl' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cache_subsystem/wt_dcache_ctrl.sv:16] +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cache_subsystem/wt_dcache_ctrl.sv:134] INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cache_subsystem/wt_dcache_ctrl.sv:134] INFO: [Synth 8-6155] done synthesizing module 'wt_dcache_ctrl' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cache_subsystem/wt_dcache_ctrl.sv:16] INFO: [Synth 8-6157] synthesizing module 'wt_dcache_missunit' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cache_subsystem/wt_dcache_missunit.sv:17] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'lzc__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000001000 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized2' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/lzc.sv:25] +// Tcl Message: Parameter LfsrWidth bound to: 32'b00000000000000000000000000001000 Parameter OutWidth bound to: 32'b00000000000000000000000000000011 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/lfsr.sv:22] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cache_subsystem/wt_dcache_missunit.sv:98] +// Tcl Message: Parameter Seed bound to: 32'b00000000000000000000000000000011 Parameter MaxExp bound to: 32'b00000000000000000000000000010000 +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/include/wt_cache_pkg.sv:134] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cache_subsystem/wt_dcache_wbuffer.sv:142] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cache_subsystem/wt_dcache_wbuffer.sv:116] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000000010 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter FPGA_EN bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'cva6_fifo_v3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cva6_fifo_v3.sv:16] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000000100 Parameter DataWidth bound to: 32'b00000000000000000000000000000001 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000001000 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized4' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/frontend/frontend.sv:235] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/frontend/frontend.sv:235] +// Tcl Message: Parameter FPGA_ALTERA bound to: 1'b0 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter FPGA_EN bound to: 1'b0 Parameter FPGA_ALTERA bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FPGA_EN bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/include/ariane_pkg.sv:562] +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/issue_read_operands.sv:382] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/issue_read_operands.sv:399] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000001001 Parameter ExtPrio bound to: 1'b1 Parameter AxiVldRdy bound to: 1'b1 +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000001101 Parameter DataWidth bound to: 32'b00000000000000000000000001000000 Parameter ExtPrio bound to: 1'b1 Parameter AxiVldRdy bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/fpu_wrap.sv:440] +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cvfpu/src/fpnew_rounding.sv:48] +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cvfpu/src/fpnew_rounding.sv:48] +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cvfpu/src/fpnew_pkg.sv:89] +// Tcl Message: Parameter AbsWidth bound to: 32'b00000000000000000000000001000000 +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cvfpu/src/fpnew_rounding.sv:48] INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/core/cvfpu/src/fpnew_pkg.sv:89] +// Tcl Message: Parameter DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FPGA_EN bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/clint/axi_lite_interface.sv:78] +// Tcl Message: Parameter STAGES bound to: 32'b00000000000000000000000000000010 Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-155] case statement is not full and has no default [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/axi_mem_if/src/axi2mem.sv:192] INFO: [Synth 8-155] case statement is not full and has no default [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/axi_mem_if/src/axi2mem.sv:234] INFO: [Synth 8-155] case statement is not full and has no default [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/axi_mem_if/src/axi2mem.sv:122] +// Tcl Message: Parameter AxiAddrWidth bound to: 64 - type: integer Parameter AxiDataWidth bound to: 64 - type: integer Parameter AxiIdWidth bound to: 5 - type: integer Parameter AxiUserWidth bound to: 64 - type: integer Parameter InclUART bound to: 1'b1 Parameter InclSPI bound to: 1'b1 Parameter InclEthernet bound to: 1'b0 Parameter InclGPIO bound to: 1'b1 +// Tcl Message: Parameter SIZE bound to: 2 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:28' bound to instance 'UART_IF_CTS' of component 'slib_input_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:402] INFO: [Synth 8-638] synthesizing module 'slib_input_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:41] +// Tcl Message: Parameter SIZE bound to: 2 - type: integer +// Tcl Message: INFO: [Synth 8-256] done synthesizing module 'slib_input_filter' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:41] +// Tcl Message: Parameter SIZE bound to: 2 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:28' bound to instance 'UART_IF_DSR' of component 'slib_input_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:403] +// Tcl Message: Parameter SIZE bound to: 2 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:28' bound to instance 'UART_IF_DCD' of component 'slib_input_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:404] +// Tcl Message: Parameter SIZE bound to: 2 - type: integer +// Tcl Message: Parameter RATIO bound to: 8 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_clock_div' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_clock_div.vhd:29' bound to instance 'UART_BG2' of component 'slib_clock_div' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:752] INFO: [Synth 8-638] synthesizing module 'slib_clock_div' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_clock_div.vhd:41] +// Tcl Message: Parameter RATIO bound to: 8 - type: integer +// Tcl Message: INFO: [Synth 8-256] done synthesizing module 'slib_clock_div' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_clock_div.vhd:41] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_edge_detect.vhd:28' bound to instance 'UART_RCLK' of component 'slib_edge_detect' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:758] +// Tcl Message: Parameter WIDTH bound to: 8 - type: integer Parameter SIZE_E bound to: 6 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_fifo' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_fifo.vhd:29' bound to instance 'UART_TXFF' of component 'slib_fifo' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:765] INFO: [Synth 8-638] synthesizing module 'slib_fifo' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_fifo.vhd:48] +// Tcl Message: Parameter WIDTH bound to: 8 - type: integer Parameter SIZE_E bound to: 6 - type: integer +// Tcl Message: INFO: [Synth 8-256] done synthesizing module 'slib_fifo' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_fifo.vhd:48] +// Tcl Message: Parameter WIDTH bound to: 11 - type: integer Parameter SIZE_E bound to: 6 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_fifo' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_fifo.vhd:29' bound to instance 'UART_RXFF' of component 'slib_fifo' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:784] INFO: [Synth 8-638] synthesizing module 'slib_fifo__parameterized1' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_fifo.vhd:48] +// Tcl Message: Parameter WIDTH bound to: 11 - type: integer Parameter SIZE_E bound to: 6 - type: integer +// Tcl Message: Parameter WIDTH bound to: 4 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_counter' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_counter.vhd:29' bound to instance 'RX_BRC' of component 'slib_counter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/uart_receiver.vhd:122] INFO: [Synth 8-638] synthesizing module 'slib_counter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_counter.vhd:46] +// Tcl Message: Parameter WIDTH bound to: 4 - type: integer +// Tcl Message: INFO: [Synth 8-256] done synthesizing module 'slib_counter' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_counter.vhd:46] +// Tcl Message: Parameter WIDTH bound to: 4 - type: integer Parameter THRESHOLD bound to: 10 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_mv_filter' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_mv_filter.vhd:29' bound to instance 'RX_MVF' of component 'slib_mv_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/uart_receiver.vhd:137] INFO: [Synth 8-638] synthesizing module 'slib_mv_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_mv_filter.vhd:44] +// Tcl Message: Parameter WIDTH bound to: 4 - type: integer Parameter THRESHOLD bound to: 10 - type: integer +// Tcl Message: INFO: [Synth 8-256] done synthesizing module 'slib_mv_filter' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_mv_filter.vhd:44] +// Tcl Message: Parameter SIZE bound to: 4 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:28' bound to instance 'RX_IFSB' of component 'slib_input_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/uart_receiver.vhd:150] INFO: [Synth 8-638] synthesizing module 'slib_input_filter__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:41] +// Tcl Message: Parameter SIZE bound to: 4 - type: integer +// Tcl Message: INFO: [Synth 8-155] case statement is not full and has no default [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_timer/timer.sv:92] INFO: [Synth 8-155] case statement is not full and has no default [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/apb_timer/timer.sv:116] +// Tcl Message: Parameter ADDR_WIDTH bound to: 32'sb00000000000000000000000000100000 Parameter DATA_WIDTH bound to: 32'sb00000000000000000000000000100000 Parameter N_SOURCE bound to: 32'sb00000000000000000000000000011110 Parameter N_TARGET bound to: 32'sb00000000000000000000000000000010 Parameter MAX_PRIO bound to: 32'sb00000000000000000000000000000111 Parameter N_SOURCE bound to: 32'sb00000000000000000000000000011110 Parameter MAX_PRIO bound to: 32'sb00000000000000000000000000000111 Parameter ALGORITHM bound to: SEQUENTIAL - type: string Parameter N_SOURCE bound to: 32'sb00000000000000000000000000011110 +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv:580] INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv:809] +// Tcl Message: Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv:39] +// Tcl Message: INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +// Tcl Message: INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: Finished RTL Elaboration : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 10892.938 ; gain = 1120.000 ; free physical = 8535 ; free virtual = 16478 +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- +// Tcl Message: Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 10892.938 ; gain = 1120.000 ; free physical = 8509 ; free virtual = 16475 +// Tcl Message: --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- +// Tcl Message: Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 10892.938 ; gain = 1120.000 ; free physical = 8509 ; free virtual = 16475 +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 10932.688 ; gain = 0.000 ; free physical = 8643 ; free virtual = 16579 +// Tcl Message: INFO: [Netlist 29-17] Analyzing 1083 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.1 INFO: [Project 1-570] Preparing netlist for logic optimization +// Tcl Message: INFO: [Opt 31-140] Inserted 2 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 3 OBUFs to IO ports without IO buffers. +// Tcl Message: Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/bd_0/ip/ip_0/bd_f0c7_microblaze_I_0.xdc] for cell 'i_ddr/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0' Finished Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/bd_0/ip/ip_0/bd_f0c7_microblaze_I_0.xdc] for cell 'i_ddr/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0' +// Tcl Message: INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/bd_0/ip/ip_0/bd_f0c7_microblaze_I_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +// Tcl Message: Finished Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/par/xlnx_mig_ddr4.xdc] for cell 'i_ddr/inst' +// Tcl Message: INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/par/xlnx_mig_ddr4.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +// Tcl Message: INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.gen/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +// Tcl Message: INFO: [Timing 38-2] Deriving generated clocks +// Tcl Message: Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/constraints/vcu118.xdc] +// Tcl Message: Finished Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/constraints/vcu118.xdc] +// Tcl Message: INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/constraints/vcu118.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +// Tcl Message: Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/constraints/ariane.xdc] +// Tcl Message: Finished Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/constraints/ariane.xdc] +// Tcl Message: INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/constraints/ariane.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: Completed Processing XDC Constraints +// Tcl Message: INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 11900.746 ; gain = 0.000 ; free physical = 7728 ; free virtual = 15727 +// TclEventType: RUN_MODIFY +// TclEventType: RUN_OPTIONS_MODIFIED +// TclEventType: RUN_LAUNCH +// TclEventType: RUN_MODIFY +// TclEventType: RUN_STATUS_CHANGE +// HMemoryUtils.trashcanNow. Engine heap size: 6,550 MB. GUI used memory: 201 MB. Current time: 4/29/25, 11:21:17 AM CEST +// Tcl Message: RTL Elaboration Complete: : Time (s): cpu = 00:01:11 ; elapsed = 00:00:47 . Memory (MB): peak = 12060.207 ; gain = 2287.270 ; free physical = 7209 ; free virtual = 15231 +// Tcl Message: 428 Infos, 375 Warnings, 1 Critical Warnings and 0 Errors encountered. synth_design completed successfully +// Tcl Message: synth_design: Time (s): cpu = 00:01:18 ; elapsed = 00:00:55 . Memory (MB): peak = 12060.207 ; gain = 3289.980 ; free physical = 7209 ; free virtual = 15231 +// Tcl Message: INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] +// Tcl Message: # set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] # launch_runs synth_1 +// Tcl Message: [Tue Apr 29 11:21:16 2025] Launched synth_1... Run output will be captured here: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/synth_1/runme.log +// Tcl Message: # wait_on_run synth_1 +// Tcl Message: [Tue Apr 29 11:21:16 2025] Waiting for synth_1 to finish... +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: [Tue Apr 29 11:21:21 2025] Waiting for synth_1 to finish... +// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED +// RouteApi::loadEngineXgdAndInitRouteStorage elapsed time: 8.9s +// [Engine Memory]: 6,884 MB (+158519kb) [00:01:18] +// Tcl Message: [Tue Apr 29 11:21:26 2025] Waiting for synth_1 to finish... +// Tcl Message: [Tue Apr 29 11:21:32 2025] Waiting for synth_1 to finish... +// Tcl Message: [Tue Apr 29 11:21:42 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,886 MB. GUI used memory: 188 MB. Current time: 4/29/25, 11:21:47 AM CEST +// Tcl Message: [Tue Apr 29 11:21:52 2025] Waiting for synth_1 to finish... +// Tcl Message: [Tue Apr 29 11:22:02 2025] Waiting for synth_1 to finish... +// Tcl Message: [Tue Apr 29 11:22:12 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,563 MB. GUI used memory: 225 MB. Current time: 4/29/25, 11:22:17 AM CEST +// Tcl Message: [Tue Apr 29 11:22:32 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,563 MB. GUI used memory: 224 MB. Current time: 4/29/25, 11:22:47 AM CEST +// Tcl Message: [Tue Apr 29 11:22:52 2025] Waiting for synth_1 to finish... +// Tcl Message: [Tue Apr 29 11:23:12 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,564 MB. GUI used memory: 187 MB. Current time: 4/29/25, 11:23:17 AM CEST +// Tcl Message: [Tue Apr 29 11:23:32 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,556 MB. GUI used memory: 212 MB. Current time: 4/29/25, 11:23:47 AM CEST +// Tcl Message: [Tue Apr 29 11:24:12 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,556 MB. GUI used memory: 186 MB. Current time: 4/29/25, 11:24:17 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 6,550 MB. GUI used memory: 186 MB. Current time: 4/29/25, 11:24:47 AM CEST +// Tcl Message: [Tue Apr 29 11:24:52 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,550 MB. GUI used memory: 186 MB. Current time: 4/29/25, 11:25:17 AM CEST +// Tcl Message: [Tue Apr 29 11:25:32 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,536 MB. GUI used memory: 186 MB. Current time: 4/29/25, 11:25:47 AM CEST +// Tcl Message: [Tue Apr 29 11:26:12 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,536 MB. GUI used memory: 186 MB. Current time: 4/29/25, 11:26:17 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 6,536 MB. GUI used memory: 218 MB. Current time: 4/29/25, 11:26:47 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 6,536 MB. GUI used memory: 188 MB. Current time: 4/29/25, 11:27:17 AM CEST +// Tcl Message: [Tue Apr 29 11:27:32 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,536 MB. GUI used memory: 187 MB. Current time: 4/29/25, 11:27:47 AM CEST +// TclEventType: RUN_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_STEP_COMPLETED +// [GUI Memory]: 266 MB (+5021kb) [00:08:04] +// Tcl Message: [Tue Apr 29 11:28:10 2025] synth_1 finished +// Tcl Message: wait_on_runs: Time (s): cpu = 00:07:10 ; elapsed = 00:06:54 . Memory (MB): peak = 12537.477 ; gain = 477.270 ; free physical = 20267 ; free virtual = 25568 +// Tcl Message: # open_run synth_1 +// Tcl Message: Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xcvu9p-flga2104-2L-e +// HMemoryUtils.trashcanNow. Engine heap size: 6,530 MB. GUI used memory: 255 MB. Current time: 4/29/25, 11:28:17 AM CEST +// TclEventType: DEBUG_PORT_ADD +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_CNS_STALE +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: SIGNAL_INTERFACE_ADD +// TclEventType: SIGNAL_HIERARCHY_CHANGED +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: TIMING_RESULTS_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// HMemoryUtils.trashcanNow. Engine heap size: 6,955 MB. GUI used memory: 261 MB. Current time: 4/29/25, 11:28:40 AM CEST +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: FLOORPLAN_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: DESIGN_NEW +// HMemoryUtils.trashcanNow. Engine heap size: 6,990 MB. GUI used memory: 198 MB. Current time: 4/29/25, 11:28:43 AM CEST +// TclEventType: DESIGN_NEW +// DeviceView Instantiated +// TclEventType: CURR_DESIGN_SET +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.78 . Memory (MB): peak = 12537.477 ; gain = 0.000 ; free physical = 20267 ; free virtual = 25589 +// Tcl Message: INFO: [Netlist 29-17] Analyzing 5370 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.1 INFO: [Project 1-570] Preparing netlist for logic optimization +// Tcl Message: INFO: [Chipscope 16-324] Core: i_ddr UUID: 95d64970-6efe-555a-a048-dc3a209f704a +// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.gen/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.gen/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc:57] +// Tcl Message: Finished Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/constraints/vcu118.xdc] Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/constraints/ariane.xdc] +// Tcl Message: INFO: [Project 1-1714] 53 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +// Tcl Message: Generating merged BMM file for the design top 'ariane_xilinx'... +// Tcl Message: INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/sw/calibration_0/Debug/calibration_ddr.elf +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 12932.113 ; gain = 0.000 ; free physical = 19748 ; free virtual = 25179 +// Device view-level: 0.0 +// [GUI Memory]: 286 MB (+6243kb) [00:08:39] +// Tcl Message: open_run: Time (s): cpu = 00:00:42 ; elapsed = 00:00:34 . Memory (MB): peak = 13062.906 ; gain = 525.430 ; free physical = 19554 ; free virtual = 25003 +// Tcl Message: # exec mkdir -p reports/ # exec rm -rf reports/* # check_timing -verbose -file reports/$project.check_timing.rpt +// [Engine Memory]: 7,258 MB (+31555kb) [00:08:39] +// HMemoryUtils.trashcanNow. Engine heap size: 7,315 MB. GUI used memory: 212 MB. Current time: 4/29/25, 11:28:47 AM CEST +// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. +// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED +// RouteApi::loadEngineXgdAndInitRouteStorage elapsed time: 7s +// TclEventType: TIMING_RESULTS_STALE +// Tcl Message: check_timing: Time (s): cpu = 00:00:44 ; elapsed = 00:00:20 . Memory (MB): peak = 14254.750 ; gain = 1181.844 ; free physical = 18177 ; free virtual = 23781 +// Tcl Message: # report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +// Tcl Message: INFO: [Timing 38-78] ReportTimingParams: -max_paths 100 -nworst 100 -delay_type max -sort_by slack. +// Tcl Message: # report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by group. +// Tcl Message: # report_utilization -hierarchical -file reports/$project.utilization.rpt +// Tcl Message: # report_cdc -file reports/$project.cdc.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: No interconnect No Cell Dly, Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +// Tcl Message: INFO: [Timing 38-433] Consider using Xilinx recommended XPM_CDC modules to avoid Critical severities INFO: [Timing 38-314] The report_cdc command only analyzes and reports clock domain crossing paths where clocks have been defined on both source and destination sides. Ports with no input delay constraint are skipped. Please run check_timing to verify there are no missing clock definitions in your design, nor any unconstrained input port. +// Tcl Message: # report_clock_interaction -file reports/$project.clock_interaction.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +// TclEventType: TIMING_RESULTS_STALE +// TclEventType: RUN_MODIFY +// [Engine Memory]: 8,363 MB (+778390kb) [00:09:08] +// TclEventType: RUN_OPTIONS_MODIFIED +// TclEventType: RUN_MODIFY +// TclEventType: RUN_OPTIONS_MODIFIED +// Tcl Message: # set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1] # set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1] # launch_runs impl_1 +// HMemoryUtils.trashcanNow. Engine heap size: 8,433 MB. GUI used memory: 210 MB. Current time: 4/29/25, 11:29:15 AM CEST +// Tcl Message: INFO: [Timing 38-480] Writing timing data to binary archive. +// Tcl Message: Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. +// Tcl Message: Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.32 . Memory (MB): peak = 14305.773 ; gain = 40.020 ; free physical = 18143 ; free virtual = 23793 +// HMemoryUtils.trashcanNow. Engine heap size: 8,433 MB. GUI used memory: 210 MB. Current time: 4/29/25, 11:29:17 AM CEST +// TclEventType: RUN_LAUNCH +// TclEventType: RUN_MODIFY +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: [Tue Apr 29 11:29:22 2025] Launched impl_1... Run output will be captured here: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/runme.log +// Tcl Message: launch_runs: Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 14325.773 ; gain = 68.023 ; free physical = 18085 ; free virtual = 23738 +// Tcl Message: # wait_on_run impl_1 +// Tcl Message: [Tue Apr 29 11:29:22 2025] Waiting for impl_1 to finish... +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: [Tue Apr 29 11:29:27 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 11:29:32 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 11:29:37 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,416 MB. GUI used memory: 210 MB. Current time: 4/29/25, 11:29:47 AM CEST +// Tcl Message: [Tue Apr 29 11:29:47 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 11:29:57 2025] Waiting for impl_1 to finish... +// TclEventType: RUN_STEP_COMPLETED +// Tcl Message: [Tue Apr 29 11:30:07 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,408 MB. GUI used memory: 211 MB. Current time: 4/29/25, 11:30:17 AM CEST +// Tcl Message: [Tue Apr 29 11:30:17 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 11:30:37 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,408 MB. GUI used memory: 261 MB. Current time: 4/29/25, 11:30:47 AM CEST +// Tcl Message: [Tue Apr 29 11:30:57 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,408 MB. GUI used memory: 211 MB. Current time: 4/29/25, 11:31:17 AM CEST +// Tcl Message: [Tue Apr 29 11:31:17 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 11:31:37 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,408 MB. GUI used memory: 211 MB. Current time: 4/29/25, 11:31:47 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,408 MB. GUI used memory: 211 MB. Current time: 4/29/25, 11:32:17 AM CEST +// Tcl Message: [Tue Apr 29 11:32:17 2025] Waiting for impl_1 to finish... +// Elapsed time: 746 seconds +selectButton(RDIResource.ProgressDialog_BACKGROUND, "Background"); // a +selectTab((HResource) null, (HResource) null, "Messages", 1); // aa +// HMemoryUtils.trashcanNow. Engine heap size: 8,411 MB. GUI used memory: 232 MB. Current time: 4/29/25, 11:32:47 AM CEST +selectCheckBox(PAResourceItoN.MsgView_WARNING_MESSAGES, (String) null, false); // f: FALSE +selectCheckBox(PAResourceItoN.MsgView_INFORMATION_MESSAGES, (String) null, false); // f: FALSE +// TclEventType: RUN_STEP_COMPLETED +// Tcl Message: [Tue Apr 29 11:32:57 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,412 MB. GUI used memory: 210 MB. Current time: 4/29/25, 11:33:17 AM CEST +// Tcl Message: [Tue Apr 29 11:33:37 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,412 MB. GUI used memory: 209 MB. Current time: 4/29/25, 11:33:47 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,412 MB. GUI used memory: 209 MB. Current time: 4/29/25, 11:34:17 AM CEST +// Tcl Message: [Tue Apr 29 11:34:17 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 11:35:37 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 11:36:57 2025] Waiting for impl_1 to finish... +// TclEventType: RUN_STEP_COMPLETED +// Tcl Message: [Tue Apr 29 11:38:17 2025] Waiting for impl_1 to finish... +// TclEventType: RUN_STEP_COMPLETED +// Tcl Message: [Tue Apr 29 11:39:37 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,413 MB. GUI used memory: 209 MB. Current time: 4/29/25, 11:40:47 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,413 MB. GUI used memory: 209 MB. Current time: 4/29/25, 11:41:17 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,413 MB. GUI used memory: 209 MB. Current time: 4/29/25, 11:41:47 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,413 MB. GUI used memory: 209 MB. Current time: 4/29/25, 11:42:17 AM CEST +// Tcl Message: [Tue Apr 29 11:42:17 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,413 MB. GUI used memory: 209 MB. Current time: 4/29/25, 11:42:47 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,413 MB. GUI used memory: 209 MB. Current time: 4/29/25, 11:43:17 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,413 MB. GUI used memory: 209 MB. Current time: 4/29/25, 11:43:47 AM CEST +// TclEventType: RUN_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_STEP_COMPLETED +// TclEventType: RUN_LAUNCH +// TclEventType: RUN_MODIFY +// Tcl Message: [Tue Apr 29 11:44:07 2025] impl_1 finished +// Tcl Message: wait_on_runs: Time (s): cpu = 00:00:32 ; elapsed = 00:14:45 . Memory (MB): peak = 14325.773 ; gain = 0.000 ; free physical = 15550 ; free virtual = 23456 +// Tcl Message: # launch_runs impl_1 -to_step write_bitstream +// Tcl Message: [Tue Apr 29 11:44:07 2025] Launched impl_1... Run output will be captured here: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/runme.log +// Tcl Message: # wait_on_run impl_1 +// Tcl Message: [Tue Apr 29 11:44:07 2025] Waiting for impl_1 to finish... +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: [Tue Apr 29 11:44:12 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,398 MB. GUI used memory: 211 MB. Current time: 4/29/25, 11:44:17 AM CEST +// Tcl Message: [Tue Apr 29 11:44:17 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 11:44:22 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 11:44:32 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 11:44:42 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,398 MB. GUI used memory: 237 MB. Current time: 4/29/25, 11:44:47 AM CEST +// Tcl Message: [Tue Apr 29 11:44:52 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 11:45:02 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,398 MB. GUI used memory: 210 MB. Current time: 4/29/25, 11:45:17 AM CEST +// Tcl Message: [Tue Apr 29 11:45:22 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 11:45:42 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,398 MB. GUI used memory: 210 MB. Current time: 4/29/25, 11:45:47 AM CEST +// Tcl Message: [Tue Apr 29 11:46:02 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,398 MB. GUI used memory: 210 MB. Current time: 4/29/25, 11:46:17 AM CEST +// Tcl Message: [Tue Apr 29 11:46:22 2025] Waiting for impl_1 to finish... +// TclEventType: RUN_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: [Tue Apr 29 11:46:27 2025] impl_1 finished +// Tcl Message: wait_on_runs: Time (s): cpu = 00:00:06 ; elapsed = 00:02:20 . Memory (MB): peak = 14325.773 ; gain = 0.000 ; free physical = 15411 ; free virtual = 23421 +// Tcl Message: # open_run impl_1 +// HMemoryUtils.trashcanNow. Engine heap size: 8,657 MB. GUI used memory: 211 MB. Current time: 4/29/25, 11:46:35 AM CEST +// TclEventType: SIGNAL_INTERFACE_ADD +// TclEventType: SIGNAL_HIERARCHY_CHANGED +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_CNS_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// HMemoryUtils.trashcanNow. Engine heap size: 9,117 MB. GUI used memory: 210 MB. Current time: 4/29/25, 11:46:47 AM CEST +// TclEventType: FLOORPLAN_MODIFY +// TclEventType: DESIGN_NEW +// HMemoryUtils.trashcanNow. Engine heap size: 9,142 MB. GUI used memory: 210 MB. Current time: 4/29/25, 11:46:48 AM CEST +// [Engine Memory]: 9,142 MB (+377878kb) [00:26:42] +// TclEventType: DESIGN_NEW +// DeviceView Instantiated +// TclEventType: CURR_DESIGN_SET +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.79 . Memory (MB): peak = 14325.773 ; gain = 0.000 ; free physical = 15366 ; free virtual = 23358 +// Tcl Message: INFO: [Netlist 29-17] Analyzing 5336 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.1 INFO: [Project 1-570] Preparing netlist for logic optimization +// Tcl Message: INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Project 1-853] Binary constraint restore complete. +// Tcl Message: Reading XDEF placement. Reading placer database... Reading XDEF routing. +// Tcl Message: Read XDEF Files: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 15000.852 ; gain = 150.633 ; free physical = 14759 ; free virtual = 22753 +// Tcl Message: Restored from archive | CPU: 6.860000 secs | Memory: 153.974281 MB | +// Tcl Message: Finished XDEF File Restore: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 15000.852 ; gain = 150.633 ; free physical = 14759 ; free virtual = 22753 +// Tcl Message: Generating merged BMM file for the design top 'ariane_xilinx'... +// Tcl Message: INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/sw/calibration_0/Debug/calibration_ddr.elf +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 15024.852 ; gain = 0.000 ; free physical = 14735 ; free virtual = 22729 +// Device view-level: 0.0 +// [GUI Memory]: 318 MB (+18694kb) [00:26:43] +// [Engine Memory]: 9,655 MB (+58838kb) [00:26:43] +// Tcl Message: open_run: Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 15402.039 ; gain = 1076.266 ; free physical = 14387 ; free virtual = 22399 +// Tcl Message: # write_verilog -force -mode funcsim work-fpga/${project}_funcsim.v +// Tcl Message: # write_verilog -force -mode timesim work-fpga/${project}_timesim.v +// Tcl Message: # write_sdf -force work-fpga/${project}_timesim.sdf +// Elapsed time: 849 seconds +selectButton(RDIResource.BaseDialog_OK, "OK"); // a +dismissDialog("Device"); // u +selectTab((HResource) null, (HResource) null, "Messages", 1); // aa +// [Engine Memory]: 10,386 MB (+260408kb) [00:26:54] +// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED +// RouteApi::loadEngineXgdAndInitRouteStorage elapsed time: 12.3s +// Device view-level: 0.0 +// RouteApi::getRouteInfo length(bytes): 196076 +// [GUI Memory]: 336 MB (+2529kb) [00:26:57] +// RouteApi::getRouteInfo length(bytes): 196079 +// Device view-level: 0.0 +// RouteApi::getRouteInfo length(bytes): 196078 +// Tcl Message: write_sdf: Time (s): cpu = 00:01:39 ; elapsed = 00:00:09 . Memory (MB): peak = 16207.574 ; gain = 728.336 ; free physical = 13027 ; free virtual = 21520 +// Tcl Message: # exec mkdir -p reports/ # exec rm -rf reports/* # check_timing -file reports/${project}.check_timing.rpt +// TclEventType: TIMING_RESULTS_STALE +// Tcl Message: check_timing: Time (s): cpu = 00:00:27 ; elapsed = 00:00:06 . Memory (MB): peak = 16207.574 ; gain = 0.000 ; free physical = 13058 ; free virtual = 21528 +// Tcl Message: # report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/${project}.timing_WORST_100.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +// Tcl Message: INFO: [Timing 38-78] ReportTimingParams: -max_paths 100 -nworst 100 -delay_type max -sort_by slack. +// Tcl Message: # report_timing -nworst 1 -delay_type max -sort_by group -file reports/${project}.timing.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by group. +// Tcl Message: # report_utilization -hierarchical -file reports/${project}.utilization.rpt +// TclEventType: STOP_PROGRESS_DIALOG +// Elapsed Time for: 'K.d': 27m:01s +// Elapsed time: 19 seconds +dismissDialog("Sourcing Tcl script 'scripts/run.tcl'"); // bq +// RouteApi::getRouteInfo length(bytes): 196078 +// HMemoryUtils.trashcanNow. Engine heap size: 10,407 MB. GUI used memory: 252 MB. Current time: 4/29/25, 11:47:19 AM CEST +// TclEventType: STOP_PROGRESS_DIALOG +// RouteApi::getRouteInfo length(bytes): 196078 +// Elapsed Time for: 'L.f': 27m:04s +// Tcl Message: update_compile_order -fileset sources_1 +// RouteApi: Init Delay Mediator Swing Worker Finished +// RouteApi: Init Delay Mediator Swing Worker Finished +// Elapsed Time for: 'L.f': 27m:06s +selectButton(RDIResource.BaseDialog_OK, "OK"); // a +// Run Command: PAResourceCommand.PACommandNames_REPORTS_WINDOW +dismissDialog("Bitstream Generation Completed"); // Q.a +selectTab((HResource) null, (HResource) null, "Messages", 1); // aa +// Elapsed Time for: 'L.f': 27m:10s +// TclEventType: FILE_SET_CHANGE +// TclEventType: DG_GRAPH_STALE +// Elapsed Time for: 'L.f': 27m:12s +// Elapsed Time for: 'L.f': 27m:14s +expandTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Analysis Results, sources_1, [HDL 9-3952] use of undefined macro 'RVFI_PROBES_INSTR_T' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/ariane_xilinx.sv:201]. ]", 2); // u.d +collapseTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Analysis Results, sources_1, [HDL 9-3952] use of undefined macro 'RVFI_PROBES_INSTR_T' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/ariane_xilinx.sv:201]. ]", 2); // u.d +expandTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Analysis Results, sim_1, [HDL 9-3952] use of undefined macro 'READREGFLAGS_T' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/src/ariane.sv:26]. ]", 6); // u.d +collapseTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Analysis Results, sim_1, [HDL 9-3952] use of undefined macro 'READREGFLAGS_T' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/src/ariane.sv:26]. ]", 6); // u.d +selectTab((HResource) null, (HResource) null, "Sources", 0); // aa +selectButton(PAResourceEtoH.FileSetPanel_MESSAGES, "520"); // g +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager]", 50, true); // f - Node +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER +// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes' +// Tcl (Dont Echo) Command: 'load_features labtools' +// TclEventType: LOAD_FEATURE +// TclEventType: HW_SESSION_OPEN +closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // t +// Tcl Message: open_hw_manager +dismissDialog("Open Hardware Manager"); // bq +// HMemoryUtils.trashcanNow. Engine heap size: 10,479 MB. GUI used memory: 258 MB. Current time: 4/29/25, 11:47:50 AM CEST +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Open Target]", 48, false); // f +// Run Command: PAResourceCommand.PACommandNames_OPEN_HW_TARGET +selectMenu(PAResourceOtoP.ProgramDebugTab_OPEN_RECENTLY_OPENED_TARGET, "Recent Targets"); // al +selectMenuItem(PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET, "Auto Connect"); // ao +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER +// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes' +// Run Command: PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET +// Tcl Message: connect_hw_server -allow_non_jtag +// TclEventType: HW_SERVER_UPDATE +// Tcl Message: INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 INFO: [Labtools 27-2222] Launching hw_server... +// TclEventType: HW_SERVER_UPDATE +// Tcl Message: INFO: [Labtools 27-2221] Launch Output: ****** Xilinx hw_server v2023.1 **** Build date : May 7 2023 at 15:13:34 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0 INFO: [Labtools 27-3417] Launching cs_server... +// TclEventType: HW_SERVER_UPDATE +// Tcl Message: INFO: [Labtools 27-2221] Launch Output: ******** Xilinx cs_server v2023.1.0 ****** Build date : Apr 10 2023-17:59:24 **** Build number : 2023.1.1681142364 ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// TclEventType: HW_TARGET_CHANGE +// Tcl Message: open_hw_target +// Tcl Message: INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210249B868A9 +// Tcl Message: ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210249B868A9. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-register this hardware target. +// Tcl Message: ERROR: [Common 17-39] 'open_hw_target' failed due to earlier errors. +// CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'open_hw_target' failed due to earlier errors. +dismissDialog("Auto Connect"); // bq +selectButton(PAResourceAtoD.CmdMsgDialog_OK, "OK"); // f +dismissDialog("Critical Messages"); // a +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_SERVER_UPDATE +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_SERVER_UPDATE +// TclEventType: HW_TARGET_NEEDS_CLOSE +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "xilinx_tcf/Digilent/210308B76CA2 (0) ; Closed", 2, "xilinx_tcf/Digilent/210308B76CA2 (0)", 0, false); // m +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "xilinx_tcf/Digilent/210308B76CA2 (0) ; Closed", 2, "xilinx_tcf/Digilent/210308B76CA2 (0)", 0, false, false, false, false, true, false); // m - Popup Trigger +selectMenuItem(PAResourceCommand.PACommandNames_OPEN_TARGET, "Open Target"); // ao +// Run Command: PAResourceCommand.PACommandNames_OPEN_TARGET +selectButton("OptionPane.button", "OK"); // JButton +// TclEventType: HW_TARGET_CLOSE +// TclEventType: HW_TARGET_UPDATE +// TclEventType: DEBUG_PROBE_DELETE +// Tcl Message: close_hw_target {localhost:3121/xilinx_tcf/Digilent/210249B868A9} +// Tcl Message: INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210249B868A9 +// TclEventType: HW_TARGET_CHANGE +// TclEventType: HW_TARGET_CLOSE +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_ADD +// TclEventType: HW_TARGET_UPDATE +// Tcl Message: open_hw_target {localhost:3121/xilinx_tcf/Digilent/210308B76CA2} +// Tcl Message: INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308B76CA2 +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROGRAM.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.bit} [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: set_property FULL_PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: current_hw_device [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_CHANGE +// TclEventType: HW_MIG_ADD +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_DEVICE_CHANGE +closeView(PAResourceOtoP.PAViews_MIG, "MIG - MIG_1"); // b +// TclEventType: HW_DEVICE_PROBES_CHANGE +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// Tcl Message: refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0] +// Tcl Message: INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s). +dismissDialog("Open Target"); // bq +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 49, false); // f +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +// HMemoryUtils.trashcanNow. Engine heap size: 10,676 MB. GUI used memory: 258 MB. Current time: 4/29/25, 11:48:10 AM CEST +selectMenuItem((HResource) null, "xcvu9p_0"); // ao +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER +// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes' +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program"); // a +// TclEventType: HW_DEVICE_CHANGE +dismissDialog("Program Device"); // aP +// Tcl Message: set_property PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: set_property FULL_PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROGRAM.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.bit} [get_hw_devices xcvu9p_0] +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_MIG_DELETE +closeView(PAResourceOtoP.PAViews_MIG, "MIG - MIG_1"); // b +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_TARGET_NEEDS_CLOSE +// Tcl Message: program_hw_devices [get_hw_devices xcvu9p_0] +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH +// Tcl Message: program_hw_devices: Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 16271.906 ; gain = 0.000 ; free physical = 12642 ; free virtual = 21274 +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_CHANGE +// TclEventType: HW_MIG_ADD +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// Tcl Message: refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0] +// Tcl Message: INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s). +// 'D' command handler elapsed time: 22 seconds +// Elapsed time: 17 seconds +dismissDialog("Program Device"); // bq +// TclEventType: HW_SERVER_UPDATE +// Elapsed time: 319 seconds +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 49, false); // f +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectMenuItem((HResource) null, "xcvu9p_0"); // ao +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER +// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes' +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectButton(PAResourceOtoP.ProgramFpgaDialog_SPECIFY_BITSTREAM_FILE, (String) null); // r +setFileChooser("/home/stagiaire/Documents/cva6_main/cva6_vcu118_save2/test_bof.bit"); +selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program"); // a +// TclEventType: HW_DEVICE_CHANGE +dismissDialog("Program Device"); // aP +// Tcl Message: set_property PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: set_property FULL_PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROGRAM.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save2/test_bof.bit} [get_hw_devices xcvu9p_0] +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_MIG_DELETE +closeView(PAResourceOtoP.PAViews_MIG, "MIG - MIG_1"); // b +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_TARGET_NEEDS_CLOSE +// Tcl Message: program_hw_devices [get_hw_devices xcvu9p_0] +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH +// Tcl Message: program_hw_devices: Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 16279.285 ; gain = 0.000 ; free physical = 12701 ; free virtual = 21523 +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_CHANGE +// TclEventType: HW_MIG_ADD +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// Tcl Message: refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0] +// Tcl Message: INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s). +// 'D' command handler elapsed time: 28 seconds +// Elapsed time: 16 seconds +dismissDialog("Program Device"); // bq +// TclEventType: HW_SERVER_UPDATE +// Elapsed time: 38 seconds +selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 475, 63); // cD +selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 487, 50); // cD +selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 789, 62); // cD +selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 789, 62); // cD +selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 746, 76); // cD +selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 722, 112); // cD +selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 814, 82); // cD +typeControlKey(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, "RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR", 'c'); // cD +// Elapsed time: 46 seconds +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 49, false); // f +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectMenuItem((HResource) null, "xcvu9p_0"); // ao +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER +// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes' +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program"); // a +// TclEventType: HW_DEVICE_CHANGE +dismissDialog("Program Device"); // aP +// Tcl Message: set_property PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: set_property FULL_PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROGRAM.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save2/test_bof.bit} [get_hw_devices xcvu9p_0] +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_MIG_DELETE +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_TARGET_NEEDS_CLOSE +// Tcl Message: program_hw_devices [get_hw_devices xcvu9p_0] +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH +// Tcl Message: program_hw_devices: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 16279.285 ; gain = 0.000 ; free physical = 12269 ; free virtual = 21323 +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_CHANGE +// TclEventType: HW_MIG_ADD +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// Tcl Message: refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0] +// Tcl Message: INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s). +// 'D' command handler elapsed time: 20 seconds +// Elapsed time: 17 seconds +dismissDialog("Program Device"); // bq +// TclEventType: HW_SERVER_UPDATE +// Elapsed time: 143 seconds +selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 2, 33); // cD +selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 2, 47); // cD +typeControlKey(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, "RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR", 'c'); // cD +// Elapsed time: 32 seconds +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Open Target]", 48, false); // f +// Run Command: PAResourceCommand.PACommandNames_OPEN_HW_TARGET +selectMenu(PAResourceOtoP.ProgramDebugTab_OPEN_RECENTLY_OPENED_TARGET, "Recent Targets"); // al +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 49, false); // f +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectMenuItem((HResource) null, "xcvu9p_0"); // ao +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER +// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes' +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program"); // a +// TclEventType: HW_DEVICE_CHANGE +dismissDialog("Program Device"); // aP +// Tcl Message: set_property PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: set_property FULL_PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROGRAM.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save2/test_bof.bit} [get_hw_devices xcvu9p_0] +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_MIG_DELETE +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_TARGET_NEEDS_CLOSE +// Tcl Message: program_hw_devices [get_hw_devices xcvu9p_0] +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH +// Tcl Message: program_hw_devices: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 16279.285 ; gain = 0.000 ; free physical = 12389 ; free virtual = 21446 +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_CHANGE +// TclEventType: HW_MIG_ADD +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// Tcl Message: refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0] +// Tcl Message: INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s). +// 'D' command handler elapsed time: 24 seconds +// Elapsed time: 16 seconds +dismissDialog("Program Device"); // bq +// TclEventType: HW_SERVER_UPDATE +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 49, false); // f +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectMenuItem((HResource) null, "xcvu9p_0"); // ao +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER +// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes' +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectButton(PAResourceOtoP.ProgramFpgaDialog_SPECIFY_BITSTREAM_FILE, (String) null); // r +setFileChooser("/home/stagiaire/Documents/cva6_main/cva6_vcu118_1.bit"); +selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program"); // a +// TclEventType: HW_DEVICE_CHANGE +dismissDialog("Program Device"); // aP +// Tcl Message: set_property PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: set_property FULL_PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROGRAM.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_1.bit} [get_hw_devices xcvu9p_0] +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_MIG_DELETE +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_TARGET_NEEDS_CLOSE +// Tcl Message: program_hw_devices [get_hw_devices xcvu9p_0] +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH +// Tcl Message: program_hw_devices: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 16279.285 ; gain = 0.000 ; free physical = 12368 ; free virtual = 21449 +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_CHANGE +// TclEventType: HW_MIG_ADD +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_DEVICE_CHANGE +// Elapsed time: 17 seconds +closeView(PAResourceOtoP.PAViews_MIG, "MIG - MIG_1"); // b +// TclEventType: HW_DEVICE_PROBES_CHANGE +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// Tcl Message: refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0] +// Tcl Message: INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s). +// 'D' command handler elapsed time: 25 seconds +// TclEventType: HW_SERVER_UPDATE +dismissDialog("Program Device"); // bq +selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 4, 54); // cD +selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 2, 50); // cD +typeControlKey(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, "RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR", 'c'); // cD +// HMemoryUtils.trashcanNow. Engine heap size: 10,650 MB. GUI used memory: 271 MB. Current time: 4/29/25, 12:18:10 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 10,650 MB. GUI used memory: 255 MB. Current time: 4/29/25, 12:48:10 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 10,637 MB. GUI used memory: 250 MB. Current time: 4/29/25, 1:18:10 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 10,623 MB. GUI used memory: 249 MB. Current time: 4/29/25, 1:48:10 PM CEST +// Elapsed time: 6859 seconds +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "MIG_1 ; CAL FAIL", 5, "CAL FAIL", 1, false); // m +// Elapsed time: 20 seconds +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 49, false); // f +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectMenuItem((HResource) null, "xcvu9p_0"); // ao +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER +// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes' +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectButton(PAResourceOtoP.ProgramFpgaDialog_SPECIFY_BITSTREAM_FILE, (String) null); // r +setFileChooser("/home/stagiaire/Documents/cva6_main/cva6_vcu118_save2/test_bof.bit"); +selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program"); // a +// TclEventType: HW_DEVICE_CHANGE +dismissDialog("Program Device"); // aP +// Tcl Message: set_property PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: set_property FULL_PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROGRAM.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save2/test_bof.bit} [get_hw_devices xcvu9p_0] +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_MIG_DELETE +closeView(PAResourceOtoP.PAViews_MIG, "MIG - MIG_1"); // b +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_TARGET_NEEDS_CLOSE +// Tcl Message: program_hw_devices [get_hw_devices xcvu9p_0] +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH +// Tcl Message: program_hw_devices: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 16279.285 ; gain = 0.000 ; free physical = 11506 ; free virtual = 20818 +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_CHANGE +// TclEventType: HW_MIG_ADD +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// Tcl Message: refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0] +// Tcl Message: INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s). +// 'D' command handler elapsed time: 24 seconds +// Elapsed time: 16 seconds +dismissDialog("Program Device"); // bq +// TclEventType: HW_SERVER_UPDATE +// Elapsed time: 43 seconds +selectMenu(PAResourceItoN.MainMenuMgr_FILE, "File"); // ag +selectMenu(PAResourceItoN.MainMenuMgr_PROJECT, "Project"); // al +selectMenu(PAResourceItoN.MainMenuMgr_CHECKPOINT, "Checkpoint"); // al +selectMenu(PAResourceItoN.MainMenuMgr_IP, "IP"); // al +selectMenu(PAResourceItoN.MainMenuMgr_TEXT_EDITOR, "Text Editor"); // al +selectMenu(PAResourceItoN.MainMenuMgr_IP, "IP"); // al +selectMenu(PAResourceItoN.MainMenuMgr_CHECKPOINT, "Checkpoint"); // al +selectMenu(PAResourceItoN.MainMenuMgr_IP, "IP"); // al +selectMenu(PAResourceItoN.MainMenuMgr_TEXT_EDITOR, "Text Editor"); // al +selectMenu(PAResourceItoN.MainMenuMgr_IMPORT, "Import"); // al +selectMenu(PAResourceItoN.MainMenuMgr_EXPORT, "Export"); // al +selectMenu(PAResourceItoN.MainMenuMgr_EXPORT, "Export"); // al +selectMenu(PAResourceItoN.MainMenuMgr_IMPORT, "Import"); // al +selectMenu(PAResourceItoN.MainMenuMgr_TEXT_EDITOR, "Text Editor"); // al +selectMenu(PAResourceItoN.MainMenuMgr_IP, "IP"); // al +selectMenu(PAResourceItoN.MainMenuMgr_CHECKPOINT, "Checkpoint"); // al +selectMenu(PAResourceItoN.MainMenuMgr_PROJECT, "Project"); // al +selectMenu(PAResourceItoN.MainMenuMgr_CHECKPOINT, "Checkpoint"); // al +selectMenu(PAResourceItoN.MainMenuMgr_PROJECT, "Project"); // al +dismissMenu(PAResourceItoN.MainMenuMgr_FILE, "File"); // ag +selectMenu(PAResourceItoN.MainMenuMgr_REPORTS, "Reports"); // ag +dismissMenu(PAResourceItoN.MainMenuMgr_REPORTS, "Reports"); // ag +selectMenu(PAResourceItoN.MainMenuMgr_TOOLS, "Tools"); // ag +dismissMenu(PAResourceItoN.MainMenuMgr_TOOLS, "Tools"); // ag +selectMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // ag +selectMenu(PAResourceItoN.MainMenuMgr_SETTINGS, "Settings"); // al +selectMenu(PAResourceCommand.PACommandNames_SIMULATION_RUN, "Run Simulation"); // ag +selectMenu(PAResourceItoN.MainMenuMgr_OPEN, "Open Implemented Design"); // al +dismissMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // ag +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 49, false); // f +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectMenuItem((HResource) null, "xcvu9p_0"); // ao +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER +// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes' +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectButton(PAResourceOtoP.ProgramFpgaDialog_SPECIFY_BITSTREAM_FILE, (String) null); // r +setFileChooser("/home/stagiaire/Documents/cva6_main/cva6_vcu118_1.bit"); +selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program"); // a +// TclEventType: HW_DEVICE_CHANGE +dismissDialog("Program Device"); // aP +// Tcl Message: set_property PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: set_property FULL_PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROGRAM.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_1.bit} [get_hw_devices xcvu9p_0] +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_MIG_DELETE +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_TARGET_NEEDS_CLOSE +// Tcl Message: program_hw_devices [get_hw_devices xcvu9p_0] +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH +// Tcl Message: program_hw_devices: Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 16279.285 ; gain = 0.000 ; free physical = 11513 ; free virtual = 20826 +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_CHANGE +// TclEventType: HW_MIG_ADD +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_DEVICE_CHANGE +// Elapsed time: 16 seconds +closeView(PAResourceOtoP.PAViews_MIG, "MIG - MIG_1"); // b +// TclEventType: HW_DEVICE_PROBES_CHANGE +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// Tcl Message: refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0] +// Tcl Message: INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s). +// 'D' command handler elapsed time: 25 seconds +dismissDialog("Program Device"); // bq +// TclEventType: HW_SERVER_UPDATE +// Elapsed time: 87 seconds +selectTable(PAResourceItoN.MigStatusPanel_STATUS_TABLE, "1 - DQS Gate ; FAIL", 0, "1 - DQS Gate", 0); // h +selectTable(PAResourceItoN.MigStatusPanel_STATUS_TABLE, "1 - DQS Gate ; FAIL", 0, "1 - DQS Gate", 0, false, false, false, false, true); // h - Double Click +selectTable(PAResourceItoN.MigStatusPanel_STATUS_TABLE, "1 - DQS Gate ; FAIL", 0, "FAIL", 1); // h +selectTable(PAResourceItoN.MigStatusPanel_STATUS_TABLE, "1 - DQS Gate ; FAIL", 0, "FAIL", 1, false, false, false, false, true); // h - Double Click +// Elapsed time: 299 seconds +selectTableHeader(PAResourceItoN.MigStatusPanel_STATUS_TABLE, "Calibration Stage", 0); // h +selectTable(PAResourceItoN.MigStatusPanel_STATUS_TABLE, "1 - DQS Gate ; FAIL", 0, "1 - DQS Gate", 0); // h +selectTable(PAResourceItoN.MigStatusPanel_STATUS_TABLE, "2 - DQS Gate Sanity Check ; ", 1, "2 - DQS Gate Sanity Check", 0); // h +selectTable(PAResourceItoN.MigStatusPanel_STATUS_TABLE, "4 - Read Per-Bit Deskew ; ", 3, "4 - Read Per-Bit Deskew", 0); // h +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "SysMon ; ", 4, "SysMon", 0, false); // m +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "MIG_1 ; CAL FAIL", 5, "CAL FAIL", 1, false); // m +selectButton(PAResourceEtoH.HardwareMigPropPanels_OPEN_MIG_DASHBOARD, "Open MIG Dashboard"); // g +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_DASHBOARD +selectButton(PAResourceItoN.MigDashboardView_IF_CURRENT_MIG_REFRESH_RATE_ZERO, "MIG_auto_refresh"); // v: FALSE +// Run Command: PAResourceCommand.PACommandNames_STOP_AUTO_REFRESH +// Tcl Message: set_property MIG_REFRESH_RATE 0 [ get_hw_migs localhost:3121/xilinx_tcf/Digilent/210308B76CA2/0_1/MIG_1] +// Elapsed time: 90 seconds +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "SysMon ; ", 4, "SysMon", 0, false); // m +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "SysMon ; ", 4, "SysMon", 0, false, false, false, false, false, true); // m - Double Click +// Run Command: PAResourceCommand.PACommandNames_NEW_HARDWARE_DASHBOARD +dismissDialog("New Dashboard"); // a +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_TARGET_CLOSE +// Elapsed time: 135 seconds +closeView(PAResourceOtoP.PAViews_MIG, "MIG - MIG_1"); // b +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_MIG_DELETE +// TclEventType: HW_SYSMON_DELETE +// TclEventType: HW_TARGET_UPDATE +// TclEventType: DEBUG_PROBE_DELETE +// Tcl Message: ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210308B76CA2 +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_SERVER_UPDATE +selectButton(PAResourceAtoD.CmdMsgDialog_OK, "OK"); // f +dismissDialog("Close Hardware Target"); // j.a +// Elapsed time: 10 seconds +selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // j +closeTask("Program and Debug", "Hardware Manager", "DesignTask.PROGRAM_DEBUG"); +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_SERVER_CLOSE +// TclEventType: HW_SESSION_CLOSE +// RouteApi::getRouteInfo length(bytes): 196078 +// Tcl Message: close_hw_manager +dismissDialog("Close Hardware Manager"); // bq +// RouteApi::getRouteInfo length(bytes): 196078 +// Elapsed time: 96 seconds +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Open Target]", 51, false); // f +// Run Command: PAResourceCommand.PACommandNames_OPEN_HW_TARGET +selectMenu(PAResourceOtoP.ProgramDebugTab_OPEN_RECENTLY_OPENED_TARGET, "Recent Targets"); // al +selectMenuItem(PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET, "Auto Connect"); // ao +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER +// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes' +// TclEventType: HW_SESSION_OPEN +closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // t +// Tcl Message: open_hw_manager +// Run Command: PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET +dismissDialog("Open Hardware Manager"); // bq +// TclEventType: HW_SERVER_UPDATE +// Tcl Message: connect_hw_server -allow_non_jtag +// Tcl Message: INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 INFO: [Labtools 27-2222] Launching hw_server... INFO: [Labtools 27-2221] Launch Output: ****** Xilinx hw_server v2023.1 **** Build date : May 7 2023 at 15:13:34 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0 INFO: [Labtools 27-3417] Launching cs_server... +// TclEventType: HW_SERVER_UPDATE +// Tcl Message: INFO: [Labtools 27-2221] Launch Output: ******** Xilinx cs_server v2023.1.0 ****** Build date : Apr 10 2023-17:59:24 **** Build number : 2023.1.1681142364 ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// TclEventType: HW_TARGET_CHANGE +// TclEventType: HW_TARGET_CLOSE +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_ADD +// TclEventType: HW_TARGET_UPDATE +// Tcl Message: open_hw_target +// Tcl Message: INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308B76CA2 +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROGRAM.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_1.bit} [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: set_property FULL_PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: current_hw_device [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_CHANGE +// TclEventType: HW_MIG_ADD +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_DEVICE_CHANGE +closeView(PAResourceOtoP.PAViews_MIG, "MIG - MIG_1"); // b +// TclEventType: HW_DEVICE_PROBES_CHANGE +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// Tcl Message: refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0] +// Tcl Message: INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s). +dismissDialog("Auto Connect"); // bq +// HMemoryUtils.trashcanNow. Engine heap size: 10,892 MB. GUI used memory: 251 MB. Current time: 4/29/25, 2:09:30 PM CEST +// [GUI Memory]: 357 MB (+3705kb) [02:57:33] +// Elapsed time: 1139 seconds +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "MIG_1 ; CAL FAIL", 4, "MIG_1", 0, false); // m +selectTableHeader(PAResourceItoN.MigStatusPanel_STATUS_TABLE, "Calibration Stage", 0); // h +selectTable(PAResourceItoN.MigStatusPanel_STATUS_TABLE, "1 - DQS Gate ; FAIL", 0, "1 - DQS Gate", 0); // h +// Elapsed time: 53 seconds +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 49, false); // f +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectMenuItem((HResource) null, "xcvu9p_0"); // ao +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER +// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes' +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectButton(PAResourceOtoP.ProgramFpgaDialog_SPECIFY_BITSTREAM_FILE, (String) null); // r +setFileChooser("/home/stagiaire/Documents/cva6_main/cva6_vcu118_save2/test_bof.bit"); +selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program"); // a +dismissDialog("Program Device"); // aP +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: set_property FULL_PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROGRAM.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save2/test_bof.bit} [get_hw_devices xcvu9p_0] +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_MIG_DELETE +closeView(PAResourceOtoP.PAViews_MIG, "MIG - MIG_1"); // b +// TclEventType: HW_DEVICE_UPDATE +// Tcl Message: program_hw_devices [get_hw_devices xcvu9p_0] +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH +// Tcl Message: program_hw_devices: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 16286.215 ; gain = 0.000 ; free physical = 10818 ; free virtual = 21083 +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_CHANGE +// TclEventType: HW_MIG_ADD +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// Tcl Message: refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0] +// Tcl Message: INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s). +// 'D' command handler elapsed time: 33 seconds +// Elapsed time: 16 seconds +dismissDialog("Program Device"); // bq +// TclEventType: HW_SERVER_UPDATE +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "MIG_1 ; INVALID", 4, "INVALID", 1, false); // m +selectTab((HResource) null, (HResource) null, "Messages", 1); // aa +// Elapsed time: 24 seconds +selectButton(PAResourceItoN.MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED, "Messages_cleanUpMessages"); // B +// Elapsed time: 11 seconds +expandTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Analysis Results, sources_1, [HDL 9-3116] 'slave' is not a type [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save/corev_apu/fpga/src/ariane_xilinx.sv:746]. ]", 4); // u.d diff --git a/corev_apu/fpga/vivado_pid1465060.str b/corev_apu/fpga/vivado_pid1465060.str new file mode 100644 index 0000000000..a74ca4eb61 --- /dev/null +++ b/corev_apu/fpga/vivado_pid1465060.str @@ -0,0 +1,2193 @@ +/* + +AMD Vivado v2023.1 (64-bit) [Major: 2023, Minor: 1] +SW Build: 3865809 on Sun May 7 15:04:56 MDT 2023 +IP Build: 3864474 on Sun May 7 20:36:21 MDT 2023 +IP Build: 3864474 on Sun May 7 20:36:21 MDT 2023 + +Process ID (PID): 1465060 +License: Customer +Mode: GUI Mode + +Current time: Tue Apr 29 14:56:50 CEST 2025 +Time zone: Central European Standard Time (Europe/Paris) + +OS: Ubuntu +OS Version: 6.11.0-24-generic +OS Architecture: amd64 +Available processors (cores): 22 + +Display: 1 +Screen size: 1920x1080 +Screen resolution (DPI): 100 +Available screens: 3 +Default font: family=Dialog,name=Dialog,style=plain,size=12 +Scale size: 12 +OS font scaling: 100% + +Java version: 17.0.3 64-bit +JavaFX version: 17.0.1 +Java home: /tools/Xilinx/Vivado/2023.1/tps/lnx64/jre17.0.3_7 +Java executable: /tools/Xilinx/Vivado/2023.1/tps/lnx64/jre17.0.3_7/bin/java +Java arguments: [-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Djdk.gtk.version=2, -Dsun.java2d.uiScale.enabled=false, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, -XX:+UseStringDeduplication, -XX:MaxGCPauseMillis=200, -XX:+ParallelRefProcEnabled, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/java.awt.event=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-exports=java.base/java.nio=ALL-UNNAMED, --add-exports=java.desktop/sun.swing=ALL-UNNAMED, --add-exports=java.desktop/javax.swing=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-exports=java.desktop/sun.swing=ALL-UNNAMED, --add-exports=java.desktop/sun.swing.table=ALL-UNNAMED, --add-exports=java.desktop/sun.swing.plaf.synth=ALL-UNNAMED, --add-exports=java.desktop/sun.awt.shell=ALL-UNNAMED, --add-exports=java.base/sun.security.action=ALL-UNNAMED, --add-exports=java.desktop/sun.font=ALL-UNNAMED, --add-opens=java.desktop/sun.awt.X11=ALL-UNNAMED, -XX:NewSize=80m, -XX:MaxNewSize=80m, -Xms512m, -Xmx4072m, -Xss10m, -Xrs] +Java initial memory (-Xms): 512 MB +Java maximum memory (-Xmx): 3 GB + +User name: stagiaire +User home directory: /home/stagiaire +User working directory: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga +User country: US +User language: en +User locale: en_US + +RDI_BASEROOT: /tools/Xilinx/Vivado +HDI_APPROOT: /tools/Xilinx/Vivado/2023.1 +RDI_DATADIR: /tools/Xilinx/SharedData/2023.1/data:/tools/Xilinx/Vivado/2023.1/data +RDI_BINDIR: /tools/Xilinx/Vivado/2023.1/bin + +Vivado preferences file: /home/stagiaire/.Xilinx/Vivado/2023.1/vivado.xml +Vivado preferences directory: /home/stagiaire/.Xilinx/Vivado/2023.1/ +Vivado layouts directory: /home/stagiaire/.Xilinx/Vivado/2023.1/data/layouts +PlanAhead jar file: /tools/Xilinx/Vivado/2023.1/lib/classes/planAhead.jar +Vivado log file: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/vivado.log +Vivado journal file: +Engine tmp dir: ./.Xil/Vivado-1465060-qdtis2423h +Non-Default Parameters: [] + +Xilinx & AMD Environment Variables +-------------------------------------------------------------------------------------------- +GNOME_SHELL_SESSION_MODE: ubuntu +RDI_APPROOT: /tools/Xilinx/Vivado/2023.1 +RDI_BASEROOT: /tools/Xilinx/Vivado +RDI_BINROOT: /tools/Xilinx/Vivado/2023.1/bin +RDI_BUILD: yes +RDI_DATADIR: /tools/Xilinx/SharedData/2023.1/data:/tools/Xilinx/Vivado/2023.1/data +RDI_INSTALLROOT: /tools/Xilinx +RDI_INSTALLVER: 2023.1 +RDI_JAVA_PLATFORM: +RDI_JAVA_VERSION: 17.0.3_7 +RDI_LIBDIR: /tools/Xilinx/Vivado/2023.1/lib/lnx64.o/Ubuntu:/tools/Xilinx/Vivado/2023.1/lib/lnx64.o +RDI_OPT_EXT: .o +RDI_PATCHROOT: +RDI_PLATFORM: lnx64 +RDI_PREPEND_PATH: /tools/Xilinx/Vitis/2023.1/bin:/tools/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/lin64 +RDI_PROG: /tools/Xilinx/Vivado/2023.1/bin/unwrapped/lnx64.o/vivado +RDI_SESSION_INFO: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga:qdtis2423h_1745931400_1464992 +RDI_SHARED_DATA: /tools/Xilinx/SharedData/2023.1/data +RDI_TPS_ROOT: /tools/Xilinx/Vivado/2023.1/tps/lnx64 +RDI_USE_JDK17: True +SHELL: /bin/bash +XILINX: /tools/Xilinx/Vivado/2023.1/ids_lite/ISE +XILINX_BOARD: xilinx.com:vcu118:part0:2.0 +XILINX_DSP: /tools/Xilinx/Vivado/2023.1/ids_lite/ISE +XILINX_HLS: /tools/Xilinx/Vitis_HLS/2023.1 +XILINX_PART: xcvu9p-flga2104-2L-e +XILINX_PLANAHEAD: /tools/Xilinx/Vivado/2023.1 +XILINX_SDK: /tools/Xilinx/Vitis/2023.1 +XILINX_VITIS: /tools/Xilinx/Vitis/2023.1 +XILINX_VIVADO: /tools/Xilinx/Vivado/2023.1 +XILINX_VIVADO_HLS: /tools/Xilinx/Vivado/2023.1 + + +GUI allocated memory: 512 MB +GUI max memory: 4,072 MB +Engine allocated memory: 2,437 MB + +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + +*/ + +// TclEventType: START_GUI +// Tcl Message: start_gui +// TclEventType: START_PROGRESS_DIALOG +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: FLOW_ADDED +// Tcl Message: source scripts/prologue.tcl +// Tcl Message: # set project ariane # create_project $project . -force -part $::env(XILINX_PART) +// TclEventType: FILE_SET_NEW +// TclEventType: RUN_ADD +// TclEventType: RUN_CURRENT +// TclEventType: PROJECT_DASHBOARD_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_NEW +// [GUI Memory]: 99 MB (+101141kb) [00:00:08] +// [Engine Memory]: 2,534 MB (+2505525kb) [00:00:08] +// [GUI Memory]: 124 MB (+21005kb) [00:00:09] +// WARNING: HEventQueue.dispatchEvent() is taking 1009 ms. +// TclEventType: FILE_SET_OPTIONS_CHANGE +// HMemoryUtils.trashcanNow. Engine heap size: 2,689 MB. GUI used memory: 74 MB. Current time: 4/29/25, 2:56:52 PM CEST +// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2023.1/data/ip'. +// TclEventType: FILE_SET_OPTIONS_CHANGE +// [Engine Memory]: 2,692 MB (+32544kb) [00:00:10] +// TclEventType: FILE_SET_OPTIONS_CHANGE +// TclEventType: BOARD_MODIFIED +// TclEventType: MSGMGR_REFRESH_MSG +// TclEventType: STOP_PROGRESS_DIALOG +dismissDialog("Sourcing Tcl script 'scripts/prologue.tcl'"); // bq +// Tcl Message: create_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 8716.480 ; gain = 491.762 ; free physical = 19177 ; free virtual = 27708 +// Tcl Message: # set_property board_part $::env(XILINX_BOARD) [current_project] # set_param general.maxThreads 8 # set_msg_config -id {[Synth 8-5858]} -new_severity "info" # set_msg_config -id {[Synth 8-4480]} -limit 1000 +// TclEventType: STOP_PROGRESS_DIALOG +// TclEventType: START_PROGRESS_DIALOG +// TclEventType: FILE_SET_CHANGE +// Tcl Message: source scripts/run.tcl +// TclEventType: FILE_SET_CHANGE +// [GUI Memory]: 132 MB (+1579kb) [00:00:12] +// TclEventType: FILE_SET_CHANGE +// TclEventType: FILE_SET_OPTIONS_CHANGE +// TclEventType: FILE_SET_CHANGE +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// Tcl Message: # add_files -fileset constrs_1 -norecurse constraints/$project.xdc # synth_design -rtl -name rtl_1 +// Tcl Message: Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xcvu9p-flga2104-2L-e Top: ariane_xilinx +// TclEventType: ELABORATE_START +// [Engine Memory]: 3,712 MB (+928277kb) [00:00:23] +// HMemoryUtils.trashcanNow. Engine heap size: 4,417 MB. GUI used memory: 77 MB. Current time: 4/29/25, 2:57:11 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 4,871 MB. GUI used memory: 89 MB. Current time: 4/29/25, 2:57:23 PM CEST +// TclEventType: ELABORATE_FINISH +// HMemoryUtils.trashcanNow. Engine heap size: 5,496 MB. GUI used memory: 76 MB. Current time: 4/29/25, 2:57:41 PM CEST +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_CNS_STALE +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: SIGNAL_INTERFACE_ADD +// TclEventType: SIGNAL_HIERARCHY_CHANGED +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// [Engine Memory]: 5,832 MB (+2029112kb) [00:01:06] +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: FLOORPLAN_MODIFY +// TclEventType: DESIGN_NEW +// HMemoryUtils.trashcanNow. Engine heap size: 5,884 MB. GUI used memory: 76 MB. Current time: 4/29/25, 2:57:50 PM CEST +// [GUI Memory]: 140 MB (+1448kb) [00:01:08] +// [GUI Memory]: 149 MB (+2392kb) [00:01:08] +// TclEventType: DESIGN_NEW +// [GUI Memory]: 163 MB (+7527kb) [00:01:09] +// [GUI Memory]: 179 MB (+8099kb) [00:01:09] +// [GUI Memory]: 195 MB (+7315kb) [00:01:09] +// [Engine Memory]: 6,155 MB (+32106kb) [00:01:09] +// [GUI Memory]: 206 MB (+594kb) [00:01:09] +// [GUI Memory]: 232 MB (+16574kb) [00:01:09] +// Xgd.load filename: /tools/Xilinx/Vivado/2023.1/data/parts/xilinx/virtexuplus/devint/virtexuplus/xcvu9p/xcvu9p.xgd; ZipEntry: xcvu9p_detail.xgd elapsed time: 0.9s +// DeviceModel: Load Xgds SwingWorker Join Forever elapsed time: 1s +// [GUI Memory]: 256 MB (+13086kb) [00:01:09] +// [Engine Memory]: 6,571 MB (+114039kb) [00:01:09] +// WARNING: HEventQueue.dispatchEvent() is taking 1541 ms. +// TclEventType: CURR_DESIGN_SET +// Tcl Message: INFO: [Device 21-403] Loading part xcvu9p-flga2104-2L-e +// Tcl Message: INFO: [Synth 8-11241] undeclared symbol 'dout', assumed default net type 'wire' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/ariane-ethernet/dualmem_widen8.sv:88] +// Tcl Message: INFO: [Synth 8-11241] undeclared symbol 'led', assumed default net type 'wire' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/ariane_xilinx.sv:928] INFO: [Synth 8-11241] undeclared symbol 'sw', assumed default net type 'wire' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/ariane_xilinx.sv:929] INFO: [Synth 8-11241] undeclared symbol 'unused_switches', assumed default net type 'wire' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/ariane_xilinx.sv:929] +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 10103.402 ; gain = 340.578 ; free physical = 17743 ; free virtual = 26317 +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'ariane_xilinx' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/ariane_xilinx.sv:14] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 4 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 4 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'axi_xbar' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/axi/src/axi_xbar.sv:18] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'addr_decode' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/addr_decode.sv:30] +// Tcl Message: Parameter NoIndices bound to: 32'b00000000000000000000000000001010 Parameter NoRules bound to: 32'b00000000000000000000000000001010 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'addr_decode' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/addr_decode.sv:30] INFO: [Synth 8-6157] synthesizing module 'axi_demux' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/axi/src/axi_demux.sv:19] +// Tcl Message: Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter NoMstPorts bound to: 32'b00000000000000000000000000001011 Parameter MaxTrans bound to: 32'b00000000000000000000000000000001 Parameter AxiLookBits bound to: 32'b00000000000000000000000000000100 Parameter UniqueIds bound to: 1'b0 Parameter FallThrough bound to: 1'b0 Parameter SpillAw bound to: 1'b1 Parameter SpillW bound to: 1'b1 Parameter SpillB bound to: 1'b1 Parameter SpillAr bound to: 1'b1 Parameter SpillR bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'axi_demux_id_counters' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/axi/src/axi_demux.sv:576] +// Tcl Message: Parameter AxiIdBits bound to: 32'b00000000000000000000000000000100 Parameter CounterWidth bound to: 32'b00000000000000000000000000000001 +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-6157] synthesizing module 'delta_counter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000000001 Parameter STICKY_OVERFLOW bound to: 1'b0 +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'fifo_v3' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized1' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized1' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized1' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized1' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000001011 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'lzc' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/lzc.sv:25] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000001011 Parameter MODE bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lzc' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized2' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized2' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized3' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized3' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000001011 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6155] done synthesizing module 'axi_demux' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/axi/src/axi_demux.sv:19] INFO: [Synth 8-6157] synthesizing module 'axi_err_slv' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/axi/src/axi_err_slv.sv:19] +// Tcl Message: Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter Resp bound to: 2'b11 Parameter ATOPs bound to: 1'b1 Parameter MaxTrans bound to: 32'b00000000000000000000000000000100 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'axi_atop_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/axi/src/axi_atop_filter.sv:37] +// Tcl Message: Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter AxiMaxWriteTxns bound to: 32'b00000000000000000000000000000100 +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b1 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized1' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized2' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized3' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'counter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/counter.sv:14] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000001000 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'delta_counter__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000001000 Parameter STICKY_OVERFLOW bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'delta_counter__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] INFO: [Synth 8-6155] done synthesizing module 'counter' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/counter.sv:14] INFO: [Synth 8-6155] done synthesizing module 'axi_err_slv' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/axi/src/axi_err_slv.sv:19] INFO: [Synth 8-6157] synthesizing module 'axi_mux' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/axi/src/axi_mux.sv:27] +// Tcl Message: Parameter SlvAxiIDWidth bound to: 32'b00000000000000000000000000000100 Parameter NoSlvPorts bound to: 32'b00000000000000000000000000000010 Parameter MaxWTrans bound to: 32'b00000000000000000000000000000001 Parameter FallThrough bound to: 1'b0 Parameter SpillAw bound to: 1'b1 Parameter SpillW bound to: 1'b1 Parameter SpillB bound to: 1'b1 Parameter SpillAr bound to: 1'b1 Parameter SpillR bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'axi_id_prepend' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/axi/src/axi_id_prepend.sv:18] +// Tcl Message: Parameter NoBus bound to: 1 - type: integer Parameter AxiIdWidthSlvPort bound to: 32'b00000000000000000000000000000100 Parameter AxiIdWidthMstPort bound to: 32'b00000000000000000000000000000101 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'axi_id_prepend' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/axi/src/axi_id_prepend.sv:18] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree__parameterized1' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000000010 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'lzc__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/lzc.sv:25] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000000010 Parameter MODE bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized1' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized4' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized4' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized4' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized4' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized4' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized4' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized5' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized5' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized5' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized5' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000000010 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized2' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized6' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized6' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized6' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized6' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized7' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized7' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: Parameter IrLength bound to: 32'b00000000000000000000000000000101 Parameter IdcodeValue bound to: 1 - type: integer +// Tcl Message: Parameter NrHarts bound to: 32'b00000000000000000000000000000001 Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter SelectableHarts bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'dm_csrs' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/riscv-dbg/src/dm_csrs.sv:18] +// Tcl Message: Parameter NrHarts bound to: 32'b00000000000000000000000000000001 Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter SelectableHarts bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/riscv-dbg/src/dm_csrs.sv:294] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/riscv-dbg/src/dm_csrs.sv:360] INFO: [Synth 8-6157] synthesizing module 'fifo_v2__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv:13] +// Tcl Message: Parameter DEPTH bound to: 32'b00000000000000000000000000000010 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized5' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized5' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6155] done synthesizing module 'fifo_v2__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv:13] INFO: [Synth 8-6155] done synthesizing module 'dm_csrs' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/riscv-dbg/src/dm_csrs.sv:18] INFO: [Synth 8-6157] synthesizing module 'dm_sba' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/riscv-dbg/src/dm_sba.sv:18] +// Tcl Message: Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter ReadByteEnable bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/riscv-dbg/src/dm_sba.sv:72] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/riscv-dbg/src/dm_sba.sv:101] INFO: [Synth 8-6155] done synthesizing module 'dm_sba' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/riscv-dbg/src/dm_sba.sv:18] INFO: [Synth 8-6157] synthesizing module 'dm_mem' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/riscv-dbg/src/dm_mem.sv:19] +// Tcl Message: Parameter NrHarts bound to: 32'b00000000000000000000000000000001 Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter SelectableHarts bound to: 1'b1 Parameter DmBaseAddress bound to: 32'b00000000000000000001000000000000 +// Tcl Message: Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_ADDR_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cache_subsystem/axi_adapter.sv:486] INFO: [Synth 8-6155] done synthesizing module 'axi_adapter' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cache_subsystem/axi_adapter.sv:19] INFO: [Synth 8-6157] synthesizing module 'ariane' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/src/ariane.sv:17] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'cva6' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cva6.sv:18] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'perf_counters' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/perf_counters.sv:16] +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'perf_counters' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/perf_counters.sv:16] INFO: [Synth 8-6157] synthesizing module 'wt_cache_subsystem' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cache_subsystem/wt_cache_subsystem.sv:22] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'cva6_icache' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cache_subsystem/cva6_icache.sv:28] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'sram_cache' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/common/local/util/sram_cache.sv:21] +// Tcl Message: Parameter DATA_WIDTH bound to: 45 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer Parameter BYTE_ACCESS bound to: 0 - type: integer Parameter TECHNO_CUT bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'sram' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/common/local/util/sram.sv:21] +// Tcl Message: Parameter DATA_WIDTH bound to: 45 - type: integer Parameter USER_WIDTH bound to: 1 - type: integer Parameter USER_EN bound to: 0 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'tc_sram_wrapper' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/common/local/util/tc_sram_fpga_wrapper.sv:10] +// Tcl Message: Parameter NumWords bound to: 256 - type: integer Parameter DataWidth bound to: 32'b00000000000000000000000001000000 Parameter ByteWidth bound to: 8 - type: integer Parameter NumPorts bound to: 1 - type: integer Parameter Latency bound to: 1 - type: integer Parameter SimInit bound to: none - type: string Parameter PrintSimCfg bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'SyncSpRamBeNx64' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv:28] +// Tcl Message: Parameter ADDR_WIDTH bound to: 8 - type: integer Parameter DATA_DEPTH bound to: 256 - type: integer Parameter OUT_REGS bound to: 0 - type: integer Parameter SIM_INIT bound to: 1 - type: integer +// Tcl Message: Parameter DATA_WIDTH bound to: 128 - type: integer Parameter USER_WIDTH bound to: 128 - type: integer Parameter USER_EN bound to: 0 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer Parameter BYTE_ACCESS bound to: 0 - type: integer Parameter TECHNO_CUT bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'sram__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/common/local/util/sram.sv:21] +// Tcl Message: Parameter DATA_WIDTH bound to: 128 - type: integer Parameter USER_WIDTH bound to: 128 - type: integer Parameter USER_EN bound to: 0 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'sram__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/common/local/util/sram.sv:21] INFO: [Synth 8-6155] done synthesizing module 'sram_cache__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/common/local/util/sram_cache.sv:21] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cache_subsystem/cva6_icache.sv:220] INFO: [Synth 8-6157] synthesizing module 'lzc__parameterized1' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/lzc.sv:25] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000000100 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized1' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Synth 8-6157] synthesizing module 'lfsr' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/lfsr.sv:22] +// Tcl Message: Parameter LfsrWidth bound to: 32'b00000000000000000000000000001000 Parameter OutWidth bound to: 32'b00000000000000000000000000000010 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lfsr' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/lfsr.sv:22] INFO: [Synth 8-6155] done synthesizing module 'cva6_icache' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cache_subsystem/cva6_icache.sv:28] INFO: [Synth 8-6157] synthesizing module 'wt_dcache' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cache_subsystem/wt_dcache.sv:16] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'wt_dcache_ctrl' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cache_subsystem/wt_dcache_ctrl.sv:16] +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cache_subsystem/wt_dcache_ctrl.sv:134] INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cache_subsystem/wt_dcache_ctrl.sv:134] INFO: [Synth 8-6155] done synthesizing module 'wt_dcache_ctrl' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cache_subsystem/wt_dcache_ctrl.sv:16] INFO: [Synth 8-6157] synthesizing module 'wt_dcache_missunit' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cache_subsystem/wt_dcache_missunit.sv:17] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'lzc__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000001000 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized2' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/lzc.sv:25] +// Tcl Message: Parameter LfsrWidth bound to: 32'b00000000000000000000000000001000 Parameter OutWidth bound to: 32'b00000000000000000000000000000011 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/lfsr.sv:22] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cache_subsystem/wt_dcache_missunit.sv:98] +// Tcl Message: Parameter Seed bound to: 32'b00000000000000000000000000000011 Parameter MaxExp bound to: 32'b00000000000000000000000000010000 +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/include/wt_cache_pkg.sv:134] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cache_subsystem/wt_dcache_wbuffer.sv:142] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cache_subsystem/wt_dcache_wbuffer.sv:116] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000000010 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter FPGA_EN bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'cva6_fifo_v3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cva6_fifo_v3.sv:16] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000000100 Parameter DataWidth bound to: 32'b00000000000000000000000000000001 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000001000 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized4' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/frontend/frontend.sv:235] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/frontend/frontend.sv:235] +// Tcl Message: Parameter FPGA_ALTERA bound to: 1'b0 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter FPGA_EN bound to: 1'b0 Parameter FPGA_ALTERA bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FPGA_EN bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/include/ariane_pkg.sv:562] +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/issue_read_operands.sv:382] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/issue_read_operands.sv:399] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000001001 Parameter ExtPrio bound to: 1'b1 Parameter AxiVldRdy bound to: 1'b1 +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000001101 Parameter DataWidth bound to: 32'b00000000000000000000000001000000 Parameter ExtPrio bound to: 1'b1 Parameter AxiVldRdy bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/fpu_wrap.sv:440] +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cvfpu/src/fpnew_rounding.sv:48] +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cvfpu/src/fpnew_rounding.sv:48] +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cvfpu/src/fpnew_pkg.sv:89] +// Tcl Message: Parameter AbsWidth bound to: 32'b00000000000000000000000001000000 +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cvfpu/src/fpnew_rounding.sv:48] INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/core/cvfpu/src/fpnew_pkg.sv:89] +// Tcl Message: Parameter DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FPGA_EN bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/clint/axi_lite_interface.sv:78] +// Tcl Message: Parameter STAGES bound to: 32'b00000000000000000000000000000010 Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-155] case statement is not full and has no default [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/axi_mem_if/src/axi2mem.sv:192] INFO: [Synth 8-155] case statement is not full and has no default [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/axi_mem_if/src/axi2mem.sv:234] INFO: [Synth 8-155] case statement is not full and has no default [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/axi_mem_if/src/axi2mem.sv:122] +// Tcl Message: Parameter AxiAddrWidth bound to: 64 - type: integer Parameter AxiDataWidth bound to: 64 - type: integer Parameter AxiIdWidth bound to: 5 - type: integer Parameter AxiUserWidth bound to: 64 - type: integer Parameter InclUART bound to: 1'b1 Parameter InclSPI bound to: 1'b1 Parameter InclEthernet bound to: 1'b0 Parameter InclGPIO bound to: 1'b1 +// Tcl Message: Parameter SIZE bound to: 2 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:28' bound to instance 'UART_IF_CTS' of component 'slib_input_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:402] INFO: [Synth 8-638] synthesizing module 'slib_input_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:41] +// Tcl Message: Parameter SIZE bound to: 2 - type: integer +// Tcl Message: INFO: [Synth 8-256] done synthesizing module 'slib_input_filter' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:41] +// Tcl Message: Parameter SIZE bound to: 2 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:28' bound to instance 'UART_IF_DSR' of component 'slib_input_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:403] +// Tcl Message: Parameter SIZE bound to: 2 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:28' bound to instance 'UART_IF_DCD' of component 'slib_input_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:404] +// Tcl Message: Parameter SIZE bound to: 2 - type: integer +// Tcl Message: Parameter RATIO bound to: 8 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_clock_div' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_clock_div.vhd:29' bound to instance 'UART_BG2' of component 'slib_clock_div' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:752] INFO: [Synth 8-638] synthesizing module 'slib_clock_div' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_clock_div.vhd:41] +// Tcl Message: Parameter RATIO bound to: 8 - type: integer +// Tcl Message: INFO: [Synth 8-256] done synthesizing module 'slib_clock_div' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_clock_div.vhd:41] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_edge_detect.vhd:28' bound to instance 'UART_RCLK' of component 'slib_edge_detect' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:758] +// Tcl Message: Parameter WIDTH bound to: 8 - type: integer Parameter SIZE_E bound to: 6 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_fifo' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_fifo.vhd:29' bound to instance 'UART_TXFF' of component 'slib_fifo' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:765] INFO: [Synth 8-638] synthesizing module 'slib_fifo' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_fifo.vhd:48] +// Tcl Message: Parameter WIDTH bound to: 8 - type: integer Parameter SIZE_E bound to: 6 - type: integer +// Tcl Message: INFO: [Synth 8-256] done synthesizing module 'slib_fifo' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_fifo.vhd:48] +// Tcl Message: Parameter WIDTH bound to: 11 - type: integer Parameter SIZE_E bound to: 6 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_fifo' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_fifo.vhd:29' bound to instance 'UART_RXFF' of component 'slib_fifo' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:784] INFO: [Synth 8-638] synthesizing module 'slib_fifo__parameterized1' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_fifo.vhd:48] +// Tcl Message: Parameter WIDTH bound to: 11 - type: integer Parameter SIZE_E bound to: 6 - type: integer +// Tcl Message: Parameter WIDTH bound to: 4 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_counter' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_counter.vhd:29' bound to instance 'RX_BRC' of component 'slib_counter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/uart_receiver.vhd:122] INFO: [Synth 8-638] synthesizing module 'slib_counter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_counter.vhd:46] +// Tcl Message: Parameter WIDTH bound to: 4 - type: integer +// Tcl Message: INFO: [Synth 8-256] done synthesizing module 'slib_counter' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_counter.vhd:46] +// Tcl Message: Parameter WIDTH bound to: 4 - type: integer Parameter THRESHOLD bound to: 10 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_mv_filter' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_mv_filter.vhd:29' bound to instance 'RX_MVF' of component 'slib_mv_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/uart_receiver.vhd:137] INFO: [Synth 8-638] synthesizing module 'slib_mv_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_mv_filter.vhd:44] +// Tcl Message: Parameter WIDTH bound to: 4 - type: integer Parameter THRESHOLD bound to: 10 - type: integer +// Tcl Message: INFO: [Synth 8-256] done synthesizing module 'slib_mv_filter' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_mv_filter.vhd:44] +// Tcl Message: Parameter SIZE bound to: 4 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:28' bound to instance 'RX_IFSB' of component 'slib_input_filter' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/uart_receiver.vhd:150] INFO: [Synth 8-638] synthesizing module 'slib_input_filter__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:41] +// Tcl Message: Parameter SIZE bound to: 4 - type: integer +// Tcl Message: INFO: [Synth 8-155] case statement is not full and has no default [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_timer/timer.sv:92] INFO: [Synth 8-155] case statement is not full and has no default [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/src/apb_timer/timer.sv:116] +// Tcl Message: Parameter ADDR_WIDTH bound to: 32'sb00000000000000000000000000100000 Parameter DATA_WIDTH bound to: 32'sb00000000000000000000000000100000 Parameter N_SOURCE bound to: 32'sb00000000000000000000000000011110 Parameter N_TARGET bound to: 32'sb00000000000000000000000000000010 Parameter MAX_PRIO bound to: 32'sb00000000000000000000000000000111 Parameter N_SOURCE bound to: 32'sb00000000000000000000000000011110 Parameter MAX_PRIO bound to: 32'sb00000000000000000000000000000111 Parameter ALGORITHM bound to: SEQUENTIAL - type: string Parameter N_SOURCE bound to: 32'sb00000000000000000000000000011110 +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv:580] INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv:809] +// Tcl Message: Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv:39] +// Tcl Message: INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +// Tcl Message: INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: Finished RTL Elaboration : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 10890.082 ; gain = 1127.258 ; free physical = 16692 ; free virtual = 25380 +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- +// Tcl Message: Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 10890.082 ; gain = 1127.258 ; free physical = 16690 ; free virtual = 25372 +// Tcl Message: --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- +// Tcl Message: Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 10890.082 ; gain = 1127.258 ; free physical = 16690 ; free virtual = 25372 +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 10919.926 ; gain = 0.000 ; free physical = 16710 ; free virtual = 25379 +// Tcl Message: INFO: [Netlist 29-17] Analyzing 1083 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.1 INFO: [Project 1-570] Preparing netlist for logic optimization +// Tcl Message: INFO: [Opt 31-140] Inserted 2 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 6 OBUFs to IO ports without IO buffers. +// Tcl Message: Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/bd_0/ip/ip_0/bd_f0c7_microblaze_I_0.xdc] for cell 'i_ddr/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0' Finished Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/bd_0/ip/ip_0/bd_f0c7_microblaze_I_0.xdc] for cell 'i_ddr/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0' +// Tcl Message: INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/bd_0/ip/ip_0/bd_f0c7_microblaze_I_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +// Tcl Message: Finished Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/par/xlnx_mig_ddr4.xdc] for cell 'i_ddr/inst' +// Tcl Message: INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/par/xlnx_mig_ddr4.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +// Tcl Message: INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.gen/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +// Tcl Message: INFO: [Timing 38-2] Deriving generated clocks +// Tcl Message: Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/constraints/vcu118.xdc] +// Tcl Message: Finished Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/constraints/vcu118.xdc] +// Tcl Message: INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/constraints/vcu118.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +// Tcl Message: Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/constraints/ariane.xdc] +// Tcl Message: Finished Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/constraints/ariane.xdc] +// Tcl Message: INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/constraints/ariane.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: Completed Processing XDC Constraints +// Tcl Message: INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 11892.621 ; gain = 0.000 ; free physical = 15961 ; free virtual = 24623 +// TclEventType: RUN_MODIFY +// TclEventType: RUN_OPTIONS_MODIFIED +// TclEventType: RUN_LAUNCH +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_MODIFY +// HMemoryUtils.trashcanNow. Engine heap size: 6,726 MB. GUI used memory: 178 MB. Current time: 4/29/25, 2:57:54 PM CEST +// Tcl Message: RTL Elaboration Complete: : Time (s): cpu = 00:01:13 ; elapsed = 00:00:48 . Memory (MB): peak = 12078.152 ; gain = 2315.328 ; free physical = 15337 ; free virtual = 24030 +// Tcl Message: 428 Infos, 362 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully +// Tcl Message: synth_design: Time (s): cpu = 00:01:19 ; elapsed = 00:00:55 . Memory (MB): peak = 12078.152 ; gain = 3305.164 ; free physical = 15337 ; free virtual = 24030 +// Tcl Message: INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] +// Tcl Message: # set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] # launch_runs synth_1 +// Tcl Message: [Tue Apr 29 14:57:53 2025] Launched synth_1... Run output will be captured here: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/ariane.runs/synth_1/runme.log +// Tcl Message: # wait_on_run synth_1 +// Tcl Message: [Tue Apr 29 14:57:54 2025] Waiting for synth_1 to finish... +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: [Tue Apr 29 14:57:59 2025] Waiting for synth_1 to finish... +// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED +// RouteApi::loadEngineXgdAndInitRouteStorage elapsed time: 8.7s +// Tcl Message: [Tue Apr 29 14:58:04 2025] Waiting for synth_1 to finish... +// Tcl Message: [Tue Apr 29 14:58:09 2025] Waiting for synth_1 to finish... +// Tcl Message: [Tue Apr 29 14:58:19 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,558 MB. GUI used memory: 210 MB. Current time: 4/29/25, 2:58:23 PM CEST +// Tcl Message: [Tue Apr 29 14:58:29 2025] Waiting for synth_1 to finish... +// Tcl Message: [Tue Apr 29 14:58:39 2025] Waiting for synth_1 to finish... +// Tcl Message: [Tue Apr 29 14:58:49 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,551 MB. GUI used memory: 236 MB. Current time: 4/29/25, 2:58:53 PM CEST +// Tcl Message: [Tue Apr 29 14:59:09 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,551 MB. GUI used memory: 189 MB. Current time: 4/29/25, 2:59:23 PM CEST +// Tcl Message: [Tue Apr 29 14:59:29 2025] Waiting for synth_1 to finish... +// Tcl Message: [Tue Apr 29 14:59:49 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,552 MB. GUI used memory: 223 MB. Current time: 4/29/25, 2:59:53 PM CEST +// Tcl Message: [Tue Apr 29 15:00:09 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,552 MB. GUI used memory: 186 MB. Current time: 4/29/25, 3:00:24 PM CEST +// Tcl Message: [Tue Apr 29 15:00:49 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,552 MB. GUI used memory: 186 MB. Current time: 4/29/25, 3:00:54 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 6,553 MB. GUI used memory: 186 MB. Current time: 4/29/25, 3:01:24 PM CEST +// Tcl Message: [Tue Apr 29 15:01:29 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,553 MB. GUI used memory: 186 MB. Current time: 4/29/25, 3:01:54 PM CEST +// Tcl Message: [Tue Apr 29 15:02:09 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,546 MB. GUI used memory: 186 MB. Current time: 4/29/25, 3:02:24 PM CEST +// Tcl Message: [Tue Apr 29 15:02:49 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,546 MB. GUI used memory: 186 MB. Current time: 4/29/25, 3:02:54 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 6,546 MB. GUI used memory: 186 MB. Current time: 4/29/25, 3:03:24 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 6,546 MB. GUI used memory: 186 MB. Current time: 4/29/25, 3:03:54 PM CEST +// Tcl Message: [Tue Apr 29 15:04:09 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,546 MB. GUI used memory: 187 MB. Current time: 4/29/25, 3:04:24 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 6,546 MB. GUI used memory: 187 MB. Current time: 4/29/25, 3:04:54 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 6,546 MB. GUI used memory: 187 MB. Current time: 4/29/25, 3:05:24 PM CEST +// Tcl Message: [Tue Apr 29 15:05:29 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,546 MB. GUI used memory: 187 MB. Current time: 4/29/25, 3:05:54 PM CEST +// TclEventType: RUN_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_STEP_COMPLETED +// [GUI Memory]: 270 MB (+807kb) [00:09:22] +// Tcl Message: [Tue Apr 29 15:06:03 2025] synth_1 finished +// Tcl Message: wait_on_runs: Time (s): cpu = 00:07:32 ; elapsed = 00:08:10 . Memory (MB): peak = 12556.422 ; gain = 468.270 ; free physical = 18847 ; free virtual = 23210 +// Tcl Message: # open_run synth_1 +// Tcl Message: Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xcvu9p-flga2104-2L-e +// HMemoryUtils.trashcanNow. Engine heap size: 6,532 MB. GUI used memory: 198 MB. Current time: 4/29/25, 3:06:24 PM CEST +// TclEventType: DEBUG_PORT_ADD +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_CNS_STALE +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: SIGNAL_INTERFACE_ADD +// TclEventType: SIGNAL_HIERARCHY_CHANGED +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// HMemoryUtils.trashcanNow. Engine heap size: 6,558 MB. GUI used memory: 196 MB. Current time: 4/29/25, 3:06:54 PM CEST +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// [Engine Memory]: 6,921 MB (+22451kb) [00:10:18] +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: TIMING_RESULTS_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: FLOORPLAN_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: DESIGN_NEW +// HMemoryUtils.trashcanNow. Engine heap size: 6,981 MB. GUI used memory: 196 MB. Current time: 4/29/25, 3:07:14 PM CEST +// TclEventType: DESIGN_NEW +// DeviceView Instantiated +// TclEventType: CURR_DESIGN_SET +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.79 . Memory (MB): peak = 12556.422 ; gain = 0.000 ; free physical = 18750 ; free virtual = 23170 +// Tcl Message: INFO: [Netlist 29-17] Analyzing 5370 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.1 INFO: [Project 1-570] Preparing netlist for logic optimization +// Tcl Message: INFO: [Chipscope 16-324] Core: i_ddr UUID: 95d64970-6efe-555a-a048-dc3a209f704a +// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.gen/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.gen/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc:57] +// Tcl Message: Finished Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/constraints/vcu118.xdc] Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/constraints/ariane.xdc] +// Tcl Message: INFO: [Project 1-1714] 53 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +// Tcl Message: Generating merged BMM file for the design top 'ariane_xilinx'... +// Tcl Message: INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/sw/calibration_0/Debug/calibration_ddr.elf +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 12920.602 ; gain = 0.000 ; free physical = 17737 ; free virtual = 22450 +// Device view-level: 0.0 +// Tcl Message: open_run: Time (s): cpu = 00:00:44 ; elapsed = 00:01:12 . Memory (MB): peak = 13065.656 ; gain = 509.234 ; free physical = 17505 ; free virtual = 22194 +// Tcl Message: # exec mkdir -p reports/ # exec rm -rf reports/* # check_timing -verbose -file reports/$project.check_timing.rpt +// [GUI Memory]: 284 MB (+620kb) [00:10:34] +// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. +// [Engine Memory]: 7,341 MB (+77981kb) [00:10:37] +// Device view-level: 0.0 +// [GUI Memory]: 298 MB (+671kb) [00:10:38] +// HMemoryUtils.trashcanNow. Engine heap size: 7,491 MB. GUI used memory: 221 MB. Current time: 4/29/25, 3:07:24 PM CEST +// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED +// RouteApi::loadEngineXgdAndInitRouteStorage elapsed time: 9.7s +// WARNING: HEventQueue.dispatchEvent() is taking 10414 ms. +// TclEventType: TIMING_RESULTS_STALE +// Tcl Message: check_timing: Time (s): cpu = 00:00:48 ; elapsed = 00:00:21 . Memory (MB): peak = 14279.820 ; gain = 1214.164 ; free physical = 16394 ; free virtual = 21393 +// Tcl Message: # report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 100 -nworst 100 -delay_type max -sort_by slack. +// Tcl Message: # report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by group. +// Tcl Message: # report_utilization -hierarchical -file reports/$project.utilization.rpt +// Tcl Message: # report_cdc -file reports/$project.cdc.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: No interconnect No Cell Dly, Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +// Tcl Message: INFO: [Timing 38-433] Consider using Xilinx recommended XPM_CDC modules to avoid Critical severities INFO: [Timing 38-314] The report_cdc command only analyzes and reports clock domain crossing paths where clocks have been defined on both source and destination sides. Ports with no input delay constraint are skipped. Please run check_timing to verify there are no missing clock definitions in your design, nor any unconstrained input port. +// Tcl Message: # report_clock_interaction -file reports/$project.clock_interaction.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +// TclEventType: TIMING_RESULTS_STALE +// TclEventType: RUN_MODIFY +// [Engine Memory]: 8,371 MB (+694238kb) [00:11:03] +// TclEventType: RUN_OPTIONS_MODIFIED +// TclEventType: RUN_MODIFY +// TclEventType: RUN_OPTIONS_MODIFIED +// Tcl Message: # set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1] # set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1] # launch_runs impl_1 +// Tcl Message: Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. +// Tcl Message: Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.33 . Memory (MB): peak = 14323.836 ; gain = 42.016 ; free physical = 16142 ; free virtual = 21333 +// HMemoryUtils.trashcanNow. Engine heap size: 8,433 MB. GUI used memory: 220 MB. Current time: 4/29/25, 3:07:51 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,403 MB. GUI used memory: 220 MB. Current time: 4/29/25, 3:07:54 PM CEST +// TclEventType: RUN_LAUNCH +// TclEventType: RUN_MODIFY +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: [Tue Apr 29 15:07:54 2025] Launched impl_1... Run output will be captured here: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/ariane.runs/impl_1/runme.log +// Tcl Message: launch_runs: Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 14333.836 ; gain = 54.016 ; free physical = 16280 ; free virtual = 21502 +// Tcl Message: # wait_on_run impl_1 +// Tcl Message: [Tue Apr 29 15:07:54 2025] Waiting for impl_1 to finish... +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: [Tue Apr 29 15:07:59 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 15:08:04 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 15:08:09 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 15:08:19 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,415 MB. GUI used memory: 220 MB. Current time: 4/29/25, 3:08:24 PM CEST +// TclEventType: RUN_STEP_COMPLETED +// Tcl Message: [Tue Apr 29 15:08:29 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 15:08:39 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 15:08:49 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,415 MB. GUI used memory: 220 MB. Current time: 4/29/25, 3:08:54 PM CEST +// Tcl Message: [Tue Apr 29 15:09:09 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,415 MB. GUI used memory: 220 MB. Current time: 4/29/25, 3:09:24 PM CEST +// Tcl Message: [Tue Apr 29 15:09:29 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 15:09:49 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,415 MB. GUI used memory: 220 MB. Current time: 4/29/25, 3:09:54 PM CEST +// Tcl Message: [Tue Apr 29 15:10:09 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,415 MB. GUI used memory: 220 MB. Current time: 4/29/25, 3:10:24 PM CEST +// Tcl Message: [Tue Apr 29 15:10:49 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,415 MB. GUI used memory: 220 MB. Current time: 4/29/25, 3:10:54 PM CEST +// TclEventType: RUN_STEP_COMPLETED +// Tcl Message: [Tue Apr 29 15:11:29 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 15:12:09 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 15:12:49 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 15:14:09 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 15:15:29 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,416 MB. GUI used memory: 221 MB. Current time: 4/29/25, 3:16:23 PM CEST +// Tcl Message: [Tue Apr 29 15:16:49 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,416 MB. GUI used memory: 221 MB. Current time: 4/29/25, 3:16:53 PM CEST +// TclEventType: RUN_STEP_COMPLETED +// HMemoryUtils.trashcanNow. Engine heap size: 8,416 MB. GUI used memory: 222 MB. Current time: 4/29/25, 3:17:23 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,416 MB. GUI used memory: 246 MB. Current time: 4/29/25, 3:17:53 PM CEST +// Tcl Message: [Tue Apr 29 15:18:09 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,417 MB. GUI used memory: 221 MB. Current time: 4/29/25, 3:18:23 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,417 MB. GUI used memory: 245 MB. Current time: 4/29/25, 3:18:53 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,417 MB. GUI used memory: 245 MB. Current time: 4/29/25, 3:19:23 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,417 MB. GUI used memory: 221 MB. Current time: 4/29/25, 3:19:54 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,417 MB. GUI used memory: 245 MB. Current time: 4/29/25, 3:20:23 PM CEST +// Tcl Message: [Tue Apr 29 15:20:49 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,417 MB. GUI used memory: 221 MB. Current time: 4/29/25, 3:20:54 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,417 MB. GUI used memory: 221 MB. Current time: 4/29/25, 3:21:24 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,417 MB. GUI used memory: 221 MB. Current time: 4/29/25, 3:21:54 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,417 MB. GUI used memory: 245 MB. Current time: 4/29/25, 3:22:24 PM CEST +// TclEventType: RUN_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_STEP_COMPLETED +// HMemoryUtils.trashcanNow. Engine heap size: 8,409 MB. GUI used memory: 222 MB. Current time: 4/29/25, 3:22:54 PM CEST +// TclEventType: RUN_LAUNCH +// TclEventType: RUN_MODIFY +// Tcl Message: [Tue Apr 29 15:22:54 2025] impl_1 finished +// Tcl Message: wait_on_runs: Time (s): cpu = 00:00:30 ; elapsed = 00:15:00 . Memory (MB): peak = 14333.836 ; gain = 0.000 ; free physical = 11827 ; free virtual = 20932 +// Tcl Message: # launch_runs impl_1 -to_step write_bitstream +// Tcl Message: [Tue Apr 29 15:22:54 2025] Launched impl_1... Run output will be captured here: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/ariane.runs/impl_1/runme.log +// Tcl Message: # wait_on_run impl_1 +// Tcl Message: [Tue Apr 29 15:22:54 2025] Waiting for impl_1 to finish... +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: [Tue Apr 29 15:22:59 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 15:23:04 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 15:23:09 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 15:23:19 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,711 MB. GUI used memory: 223 MB. Current time: 4/29/25, 3:23:21 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,543 MB. GUI used memory: 223 MB. Current time: 4/29/25, 3:23:24 PM CEST +// Tcl Message: [Tue Apr 29 15:23:29 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 15:23:40 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 29 15:23:50 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,543 MB. GUI used memory: 265 MB. Current time: 4/29/25, 3:23:54 PM CEST +// Tcl Message: [Tue Apr 29 15:24:10 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,543 MB. GUI used memory: 222 MB. Current time: 4/29/25, 3:24:24 PM CEST +// Tcl Message: [Tue Apr 29 15:24:30 2025] Waiting for impl_1 to finish... +// TclEventType: RUN_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: [Tue Apr 29 15:24:49 2025] impl_1 finished +// Tcl Message: wait_on_runs: Time (s): cpu = 00:02:43 ; elapsed = 00:01:55 . Memory (MB): peak = 14333.836 ; gain = 0.000 ; free physical = 11489 ; free virtual = 20678 +// Tcl Message: # open_run impl_1 +// HMemoryUtils.trashcanNow. Engine heap size: 8,571 MB. GUI used memory: 223 MB. Current time: 4/29/25, 3:24:54 PM CEST +// TclEventType: SIGNAL_INTERFACE_ADD +// TclEventType: SIGNAL_HIERARCHY_CHANGED +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_CNS_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: FLOORPLAN_MODIFY +// HMemoryUtils.trashcanNow. Engine heap size: 9,275 MB. GUI used memory: 223 MB. Current time: 4/29/25, 3:25:11 PM CEST +// TclEventType: DESIGN_NEW +// HMemoryUtils.trashcanNow. Engine heap size: 9,275 MB. GUI used memory: 223 MB. Current time: 4/29/25, 3:25:12 PM CEST +// [Engine Memory]: 9,275 MB (+509064kb) [00:28:29] +// TclEventType: DESIGN_NEW +// [GUI Memory]: 317 MB (+3631kb) [00:28:30] +// DeviceView Instantiated +// WARNING: HEventQueue.dispatchEvent() is taking 10969 ms. +// TclEventType: CURR_DESIGN_SET +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.83 ; elapsed = 00:00:00.83 . Memory (MB): peak = 14333.836 ; gain = 0.000 ; free physical = 11529 ; free virtual = 20717 +// Tcl Message: INFO: [Netlist 29-17] Analyzing 5336 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.1 INFO: [Project 1-570] Preparing netlist for logic optimization +// Tcl Message: INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Project 1-853] Binary constraint restore complete. +// Tcl Message: Reading XDEF placement. Reading placer database... Reading XDEF routing. +// Tcl Message: Read XDEF Files: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 14999.094 ; gain = 149.234 ; free physical = 10529 ; free virtual = 19792 +// Tcl Message: Restored from archive | CPU: 7.670000 secs | Memory: 124.827370 MB | +// Tcl Message: Finished XDEF File Restore: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 14999.094 ; gain = 149.234 ; free physical = 10511 ; free virtual = 19780 +// Tcl Message: Generating merged BMM file for the design top 'ariane_xilinx'... +// Tcl Message: INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/sw/calibration_0/Debug/calibration_ddr.elf +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 15041.094 ; gain = 0.000 ; free physical = 10533 ; free virtual = 19801 +// Device view-level: 0.0 +// [Engine Memory]: 9,762 MB (+24189kb) [00:28:41] +// [GUI Memory]: 333 MB (+38kb) [00:28:41] +// [Engine Memory]: 10,253 MB (+3482kb) [00:28:41] +// Tcl Message: open_run: Time (s): cpu = 00:00:45 ; elapsed = 00:00:34 . Memory (MB): peak = 15471.812 ; gain = 1137.977 ; free physical = 10267 ; free virtual = 19541 +// Tcl Message: # write_verilog -force -mode funcsim work-fpga/${project}_funcsim.v +// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED +// RouteApi::loadEngineXgdAndInitRouteStorage elapsed time: 13s +// Device view-level: 0.0 +// RouteApi::getRouteInfo length(bytes): 182638 +// Tcl Message: # write_verilog -force -mode timesim work-fpga/${project}_timesim.v +// HMemoryUtils.trashcanNow. Engine heap size: 10,388 MB. GUI used memory: 264 MB. Current time: 4/29/25, 3:25:28 PM CEST +// Tcl Message: # write_sdf -force work-fpga/${project}_timesim.sdf +// Tcl Message: write_sdf: Time (s): cpu = 00:01:20 ; elapsed = 00:00:08 . Memory (MB): peak = 16107.422 ; gain = 0.000 ; free physical = 9220 ; free virtual = 18971 +// Tcl Message: # exec mkdir -p reports/ # exec rm -rf reports/* # check_timing -file reports/${project}.check_timing.rpt +// TclEventType: TIMING_RESULTS_STALE +// Tcl Message: check_timing: Time (s): cpu = 00:00:28 ; elapsed = 00:00:07 . Memory (MB): peak = 16107.422 ; gain = 0.000 ; free physical = 9059 ; free virtual = 18794 +// Tcl Message: # report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/${project}.timing_WORST_100.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +// Tcl Message: INFO: [Timing 38-78] ReportTimingParams: -max_paths 100 -nworst 100 -delay_type max -sort_by slack. +// HMemoryUtils.trashcanNow. Engine heap size: 10,511 MB. GUI used memory: 264 MB. Current time: 4/29/25, 3:25:48 PM CEST +// Tcl Message: # report_timing -nworst 1 -delay_type max -sort_by group -file reports/${project}.timing.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by group. +// Tcl Message: # report_utilization -hierarchical -file reports/${project}.utilization.rpt +// TclEventType: STOP_PROGRESS_DIALOG +// Elapsed Time for: 'K.d': 28m:59s +// Elapsed time: 1740 seconds +dismissDialog("Sourcing Tcl script 'scripts/run.tcl'"); // bq +// TclEventType: STOP_PROGRESS_DIALOG +// RouteApi::getRouteInfo length(bytes): 182638 +// RouteApi: Init Delay Mediator Swing Worker Finished +// RouteApi::getRouteInfo length(bytes): 182638 +// RouteApi: Init Delay Mediator Swing Worker Finished +// Elapsed Time for: 'L.f': 29m:03s +// Tcl Message: update_compile_order -fileset sources_1 +// Elapsed Time for: 'L.f': 29m:05s +// [GUI Memory]: 355 MB (+6109kb) [00:29:16] +// Elapsed Time for: 'L.f': 29m:07s +// TclEventType: FILE_SET_CHANGE +// TclEventType: DG_GRAPH_STALE +// Elapsed Time for: 'L.f': 29m:09s +// Elapsed Time for: 'L.f': 29m:11s +// Elapsed time: 833 seconds +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Generate Bitstream]", 49, false); // f +// Run Command: PAResourceCommand.PACommandNames_RUN_BITGEN +selectButton("OptionPane.button", "Cancel"); // JButton +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager]", 50, true); // f - Node +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER +// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes' +// Tcl (Dont Echo) Command: 'load_features labtools' +// TclEventType: LOAD_FEATURE +// TclEventType: HW_SESSION_OPEN +// Tcl Message: open_hw_manager +closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // t +dismissDialog("Open Hardware Manager"); // bq +// HMemoryUtils.trashcanNow. Engine heap size: 10,600 MB. GUI used memory: 271 MB. Current time: 4/29/25, 3:39:53 PM CEST +selectButton(PAResourceOtoP.ProgramDebugTab_OPEN_TARGET, "Open target"); // g +selectMenu(PAResourceOtoP.ProgramDebugTab_OPEN_RECENTLY_OPENED_TARGET, "Recent Targets"); // al +selectMenuItem(PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET, "Auto Connect"); // ao +// Run Command: PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET +// TclEventType: HW_SERVER_UPDATE +// Tcl Message: connect_hw_server -allow_non_jtag +// Tcl Message: INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 INFO: [Labtools 27-2222] Launching hw_server... INFO: [Labtools 27-2221] Launch Output: ****** Xilinx hw_server v2023.1 **** Build date : May 7 2023 at 15:13:34 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0 INFO: [Labtools 27-3417] Launching cs_server... +// TclEventType: HW_SERVER_UPDATE +// Tcl Message: INFO: [Labtools 27-2221] Launch Output: ******** Xilinx cs_server v2023.1.0 ****** Build date : Apr 10 2023-17:59:24 **** Build number : 2023.1.1681142364 ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// TclEventType: HW_TARGET_CHANGE +// TclEventType: HW_TARGET_CLOSE +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_ADD +// TclEventType: HW_TARGET_UPDATE +// Tcl Message: open_hw_target +// Tcl Message: INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308B76CA2 +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROGRAM.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.bit} [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: set_property FULL_PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: current_hw_device [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_CHANGE +// TclEventType: HW_MIG_ADD +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// Tcl Message: refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0] +// Tcl Message: INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s). +dismissDialog("Auto Connect"); // bq +selectButton(PAResourceAtoD.CmdMsgDialog_OK, "OK"); // f +dismissDialog("Critical Messages"); // a +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Add Configuration Memory Device]", 50, false); // f +// Run Command: PAResourceCommand.PACommandNames_ADD_CONFIG_MEMORY +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 49, false); // f +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectMenuItem((HResource) null, "xcvu9p_0"); // ao +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER +// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes' +// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA +selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program"); // a +// TclEventType: HW_DEVICE_CHANGE +dismissDialog("Program Device"); // aP +// Tcl Message: set_property PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: set_property FULL_PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROGRAM.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.bit} [get_hw_devices xcvu9p_0] +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_MIG_DELETE +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_TARGET_NEEDS_CLOSE +// Tcl Message: program_hw_devices [get_hw_devices xcvu9p_0] +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH +// Tcl Message: program_hw_devices: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 16246.340 ; gain = 0.000 ; free physical = 8864 ; free virtual = 18747 +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_CHANGE +// TclEventType: HW_MIG_ADD +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_DEVICE_CHANGE +// Elapsed time: 16 seconds +closeView(PAResourceOtoP.PAViews_MIG, "MIG - MIG_1"); // b +// TclEventType: HW_DEVICE_PROBES_CHANGE +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// Tcl Message: refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0] +// Tcl Message: INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s). +// 'D' command handler elapsed time: 20 seconds +dismissDialog("Program Device"); // bq +// TclEventType: HW_SERVER_UPDATE +// Elapsed time: 114 seconds +selectCodeEditor(RDIResource.TclConsoleView_TCL_CONSOLE_CODE_EDITOR, 342, 32); // cD +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_TARGET_CLOSE +// Elapsed time: 27 seconds +closeView(PAResourceOtoP.PAViews_MIG, "MIG - MIG_1"); // b +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_MIG_DELETE +// TclEventType: HW_SYSMON_DELETE +// TclEventType: HW_TARGET_UPDATE +// TclEventType: DEBUG_PROBE_DELETE +// Tcl Message: ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210308B76CA2 +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_SERVER_UPDATE +selectButton(PAResourceAtoD.CmdMsgDialog_OK, "OK"); // f +dismissDialog("Close Hardware Target"); // j.a +selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // j +closeTask("Program and Debug", "Hardware Manager", "DesignTask.PROGRAM_DEBUG"); +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_SERVER_CLOSE +// TclEventType: HW_SESSION_CLOSE +// RouteApi::getRouteInfo length(bytes): 182636 +// HMemoryUtils.trashcanNow. Engine heap size: 10,665 MB. GUI used memory: 273 MB. Current time: 4/29/25, 3:42:53 PM CEST +// Tcl Message: close_hw_manager +// Device view-level: 0.0 +// [Engine Memory]: 11,844 MB (+1130385kb) [00:46:11] +// RouteApi::getRouteInfo length(bytes): 182638 +dismissDialog("Close Hardware Manager"); // bq +// Device view-level: 0.0 +// RouteApi::getRouteInfo length(bytes): 182638 +// Elapsed time: 69 seconds +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Project Summary", 0); // o +// Elapsed time: 11 seconds +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager]", 50, true); // f - Node +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER +// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes' +// TclEventType: HW_SESSION_OPEN +// Tcl Message: open_hw_manager +closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // t +dismissDialog("Open Hardware Manager"); // bq +selectButton(PAResourceOtoP.ProgramDebugTab_OPEN_TARGET, "Open target"); // g +selectMenuItem(PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET, "Auto Connect"); // ao +// Run Command: PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET +// Tcl Message: connect_hw_server -allow_non_jtag +// Tcl Message: INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 INFO: [Labtools 27-2222] Launching hw_server... +// TclEventType: HW_SERVER_UPDATE +// Tcl Message: INFO: [Labtools 27-2221] Launch Output: ****** Xilinx hw_server v2023.1 **** Build date : May 7 2023 at 15:13:34 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0 INFO: [Labtools 27-3417] Launching cs_server... +// TclEventType: HW_SERVER_UPDATE +// Tcl Message: INFO: [Labtools 27-2221] Launch Output: ******** Xilinx cs_server v2023.1.0 ****** Build date : Apr 10 2023-17:59:24 **** Build number : 2023.1.1681142364 ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// TclEventType: HW_TARGET_CHANGE +// TclEventType: HW_TARGET_CLOSE +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_ADD +// TclEventType: HW_TARGET_UPDATE +// Tcl Message: open_hw_target +// Tcl Message: INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308B76CA2 +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROGRAM.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.bit} [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: set_property FULL_PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: current_hw_device [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_CHANGE +// TclEventType: HW_MIG_ADD +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_DEVICE_CHANGE +closeView(PAResourceOtoP.PAViews_MIG, "MIG - MIG_1"); // b +// TclEventType: HW_DEVICE_PROBES_CHANGE +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// Tcl Message: refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0] +// Tcl Message: INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s). +dismissDialog("Auto Connect"); // bq +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "MIG_1 ; CAL FAIL", 4, "CAL FAIL", 1, false); // m +// Elapsed time: 13 seconds +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "MIG_1 ; CAL FAIL", 4, "MIG_1", 0, false); // m +// Elapsed time: 26 seconds +selectTable(PAResourceItoN.MigStatusPanel_STATUS_TABLE, "1 - DQS Gate ; FAIL", 0, "FAIL", 1); // h +// Elapsed time: 174 seconds +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "SysMon ; ", 3, "SysMon", 0, false); // m +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "MIG_1 ; CAL FAIL", 4, "MIG_1", 0, false); // m +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "MIG_1 ; CAL FAIL", 4, "MIG_1", 0, false, false, false, false, true, false); // m - Popup Trigger +selectMenuItem(RDIResourceCommand.RDICommands_PROPERTIES, "MIG Core Properties..."); // ao +// Run Command: RDIResourceCommand.RDICommands_PROPERTIES +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "MIG_1 ; CAL FAIL", 4, "MIG_1", 0, false, false, false, false, true, false); // m - Popup Trigger +// Elapsed time: 11 seconds +selectMenuItem(RDIResourceCommand.RDICommands_PROPERTIES, "MIG Core Properties..."); // ao +// Run Command: RDIResourceCommand.RDICommands_PROPERTIES +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "MIG_1 ; CAL FAIL", 4, "MIG_1", 0, false); // m +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "MIG_1 ; CAL FAIL", 4, "MIG_1", 0, false, false, false, false, true, false); // m - Popup Trigger +// HMemoryUtils.trashcanNow. Engine heap size: 11,910 MB. GUI used memory: 276 MB. Current time: 4/29/25, 3:48:38 PM CEST +selectButton(PAResourceEtoH.HardwareMigPropPanels_OPEN_MIG_DASHBOARD, "Open MIG Dashboard"); // g +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_DASHBOARD +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_SERVER_UPDATE +// TclEventType: HW_TARGET_NEEDS_CLOSE +// TclEventType: HW_TARGET_CLOSE +// Elapsed time: 378 seconds +closeView(PAResourceOtoP.PAViews_MIG, "MIG - MIG_1"); // b +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_MIG_DELETE +// TclEventType: HW_SYSMON_DELETE +// TclEventType: HW_TARGET_UPDATE +// TclEventType: DEBUG_PROBE_DELETE +// TclEventType: HW_SERVER_UPDATE +// Tcl Message: ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210308B76CA2 +// TclEventType: HW_SERVER_UPDATE +// Elapsed time: 16 seconds +selectButton(PAResourceAtoD.CmdMsgDialog_OK, "OK"); // f +dismissDialog("Close Hardware Target"); // j.a +selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // j +closeTask("Program and Debug", "Hardware Manager", "DesignTask.PROGRAM_DEBUG"); +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_SERVER_CLOSE +// TclEventType: HW_SESSION_CLOSE +// Tcl Message: close_hw_manager +dismissDialog("Close Hardware Manager"); // bq +// Elapsed time: 444 seconds +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design]", 36, true); // f - Node +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Open Target]", 40, false); // f +// Run Command: PAResourceCommand.PACommandNames_OPEN_HW_TARGET +selectMenu(PAResourceOtoP.ProgramDebugTab_OPEN_RECENTLY_OPENED_TARGET, "Recent Targets"); // al +selectMenuItem(PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET, "Auto Connect"); // ao +// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER +// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes' +// TclEventType: HW_SESSION_OPEN +// Tcl Message: open_hw_manager +closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // t +// Run Command: PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET +dismissDialog("Open Hardware Manager"); // bq +// TclEventType: HW_SERVER_UPDATE +// Tcl Message: connect_hw_server -allow_non_jtag +// Tcl Message: INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 INFO: [Labtools 27-2222] Launching hw_server... INFO: [Labtools 27-2221] Launch Output: ****** Xilinx hw_server v2023.1 **** Build date : May 7 2023 at 15:13:34 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0 INFO: [Labtools 27-3417] Launching cs_server... +// TclEventType: HW_SERVER_UPDATE +// Tcl Message: INFO: [Labtools 27-2221] Launch Output: ******** Xilinx cs_server v2023.1.0 ****** Build date : Apr 10 2023-17:59:24 **** Build number : 2023.1.1681142364 ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// TclEventType: HW_TARGET_CHANGE +// TclEventType: HW_TARGET_CLOSE +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_ADD +// TclEventType: HW_TARGET_UPDATE +// Tcl Message: open_hw_target +// Tcl Message: INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308B76CA2 +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROGRAM.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.bit} [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// Tcl Message: set_property PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: set_property FULL_PROBES.FILE {/home/stagiaire/Documents/cva6_main/cva6_vcu118_save3/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.ltx} [get_hw_devices xcvu9p_0] +// Tcl Message: current_hw_device [get_hw_devices xcvu9p_0] +// TclEventType: HW_DEVICE_CHANGE +// TclEventType: HW_SYSMON_CHANGE +// TclEventType: HW_MIG_ADD +// TclEventType: HW_DEVICE_UPDATE +// TclEventType: HW_DEVICE_CHANGE +closeView(PAResourceOtoP.PAViews_MIG, "MIG - MIG_1"); // b +// TclEventType: HW_DEVICE_PROBES_CHANGE +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: HW_DEVICE_PROBES_CHANGE +// Tcl Message: refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0] +// Tcl Message: INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s). +dismissDialog("Auto Connect"); // bq +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "MIG_1 ; CAL FAIL", 4, "CAL FAIL", 1, false); // m +// Elapsed time: 38 seconds +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "xilinx_tcf/Digilent/210308B76CA2 (1) ; Open", 1, "xilinx_tcf/Digilent/210308B76CA2 (1)", 0, true); // m - Node +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "xcvu9p_0 (2) ; Programmed", 2, "xcvu9p_0 (2)", 0, true); // m - Node +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "xilinx_tcf/Digilent/210249B868A9 (0) ; Closed", 5, "xilinx_tcf/Digilent/210249B868A9 (0)", 0, false); // m +expandTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "xilinx_tcf/Digilent/210249B868A9 (0) ; Closed", 5); // m +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "xilinx_tcf/Digilent/210249B868A9 (0) ; Closed", 5, "xilinx_tcf/Digilent/210249B868A9 (0)", 0, false, false, false, false, false, true); // m - Double Click +selectTreeTable(PAResourceEtoH.HardwareTreePanel_HARDWARE_TREE_TABLE, "SysMon ; ", 3, "SysMon", 0, false); // m +selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // j +closeTask("Program and Debug", "Hardware Manager", "DesignTask.PROGRAM_DEBUG"); +// TclEventType: HW_OBJECT_DELETE +// TclEventType: HW_SERVER_CLOSE +// TclEventType: HW_MIG_DELETE +closeView(PAResourceOtoP.PAViews_MIG, "MIG - MIG_1"); // b +// TclEventType: HW_SYSMON_DELETE +// TclEventType: HW_TARGET_CLOSE +// TclEventType: HW_TARGET_UPDATE +// TclEventType: DEBUG_PROBE_DELETE +// TclEventType: HW_SESSION_CLOSE +// Tcl Message: close_hw_manager +dismissDialog("Close Hardware Manager"); // bq +expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, ariane_xilinx (ariane_xilinx.sv)]", 3); // E +collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, ariane_xilinx (ariane_xilinx.sv)]", 3); // E +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, ariane_xilinx (ariane_xilinx.sv)]", 3, true); // E - Node +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, ariane_xilinx (ariane_xilinx.sv)]", 3, true, false, false, false, false, true); // E - Double Click - Node +selectCodeEditor("ariane_xilinx.sv", 164, 155); // ad +selectCodeEditor("ariane_xilinx.sv", 183, 164); // ad +selectCodeEditor("ariane_xilinx.sv", 183, 164, false, false, false, false, true); // ad - Double Click +// HMemoryUtils.trashcanNow. Engine heap size: 10,904 MB. GUI used memory: 263 MB. Current time: 4/29/25, 4:18:38 PM CEST diff --git a/corev_apu/fpga/vivado_pid2437936.str b/corev_apu/fpga/vivado_pid2437936.str new file mode 100644 index 0000000000..52e2312bb5 --- /dev/null +++ b/corev_apu/fpga/vivado_pid2437936.str @@ -0,0 +1,1968 @@ +/* + +AMD Vivado v2023.1 (64-bit) [Major: 2023, Minor: 1] +SW Build: 3865809 on Sun May 7 15:04:56 MDT 2023 +IP Build: 3864474 on Sun May 7 20:36:21 MDT 2023 +IP Build: 3864474 on Sun May 7 20:36:21 MDT 2023 + +Process ID (PID): 2437936 +License: Customer +Mode: GUI Mode + +Current time: Tue Apr 22 11:31:32 CEST 2025 +Time zone: Central European Standard Time (Europe/Paris) + +OS: Ubuntu +OS Version: 6.11.0-21-generic +OS Architecture: amd64 +Available processors (cores): 22 + +Display: 1 +Screen size: 1920x1080 +Screen resolution (DPI): 100 +Available screens: 3 +Default font: family=Dialog,name=Dialog,style=plain,size=12 +Scale size: 12 +OS font scaling: 100% + +Java version: 17.0.3 64-bit +JavaFX version: 17.0.1 +Java home: /tools/Xilinx/Vivado/2023.1/tps/lnx64/jre17.0.3_7 +Java executable: /tools/Xilinx/Vivado/2023.1/tps/lnx64/jre17.0.3_7/bin/java +Java arguments: [-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Djdk.gtk.version=2, -Dsun.java2d.uiScale.enabled=false, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, -XX:+UseStringDeduplication, -XX:MaxGCPauseMillis=200, -XX:+ParallelRefProcEnabled, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/java.awt.event=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-exports=java.base/java.nio=ALL-UNNAMED, --add-exports=java.desktop/sun.swing=ALL-UNNAMED, --add-exports=java.desktop/javax.swing=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-exports=java.desktop/sun.swing=ALL-UNNAMED, --add-exports=java.desktop/sun.swing.table=ALL-UNNAMED, --add-exports=java.desktop/sun.swing.plaf.synth=ALL-UNNAMED, --add-exports=java.desktop/sun.awt.shell=ALL-UNNAMED, --add-exports=java.base/sun.security.action=ALL-UNNAMED, --add-exports=java.desktop/sun.font=ALL-UNNAMED, --add-opens=java.desktop/sun.awt.X11=ALL-UNNAMED, -XX:NewSize=80m, -XX:MaxNewSize=80m, -Xms512m, -Xmx4072m, -Xss10m, -Xrs] +Java initial memory (-Xms): 512 MB +Java maximum memory (-Xmx): 3 GB + +User name: stagiaire +User home directory: /home/stagiaire +User working directory: /home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga +User country: US +User language: en +User locale: en_US + +RDI_BASEROOT: /tools/Xilinx/Vivado +HDI_APPROOT: /tools/Xilinx/Vivado/2023.1 +RDI_DATADIR: /tools/Xilinx/SharedData/2023.1/data:/tools/Xilinx/Vivado/2023.1/data +RDI_BINDIR: /tools/Xilinx/Vivado/2023.1/bin + +Vivado preferences file: /home/stagiaire/.Xilinx/Vivado/2023.1/vivado.xml +Vivado preferences directory: /home/stagiaire/.Xilinx/Vivado/2023.1/ +Vivado layouts directory: /home/stagiaire/.Xilinx/Vivado/2023.1/data/layouts +PlanAhead jar file: /tools/Xilinx/Vivado/2023.1/lib/classes/planAhead.jar +Vivado log file: /home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/vivado.log +Vivado journal file: +Engine tmp dir: ./.Xil/Vivado-2437936-qdtis2423h +Non-Default Parameters: [] + +Xilinx & AMD Environment Variables +-------------------------------------------------------------------------------------------- +GNOME_SHELL_SESSION_MODE: ubuntu +RDI_APPROOT: /tools/Xilinx/Vivado/2023.1 +RDI_BASEROOT: /tools/Xilinx/Vivado +RDI_BINROOT: /tools/Xilinx/Vivado/2023.1/bin +RDI_BUILD: yes +RDI_DATADIR: /tools/Xilinx/SharedData/2023.1/data:/tools/Xilinx/Vivado/2023.1/data +RDI_INSTALLROOT: /tools/Xilinx +RDI_INSTALLVER: 2023.1 +RDI_JAVA_PLATFORM: +RDI_JAVA_VERSION: 17.0.3_7 +RDI_LIBDIR: /tools/Xilinx/Vivado/2023.1/lib/lnx64.o/Ubuntu:/tools/Xilinx/Vivado/2023.1/lib/lnx64.o +RDI_OPT_EXT: .o +RDI_PATCHROOT: +RDI_PLATFORM: lnx64 +RDI_PREPEND_PATH: /tools/Xilinx/Vitis/2023.1/bin:/tools/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/lin64 +RDI_PROG: /tools/Xilinx/Vivado/2023.1/bin/unwrapped/lnx64.o/vivado +RDI_SESSION_INFO: /home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga:qdtis2423h_1745314282_2437868 +RDI_SHARED_DATA: /tools/Xilinx/SharedData/2023.1/data +RDI_TPS_ROOT: /tools/Xilinx/Vivado/2023.1/tps/lnx64 +RDI_USE_JDK17: True +SHELL: /bin/bash +XILINX: /tools/Xilinx/Vivado/2023.1/ids_lite/ISE +XILINX_BOARD: xilinx.com:vcu118:part0:2.0 +XILINX_DSP: /tools/Xilinx/Vivado/2023.1/ids_lite/ISE +XILINX_HLS: /tools/Xilinx/Vitis_HLS/2023.1 +XILINX_PART: xcvu9p-flga2104-2L-e +XILINX_PLANAHEAD: /tools/Xilinx/Vivado/2023.1 +XILINX_SDK: /tools/Xilinx/Vitis/2023.1 +XILINX_VITIS: /tools/Xilinx/Vitis/2023.1 +XILINX_VIVADO: /tools/Xilinx/Vivado/2023.1 +XILINX_VIVADO_HLS: /tools/Xilinx/Vivado/2023.1 + + +GUI allocated memory: 512 MB +GUI max memory: 4,072 MB +Engine allocated memory: 2,465 MB + +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + +*/ + +// TclEventType: START_GUI +// TclEventType: START_PROGRESS_DIALOG +// Tcl Message: start_gui +// TclEventType: START_PROGRESS_DIALOG +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: FLOW_ADDED +// Tcl Message: source scripts/prologue.tcl +// Tcl Message: # set project ariane # create_project $project . -force -part $::env(XILINX_PART) +// TclEventType: FILE_SET_NEW +// TclEventType: RUN_ADD +// TclEventType: RUN_CURRENT +// TclEventType: PROJECT_DASHBOARD_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_NEW +// [GUI Memory]: 99 MB (+100847kb) [00:00:08] +// [Engine Memory]: 2,540 MB (+2512140kb) [00:00:08] +// [GUI Memory]: 124 MB (+21019kb) [00:00:08] +// TclEventType: FILE_SET_OPTIONS_CHANGE +// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2023.1/data/ip'. +// HMemoryUtils.trashcanNow. Engine heap size: 2,734 MB. GUI used memory: 75 MB. Current time: 4/22/25, 11:31:34 AM CEST +// TclEventType: FILE_SET_OPTIONS_CHANGE +// [Engine Memory]: 2,736 MB (+72018kb) [00:00:09] +// TclEventType: FILE_SET_OPTIONS_CHANGE +// TclEventType: BOARD_MODIFIED +// TclEventType: MSGMGR_REFRESH_MSG +// TclEventType: STOP_PROGRESS_DIALOG +// Tcl Message: create_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 8761.379 ; gain = 545.016 ; free physical = 16969 ; free virtual = 28787 +// Tcl Message: # set_property board_part $::env(XILINX_BOARD) [current_project] # set_param general.maxThreads 8 # set_msg_config -id {[Synth 8-5858]} -new_severity "info" # set_msg_config -id {[Synth 8-4480]} -limit 1000 +dismissDialog("Sourcing Tcl script 'scripts/prologue.tcl'"); // bq +// TclEventType: STOP_PROGRESS_DIALOG +// TclEventType: START_PROGRESS_DIALOG +// TclEventType: FILE_SET_CHANGE +// Tcl Message: source scripts/run.tcl +// TclEventType: FILE_SET_CHANGE +// [GUI Memory]: 135 MB (+6005kb) [00:00:11] +// TclEventType: FILE_SET_CHANGE +// TclEventType: FILE_SET_OPTIONS_CHANGE +// TclEventType: FILE_SET_CHANGE +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// Tcl Message: # add_files -fileset constrs_1 -norecurse constraints/$project.xdc # synth_design -rtl -name rtl_1 +// Tcl Message: Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xcvu9p-flga2104-2L-e Top: ariane_xilinx +// [Engine Memory]: 3,701 MB (+868985kb) [00:00:20] +// TclEventType: ELABORATE_START +// HMemoryUtils.trashcanNow. Engine heap size: 4,486 MB. GUI used memory: 78 MB. Current time: 4/22/25, 11:31:53 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 4,862 MB. GUI used memory: 76 MB. Current time: 4/22/25, 11:32:05 AM CEST +// TclEventType: ELABORATE_FINISH +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// HMemoryUtils.trashcanNow. Engine heap size: 5,829 MB. GUI used memory: 76 MB. Current time: 4/22/25, 11:32:23 AM CEST +// TclEventType: POWER_CNS_STALE +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: SIGNAL_INTERFACE_ADD +// TclEventType: SIGNAL_HIERARCHY_CHANGED +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: FLOORPLAN_MODIFY +// TclEventType: DESIGN_NEW +// [Engine Memory]: 5,881 MB (+2091317kb) [00:01:04] +// HMemoryUtils.trashcanNow. Engine heap size: 5,881 MB. GUI used memory: 76 MB. Current time: 4/22/25, 11:32:29 AM CEST +// TclEventType: DESIGN_NEW +// [GUI Memory]: 158 MB (+16399kb) [00:01:05] +// [GUI Memory]: 170 MB (+3923kb) [00:01:05] +// [GUI Memory]: 184 MB (+6493kb) [00:01:05] +// [GUI Memory]: 216 MB (+24073kb) [00:01:05] +// Xgd.load filename: /tools/Xilinx/Vivado/2023.1/data/parts/xilinx/virtexuplus/devint/virtexuplus/xcvu9p/xcvu9p.xgd; ZipEntry: xcvu9p_detail.xgd elapsed time: 0.9s +// DeviceModel: Load Xgds SwingWorker Join Forever elapsed time: 1s +// [GUI Memory]: 247 MB (+20685kb) [00:01:06] +// [Engine Memory]: 6,673 MB (+522168kb) [00:01:06] +// WARNING: HEventQueue.dispatchEvent() is taking 1622 ms. +// TclEventType: CURR_DESIGN_SET +// Tcl Message: INFO: [Device 21-403] Loading part xcvu9p-flga2104-2L-e +// Tcl Message: INFO: [Synth 8-11241] undeclared symbol 'dout', assumed default net type 'wire' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/ariane-ethernet/dualmem_widen8.sv:88] +// Tcl Message: INFO: [Synth 8-11241] undeclared symbol 'led', assumed default net type 'wire' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/ariane_xilinx.sv:919] INFO: [Synth 8-11241] undeclared symbol 'sw', assumed default net type 'wire' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/ariane_xilinx.sv:920] INFO: [Synth 8-11241] undeclared symbol 'unused_switches', assumed default net type 'wire' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/ariane_xilinx.sv:920] +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 10104.723 ; gain = 334.641 ; free physical = 15603 ; free virtual = 27400 +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'ariane_xilinx' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/ariane_xilinx.sv:14] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 4 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/tb/axi_intf.sv:19] +// Tcl Message: Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 4 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'axi_xbar' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/axi/src/axi_xbar.sv:18] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'addr_decode' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/addr_decode.sv:30] +// Tcl Message: Parameter NoIndices bound to: 32'b00000000000000000000000000001010 Parameter NoRules bound to: 32'b00000000000000000000000000001010 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'addr_decode' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/addr_decode.sv:30] INFO: [Synth 8-6157] synthesizing module 'axi_demux' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/axi/src/axi_demux.sv:19] +// Tcl Message: Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter NoMstPorts bound to: 32'b00000000000000000000000000001011 Parameter MaxTrans bound to: 32'b00000000000000000000000000000001 Parameter AxiLookBits bound to: 32'b00000000000000000000000000000100 Parameter UniqueIds bound to: 1'b0 Parameter FallThrough bound to: 1'b0 Parameter SpillAw bound to: 1'b1 Parameter SpillW bound to: 1'b1 Parameter SpillB bound to: 1'b1 Parameter SpillAr bound to: 1'b1 Parameter SpillR bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'axi_demux_id_counters' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/axi/src/axi_demux.sv:576] +// Tcl Message: Parameter AxiIdBits bound to: 32'b00000000000000000000000000000100 Parameter CounterWidth bound to: 32'b00000000000000000000000000000001 +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-6157] synthesizing module 'delta_counter' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000000001 Parameter STICKY_OVERFLOW bound to: 1'b0 +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'fifo_v3' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized1' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized1' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized1' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized1' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000001011 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'lzc' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/lzc.sv:25] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000001011 Parameter MODE bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lzc' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized2' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized2' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized3' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized3' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000001011 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6155] done synthesizing module 'axi_demux' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/axi/src/axi_demux.sv:19] INFO: [Synth 8-6157] synthesizing module 'axi_err_slv' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/axi/src/axi_err_slv.sv:19] +// Tcl Message: Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter Resp bound to: 2'b11 Parameter ATOPs bound to: 1'b1 Parameter MaxTrans bound to: 32'b00000000000000000000000000000100 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'axi_atop_filter' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/axi/src/axi_atop_filter.sv:37] +// Tcl Message: Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter AxiMaxWriteTxns bound to: 32'b00000000000000000000000000000100 +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/axi/src/axi_atop_filter.sv:118] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/axi/src/axi_atop_filter.sv:268] INFO: [Synth 8-6157] synthesizing module 'stream_register' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/stream_register.sv:14] INFO: [Synth 8-6157] synthesizing module 'fifo_v2' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b1 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized1' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized2' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized3' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'counter' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/counter.sv:14] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000001000 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'delta_counter__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000001000 Parameter STICKY_OVERFLOW bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'delta_counter__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] INFO: [Synth 8-6155] done synthesizing module 'counter' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/counter.sv:14] INFO: [Synth 8-6155] done synthesizing module 'axi_err_slv' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/axi/src/axi_err_slv.sv:19] INFO: [Synth 8-6157] synthesizing module 'axi_mux' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/axi/src/axi_mux.sv:27] +// Tcl Message: Parameter SlvAxiIDWidth bound to: 32'b00000000000000000000000000000100 Parameter NoSlvPorts bound to: 32'b00000000000000000000000000000010 Parameter MaxWTrans bound to: 32'b00000000000000000000000000000001 Parameter FallThrough bound to: 1'b0 Parameter SpillAw bound to: 1'b1 Parameter SpillW bound to: 1'b1 Parameter SpillB bound to: 1'b1 Parameter SpillAr bound to: 1'b1 Parameter SpillR bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'axi_id_prepend' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/axi/src/axi_id_prepend.sv:18] +// Tcl Message: Parameter NoBus bound to: 1 - type: integer Parameter AxiIdWidthSlvPort bound to: 32'b00000000000000000000000000000100 Parameter AxiIdWidthMstPort bound to: 32'b00000000000000000000000000000101 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'axi_id_prepend' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/axi/src/axi_id_prepend.sv:18] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree__parameterized1' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000000010 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'lzc__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/lzc.sv:25] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000000010 Parameter MODE bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized1' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized4' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized4' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized4' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized4' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized4' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized4' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized5' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized5' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized5' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized5' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000000010 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized2' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized6' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized6' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized6' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized6' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized7' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized7' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] +// Tcl Message: Parameter Bypass bound to: 1'b0 +// Tcl Message: Parameter IrLength bound to: 32'b00000000000000000000000000000101 Parameter IdcodeValue bound to: 1 - type: integer +// Tcl Message: Parameter NrHarts bound to: 32'b00000000000000000000000000000001 Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter SelectableHarts bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'dm_csrs' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/riscv-dbg/src/dm_csrs.sv:18] +// Tcl Message: Parameter NrHarts bound to: 32'b00000000000000000000000000000001 Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter SelectableHarts bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/riscv-dbg/src/dm_csrs.sv:294] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/riscv-dbg/src/dm_csrs.sv:360] INFO: [Synth 8-6157] synthesizing module 'fifo_v2__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv:13] +// Tcl Message: Parameter DEPTH bound to: 32'b00000000000000000000000000000010 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized5' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized5' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6155] done synthesizing module 'fifo_v2__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv:13] INFO: [Synth 8-6155] done synthesizing module 'dm_csrs' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/riscv-dbg/src/dm_csrs.sv:18] INFO: [Synth 8-6157] synthesizing module 'dm_sba' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/riscv-dbg/src/dm_sba.sv:18] +// Tcl Message: Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter ReadByteEnable bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/riscv-dbg/src/dm_sba.sv:72] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/riscv-dbg/src/dm_sba.sv:101] INFO: [Synth 8-6155] done synthesizing module 'dm_sba' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/riscv-dbg/src/dm_sba.sv:18] INFO: [Synth 8-6157] synthesizing module 'dm_mem' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/riscv-dbg/src/dm_mem.sv:19] +// Tcl Message: Parameter NrHarts bound to: 32'b00000000000000000000000000000001 Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter SelectableHarts bound to: 1'b1 Parameter DmBaseAddress bound to: 32'b00000000000000000001000000000000 +// Tcl Message: Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_ADDR_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/axi_adapter.sv:486] INFO: [Synth 8-6155] done synthesizing module 'axi_adapter' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/axi_adapter.sv:19] INFO: [Synth 8-6157] synthesizing module 'ariane' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/src/ariane.sv:17] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'cva6' [/home/stagiaire/Documents/cva6_main/cva6_base/core/cva6.sv:18] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'perf_counters' [/home/stagiaire/Documents/cva6_main/cva6_base/core/perf_counters.sv:16] +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'perf_counters' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/core/perf_counters.sv:16] INFO: [Synth 8-6157] synthesizing module 'wt_cache_subsystem' [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_cache_subsystem.sv:22] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'cva6_icache' [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/cva6_icache.sv:28] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'sram_cache' [/home/stagiaire/Documents/cva6_main/cva6_base/common/local/util/sram_cache.sv:21] +// Tcl Message: Parameter DATA_WIDTH bound to: 45 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer Parameter BYTE_ACCESS bound to: 0 - type: integer Parameter TECHNO_CUT bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'sram' [/home/stagiaire/Documents/cva6_main/cva6_base/common/local/util/sram.sv:21] +// Tcl Message: Parameter DATA_WIDTH bound to: 45 - type: integer Parameter USER_WIDTH bound to: 1 - type: integer Parameter USER_EN bound to: 0 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'tc_sram_wrapper' [/home/stagiaire/Documents/cva6_main/cva6_base/common/local/util/tc_sram_fpga_wrapper.sv:10] +// Tcl Message: Parameter NumWords bound to: 256 - type: integer Parameter DataWidth bound to: 32'b00000000000000000000000001000000 Parameter ByteWidth bound to: 8 - type: integer Parameter NumPorts bound to: 1 - type: integer Parameter Latency bound to: 1 - type: integer Parameter SimInit bound to: none - type: string Parameter PrintSimCfg bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'SyncSpRamBeNx64' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv:28] +// Tcl Message: Parameter ADDR_WIDTH bound to: 8 - type: integer Parameter DATA_DEPTH bound to: 256 - type: integer Parameter OUT_REGS bound to: 0 - type: integer Parameter SIM_INIT bound to: 1 - type: integer +// Tcl Message: Parameter DATA_WIDTH bound to: 128 - type: integer Parameter USER_WIDTH bound to: 128 - type: integer Parameter USER_EN bound to: 0 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer Parameter BYTE_ACCESS bound to: 0 - type: integer Parameter TECHNO_CUT bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'sram__parameterized0' [/home/stagiaire/Documents/cva6_main/cva6_base/common/local/util/sram.sv:21] +// Tcl Message: Parameter DATA_WIDTH bound to: 128 - type: integer Parameter USER_WIDTH bound to: 128 - type: integer Parameter USER_EN bound to: 0 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'sram__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/common/local/util/sram.sv:21] INFO: [Synth 8-6155] done synthesizing module 'sram_cache__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/common/local/util/sram_cache.sv:21] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/cva6_icache.sv:220] INFO: [Synth 8-6157] synthesizing module 'lzc__parameterized1' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/lzc.sv:25] +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000000100 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized1' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Synth 8-6157] synthesizing module 'lfsr' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/lfsr.sv:22] +// Tcl Message: Parameter LfsrWidth bound to: 32'b00000000000000000000000000001000 Parameter OutWidth bound to: 32'b00000000000000000000000000000010 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lfsr' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/lfsr.sv:22] INFO: [Synth 8-6155] done synthesizing module 'cva6_icache' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/cva6_icache.sv:28] INFO: [Synth 8-6157] synthesizing module 'wt_dcache' [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_dcache.sv:16] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'wt_dcache_ctrl' [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_dcache_ctrl.sv:16] +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_dcache_ctrl.sv:134] INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_dcache_ctrl.sv:134] INFO: [Synth 8-6155] done synthesizing module 'wt_dcache_ctrl' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_dcache_ctrl.sv:16] INFO: [Synth 8-6157] synthesizing module 'wt_dcache_missunit' [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_dcache_missunit.sv:17] +// Tcl Message: INFO: [Synth 8-6157] synthesizing module 'lzc__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +// Tcl Message: Parameter WIDTH bound to: 32'b00000000000000000000000000001000 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized2' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/lzc.sv:25] +// Tcl Message: Parameter LfsrWidth bound to: 32'b00000000000000000000000000001000 Parameter OutWidth bound to: 32'b00000000000000000000000000000011 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized0' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/lfsr.sv:22] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_dcache_missunit.sv:98] +// Tcl Message: Parameter Seed bound to: 32'b00000000000000000000000000000011 Parameter MaxExp bound to: 32'b00000000000000000000000000010000 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'exp_backoff' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/exp_backoff.sv:23] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_dcache_missunit.sv:350] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_dcache_missunit.sv:451] INFO: [Synth 8-6155] done synthesizing module 'wt_dcache_missunit' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_dcache_missunit.sv:17] +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/include/wt_cache_pkg.sv:134] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_dcache_wbuffer.sv:142] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_dcache_wbuffer.sv:116] +// Tcl Message: Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000000010 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter FPGA_EN bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'cva6_fifo_v3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/core/cva6_fifo_v3.sv:16] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000000100 Parameter DataWidth bound to: 32'b00000000000000000000000000000001 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized3' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000001000 Parameter LockIn bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized4' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_axi_adapter.sv:197] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_axi_adapter.sv:206] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_axi_adapter.sv:231] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/cache_subsystem/wt_axi_adapter.sv:248] +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/frontend/frontend.sv:235] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/frontend/frontend.sv:235] +// Tcl Message: Parameter FPGA_ALTERA bound to: 1'b0 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter FPGA_EN bound to: 1'b0 Parameter FPGA_ALTERA bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FPGA_EN bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/include/ariane_pkg.sv:562] +// Tcl Message: INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/issue_read_operands.sv:382] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/stagiaire/Documents/cva6_main/cva6_base/core/issue_read_operands.sv:399] +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000001001 Parameter ExtPrio bound to: 1'b1 Parameter AxiVldRdy bound to: 1'b1 +// Tcl Message: Parameter NumIn bound to: 32'b00000000000000000000000000001101 Parameter DataWidth bound to: 32'b00000000000000000000000001000000 Parameter ExtPrio bound to: 1'b1 Parameter AxiVldRdy bound to: 1'b1 +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_base/core/fpu_wrap.sv:440] +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_base/core/cvfpu/src/fpnew_rounding.sv:48] +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_base/core/cvfpu/src/fpnew_rounding.sv:48] +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_base/core/cvfpu/src/fpnew_pkg.sv:89] +// Tcl Message: Parameter AbsWidth bound to: 32'b00000000000000000000000001000000 +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_base/core/cvfpu/src/fpnew_rounding.sv:48] INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_base/core/cvfpu/src/fpnew_pkg.sv:89] +// Tcl Message: Parameter DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FPGA_EN bound to: 1'b0 +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/clint/axi_lite_interface.sv:78] +// Tcl Message: Parameter STAGES bound to: 32'b00000000000000000000000000000010 Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer +// Tcl Message: INFO: [Synth 8-155] case statement is not full and has no default [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/axi_mem_if/src/axi2mem.sv:192] INFO: [Synth 8-155] case statement is not full and has no default [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/axi_mem_if/src/axi2mem.sv:234] INFO: [Synth 8-155] case statement is not full and has no default [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/axi_mem_if/src/axi2mem.sv:122] +// Tcl Message: Parameter AxiAddrWidth bound to: 64 - type: integer Parameter AxiDataWidth bound to: 64 - type: integer Parameter AxiIdWidth bound to: 5 - type: integer Parameter AxiUserWidth bound to: 64 - type: integer Parameter InclUART bound to: 1'b1 Parameter InclSPI bound to: 1'b1 Parameter InclEthernet bound to: 1'b0 Parameter InclGPIO bound to: 1'b1 +// Tcl Message: Parameter SIZE bound to: 2 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:28' bound to instance 'UART_IF_CTS' of component 'slib_input_filter' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:402] INFO: [Synth 8-638] synthesizing module 'slib_input_filter' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:41] +// Tcl Message: Parameter SIZE bound to: 2 - type: integer +// Tcl Message: INFO: [Synth 8-256] done synthesizing module 'slib_input_filter' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:41] +// Tcl Message: Parameter SIZE bound to: 2 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:28' bound to instance 'UART_IF_DSR' of component 'slib_input_filter' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:403] +// Tcl Message: Parameter SIZE bound to: 2 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:28' bound to instance 'UART_IF_DCD' of component 'slib_input_filter' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:404] +// Tcl Message: Parameter SIZE bound to: 2 - type: integer +// Tcl Message: Parameter RATIO bound to: 8 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_clock_div' declared at '/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_clock_div.vhd:29' bound to instance 'UART_BG2' of component 'slib_clock_div' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:752] INFO: [Synth 8-638] synthesizing module 'slib_clock_div' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_clock_div.vhd:41] +// Tcl Message: Parameter RATIO bound to: 8 - type: integer +// Tcl Message: INFO: [Synth 8-256] done synthesizing module 'slib_clock_div' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_clock_div.vhd:41] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_edge_detect.vhd:28' bound to instance 'UART_RCLK' of component 'slib_edge_detect' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:758] +// Tcl Message: Parameter WIDTH bound to: 8 - type: integer Parameter SIZE_E bound to: 6 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_fifo' declared at '/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_fifo.vhd:29' bound to instance 'UART_TXFF' of component 'slib_fifo' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:765] INFO: [Synth 8-638] synthesizing module 'slib_fifo' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_fifo.vhd:48] +// Tcl Message: Parameter WIDTH bound to: 8 - type: integer Parameter SIZE_E bound to: 6 - type: integer +// Tcl Message: INFO: [Synth 8-256] done synthesizing module 'slib_fifo' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_fifo.vhd:48] +// Tcl Message: Parameter WIDTH bound to: 11 - type: integer Parameter SIZE_E bound to: 6 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_fifo' declared at '/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_fifo.vhd:29' bound to instance 'UART_RXFF' of component 'slib_fifo' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/apb_uart.vhd:784] INFO: [Synth 8-638] synthesizing module 'slib_fifo__parameterized1' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_fifo.vhd:48] +// Tcl Message: Parameter WIDTH bound to: 11 - type: integer Parameter SIZE_E bound to: 6 - type: integer +// Tcl Message: Parameter WIDTH bound to: 4 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_counter' declared at '/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_counter.vhd:29' bound to instance 'RX_BRC' of component 'slib_counter' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/uart_receiver.vhd:122] INFO: [Synth 8-638] synthesizing module 'slib_counter' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_counter.vhd:46] +// Tcl Message: Parameter WIDTH bound to: 4 - type: integer +// Tcl Message: INFO: [Synth 8-256] done synthesizing module 'slib_counter' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_counter.vhd:46] +// Tcl Message: Parameter WIDTH bound to: 4 - type: integer Parameter THRESHOLD bound to: 10 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_mv_filter' declared at '/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_mv_filter.vhd:29' bound to instance 'RX_MVF' of component 'slib_mv_filter' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/uart_receiver.vhd:137] INFO: [Synth 8-638] synthesizing module 'slib_mv_filter' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_mv_filter.vhd:44] +// Tcl Message: Parameter WIDTH bound to: 4 - type: integer Parameter THRESHOLD bound to: 10 - type: integer +// Tcl Message: INFO: [Synth 8-256] done synthesizing module 'slib_mv_filter' (0#1) [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_mv_filter.vhd:44] +// Tcl Message: Parameter SIZE bound to: 4 - type: integer +// Tcl Message: INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:28' bound to instance 'RX_IFSB' of component 'slib_input_filter' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/uart_receiver.vhd:150] INFO: [Synth 8-638] synthesizing module 'slib_input_filter__parameterized2' [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_uart/src/vhdl_orig/slib_input_filter.vhd:41] +// Tcl Message: Parameter SIZE bound to: 4 - type: integer +// Tcl Message: INFO: [Synth 8-155] case statement is not full and has no default [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_timer/timer.sv:92] INFO: [Synth 8-155] case statement is not full and has no default [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/src/apb_timer/timer.sv:116] +// Tcl Message: Parameter ADDR_WIDTH bound to: 32'sb00000000000000000000000000100000 Parameter DATA_WIDTH bound to: 32'sb00000000000000000000000000100000 Parameter N_SOURCE bound to: 32'sb00000000000000000000000000011110 Parameter N_TARGET bound to: 32'sb00000000000000000000000000000010 Parameter MAX_PRIO bound to: 32'sb00000000000000000000000000000111 Parameter N_SOURCE bound to: 32'sb00000000000000000000000000011110 Parameter MAX_PRIO bound to: 32'sb00000000000000000000000000000111 Parameter ALGORITHM bound to: SEQUENTIAL - type: string Parameter N_SOURCE bound to: 32'sb00000000000000000000000000011110 +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv:580] INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv:809] +// Tcl Message: Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 +// Tcl Message: INFO: [Synth 8-226] default block is never used [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv:39] +// Tcl Message: INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +// Tcl Message: INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 10880.973 ; gain = 1110.891 ; free physical = 14707 ; free virtual = 26498 +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- +// Tcl Message: Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 10880.973 ; gain = 1110.891 ; free physical = 14711 ; free virtual = 26502 +// Tcl Message: --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- +// Tcl Message: Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 10880.973 ; gain = 1110.891 ; free physical = 14711 ; free virtual = 26502 +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 10914.355 ; gain = 0.000 ; free physical = 14765 ; free virtual = 26557 +// Tcl Message: INFO: [Netlist 29-17] Analyzing 1083 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.1 INFO: [Project 1-570] Preparing netlist for logic optimization +// Tcl Message: INFO: [Opt 31-140] Inserted 2 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 3 OBUFs to IO ports without IO buffers. +// Tcl Message: Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/bd_0/ip/ip_0/bd_f0c7_microblaze_I_0.xdc] for cell 'i_ddr/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0' Finished Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/bd_0/ip/ip_0/bd_f0c7_microblaze_I_0.xdc] for cell 'i_ddr/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0' +// Tcl Message: INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/bd_0/ip/ip_0/bd_f0c7_microblaze_I_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +// Tcl Message: Finished Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/par/xlnx_mig_ddr4.xdc] for cell 'i_ddr/inst' +// Tcl Message: INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/par/xlnx_mig_ddr4.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +// Tcl Message: INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.gen/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +// Tcl Message: INFO: [Timing 38-2] Deriving generated clocks +// Tcl Message: Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/constraints/vcu118.xdc] +// Tcl Message: Finished Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/constraints/vcu118.xdc] +// Tcl Message: INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/constraints/vcu118.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +// Tcl Message: Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/constraints/ariane.xdc] +// Tcl Message: Finished Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/constraints/ariane.xdc] +// Tcl Message: INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/constraints/ariane.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'rtl_1' [/tools/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] +// Tcl Message: Completed Processing XDC Constraints +// Tcl Message: INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 11899.945 ; gain = 0.000 ; free physical = 13982 ; free virtual = 25776 +// TclEventType: RUN_MODIFY +// TclEventType: RUN_OPTIONS_MODIFIED +// TclEventType: RUN_LAUNCH +// TclEventType: RUN_MODIFY +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: RTL Elaboration Complete: : Time (s): cpu = 00:01:07 ; elapsed = 00:00:45 . Memory (MB): peak = 12059.805 ; gain = 2289.723 ; free physical = 13490 ; free virtual = 25309 +// Tcl Message: 428 Infos, 375 Warnings, 1 Critical Warnings and 0 Errors encountered. synth_design completed successfully +// Tcl Message: synth_design: Time (s): cpu = 00:01:13 ; elapsed = 00:00:52 . Memory (MB): peak = 12059.805 ; gain = 3250.402 ; free physical = 13490 ; free virtual = 25309 +// Tcl Message: INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] +// Tcl Message: # set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] # launch_runs synth_1 +// Tcl Message: [Tue Apr 22 11:32:32 2025] Launched synth_1... Run output will be captured here: /home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/ariane.runs/synth_1/runme.log +// Tcl Message: # wait_on_run synth_1 +// Tcl Message: [Tue Apr 22 11:32:32 2025] Waiting for synth_1 to finish... +// TclEventType: RUN_STATUS_CHANGE +// HMemoryUtils.trashcanNow. Engine heap size: 6,727 MB. GUI used memory: 181 MB. Current time: 4/22/25, 11:32:35 AM CEST +// Tcl Message: [Tue Apr 22 11:32:37 2025] Waiting for synth_1 to finish... +// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED +// RouteApi::loadEngineXgdAndInitRouteStorage elapsed time: 8s +// Tcl Message: [Tue Apr 22 11:32:42 2025] Waiting for synth_1 to finish... +// Tcl Message: [Tue Apr 22 11:32:47 2025] Waiting for synth_1 to finish... +// Tcl Message: [Tue Apr 22 11:32:57 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,533 MB. GUI used memory: 187 MB. Current time: 4/22/25, 11:33:05 AM CEST +// Tcl Message: [Tue Apr 22 11:33:07 2025] Waiting for synth_1 to finish... +// Tcl Message: [Tue Apr 22 11:33:17 2025] Waiting for synth_1 to finish... +// Tcl Message: [Tue Apr 22 11:33:27 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,527 MB. GUI used memory: 187 MB. Current time: 4/22/25, 11:33:35 AM CEST +// Tcl Message: [Tue Apr 22 11:33:47 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,527 MB. GUI used memory: 187 MB. Current time: 4/22/25, 11:34:05 AM CEST +// Tcl Message: [Tue Apr 22 11:34:07 2025] Waiting for synth_1 to finish... +// Tcl Message: [Tue Apr 22 11:34:27 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,527 MB. GUI used memory: 187 MB. Current time: 4/22/25, 11:34:35 AM CEST +// Tcl Message: [Tue Apr 22 11:34:47 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,527 MB. GUI used memory: 187 MB. Current time: 4/22/25, 11:35:05 AM CEST +// Tcl Message: [Tue Apr 22 11:35:27 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,528 MB. GUI used memory: 187 MB. Current time: 4/22/25, 11:35:35 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 6,528 MB. GUI used memory: 188 MB. Current time: 4/22/25, 11:36:05 AM CEST +// Tcl Message: [Tue Apr 22 11:36:07 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,528 MB. GUI used memory: 188 MB. Current time: 4/22/25, 11:36:35 AM CEST +// Tcl Message: [Tue Apr 22 11:36:47 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,528 MB. GUI used memory: 189 MB. Current time: 4/22/25, 11:37:05 AM CEST +// Tcl Message: [Tue Apr 22 11:37:27 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,529 MB. GUI used memory: 188 MB. Current time: 4/22/25, 11:37:35 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 6,529 MB. GUI used memory: 188 MB. Current time: 4/22/25, 11:38:05 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 6,529 MB. GUI used memory: 188 MB. Current time: 4/22/25, 11:38:35 AM CEST +// Tcl Message: [Tue Apr 22 11:38:47 2025] Waiting for synth_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 6,529 MB. GUI used memory: 188 MB. Current time: 4/22/25, 11:39:05 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 6,529 MB. GUI used memory: 188 MB. Current time: 4/22/25, 11:39:35 AM CEST +// TclEventType: RUN_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// WARNING: HEventQueue.dispatchEvent() is taking 11423 ms. +// TclEventType: RUN_STEP_COMPLETED +// WARNING: HSwingWorker (Update Runs Swing Worker) is taking 9643 ms. Increasing delay to 3000 ms. +// [GUI Memory]: 276 MB (+17654kb) [00:08:23] +// Tcl Message: [Tue Apr 22 11:39:47 2025] synth_1 finished +// Tcl Message: wait_on_runs: Time (s): cpu = 00:07:17 ; elapsed = 00:07:15 . Memory (MB): peak = 12540.070 ; gain = 480.266 ; free physical = 20385 ; free virtual = 24730 +// Tcl Message: # open_run synth_1 +// [GUI Memory]: 309 MB (+19722kb) [00:08:23] +// Tcl Message: Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xcvu9p-flga2104-2L-e +// WARNING: HEventQueue.dispatchEvent() is taking 1495 ms. +// WARNING: HTimer (ActiveMsgMonitor Process Messages Timer) is taking 10407ms to process. Increasing delay to 2000 ms. +// WARNING: HEventQueue.dispatchEvent() is taking 10408 ms. +// HMemoryUtils.trashcanNow. Engine heap size: 6,514 MB. GUI used memory: 199 MB. Current time: 4/22/25, 11:40:35 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 6,514 MB. GUI used memory: 198 MB. Current time: 4/22/25, 11:41:05 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 6,514 MB. GUI used memory: 198 MB. Current time: 4/22/25, 11:41:35 AM CEST +// TclEventType: DEBUG_PORT_ADD +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_CNS_STALE +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: SIGNAL_INTERFACE_ADD +// TclEventType: SIGNAL_HIERARCHY_CHANGED +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// HMemoryUtils.trashcanNow. Engine heap size: 6,958 MB. GUI used memory: 198 MB. Current time: 4/22/25, 11:42:13 AM CEST +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_REMOVE +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: TIMING_RESULTS_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: READ_XDC_FILE_START +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: READ_XDC_FILE_END +// TclEventType: FLOORPLAN_MODIFY +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: DESIGN_NEW +// HMemoryUtils.trashcanNow. Engine heap size: 6,983 MB. GUI used memory: 198 MB. Current time: 4/22/25, 11:42:20 AM CEST +// [Engine Memory]: 7,073 MB (+69079kb) [00:10:56] +// TclEventType: DESIGN_NEW +// DeviceView Instantiated +// WARNING: HEventQueue.dispatchEvent() is taking 1012 ms. +// TclEventType: CURR_DESIGN_SET +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.82 . Memory (MB): peak = 12540.070 ; gain = 0.000 ; free physical = 19644 ; free virtual = 24473 +// Tcl Message: INFO: [Netlist 29-17] Analyzing 5370 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.1 INFO: [Project 1-570] Preparing netlist for logic optimization +// Tcl Message: INFO: [Chipscope 16-324] Core: i_ddr UUID: 95d64970-6efe-555a-a048-dc3a209f704a +// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.gen/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.gen/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc:57] +// Tcl Message: Finished Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/constraints/vcu118.xdc] Parsing XDC File [/home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/constraints/ariane.xdc] +// Tcl Message: INFO: [Project 1-1714] 53 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +// Tcl Message: Generating merged BMM file for the design top 'ariane_xilinx'... +// Tcl Message: INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/sw/calibration_0/Debug/calibration_ddr.elf +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 12922.414 ; gain = 0.000 ; free physical = 18534 ; free virtual = 23767 +// Tcl Message: open_run: Time (s): cpu = 00:00:46 ; elapsed = 00:02:35 . Memory (MB): peak = 13002.746 ; gain = 462.676 ; free physical = 18323 ; free virtual = 23600 +// Tcl Message: # exec mkdir -p reports/ # exec rm -rf reports/* # check_timing -verbose -file reports/$project.check_timing.rpt +// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. +// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED +// RouteApi::loadEngineXgdAndInitRouteStorage elapsed time: 11.2s +// HMemoryUtils.trashcanNow. Engine heap size: 7,604 MB. GUI used memory: 209 MB. Current time: 4/22/25, 11:42:35 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,551 MB. GUI used memory: 209 MB. Current time: 4/22/25, 11:43:05 AM CEST +// [Engine Memory]: 8,551 MB (+1179634kb) [00:11:42] +// TclEventType: TIMING_RESULTS_STALE +// Tcl Message: check_timing: Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 14453.789 ; gain = 1451.043 ; free physical = 16595 ; free virtual = 22221 +// Tcl Message: # report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 100 -nworst 100 -delay_type max -sort_by slack. +// Tcl Message: # report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by group. +// Tcl Message: # report_utilization -hierarchical -file reports/$project.utilization.rpt +// Tcl Message: # report_cdc -file reports/$project.cdc.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: No interconnect No Cell Dly, Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +// Tcl Message: INFO: [Timing 38-433] Consider using Xilinx recommended XPM_CDC modules to avoid Critical severities INFO: [Timing 38-314] The report_cdc command only analyzes and reports clock domain crossing paths where clocks have been defined on both source and destination sides. Ports with no input delay constraint are skipped. Please run check_timing to verify there are no missing clock definitions in your design, nor any unconstrained input port. +// Tcl Message: # report_clock_interaction -file reports/$project.clock_interaction.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +// TclEventType: TIMING_RESULTS_STALE +// TclEventType: RUN_MODIFY +// TclEventType: RUN_OPTIONS_MODIFIED +// TclEventType: RUN_MODIFY +// TclEventType: RUN_OPTIONS_MODIFIED +// Tcl Message: # set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1] # set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1] # launch_runs impl_1 +// Tcl Message: INFO: [Timing 38-480] Writing timing data to binary archive. +// Tcl Message: Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. +// Tcl Message: Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.34 . Memory (MB): peak = 14512.812 ; gain = 50.020 ; free physical = 16545 ; free virtual = 22218 +// HMemoryUtils.trashcanNow. Engine heap size: 8,621 MB. GUI used memory: 209 MB. Current time: 4/22/25, 11:43:23 AM CEST +// TclEventType: RUN_LAUNCH +// TclEventType: RUN_MODIFY +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: [Tue Apr 22 11:43:28 2025] Launched impl_1... Run output will be captured here: /home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/ariane.runs/impl_1/runme.log +// Tcl Message: launch_runs: Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 14522.812 ; gain = 68.023 ; free physical = 16539 ; free virtual = 22213 +// Tcl Message: # wait_on_run impl_1 +// Tcl Message: [Tue Apr 22 11:43:29 2025] Waiting for impl_1 to finish... +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: [Tue Apr 22 11:43:34 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 22 11:43:39 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 22 11:43:44 2025] Waiting for impl_1 to finish... +// Device view-level: 0.0 +// Tcl Message: [Tue Apr 22 11:43:54 2025] Waiting for impl_1 to finish... +// TclEventType: RUN_STEP_COMPLETED +// Tcl Message: [Tue Apr 22 11:44:04 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 22 11:44:14 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 22 11:44:24 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 22 11:44:44 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 22 11:45:04 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,743 MB. GUI used memory: 214 MB. Current time: 4/22/25, 11:45:08 AM CEST +// Tcl Message: [Tue Apr 22 11:45:24 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 22 11:45:44 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 22 11:46:24 2025] Waiting for impl_1 to finish... +// TclEventType: RUN_STEP_COMPLETED +// Tcl Message: [Tue Apr 22 11:47:04 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,702 MB. GUI used memory: 214 MB. Current time: 4/22/25, 11:47:35 AM CEST +// Tcl Message: [Tue Apr 22 11:47:44 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 214 MB. Current time: 4/22/25, 11:48:05 AM CEST +// Tcl Message: [Tue Apr 22 11:48:24 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 214 MB. Current time: 4/22/25, 11:48:35 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 214 MB. Current time: 4/22/25, 11:49:05 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 236 MB. Current time: 4/22/25, 11:49:35 AM CEST +// Tcl Message: [Tue Apr 22 11:49:44 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 214 MB. Current time: 4/22/25, 11:50:05 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 214 MB. Current time: 4/22/25, 11:50:35 AM CEST +// Tcl Message: [Tue Apr 22 11:51:04 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 214 MB. Current time: 4/22/25, 11:51:05 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 214 MB. Current time: 4/22/25, 11:51:35 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 214 MB. Current time: 4/22/25, 11:52:05 AM CEST +// TclEventType: RUN_STEP_COMPLETED +// Tcl Message: [Tue Apr 22 11:52:24 2025] Waiting for impl_1 to finish... +// TclEventType: RUN_STEP_COMPLETED +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 216 MB. Current time: 4/22/25, 11:52:35 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 215 MB. Current time: 4/22/25, 11:53:05 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 236 MB. Current time: 4/22/25, 11:53:35 AM CEST +// Tcl Message: [Tue Apr 22 11:53:44 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 215 MB. Current time: 4/22/25, 11:54:05 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 216 MB. Current time: 4/22/25, 11:54:35 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 215 MB. Current time: 4/22/25, 11:55:05 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 236 MB. Current time: 4/22/25, 11:55:35 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 215 MB. Current time: 4/22/25, 11:56:05 AM CEST +// Tcl Message: [Tue Apr 22 11:56:24 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 215 MB. Current time: 4/22/25, 11:56:35 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 215 MB. Current time: 4/22/25, 11:57:05 AM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 8,688 MB. GUI used memory: 215 MB. Current time: 4/22/25, 11:57:35 AM CEST +// TclEventType: RUN_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_STEP_COMPLETED +// TclEventType: RUN_LAUNCH +// TclEventType: RUN_MODIFY +// Tcl Message: [Tue Apr 22 11:57:54 2025] impl_1 finished +// Tcl Message: wait_on_runs: Time (s): cpu = 00:00:30 ; elapsed = 00:14:26 . Memory (MB): peak = 14522.812 ; gain = 0.000 ; free physical = 12955 ; free virtual = 20384 +// Tcl Message: # launch_runs impl_1 -to_step write_bitstream +// Tcl Message: [Tue Apr 22 11:57:55 2025] Launched impl_1... Run output will be captured here: /home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/ariane.runs/impl_1/runme.log +// Tcl Message: # wait_on_run impl_1 +// Tcl Message: [Tue Apr 22 11:57:55 2025] Waiting for impl_1 to finish... +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: [Tue Apr 22 11:58:00 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,681 MB. GUI used memory: 216 MB. Current time: 4/22/25, 11:58:05 AM CEST +// Tcl Message: [Tue Apr 22 11:58:05 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 22 11:58:10 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 22 11:58:20 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 22 11:58:30 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,681 MB. GUI used memory: 216 MB. Current time: 4/22/25, 11:58:35 AM CEST +// Tcl Message: [Tue Apr 22 11:58:40 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 22 11:58:50 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,681 MB. GUI used memory: 276 MB. Current time: 4/22/25, 11:59:05 AM CEST +// Tcl Message: [Tue Apr 22 11:59:10 2025] Waiting for impl_1 to finish... +// Tcl Message: [Tue Apr 22 11:59:30 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,681 MB. GUI used memory: 216 MB. Current time: 4/22/25, 11:59:35 AM CEST +// Tcl Message: [Tue Apr 22 11:59:50 2025] Waiting for impl_1 to finish... +// HMemoryUtils.trashcanNow. Engine heap size: 8,681 MB. GUI used memory: 216 MB. Current time: 4/22/25, 12:00:05 PM CEST +// TclEventType: RUN_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: [Tue Apr 22 12:00:09 2025] impl_1 finished +// Tcl Message: wait_on_runs: Time (s): cpu = 00:00:07 ; elapsed = 00:02:15 . Memory (MB): peak = 14522.812 ; gain = 0.000 ; free physical = 12584 ; free virtual = 20045 +// Tcl Message: # open_run impl_1 +// TclEventType: SIGNAL_INTERFACE_ADD +// TclEventType: SIGNAL_HIERARCHY_CHANGED +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_CNS_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: PLACEDB_MODIFY_PRE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// HMemoryUtils.trashcanNow. Engine heap size: 9,142 MB. GUI used memory: 217 MB. Current time: 4/22/25, 12:00:23 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 9,208 MB. GUI used memory: 217 MB. Current time: 4/22/25, 12:00:35 PM CEST +// [Engine Memory]: 9,208 MB (+239862kb) [00:29:16] +// HMemoryUtils.trashcanNow. Engine heap size: 9,208 MB. GUI used memory: 217 MB. Current time: 4/22/25, 12:01:05 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 9,208 MB. GUI used memory: 217 MB. Current time: 4/22/25, 12:01:35 PM CEST +// TclEventType: FLOORPLAN_MODIFY +// TclEventType: DESIGN_NEW +// HMemoryUtils.trashcanNow. Engine heap size: 9,229 MB. GUI used memory: 217 MB. Current time: 4/22/25, 12:01:55 PM CEST +// TclEventType: DESIGN_NEW +// DeviceView Instantiated +// WARNING: HEventQueue.dispatchEvent() is taking 1065 ms. +// TclEventType: CURR_DESIGN_SET +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.76 . Memory (MB): peak = 14522.812 ; gain = 0.000 ; free physical = 12891 ; free virtual = 20354 +// Tcl Message: INFO: [Netlist 29-17] Analyzing 5336 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.1 INFO: [Project 1-570] Preparing netlist for logic optimization +// Tcl Message: INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Project 1-853] Binary constraint restore complete. +// Tcl Message: Reading XDEF placement. Reading placer database... Reading XDEF routing. +// Tcl Message: Read XDEF Files: Time (s): cpu = 00:00:09 ; elapsed = 00:01:11 . Memory (MB): peak = 15016.020 ; gain = 162.938 ; free physical = 12315 ; free virtual = 19880 +// Tcl Message: Restored from archive | CPU: 9.860000 secs | Memory: 153.328239 MB | +// Tcl Message: Finished XDEF File Restore: Time (s): cpu = 00:00:09 ; elapsed = 00:01:32 . Memory (MB): peak = 15016.020 ; gain = 162.938 ; free physical = 12319 ; free virtual = 19886 +// Tcl Message: Generating merged BMM file for the design top 'ariane_xilinx'... +// Tcl Message: INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/stagiaire/Documents/cva6_main/cva6_base/corev_apu/fpga/xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.gen/sources_1/ip/xlnx_mig_ddr4/sw/calibration_0/Debug/calibration_ddr.elf +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 15028.020 ; gain = 0.000 ; free physical = 12304 ; free virtual = 19871 +// Device view-level: 0.0 +// [GUI Memory]: 325 MB (+970kb) [00:30:32] +// [GUI Memory]: 342 MB (+743kb) [00:30:32] +// Tcl Message: open_run: Time (s): cpu = 00:00:29 ; elapsed = 00:01:47 . Memory (MB): peak = 15395.402 ; gain = 882.590 ; free physical = 11945 ; free virtual = 19513 +// Tcl Message: # write_verilog -force -mode funcsim work-fpga/${project}_funcsim.v +// Tcl Message: # write_verilog -force -mode timesim work-fpga/${project}_timesim.v +// Tcl Message: # write_sdf -force work-fpga/${project}_timesim.sdf +// HMemoryUtils.trashcanNow. Engine heap size: 9,822 MB. GUI used memory: 257 MB. Current time: 4/22/25, 12:02:05 PM CEST +// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED +// RouteApi::loadEngineXgdAndInitRouteStorage elapsed time: 15s +// Device view-level: 0.0 +// [Engine Memory]: 10,277 MB (+638939kb) [00:30:46] +// RouteApi::getRouteInfo length(bytes): 196078 +// Elapsed time: 1836 seconds +dismissDialog("Device"); // u +// Tcl Message: write_sdf: Time (s): cpu = 00:01:48 ; elapsed = 00:00:09 . Memory (MB): peak = 16239.113 ; gain = 762.320 ; free physical = 10696 ; free virtual = 18745 +// Tcl Message: # exec mkdir -p reports/ # exec rm -rf reports/* # check_timing -file reports/${project}.check_timing.rpt +// TclEventType: TIMING_RESULTS_STALE +// Tcl Message: check_timing: Time (s): cpu = 00:00:26 ; elapsed = 00:00:06 . Memory (MB): peak = 16239.113 ; gain = 0.000 ; free physical = 10694 ; free virtual = 18738 +// Tcl Message: # report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/${project}.timing_WORST_100.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +// Tcl Message: INFO: [Timing 38-78] ReportTimingParams: -max_paths 100 -nworst 100 -delay_type max -sort_by slack. +// Tcl Message: # report_timing -nworst 1 -delay_type max -sort_by group -file reports/${project}.timing.rpt +// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Temperature grade: E, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by group. +// Tcl Message: # report_utilization -hierarchical -file reports/${project}.utilization.rpt +// TclEventType: STOP_PROGRESS_DIALOG +// Elapsed Time for: 'K.d': 30m:50s +// Elapsed time: 14 seconds +dismissDialog("Sourcing Tcl script 'scripts/run.tcl'"); // bq +// TclEventType: STOP_PROGRESS_DIALOG +// RouteApi::getRouteInfo length(bytes): 196078 +// RouteApi: Init Delay Mediator Swing Worker Finished +// RouteApi::getRouteInfo length(bytes): 196078 +// RouteApi: Init Delay Mediator Swing Worker Finished +// Elapsed Time for: 'L.f': 30m:54s +// Tcl Message: update_compile_order -fileset sources_1 +// Elapsed Time for: 'L.f': 30m:56s +// Elapsed Time for: 'L.f': 30m:58s +// TclEventType: FILE_SET_CHANGE +// TclEventType: DG_GRAPH_STALE +// Elapsed Time for: 'L.f': 31m:00s +// Elapsed Time for: 'L.f': 31m:02s +// HMemoryUtils.trashcanNow. Engine heap size: 10,341 MB. GUI used memory: 262 MB. Current time: 4/22/25, 12:02:38 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 10,342 MB. GUI used memory: 262 MB. Current time: 4/22/25, 12:32:38 PM CEST +// HMemoryUtils.trashcanNow. Engine heap size: 10,342 MB. GUI used memory: 244 MB. Current time: 4/22/25, 1:02:38 PM CEST +// RouteApi::getRouteInfo length(bytes): 196079 +// HMemoryUtils.trashcanNow. Engine heap size: 10,348 MB. GUI used memory: 241 MB. Current time: 4/22/25, 1:08:04 PM CEST +// Device view-level: 0.0 +// RouteApi::getRouteInfo length(bytes): 196078 +// Device view-level: 0.1 +// RouteApi::getRouteInfo length(bytes): 196078 +// Elapsed time: 3941 seconds +selectTab((HResource) null, (HResource) null, "Messages", 1); // aa +// Device view-level: 0.3 +// RouteApi::getRouteInfo length(bytes): 196081 +// RouteApi::getRouteInfo length(bytes): 196081 +// Device view-level: 0.5 +// RouteApi::getRouteInfo length(bytes): 196082 +// HMemoryUtils.trashcanNow. Engine heap size: 10,343 MB. GUI used memory: 255 MB. Current time: 4/22/25, 1:08:22 PM CEST +// Device view-level: 0.7 +// RouteApi::getRouteInfo length(bytes): 196082 +// Device view-level: 1.2 +// RouteApi::getRouteInfo length(bytes): 196140 +// Device view-level: 1.4 +// RouteApi::getRouteInfo length(bytes): 196140 +// Device view-level: 1.6 +// RouteApi::getRouteInfo length(bytes): 196140 +// Device view-level: 1.8 +// RouteApi::getRouteInfo length(bytes): 196140 +// HMemoryUtils.trashcanNow. Engine heap size: 10,485 MB. GUI used memory: 257 MB. Current time: 4/22/25, 1:08:23 PM CEST +// Device view-level: 2.1 +// RouteApi::getRouteInfo length(bytes): 196140 +// RouteApi::getRouteInfo length(bytes): 196140 +// Device view-level: 2.3 +// RouteApi::getRouteInfo length(bytes): 196140 +// Device view-level: 2.1 +// RouteApi::getRouteInfo length(bytes): 196140 +// Device view-level: 1.6 +// RouteApi::getRouteInfo length(bytes): 196140 +// Device view-level: 1.4 +// RouteApi::getRouteInfo length(bytes): 196140 +// HMemoryUtils.trashcanNow. Engine heap size: 10,502 MB. GUI used memory: 257 MB. Current time: 4/22/25, 1:08:23 PM CEST +// Device view-level: 0.7 +// RouteApi::getRouteInfo length(bytes): 196082 +// Device view-level: 0.5 +// RouteApi::getRouteInfo length(bytes): 196081 +// Device view-level: 0.1 +// RouteApi::getRouteInfo length(bytes): 196078 +// Elapsed time: 30 seconds +selectMenu(PAResourceItoN.MainMenuMgr_FILE, "File"); // ag +selectMenu(PAResourceItoN.MainMenuMgr_PROJECT, "Project"); // al +selectMenu(PAResourceItoN.MainMenuMgr_CHECKPOINT, "Checkpoint"); // al +selectMenu(PAResourceItoN.MainMenuMgr_CONSTRAINTS, "Constraints"); // al +selectMenu(PAResourceItoN.MainMenuMgr_IP, "IP"); // al +selectMenu(PAResourceItoN.MainMenuMgr_TEXT_EDITOR, "Text Editor"); // al +selectMenu(PAResourceItoN.MainMenuMgr_IMPORT, "Import"); // al +selectMenu(PAResourceItoN.MainMenuMgr_EXPORT, "Export"); // al +selectMenu(PAResourceItoN.MainMenuMgr_IMPORT, "Import"); // al +selectMenu(PAResourceItoN.MainMenuMgr_TEXT_EDITOR, "Text Editor"); // al +selectMenu(PAResourceItoN.MainMenuMgr_IMPORT, "Import"); // al +selectMenu(PAResourceItoN.MainMenuMgr_EXPORT, "Export"); // al +selectMenuItem(PAResourceCommand.PACommandNames_EXPORT_BITSTREAM_FILES, "Export Bitstream File..."); // ao +dismissMenu(PAResourceItoN.MainMenuMgr_FILE, "File"); // ag +// Run Command: PAResourceCommand.PACommandNames_EXPORT_BITSTREAM_FILES +// Elapsed time: 147 seconds +dismissFileChooser(); +// 'a' command handler elapsed time: 147 seconds diff --git a/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml b/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml index 2b3c0c1e51..985b385513 100644 --- a/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml +++ b/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml @@ -69,6 +69,22 @@ xlnx_mig_7_ddr3: mig_dont_touch_param: Custom board_mig_param: Custom +xlnx_mig_ddr4: + ip: xlnx_mig_ddr4 + vendor: xilinx.com + config: + ADDN_UI_CLKOUT1_FREQ_HZ:200 + C0_DDR4_BOARD_INTERFACE: ddr4_sdram_c1 + System_Clock: Differential + +xlnx_axi_dwidth_converter512_64: + ip: axi_dwidth_converter + vendor: xilinx.com + config: + si_data_width: 64 + si_id_width: 5 + mi_data_width: 512 + xlnx_ila: ip: xlnx_ila vendor: xilinx.com @@ -89,4 +105,4 @@ xlnx_ila: max_continuous_wtransfers_waits: 1024 max_wlast_to_awvalid_waits: 1024 max_write_to_bvalid_waits: 1024 - max_continuous_rtransfers_waits: 1024 \ No newline at end of file + max_continuous_rtransfers_waits: 1024 diff --git a/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_512_64/Makefile b/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_512_64/Makefile new file mode 100644 index 0000000000..e8287162db --- /dev/null +++ b/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_512_64/Makefile @@ -0,0 +1,2 @@ +PROJECT:=xlnx_axi_dwidth_converter_512_64 +include ../common.mk diff --git a/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_512_64/tcl/run.tcl b/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_512_64/tcl/run.tcl new file mode 100644 index 0000000000..99b9681c9e --- /dev/null +++ b/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_512_64/tcl/run.tcl @@ -0,0 +1,17 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName xlnx_axi_dwidth_converter_512_64 + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -module_name $ipName + +set_property -dict [list CONFIG.SI_DATA_WIDTH {64} CONFIG.SI_ID_WIDTH {5} CONFIG.MI_DATA_WIDTH {512}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/corev_apu/fpga/xilinx/xlnx_mig_ddr4/Makefile b/corev_apu/fpga/xilinx/xlnx_mig_ddr4/Makefile new file mode 100644 index 0000000000..93f152c194 --- /dev/null +++ b/corev_apu/fpga/xilinx/xlnx_mig_ddr4/Makefile @@ -0,0 +1,2 @@ +PROJECT:=xlnx_mig_ddr4 +include ../common.mk diff --git a/corev_apu/fpga/xilinx/xlnx_mig_ddr4/tcl/run.tcl b/corev_apu/fpga/xilinx/xlnx_mig_ddr4/tcl/run.tcl new file mode 100644 index 0000000000..26d44f1dbe --- /dev/null +++ b/corev_apu/fpga/xilinx/xlnx_mig_ddr4/tcl/run.tcl @@ -0,0 +1,21 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName xlnx_mig_ddr4 + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name ddr4 -vendor xilinx.com -library ip -version 2.2 -module_name $ipName + set_property -dict [ list \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {250} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c1} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.System_Clock {Differential} \ + ] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 From d5306a7092a2a6e2d340199478a0c2ad614d2ec5 Mon Sep 17 00:00:00 2001 From: M4s Date: Tue, 29 Apr 2025 16:38:10 +0200 Subject: [PATCH 2/2] update gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 940a2865b0..548e2a2483 100644 --- a/.gitignore +++ b/.gitignore @@ -57,3 +57,4 @@ Bender.lock #modif par moi .venv /corev_apu/fpga/ariane.* +/corev_apu/fpga/vivado_pid* \ No newline at end of file