Merge pull request #412 from os-fpga/design200

updated rtl of design200

Author: NadeemYaseen

RTL_testcases/verilog_random_designs/design200_30_25_top/raptor_run.sh

@@ -200,7 +200,7 @@ parse_cga exit 1; }
     [ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl  
 
     if [ "$post_synth_sim" == true ] || [ "$post_route_sim" == true ] || [ "$bitstream_sim" == true ]; then
-        echo "setup_lec_sim">>raptor_tcl.tcl 
+        echo "setup_lec_sim 10 2">>raptor_tcl.tcl 
     else
         echo ""
     fi

RTL_testcases/verilog_random_designs/design200_30_25_top/rtl/d_latch_top.v

@@ -7,7 +7,7 @@ module d_latch_top #(parameter WIDTH=32) (clk,rst,data_in,data_out);
     reg enable;
     wire [WIDTH-1:0] d_out;
 
-    always @ (posedge clk) begin
+    always @ (posedge clk or posedge rst) begin
         if (rst)
             enable <= 0;
         else

RTL_testcases/verilog_random_designs/design200_30_25_top/rtl/decoder_top.v

@@ -9,7 +9,7 @@ module decoder_top #(parameter WIDTH=32) (clk,rst,data_in,data_out);
     reg enable;
     wire [WIDTH-1:0] d_out;
 
-    always @ (posedge clk) begin
+    always @ (posedge clk or posedge rst) begin
         if (rst)
             enable <= 0;
         else
@@ -31,7 +31,7 @@ module decoder #(parameter WIDTH=32)(
     );
     reg [WIDTH-1:0 ] data_out_w;
 
-    always @ (posedge clk) begin
+    always @ (posedge clk or posedge rst) begin
         if (rst)
             data_out <= 0;
         else
@@ -43,14 +43,14 @@ module decoder #(parameter WIDTH=32)(
 
     always @ (data_in) begin
         case(data_in[2:0])
-            3'b000: data_out_w = 32'b11111111111111111111111111111110;
-            3'b001: data_out_w = 32'b11111111111111111111111111111101;
-            3'b010: data_out_w = 32'b11111111111111111111111111111011;
-            3'b011: data_out_w = 32'b11111111111111111111111111110111;
-            3'b100: data_out_w = 32'b11111111111111111111111111101111;
-            3'b101: data_out_w = 32'b11111111111111111111111111011111;
-            3'b110: data_out_w = 32'b11111111111111111111111110111111;
-            3'b111: data_out_w = 32'b11111111111111111111111101111111;
+            3'b000: data_out_w = 32'b10111111111110111111111111111110;
+            3'b001: data_out_w = 32'b11011111111110111111111111111101;
+            3'b010: data_out_w = 32'b11101111111110111111111111111011;
+            3'b011: data_out_w = 32'b11110111111110111111111111110111;
+            3'b100: data_out_w = 32'b11111011111110111111111111101111;
+            3'b101: data_out_w = 32'b11111101111110111111111111011111;
+            3'b110: data_out_w = 32'b11111110111110111111111110111111;
+            3'b111: data_out_w = 32'b11111111011110111111111101111111;
 
             default: data_out_w = 32'b11111111111111111111111111111111;
          endcase

RTL_testcases/verilog_random_designs/design200_30_25_top/rtl/encoder.v

@@ -8,7 +8,7 @@ output reg [WIDTH-1:0] data_out
 
 reg [WIDTH-1:0 ] data_out_wire;
 
-always@(posedge clk)
+always@(posedge clk or posedge rst)
 begin 
 if(rst)
 data_out<=0;
@@ -35,7 +35,7 @@ else
 if (data_in==32'd7000)
 data_out_wire=~32'd4000;
 else
-data_out_wire=0;
+data_out_wire=32'h6789ABCD;
 end
 
 

RTL_testcases/verilog_random_designs/design200_30_25_top/rtl/full_adder_top.v

@@ -9,8 +9,8 @@ module full_adder_top #(parameter WIDTH=32) (clk,rst,data_in,data_out);
     wire cout;
 
 
-    always @ (posedge clk) begin
-        if (!rst)
+    always @ (posedge clk or posedge rst) begin
+        if (rst)
             cin <= 0;
         else
             cin <= 1;
@@ -35,7 +35,7 @@ module full_adder #(parameter WIDTH=32)(
     reg [15:0] a,b;
     reg c;
 
-    always @(posedge clk) begin
+    always @(posedge clk or posedge rst) begin
         if (rst) begin
             a<=0;
             b<=0;

RTL_testcases/verilog_random_designs/design200_30_25_top/rtl/invertion.v

@@ -21,9 +21,9 @@ module invertion
     assign bitwise_xor = data_in[31:24] ^ data_in[23:16];
 
     // Conditional operation on the upper 16 bits
-    assign conditional_invert = (data_in[31:16] == data_in[15:0]) ? ~data_in[15:0] : data_in[31:16];
+    assign conditional_invert = (data_in[31:16] == data_in[15:0]) ? data_in[15:0] : ~data_in[31:16];
 
-    always @(posedge clk) begin
+    always @(posedge clk or posedge rst) begin
         if (rst) begin
             data_out <= 0;  // Reset the entire output vector
         end else begin

RTL_testcases/verilog_random_designs/design200_30_25_top/rtl/large_adder.v

@@ -10,7 +10,7 @@ reg [WIDTH-1:0] add_out_reg_0;
 reg [WIDTH-1:0] add_out_reg_1;
 reg [WIDTH-1:0] add_out_reg_2;
 
-always@(posedge clk)
+always@(posedge clk or posedge rst)
 begin
 if(rst)
 begin
@@ -25,7 +25,7 @@ add_out_reg_1<=(data_in[WIDTH-1:WIDTH-16] - data_in[WIDTH-16-1:0]);
 add_out_reg_2<=(data_in[WIDTH-1:WIDTH-16] + data_in[WIDTH-16-1:0]);
 end
 end
-assign data_out = add_out_reg_0 * add_out_reg_1 + add_out_reg_2;
+assign data_out = add_out_reg_0 + add_out_reg_1 * add_out_reg_2;
 
 endmodule
 

RTL_testcases/verilog_random_designs/design200_30_25_top/rtl/memory_cntrl.v

@@ -27,17 +27,16 @@ always@(posedge clk)
          rd_addr<=0;
          wr_en<=0;
          rd_en<=0;
+         wr_data_mem<=0;
       end
       else 
       case(state) //synopsys full_case
          s0: 
             begin
-               wr_data_mem<=0;
-               reset_mem<=0;  
                if (wr_addr==10'b1111111111) begin
                   state<=s1;
-                  wr_addr<=0;
                   wr_en<=0;
+                  reset_mem<=0;  
                end
                else
                 begin 
@@ -50,10 +49,7 @@ always@(posedge clk)
          s1:
             begin
                rd_en<=1;
-               if(rd_addr == wr_addr)
-                  rd_addr<=wr_addr+1;
-               else 
-                  rd_addr<=rd_addr+1;
+               rd_addr<=rd_addr+1;
                state<=s1;
             end
          default: state<=s0;
@@ -95,14 +91,12 @@ output reg [DATA-1:0] rd_data_out);
 reg [DATA-1:0] mem [(2**ADDR)-1:0];
 
 always@(posedge clk) begin
-   if(!rst) begin
-      if(wr_en) begin
-         mem[wr_addr] <= wr_data_in;
+   if(wr_en) begin
+      mem[wr_addr] <= wr_data_in;
       end
    end
-end
 
-always@(posedge clk) begin
+always@(posedge clk or posedge rst) begin
    if(rst) begin 
       rd_data_out<=0; end
    else begin

RTL_testcases/verilog_random_designs/design200_30_25_top/rtl/mod_n_counter.v

@@ -5,7 +5,7 @@ module mod_n_counter #(parameter N=256, parameter WIDTH = 32)(
     output reg [WIDTH-1:0] data_out
     );
 
-    always @ (posedge clk) begin
+    always @ (posedge clk or posedge rst) begin
         if (rst)
             data_out <= 0;
         else begin

RTL_testcases/verilog_random_designs/design200_30_25_top/rtl/paritygenerator_top.v

@@ -9,7 +9,7 @@ module paritygenerator_top #(parameter WIDTH=32) (clk,rst,data_in,data_out);
     wire parity;
 
 
-    always @ (posedge clk) begin
+    always @ (posedge clk or posedge rst) begin
         if (rst)
             data_out <= 0;
         else
@@ -33,7 +33,7 @@ module paritygenerator #(parameter WIDTH=32)(
 
     reg [WIDTH-1:0] data_out_reg;
 
-    always @ (posedge clk) begin
+    always @ (posedge clk or posedge rst) begin
         if (rst)
             data_out <= 0;
         else