Merge pull request #440 from os-fpga/task/EDA-3187/add_setup_lec_sim

added setup_lec_sim for dmx512_tx

Author: NadeemYaseen

RTL_testcases/RTL_Benchmarks_Gap_Analysis/dmx512/raptor_run.sh

@@ -184,11 +184,11 @@ parse_cga exit 1; }
     [ -z "$ip_name" ] && echo "add_include_path ./rtl">>raptor_tcl.tcl || echo "" 
     # [ -z "$ip_name" ] && echo "add_library_path ./rtl">>raptor_tcl.tcl || echo "" 
     # [ -z "$ip_name" ] && echo "add_library_ext .v .sv">>raptor_tcl.tcl || echo "" 
-    [ -z "$ip_name" ] && echo "add_design_file ./rtl/dmx512_tx/dmx_dpram.v">>raptor_tcl.tcl
-    [ -z "$ip_name" ] && echo "add_design_file ./rtl/dmx512_tx/dmx_tx.v">>raptor_tcl.tcl
+    [ -z "$ip_name" ] && echo "add_design_file ./rtl/dmx512_rx/dmx_dpram.v">>raptor_tcl.tcl
+    [ -z "$ip_name" ] && echo "add_design_file ./rtl/dmx512_rx/dmx_rx.v">>raptor_tcl.tcl
     ##vary design to design
 
-    echo "set_top_module dmx_tx">>raptor_tcl.tcl 
+    echo "set_top_module dmx_rx">>raptor_tcl.tcl 
 
     ##vary design to design
     [ -z "$add_constraint_file" ] && echo "" || echo "add_constraint_file $add_constraint_file">>raptor_tcl.tcl 

RTL_testcases/RTL_Benchmarks_Gap_Analysis/dmx512/rtl/dmx512_rx/config.tcl

@@ -24,7 +24,7 @@ module dmx_dpram #(
 	input [depth-1:0] a,
 	input we,
 	input [width-1:0] di,
-	output reg [width-1:0] do,
+	output reg [width-1:0] dout,
 
 	input [depth-1:0] a2,
 	input we2,
@@ -37,7 +37,7 @@ reg [width-1:0] ram[0:(1 << depth)-1];
 always @(posedge clk) begin
 	if(we)
 		ram[a] <= di;
-	do <= ram[a];
+	dout <= ram[a];
 	if(we2)
 		ram[a2] <= di2;
 	do2 <= ram[a2];

RTL_testcases/RTL_Benchmarks_Gap_Analysis/dmx512/rtl/dmx512_rx/dmx_dpram.v

@@ -44,7 +44,7 @@ dmx_dpram channels(
 	.a(csr_a[8:0]),
 	.we(1'b0),
 	.di(8'hxx),
-	.do(csr_channel),
+	.dout(csr_channel),
 
 	.a2(channel_a),
 	.we2(channel_we),
@@ -113,11 +113,11 @@ end
 
 parameter break_threshold = clk_freq/11364;
 reg [12:0] break_counter;
-wire break = break_counter == 13'd0;
+wire brk = break_counter == 13'd0;
 always @(posedge sys_clk) begin
 	if(sys_rst|rx_r)
 		break_counter <= break_threshold;
-	else if(~break)
+	else if(~brk)
 		break_counter <= break_counter - 13'd1;
 end
 
@@ -168,7 +168,7 @@ always @(*) begin
 			ce_load = 1'b1;
 			channel_a_reset = 1'b1;
 			next_skip = 1'b1;
-			if(break)
+			if(brk)
 				next_state = WAIT_MAB;
 		end
 		WAIT_MAB: begin

RTL_testcases/RTL_Benchmarks_Gap_Analysis/dmx512/rtl/dmx512_rx/dmx_rx.v

@@ -258,6 +258,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl  
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/RTL_Benchmarks_Gap_Analysis/dmx512/rtl/dmx512_rx/sdc.json

@@ -24,7 +24,7 @@ module dmx_dpram #(
 	input [depth-1:0] a,
 	input we,
 	input [width-1:0] di,
-	output reg [width-1:0] do,
+	output reg [width-1:0] dout,
 
 	input [depth-1:0] a2,
 	input we2,
@@ -37,7 +37,7 @@ reg [width-1:0] ram[0:(1 << depth)-1];
 always @(posedge clk) begin
 	if(we)
 		ram[a] <= di;
-	do <= ram[a];
+	dout <= ram[a];
 	if(we2)
 		ram[a2] <= di2;
 	do2 <= ram[a2];

RTL_testcases/RTL_Benchmarks_Gap_Analysis/dmx512_tx/raptor_run.sh

@@ -45,7 +45,7 @@ dmx_dpram channels(
 	.a(csr_a[8:0]),
 	.we(csr_channels_we),
 	.di(csr_di[7:0]),
-	.do(csr_do_channels[7:0]),
+	.dout(csr_do_channels[7:0]),
 
 	.a2(channel_a),
 	.we2(1'b0),