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NadeemYaseenNadeemYaseen
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Merge pull request #400 from os-fpga/add
added mux_adder and manchesterencoderdecoder designs
2 parents 466e0ff + ab8b7eb commit 719253f

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‎RTL_testcases/io_constraint_testcases/manchesterencoderdecoder/pin_mapping.pin

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set_pin_loc rst HR_1_0_0P
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set_pin_loc rts HR_1_2_1P
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set_pin_loc txd HR_1_4_2P
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set_pin_loc clkin HR_1_6_3P
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set_pin_loc cts HR_1_8_4P
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set_pin_loc txcout HR_1_10_5P
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set_pin_loc txlen HR_1_12_6P
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set_pin_loc mdo HR_1_14_7P

‎RTL_testcases/io_constraint_testcases/manchesterencoderdecoder/raptor_run.sh

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#!/bin/bash
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set -e
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main_path=$PWD
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start=`date +%s`
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design="manchesterencoderdecoder"
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ip_name="" #design_level
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#select tool (verilator, vcs, ghdl, iverilog)
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tool_name="iverilog"
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#simulation stages
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post_synth_sim=false
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post_route_sim=false
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bitstream_sim=false
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#raptor options
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device="GEMINI_COMPACT_104x68"
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strategy="delay" #(area, delay, mixed, none)
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add_constraint_file="./pin_mapping.pin" #Sets SDC + location constraints Constraints: set_pin_loc, set_mode, all SDC Standard commands
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verific_parser="" #(on/off)
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synthesis_type="" #(Yosys/QL/RS)
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custom_synth_script="" #(Uses a custom Yosys templatized script)
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synth_options=""
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#synth_options <option list>: RS-Yosys Plugin Options. The following defaults exist:
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# : -effort high
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# : -fsm_encoding binary if optimization == area else onehot
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# : -carry auto
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# : -clke_strategy early
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# -effort <level> : Optimization effort level (high, medium, low)
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# -fsm_encoding <encoding> : FSM encoding:
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# binary : Compact encoding - using minimum of registers to cover the N states
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# onehot : One hot encoding - using N registers for N states
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# -carry <mode> : Carry logic inference mode:
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# all : Infer as much as possible
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# auto : Infer carries based on internal heuristics
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# none : Do not infer carries
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# -no_dsp : Do not use DSP blocks to implement multipliers and associated logic
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# -no_bram : Do not use Block RAM to implement memory components
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# -fast : Perform the fastest synthesis. Don't expect good QoR.
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# -no_simplify : Do not run special simplification algorithms in synthesis.
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# -clke_strategy <strategy>: Clock enable extraction strategy for FFs:
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# early : Perform early extraction
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# late : Perform late extraction
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# -cec : Dump verilog after key phases and use internal equivalence checking (ABC based)
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pin_loc_assign_method="" #pin_loc_assign_method <Method>: Method choices:
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# in_define_order(Default), port order pin assignment
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# random , random pin assignment
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# free , no automatic pin assignment
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pnr_options="" #VPR options
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pnr_netlist_lang="" #blif, edif, verilog
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set_channel_width="" #int
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architecture="" #<vpr_file.xml> ?<openfpga_file.xml>? : Uses the architecture file and optional openfpga arch file (For bitstream generation)
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set_device_size="" #XxY Device fabric size selection
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bitstream=$( [ "$bitstream_sim" = "true" ] && echo "enable_simulation" || echo "" )
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################################################################
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function end_time(){
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end=`date +%s`
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runtime=$((end-start))
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echo -e "\nTotal RunTime to run raptor_run.sh: $runtime">>results.log
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echo "Peak Memory Usage: 117360">>results.log
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echo "ExecEndTime: $end">>results.log
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raptor --version>>results.log
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}
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function parse_cga(){
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cd $main_path
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tail -n100 ./results_dir/raptor.log > ./results_dir/raptor_tail.log
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timeout 15m python3 ../../../parser.py ./results_dir/results.log ./results_dir/raptor_perf.log
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mv CGA_Result.json ./results_dir
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}
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command -v raptor >/dev/null 2>&1 && raptor_path=$(which raptor) || { echo >&2 echo "First you need to source Raptor"; end_time
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parse_cga exit; }
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lib_fix_path="${raptor_path:(-11)}"
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library=${raptor_path/$lib_fix_path//share/raptor/sim_models}
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#removing and creating raptor_testcase_files
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#rm -fR $PWD/results_dir
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[ ! -d $PWD/results_dir ] && mkdir $PWD/results_dir
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[ -d $PWD/results_dir ] && touch $PWD/results_dir/CGA_Result.json
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cd $main_path
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[ -f ../../../scripts/CGA_Result_default.json ] && cp ../../../scripts/CGA_Result_default.json ./results_dir/CGA_Result.json
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[ -d $PWD/results_dir ] && cd $PWD/results_dir
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echo "ExecStartTime: $start">results.log
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echo "Domain of the design: Unit Level Test">>results.log
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# Check if parameters were passed as command line arguments
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reg_id="23"
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timeout="90"
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synth_stage=""
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mute_flag=""
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if [[ $# -eq 6 ]]; then
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reg_id=$1
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timeout=$2
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post_synth_sim=$3
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device=$4
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synth_stage=$5
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mute_flag=$6
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else
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if [[ $1 == "load_toolconf" ]]; then
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# Load parameters from tool.conf file
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source $main_path/../../tool.conf
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elif [[ $1 == "clean" ]]; then
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cd $main_path
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PIDS=$(lsof +D "results_dir" | awk 'NR>1 {print $2}' | uniq)
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for PID in $PIDS; do
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if kill -0 $PID 2>/dev/null; then
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echo "Attempting to terminate process $PID..."
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kill $PID
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sleep 1
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if kill -0 $PID 2>/dev/null; then
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echo "Process $PID did not terminate gracefully. Forcing termination."
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kill -9 $PID 2>/dev/null || echo "Could not force terminate process $PID. It may have already exited."
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fi
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else
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echo "Process $PID already terminated."
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fi
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done
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rm -rf cksums.md5 newsum.md5 raptor_tcl.tcl results_dir/
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echo "Files cleaned"
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exit 0
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else
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echo "Using paramters defined in raptor_run.sh"
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fi
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fi
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if [ -z $1 ]; then
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echo "RegID: $reg_id">>results.log
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else
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echo "RegID: $1">>results.log
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fi
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if [ -z $2 ]; then
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echo "timeout: $timeout">>results.log
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else
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timeout=$2
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echo "timeout: $2">>results.log
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fi
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function compile () {
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[ -z "$ip_name" ] && temp=$(cd .. && pwd) || echo ""
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[ -z "$ip_name" ] && echo $temp || echo ""
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#finding the design
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[ -z "$ip_name" ] && echo "Current Design is $design" || echo ""
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[ -z "$ip_name" ] && design_path=`find $temp -type f -iname "$design.v"` || echo ""
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if [ -z "$design_path" ]
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then
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[ -z "$ip_name" ] && echo "No such design $design" || echo ""
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# exit 1
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else
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[ -z "$ip_name" ] && echo -e "$design Found!" || echo ""
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fi
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command -v raptor >/dev/null 2>&1 || { echo >&2 "Compilation requires Raptor but Raptor not installed."; end_time
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parse_cga exit 1; }
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#directory path where all the rtl design files are placed
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[ -z "$ip_name" ] && directory_path=$(dirname $design_path) || echo ""
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#creating a tcl file to run raptor flow
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cd ..
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echo "create_design $design">raptor_tcl.tcl
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echo "target_device 1VG28">>raptor_tcl.tcl
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##vary design to design
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[ -z "$ip_name" ] && echo "" || echo "configure_ip $ip_name"_v1_0" -mod_name=$design -Pdata_width=32 -Paddr_width=16 -Pid_width=32 -Pa_pip_out=0 -Pb_pip_out=0 -Pa_interleave=0 -Pb_interleave=0 -out_file ./$design.v">>raptor_tcl.tcl
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[ -z "$ip_name" ] && echo "" || echo "ipgenerate">>raptor_tcl.tcl
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[ -z "$ip_name" ] && echo "" || echo "add_include_path ./rapidsilicon/ip/$ip_name/v1_0/$design/src/">>raptor_tcl.tcl
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[ -z "$ip_name" ] && echo "" || echo "add_library_ext .v .sv">>raptor_tcl.tcl
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[ -z "$ip_name" ] && echo "" || echo "add_library_path rapidsilicon/ip/$ip_name/v1_0/$design/src/">>raptor_tcl.tcl
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[ -z "$ip_name" ] && echo "" || echo "add_design_file ./rapidsilicon/ip/$ip_name/v1_0/$design/src/$design.v">>raptor_tcl.tcl
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[ -z "$ip_name" ] && echo "add_include_path ./rtl">>raptor_tcl.tcl || echo ""
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[ -z "$ip_name" ] && echo "add_library_path ./rtl">>raptor_tcl.tcl || echo ""
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[ -z "$ip_name" ] && echo "add_library_ext .v .sv">>raptor_tcl.tcl || echo ""
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[ -z "$ip_name" ] && echo "add_design_file ./rtl/$design.v">>raptor_tcl.tcl || echo ""
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##vary design to design
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echo "set_top_module $design">>raptor_tcl.tcl
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##vary design to design
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[ -z "$add_constraint_file" ] && echo "" || echo "add_constraint_file $add_constraint_file">>raptor_tcl.tcl
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if [ "$post_synth_sim" == true ] || [ "$post_route_sim" == true ] || [ "$bitstream_sim" == true ]; then
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echo "add_simulation_file ./sim/co_sim_tb/co_sim_$design.v ./rtl/$design.v">>raptor_tcl.tcl
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echo "set_top_testbench co_sim_$design">>raptor_tcl.tcl
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else
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echo ""
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fi
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echo "analyze">>raptor_tcl.tcl
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[ -z "$verific_parser" ] && echo "" || echo "verific_parser $verific_parser">>raptor_tcl.tcl
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[ -z "$synthesis_type" ] && echo "" || echo "synthesis_type $synthesis_type">>raptor_tcl.tcl
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[ -z "$custom_synth_script" ] && echo "" || echo "custom_synth_script $custom_synth_script">>raptor_tcl.tcl
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[ -z "$synth_options" ] && echo "" || echo "synth_options $synth_options">>raptor_tcl.tcl
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[ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl
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if [ "$post_synth_sim" == true ]; then
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echo "# Open the input file in read mode">>raptor_tcl.tcl
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echo "set input_file [open \"$design/run_1/synth_1_1/synthesis/$design\_post_synth.v\" r]">>raptor_tcl.tcl
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echo "# Read the file content">>raptor_tcl.tcl
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echo "set file_content [read \$input_file]">>raptor_tcl.tcl
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echo "# Close the input file after reading">>raptor_tcl.tcl
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echo "close \$input_file">>raptor_tcl.tcl
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echo "set modified_content [string map {\"$design(\" \"${design}_post_synth(\"} \$file_content]">>raptor_tcl.tcl
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echo "# Open the file again, this time in write mode to overwrite the old content">>raptor_tcl.tcl
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echo "set output_file [open \"$design/run_1/synth_1_1/synthesis/$design\_post_synth.v\" w]">>raptor_tcl.tcl
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echo "# Write the modified content back to the file">>raptor_tcl.tcl
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echo "puts \$output_file \$modified_content">>raptor_tcl.tcl
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echo "# Close the file">>raptor_tcl.tcl
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echo "close \$output_file">>raptor_tcl.tcl
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echo "puts \"Modification completed.\"">>raptor_tcl.tcl
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[ "$tool_name" = "iverilog" ] && echo "simulation_options compilation icarus gate" >> raptor_tcl.tcl || echo "simulation_options compilation verilator gate" >> raptor_tcl.tcl
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[ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl
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else
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echo ""
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fi
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if [ "$synth_stage" == "1" ]; then
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echo ""
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else
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[ -z "$pin_loc_assign_method" ] && echo "" || echo "pin_loc_assign_method $pin_loc_assign_method">>raptor_tcl.tcl
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[ -z "$pnr_options" ] && echo "" || echo "pnr_options $pnr_options">>raptor_tcl.tcl
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[ -z "$pnr_netlist_lang" ] && echo "" || echo "pnr_netlist_lang $pnr_netlist_lang">>raptor_tcl.tcl
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[ -z "$set_channel_width" ] && echo "" || echo "set_channel_width $set_channel_width">>raptor_tcl.tcl
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[ -z "$architecture" ] && echo "" || echo "architecture $architecture">>raptor_tcl.tcl
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[ -z "$set_device_size" ] && echo "" || echo "set_device_size $set_device_size">>raptor_tcl.tcl
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echo "packing">>raptor_tcl.tcl
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echo "place">>raptor_tcl.tcl
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echo "route">>raptor_tcl.tcl
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if [ "$post_route_sim" == true ]; then
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echo "# Open the input file in read mode">>raptor_tcl.tcl
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echo "set input_file [open \"$design/run_1/synth_1_1/synthesis/post_pnr_wrapper_$design\_post_synth.v\" r]">>raptor_tcl.tcl
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echo "# Read the file content">>raptor_tcl.tcl
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echo "set file_content [read \$input_file]">>raptor_tcl.tcl
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echo "# Close the input file after reading">>raptor_tcl.tcl
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echo "close \$input_file">>raptor_tcl.tcl
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echo "set modified_content [string map {\"module $design(\" \"module ${design}_post_route (\"} \$file_content]">>raptor_tcl.tcl
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echo "# Open the file again, this time in write mode to overwrite the old content">>raptor_tcl.tcl
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echo "set output_file [open \"$design/run_1/synth_1_1/synthesis/post_pnr_wrapper_$design\_post_synth.v\" w]">>raptor_tcl.tcl
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echo "# Write the modified content back to the file">>raptor_tcl.tcl
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echo "puts \$output_file \$modified_content">>raptor_tcl.tcl
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echo "# Close the file">>raptor_tcl.tcl
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echo "close \$output_file">>raptor_tcl.tcl
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echo "puts \"Modification completed.\"">>raptor_tcl.tcl
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# echo "exec python3 $main_path/../../../scripts/post_route_script.py $design">>raptor_tcl.tcl
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[ "$tool_name" = "iverilog" ] && echo "simulation_options compilation icarus -DPNR=1 pnr" >> raptor_tcl.tcl || echo "simulation_options compilation verilator -DPNR=1 pnr" >> raptor_tcl.tcl
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[ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl
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else
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echo ""
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fi
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echo "setup_lec_sim">>raptor_tcl.tcl
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echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl
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echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl
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echo "power">>raptor_tcl.tcl
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echo "bitstream $bitstream">>raptor_tcl.tcl
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if [ "$bitstream_sim" == true ]; then
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echo "clear_simulation_files">>raptor_tcl.tcl
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echo "add_simulation_file testbench.sv">>raptor_tcl.tcl
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echo "add_library_path ../../../../openfpga-pd-castor-rs/k6n8_TSMC16nm_7.5T/CommonFiles/task/CustomModules/">>raptor_tcl.tcl
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echo "simulate "bitstream_bd" "icarus" ">>raptor_tcl.tcl
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else
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echo ""
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fi
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fi
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cd results_dir
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echo "Device: $device">>results.log
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echo "Strategy: $strategy">>results.log
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timeout+='m'
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if [ -d ../rtl ]; then
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rm -fr ../rtl/obj_dir ../rtl/*.vcd ../rtl/*.cpp ../rtl/simv.daidir ../rtl/csrc
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[ ! -f ../cksums.md5 ] && find ../rtl -type f -exec md5sum {} + > ../cksums.md5
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find ../rtl -type f -exec md5sum {} + > ../newsum.md5
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else
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echo ""
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fi
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#running raptor flow script
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if cmp --silent -- "../cksums.md5" "../newsum.md5" && [ -d $design ]; then
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echo "Raptor was already compiled"
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else
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timeout $timeout raptor --batch $mute_flag --script ../raptor_tcl.tcl 2>&1 | tee -a results.log
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if [ ${PIPESTATUS[0]} -eq 124 ]; then
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echo -e "\nERROR: TIM: Design Compilation took $timeout. Exiting due to timeout">>raptor.log
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cat raptor.log >> results.log
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end_time
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parse_cga
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exit
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fi
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fi
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[ -f ../newsum.md5 ] && cp ../newsum.md5 ../cksums.md5
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}
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compile
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cat raptor.log >> results.log
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echo -e "\n\n#########Raptor Performance Data#########" >> results.log
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cat raptor_perf.log >> results.log
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echo -e "#############################################\n" >> results.log
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[ -f $main_path/sim/co_sim_tb/co_sim_$design\_temp.v ] && mv $main_path/sim/co_sim_tb/co_sim_$design\_temp.v $main_path/sim/co_sim_tb/co_sim_$design.v || echo ""
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end_time
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parse_cga

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