Merge pull request #425 from os-fpga/bug/EDA-1435/updated_rtl

updated the asym_ram_tdp_write_first_dc with tb

Author: NadeemYaseen

RTL_testcases/Memory_Designs/asym_ram_tdp_write_first_dc/raptor_run.sh

@@ -10,7 +10,7 @@ ip_name="" #design_level
 tool_name="iverilog" 
 
 #simulation stages
-post_synth_sim=false 
+post_synth_sim=true 
 post_route_sim=true 
 bitstream_sim=false
 
@@ -27,7 +27,7 @@ synthesis_type="" #(Yosys/QL/RS)
 
 custom_synth_script="" #(Uses a custom Yosys templatized script)
 
-synth_options="-new_tdp36k "
+synth_options=""
                         #synth_options <option list>: RS-Yosys Plugin Options. The following defaults exist:
                         #                               :   -effort high
                         #                               :   -fsm_encoding binary if optimization == area else onehot
@@ -170,7 +170,7 @@ parse_cga exit 1; }
     cd ..
 
     echo "create_design $design">raptor_tcl.tcl 
-    echo "target_device $device">>raptor_tcl.tcl 
+    echo "target_device 1VG28">>raptor_tcl.tcl 
 
     ##vary design to design
     [ -z "$ip_name" ] && echo "" || echo "configure_ip $ip_name"_v1_0" -mod_name=$design -Pdata_width=32 -Paddr_width=16 -Pid_width=32 -Pa_pip_out=0 -Pb_pip_out=0 -Pa_interleave=0 -Pb_interleave=0 -out_file ./$design.v">>raptor_tcl.tcl
@@ -199,6 +199,7 @@ parse_cga exit 1; }
         echo ""
     fi
 
+	echo "parser_type surelog">>raptor_tcl.tcl
 	echo "analyze">>raptor_tcl.tcl
     [ -z "$verific_parser" ] && echo "" || echo "verific_parser $verific_parser">>raptor_tcl.tcl
     [ -z "$synthesis_type" ] && echo "" || echo "synthesis_type $synthesis_type">>raptor_tcl.tcl

RTL_testcases/Memory_Designs/asym_ram_tdp_write_first_dc/rtl/asym_ram_tdp_write_first_dc.v

@@ -49,8 +49,11 @@ localparam RATIO = maxWIDTH / minWIDTH;
 localparam log2RATIO = log2(RATIO);
 
 reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
-reg [WIDTHA-1:0] readA;
+reg [WIDTHA-1:0] readA = 'd0;
 reg [WIDTHB-1:0] readB;
+
+// RAM Inference for blocking assignments can be achieved 
+// in this case as it meets the blocking->nonblocking conversion criteria    
 always @(posedge clkB)
 begin
     if (enaB) 
@@ -61,6 +64,8 @@ begin
     end
 end
 
+// This block prevents current mapping in our architecture
+   /*
 always @(posedge clkA)
 begin : portA
 integer i;
@@ -76,6 +81,7 @@ reg [log2RATIO-1:0] lsbaddr ;
             end
     end
 end
+*/
 
 assign doA = readA;
 assign doB = readB;

RTL_testcases/Memory_Designs/asym_ram_tdp_write_first_dc/sim/co_sim_tb/co_sim_asym_ram_tdp_write_first_dc.v

@@ -9,16 +9,16 @@ module co_sim_asym_ram_tdp_write_first_dc;
     parameter SIZEA = 256;
     parameter ADDRWIDTHA = 8;
 
-    input clkA;
-    input clkB;
-    input weA, weB;
-    input enaA, enaB;
-    input [ADDRWIDTHA-1:0] addrA;
-    input [ADDRWIDTHB-1:0] addrB;
-    input [WIDTHA-1:0] diA;
-    input [WIDTHB-1:0] diB;
-    output [WIDTHA-1:0] doA, doA_netlist;
-    output [WIDTHB-1:0] doB, doB_netlist;
+    reg clkA;
+    reg clkB;
+    reg weA, weB;
+    reg enaA, enaB;
+    reg [ADDRWIDTHA-1:0] addrA;
+    reg [ADDRWIDTHB-1:0] addrB;
+    reg [WIDTHA-1:0] diA;
+    reg [WIDTHB-1:0] diB;
+    wire [WIDTHA-1:0] doA, doA_netlist;
+    wire [WIDTHB-1:0] doB, doB_netlist;
 
     integer mismatch=0;
     reg [6:0]cycle, i;
@@ -40,59 +40,52 @@ module co_sim_asym_ram_tdp_write_first_dc;
         clkB = 1'b0;
         forever #5 clkB = ~clkB;
     end
+
     initial begin
-        for(integer i = 0; i<1024; i=i+1) begin 
-            golden.RAM[i] ='b0;
-        end  
-    end
-    initial begin
-    {enaA, enaB, weA, weB, addrA, addrB, diA,, diB, cycle, i} = 0;
+
+        for (integer i = 0; i < 1024; i++)  begin
+            golden.RAM[i] = 'b0;
+        end
+
+        {diA, addrA, addrB, diB, enaA, enaB, weA, weB } <= 'd0;
 
 
-    repeat (1) @ (negedge clkA);
+    repeat (1) @ (negedge clkB);
     enaA = 1'b1;
-    enaB = 1'b0;
+    enaB = 1'b1;
+    weB = 1'b1;
+    weA =1'b1;
     //write 
     for (integer i=0; i<1024; i=i+1)begin
-        repeat (1) @ (negedge clkA)
-        addrA <= $urandom_range(0,511);  addrB <= $urandom_range(512,1023); weA <=1'b1; diA<= $random;
+        repeat (4) @ (negedge clkB)
+        addrA <= $urandom_range(0,511);  addrB <= $urandom_range(512,1023); weA <=1'b1; diA<= $random; diB<= $random;
         cycle = cycle +1;
 
         compare(cycle);
 
     end
 
-    repeat (1) @ (negedge clkA);
+    repeat (1) @ (negedge clkB);
     enaB = 1'b1;
-    enaA = 1'b0;
-    weA =0;
+    enaA = 1'b1;
+    weA =1;
     //reading 
     for (integer i=0; i<1024; i=i+1)begin
-        repeat (1) @ (negedge clkB)
-        addrA <= $urandom_range(0,511);  addrB <= $urandom_range(512,1023); weB <= 1; diB<= $random;
+        repeat (4) @ (negedge clkB)
+        addrA <= $urandom_range(0,511);  addrB <= $urandom_range(512,1023); weB <= 1; diA<= $random; diB<= $random;
         cycle = cycle +1;
 
         compare(cycle);
 
     end
 
-       for (integer i=0; i<1024; i=i+1)begin
-        repeat (1) @ (negedge clkB)
-        enaB = $random;
-        enaA = $random;
-        addrA <= $urandom_range(0,511);  addrB <= $urandom_range(512,1023); weA=$random; weB <= $random; diA<= $random; diB<= $random;
-        cycle = cycle +1;
-        
-        compare(cycle);
-
-    end
     if(mismatch == 0)
         $display("\n**** All Comparison Matched ***\nSimulation Passed");
     else
         $display("%0d comparison(s) mismatched\nERROR: SIM: Simulation Failed", mismatch);
 
 
-    repeat (10) @(negedge clk); $finish;
+    repeat (10) @(negedge clkB); $finish;
     end
 
     task compare(input integer cycle);

RTL_testcases/Memory_Designs/asym_ram_tdp_write_first_dc/test.config

@@ -1,6 +1,6 @@
 #test_owner:"abdulhameed.akram"
 #test_details:"test performs the raptor compile and simulation" 
-#test_status:"inactive"
+#test_status:"active"
 #simulator:"vcs"
 #stage_id:"4"
 #reg_type:"2"