Merge pull request #416 from os-fpga/setup_lec

added setup_lec_sim command for 4 designs

Author: NadeemYaseen

RTL_testcases/RTL_Benchmarks_Gap_Analysis/axi_st_d256_multichannel/raptor_run.sh

@@ -282,6 +282,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim 10 2">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/RTL_Benchmarks_Gap_Analysis/axi_st_d64/raptor_run.sh

@@ -275,6 +275,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim 10 2">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/RTL_Benchmarks_Gap_Analysis/axi_st_d64_nordy/raptor_run.sh

@@ -275,6 +275,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim 10 2">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/RTL_Benchmarks_Gap_Analysis/axi_st_d64_nordy/rtl/axi_st_d64_nordy_master_name.sv

@@ -31,6 +31,8 @@ module axi_st_d64_nordy_master_name  (
 
 );
 
+  wire user_st_vld;
+
   // Connect Data
 
   assign user_st_vld                        = 1'b1                               ; // user_st_vld is unused

RTL_testcases/RTL_Benchmarks_Gap_Analysis/axilite_noctrl_combined_ip_litex/raptor_run.sh

@@ -19,7 +19,7 @@ device="GEMINI_COMPACT_104x68"
 
 strategy="delay" #(area, delay, mixed, none) 
 
-add_constraint_file="./raptor_sdc.sdc" #Sets SDC + location constraints  Constraints: set_pin_loc, set_mode, all SDC Standard commands
+add_constraint_file="" #Sets SDC + location constraints  Constraints: set_pin_loc, set_mode, all SDC Standard commands
 
 verific_parser="" #(on/off)
 
@@ -259,6 +259,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  
@@ -272,6 +275,8 @@ parse_cga exit 1; }
         fi
     fi
 
+    [ -f rtl/sim.v ] && sed -i -e "s|MEM_FILE_PATH|$PWD/rtl|g" rtl/sim.v
+
     cd results_dir
     echo "Device: $device">>results.log
     echo "Strategy: $strategy">>results.log

RTL_testcases/RTL_Benchmarks_Gap_Analysis/axilite_noctrl_combined_ip_litex/rtl/sim.v

@@ -2697,7 +2697,7 @@ end
 // Port 0 | Read: Sync  | Write: ---- | 
 reg [31:0] mem[0:5348];
 initial begin
-	$readmemh("mem.init", mem);
+	$readmemh("MEM_FILE_PATH/mem.init", mem);
 end
 reg [31:0] mem_dat0;
 always @(posedge sys_clk_1) begin
@@ -2712,7 +2712,7 @@ assign main_simsoc_dat_r = mem_dat0;
 // Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
 reg [31:0] mem_1[0:874];
 initial begin
-	$readmemh("mem_1.init", mem_1);
+	$readmemh("MEM_FILE_PATH/mem_1.init", mem_1);
 end
 reg [9:0] mem_1_adr0;
 always @(posedge sys_clk_1) begin
@@ -2735,7 +2735,7 @@ assign main_ram_dat_r = mem_1[mem_1_adr0];
 // Port 0 | Read: Sync  | Write: ---- | 
 reg [7:0] mem_2[0:36];
 initial begin
-	$readmemh("mem_2.init", mem_2);
+	$readmemh("MEM_FILE_PATH/mem_2.init", mem_2);
 end
 reg [5:0] mem_2_adr0;
 always @(posedge sys_clk_1) begin
@@ -2750,8 +2750,8 @@ assign builder_csr_bankarray_dat_r = mem_2[mem_2_adr0];
 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 10 
 // Port 1 | Read: Sync  | Write: ---- | 
 reg [9:0] storage[0:15];
-reg [9:0] storage_dat0;
-reg [9:0] storage_dat1;
+reg [9:0] storage_dat0=10'd0;
+reg [9:0] storage_dat1=10'd0;
 always @(posedge sys_clk_1) begin
 	if (main_uart_tx_fifo_wrport_we)
 		storage[main_uart_tx_fifo_wrport_adr] <= main_uart_tx_fifo_wrport_dat_w;