Merge pull request #405 from os-fpga/post_synth_sim

made post_synth_sim flag false

Author: NadeemYaseen

RTL_testcases/RS_Primitive_example_designs/carry_infer/raptor_run.sh

@@ -10,7 +10,7 @@ ip_name="" #design_level
 tool_name="iverilog" 
 
 #simulation stages
-post_synth_sim=true 
+post_synth_sim=false 
 post_route_sim=true 
 bitstream_sim=false
 

RTL_testcases/RS_Primitive_example_designs/primitive_example_design_1/raptor_run.sh

@@ -10,7 +10,7 @@ ip_name="" #design_level
 tool_name="iverilog" 
 
 #simulation stages
-post_synth_sim=true 
+post_synth_sim=false 
 post_route_sim=true 
 bitstream_sim=false
 

RTL_testcases/RS_Primitive_example_designs/primitive_example_design_13/raptor_run.sh

@@ -10,7 +10,7 @@ ip_name="" #design_level
 tool_name="iverilog" 
 
 #simulation stages
-post_synth_sim=true 
+post_synth_sim=false 
 post_route_sim=true 
 bitstream_sim=false
 

RTL_testcases/RS_Primitive_example_designs/primitive_example_design_14/raptor_run.sh

@@ -10,7 +10,7 @@ ip_name="" #design_level
 tool_name="iverilog" 
 
 #simulation stages
-post_synth_sim=true 
+post_synth_sim=false 
 post_route_sim=true 
 bitstream_sim=false
 

RTL_testcases/RS_Primitive_example_designs/primitive_example_design_2/raptor_run.sh

@@ -10,7 +10,7 @@ ip_name="" #design_level
 tool_name="iverilog" 
 
 #simulation stages
-post_synth_sim=true 
+post_synth_sim=false 
 post_route_sim=true 
 bitstream_sim=false
 

RTL_testcases/RS_Primitive_example_designs/primitive_example_design_4/raptor_run.sh

@@ -10,7 +10,7 @@ ip_name="" #design_level
 tool_name="iverilog" 
 
 #simulation stages
-post_synth_sim=true 
+post_synth_sim=false 
 post_route_sim=true 
 bitstream_sim=false
 

RTL_testcases/RS_Primitive_example_designs/primitive_example_design_5/raptor_run.sh

@@ -10,7 +10,7 @@ ip_name="" #design_level
 tool_name="iverilog" 
 
 #simulation stages
-post_synth_sim=true 
+post_synth_sim=false 
 post_route_sim=true 
 bitstream_sim=false
 

RTL_testcases/RS_Primitive_example_designs/primitive_example_design_6/raptor_run.sh

@@ -10,7 +10,7 @@ ip_name="" #design_level
 tool_name="iverilog" 
 
 #simulation stages
-post_synth_sim=true 
+post_synth_sim=false 
 post_route_sim=true 
 bitstream_sim=false