added setup_lec_sim for 3 designs

Author: zhergarvi

RTL_testcases/RTL_Benchmarks_Gap_Analysis/fpga-median/raptor_run.sh

@@ -186,7 +186,7 @@ parse_cga exit 1; }
     # [ -z "$ip_name" ] && echo "add_library_ext .v .sv">>raptor_tcl.tcl || echo "" 
     [ -z "$ip_name" ] && echo "add_design_file ./rtl/common_network.v">>raptor_tcl.tcl
     [ -z "$ip_name" ] && echo "add_design_file ./rtl/dff_3_pipe.v">>raptor_tcl.tcl
-    [ -z "$ip_name" ] && echo "add_design_file ./rtl/dual_port_ram.v">>raptor_tcl.tcl
+    # [ -z "$ip_name" ] && echo "add_design_file ./rtl/dual_port_ram.v">>raptor_tcl.tcl
     [ -z "$ip_name" ] && echo "add_design_file ./rtl/median.v">>raptor_tcl.tcl
     [ -z "$ip_name" ] && echo "add_design_file ./rtl/node.v">>raptor_tcl.tcl
     [ -z "$ip_name" ] && echo "add_design_file ./rtl/pixel_network.v">>raptor_tcl.tcl
@@ -264,6 +264,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/test_raptor_batch_options/fsm_encoding_binary/raptor_run.sh

@@ -258,6 +258,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/test_raptor_batch_options/fsm_encoding_onehot/raptor_run.sh

@@ -258,6 +258,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl