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doc: Add changelog for 1.1 release
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CHANGELOG.md

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# Changelog
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All notable changes to this project will be documented in this file.
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It is updated on each new release based on contributions since the last release.
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The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.1.0/),
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and this project loosely follows to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
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## 1.1.0 - 2025-05-07
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### Added
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- sw: add various peripheral functions
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- sw: add expanded helloworld as peripheral test
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- pdk: add ETHZ cockpit integration
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- openroad: add startup script for ease-of-use
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- openroad: add parasitic extraction
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- ci: add short synthesis and simulation flows
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- ci: add long end-to-end flow
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- ci: add artistic rendering flow
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- openroad: add hierarchical area report
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### Changed
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- hw: make SRAM pin `A_DLY` configurable (used to be tied to low when datasheet recommends tie to high)
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**IMPORTANT: This bug may create SRAM-internal timing violations; update strongly recommended**
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- hw: update OBI dependency
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- avoid explicit use of `r_optional` assignments
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- fix index width calculations for mux/demux etc
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- hw: update common_cells dependency
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- yosys: move configurations from makefrags to `yosys_synthesis.tcl`
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- yosys: add a default croc.flist
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### Fixed
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- hw: fix OBI connections to timer peripheral
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- hw: various fixes to reduce warnings (Yosys, yosys-slang, Verilator)
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- openroad: fix LVS netlist
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- sw: fix linker script
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-test: fix uninitialized memory
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- verilator: speedup compile and synthesis
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- bender: fix cve2 vendor dependency
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## 1.0.0 - 2024-12-05
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### Added
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- Initial versioned release of the project

README.md

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MLEM was designed and prepared for tapeout by ETHZ students as a bachelor project. The exact code and scripts used for the tapeout can be seen in the frozen [mlem-tapeout](https://github.com/pulp-platform/croc/tree/mlem-tapeout) branch.
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**IMPORTANT: Update to 1.1 recommended.**
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Release 1.1 and newer includes a fix for the SRAMs where the `A_DLY` pin was tied low instead of high. The pin controls internal timings and the old version may create violations for some SRAMs.
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## Architecture
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![Croc block diagram](doc/croc_arch.svg)

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